A low power consumption power-on reset circuit

Abstract

The invention discloses a low-power power-on reset circuit, comprising a startup circuit, a Schmitt trigger, a P1 tube, a P2 tube, a P3 tube, a resistor R1, a resistor R2, a resistor R3a, a resistor R3b, a resistor R3c, a Q1 tube, a Q2 tube and a N1 tube; the N1 tube is an intrinsic field effect transistor or a depletion field effect transistor. Advantages: the circuit of the invention has low power consumption, a small area of ​​resistance, and a small change in the flip point voltage with process and temperature.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a low-power consumption power-on reset circuit. Background Art

[0002] The power-on-reset circuit (POR) is widely used in the power management systems of various chips such as MCU, sensors and SOC. Its main function is to keep the system reset and initialize the chip to a known state when the chip is powered on. Once the power supply is stable, the POR will release the reset signal and the chip will start running. The POR ensures the reliable startup of the chip, and can also reset the system to a stable state when the chip encounters power fluctuations or other abnormal conditions during operation. Usually, the POR is always in working state, so low power consumption is required, and the current is generally less than 1uA.

[0003] The POR circuit generally includes a comparator and a resistor string connected from the power supply to the ground, the resistor string tap determines the flip voltage, and the comparator implements comparison inversion. See the POR circuit mentioned in Chinese patent application number: CN202210435616.6.

[0004] The traditional POR circuit is relatively complex and consumes a lot of power. The present invention has a simple structure, low power consumption and a small area. Summary of the invention

[0005] The technical problem to be solved by the present invention is that the traditional structure POR circuit is relatively complex and consumes large power.

[0006] In order to solve the above technical problems, the present invention proposes a low-power power-on reset circuit, the main features of which are low power consumption, low cost and high precision.

[0007] The technical solutions adopted are as follows:

[0008] A low-power power-on reset circuit comprises a start-up circuit, a Schmitt trigger, a P1 tube, a P2 tube, a P3 tube, a resistor R1, a resistor R2, a resistor R3a, a resistor R3b, a resistor R3c, a Q1 tube, a Q2 tube and a N1 tube. The gates of the P1 tube and the P2 tube are connected and connected to the drain of the P2 tube, and the drain of the P2 tube is connected to the collector of the Q2 tube. The ratio of the width to length of the P1 tube and the P2 tube is M:1, and M is an arbitrary value. The sources of the P1 tube, the P2 tube and the P3 tube are connected, and the drain of the P1 tube is connected to the gate of the P3 tube and one end of the resistor R1 at the same time. The other end of the resistor R1 is connected to the collector and base of the Q1 tube at the same time. The bases of the Q1 tube and the Q2 tube are connected. The emitter junction area ratio of the Q1 tube and the Q2 tube is 1:N, where N is an arbitrary value. The emitter of the Q2 tube is connected to the emitter of the Q1 tube through the resistor R2, and is connected to the gate of the N1 tube after being connected in series with resistors R3a, R3b and R3c. The source of the N1 tube is connected to the point C between the resistors R3b and R3c, the drain of the N1 tube is connected to the drain of the P3 tube, and the Schmitt trigger is connected to the PORB node between the drain of the N1 tube and the drain of the P3 tube. The two ends of the startup circuit are respectively connected to the gate of the P1 tube and the point B between the resistors R3a and R3b.

[0009] In a further preferred embodiment of the technical solution of the present invention, the N1 tube is an intrinsic field effect transistor or a depletion field effect transistor. The threshold voltage of the N1 tube is close to 0, or less than 0, and it will be turned on when it is initially powered on to provide bias current to Q3. Later, as the power supply voltage rises, the N1 tube will be turned off, and there is no static power consumption.

[0010] In a further preferred embodiment of the technical solution of the present invention, the Q1 tube and the Q2 tube are NPN tubes, and the Q1 tube and the Q2 tube generate a positive temperature coefficient voltage.

[0011] In a further preferred embodiment of the technical solution of the present invention, the P3 tube is a PMOS tube or a PNP tube.

[0012] In a further preferred embodiment of the technical solution of the present invention, any section of the resistor R1 and / or the resistor R3 is short-circuited in the low-power power-on reset circuit to generate a hysteresis comparison voltage, thereby achieving different reset and release voltages, wherein the resistor R3a, the resistor R3b and the resistor R3c are all part of the resistor R3.

[0013] In a further preferred embodiment of the technical solution of the present invention, the P1 transistor and the P2 transistor are PMOS transistors or PNP transistors, and the P1 transistor and the P2 transistor provide current mirroring.

[0014] In a further preferred embodiment of the technical solution of the present invention, the positions of point B and point C are interchanged, the source of tube N1 is connected to point B between resistor R3b and resistor R3c, and the two ends of the start-up circuit are respectively connected to the gate of tube P1 and point C between resistor R3a and resistor R3b.

[0015] The startup circuit mentioned in the circuit of the present invention is a known circuit, known to those skilled in the art; the Schmitt trigger is a known technology in the power-on reset circuit.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The circuit of the present invention has low power consumption, small resistance area, and small change in flip point voltage with process and temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a circuit diagram of the present embodiment 1;

[0019] Figure 2 This is a circuit diagram of the second embodiment. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the following Figure 1-Figure 2 The present invention is further described in detail with reference to the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in each embodiment of the present invention described below can be combined with each other as long as they do not conflict with each other. Example 1

[0021] like Figure 1 As shown, this embodiment is a low-power power-on reset circuit, including a startup circuit, a Schmitt trigger, a P1 tube, a P2 tube, a P3 tube, a resistor R1, a resistor R2, a resistor R3a, a resistor R3b, a resistor R3c, a Q1 tube, a Q2 tube and a N1 tube. The gates of the P1 tube and the P2 tube are connected and connected to the drain of the P2 tube, and the drain of the P2 tube is connected to the collector of the Q2 tube. The ratio of the width to length of the P1 tube and the P2 tube is M:1, and M is an arbitrary value. The sources of the P1 tube, the P2 tube and the P3 tube are connected, and the drain of the P1 tube is connected to the gate of the P3 tube and one end of the resistor R1 at the same time. The other end of the resistor R1 is connected to the collector and base of the Q1 tube at the same time. The bases of the Q1 tube and the Q2 tube are connected. The emitter junction area ratio of the Q1 tube and the Q2 tube is 1:N, where N is an arbitrary value. The emitter of the Q2 tube is connected to the emitter of the Q1 tube through the resistor R2, and is connected to the gate of the N1 tube after being connected in series with resistors R3a, R3b and R3c. The source of the N1 tube is connected to the point C between the resistors R3b and R3c, the drain of the N1 tube is connected to the drain of the P3 tube, and the Schmitt trigger is connected to the PORB node between the drain of the N1 tube and the drain of the P3 tube. The two ends of the startup circuit are respectively connected to the gate of the P1 tube and the point B between the resistors R3a and R3b.

[0022] The specific working principle is as follows:

[0023] The power supply voltage VDD is initially 0, and the node PORB is 0. After PORB passes through the Schmitt trigger, a POR signal is generated, and POR is inverse to PORB. As VDD rises, the startup circuit turns on the power-on reset circuit, PORB remains low, POR is high, and the system remains reset. The current flowing through Q1 and Q2 is , so the voltage at node A is ,in, is the emitter junction voltage of Q1 tube, is the thermal voltage.

[0024] The absolute value of the threshold voltage of the P3 tube is , when the power supply voltage rises to VDD ≥ + When the P3 tube is turned on, PORB is pulled up to a high level, POR becomes a low level, the reset signal is released, and the system starts to operate normally.

[0025] The power supply switching voltage is , where the first and third terms are negative temperature coefficient terms, and the second term is a positive temperature coefficient term; the temperature coefficient of the flip voltage can be reasonably adjusted to achieve a high-precision flip voltage point.

[0026] N1 is an intrinsic field effect transistor or a depletion field effect transistor. When the power is initially turned on, point C is 0, and N1 is turned on, providing bias current to P3. As the power supply voltage rises, point C rises until N1 is turned off. Therefore, the static current only exists in P1 and P2, achieving low power consumption. Here, the positions of point B and point C can be interchanged. Figure 1 Just an illustration of one of the situations.

[0027] In addition, by short-circuiting any section of the resistor R1 and / or the resistor R3 , a hysteresis comparison voltage can be generated, thereby achieving different reset and release voltages.

[0028] That is, the manner of shorting any section of the resistor R1 and / or the resistor R3 is: shorting the resistor R1, shorting any section of the resistor R3, and shorting the resistor R1 and any section of the resistor R3. In this embodiment, the resistor R3 includes three parts, namely, the resistor R3a, the resistor R3b, and the resistor R3c. The function of the resistor R3 is to generate a positive temperature coefficient voltage. The function of the resistor R1 is to generate a positive temperature coefficient current. Example 2

[0029] like Figure 2 As shown, in the low-power power-on reset circuit of Example 1, the P3 tube can also be replaced by a PNP tube, thereby realizing a more accurate power-on reset circuit. That is, Figure 2 The Q3 tube in the circuit is a PNP tube.

[0030] The power supply flip voltage of this circuit is + The emitter junction voltage of Q3 tube The process variation is smaller, so a higher precision flip voltage point can be achieved.

[0031] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A low power consumption power-on reset circuit, characterized in that: The invention comprises a start-up circuit, a Schmitt trigger, a P1 tube, a P2 tube, a P3 tube, a resistor R1, a resistor R2, a resistor R3a, a resistor R3b, a resistor R3c, a Q1 tube, a Q2 tube and a N1 tube, wherein the N1 tube is an intrinsic field effect transistor or a depletion field effect transistor, the gates of the P1 tube and the P2 tube are connected and connected to the drain of the P2 tube, and the drain of the P2 tube is connected to the collector of the Q2 tube; the ratio of the width to length of the P1 tube and the P2 tube is M:1, and M is an arbitrary value; the sources of the P1 tube, the P2 tube and the P3 tube are connected, and the drain of the P1 tube is connected to the gate of the P3 tube and one end of the resistor R1 at the same time, The other end of the resistor R1 is connected to the collector and base of the Q1 tube at the same time. The bases of the Q1 tube and the Q2 tube are connected. The emitter junction area ratio of the Q1 tube and the Q2 tube is 1:N, where N is an arbitrary value. The emitter of the Q2 tube is connected to the emitter of the Q1 tube through the resistor R2, and is connected to the gate of the N1 tube after being connected in series with resistors R3a, R3b and R3c. The source of the N1 tube is connected to the point C between the resistors R3b and R3c, the drain of the N1 tube is connected to the drain of the P3 tube, and the Schmitt trigger is connected to the PORB node between the drain of the N1 tube and the drain of the P3 tube. The two ends of the startup circuit are respectively connected to the gate of the P1 tube and the point B between the resistors R3a and R3b.

2. The low power consumption power-on reset circuit according to claim 1, characterized in that: Q1 and Q2 are NPN tubes.

3. The low power consumption power-on reset circuit according to claim 1, characterized in that: The P3 tube is a PMOS tube or a PNP tube.

4. The low power consumption power-on reset circuit according to claim 1, characterized in that: In the low power consumption power-on reset circuit, any one section of the resistor R1 and / or the resistor R3 is short-circuited to generate a hysteresis comparison voltage, wherein the resistor R3a, the resistor R3b and the resistor R3c are all parts of the resistor R3.

5. The low power consumption power-on reset circuit according to claim 1, characterized in that: P1 and P2 are PMOS or PNP tubes.

6. The low power consumption power-on reset circuit according to claim 1, characterized in that: The positions of point B and point C are swapped, the source of tube N1 is connected to point B between resistor R3b and resistor R3c, and the two ends of the startup circuit are respectively connected to the gate of tube P1 and point C between resistor R3a and resistor R3b.

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