Integrated circuit

Abstract

The utility model discloses an integrated circuit, which belongs to the technical field of semiconductors, comprises a logic gate circuit Gata, a dead zone control unit, an over-current protection unit and a driving output unit, solves the technical problems of providing stable dead zone control, quickly responding to over-current protection and preventing simultaneous conduction of HO and LO in the process of driving an H bridge, does not need to be controlled by an MCU (Microprogrammed Control Unit), and is convenient to use. The system independence is improved, the hardware circuit response speed is high, RC delay and a Schmitt trigger are adopted, stable and reliable dead time is ensured, efficient dead time control is achieved, a current sampling resistor, a comparator and a D trigger are adopted for over-current detection, the response speed is high, an H-bridge driving signal is cut off immediately during over-current, damage is prevented, the logic gate design ensures that no driving signal exists when A = 1 and B = 1 or A = 0 and B = 0, and the system reliability is improved. H-bridge direct connection is avoided, overcurrent alarm is provided through an ALRM pin, and fault detection of the system is facilitated.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor technology, and in particular relates to an integrated circuit. Background Technology

[0002] The H-bridge drive circuit is a commonly used power electronic circuit, mainly used to control the forward and reverse rotation and speed regulation of DC motors.

[0003] The following problems typically exist in existing H-bridge driver circuits:

[0004] Lack of hardware-level dead-time control: Traditional H-bridge solutions rely on software to control dead time, which limits response speed;

[0005] Slow overcurrent protection response: Traditional solutions use MCU to acquire ADC for overcurrent detection, which results in time delay and slow response.

[0006] H-bridge shoot-through risk: Under abnormal conditions (such as abnormal PWM signal), many circuits may cause the upper and lower bridge MOSFETs of the H-bridge to conduct simultaneously, resulting in short-circuit damage. Utility Model Content

[0007] The purpose of this invention is to provide an integrated circuit that solves the technical problem of providing stable dead-time control, fast-response overcurrent protection, and preventing simultaneous conduction of HO and LO during the driving of an H-bridge.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] An integrated circuit includes a logic gate circuit Gata, a dead-time control unit, an overcurrent protection unit, and a drive output unit. The input terminals of the logic gate circuit Gata include pin A and pin B, both of which are used to connect to an external PWM signal. The output terminal of the logic gate circuit Gata is connected to the dead-time control unit.

[0010] The Gata logic gate circuit is used to process external PWM signals and generate initial H-bridge control signals;

[0011] The output of the dead zone control unit is connected to the input of the drive output unit;

[0012] The dead time control unit is used to introduce dead time through a delay circuit to prevent the upper and lower bridge control signals in the H-bridge control signal from being turned on simultaneously.

[0013] The output terminal of the drive output unit outputs HO and LO pins, both of which are used to connect to the IGBT power transistors in the external H-bridge.

[0014] The input terminals of the overcurrent protection unit include pins Vref, VS, and REST. Pin Vref is used to connect to an external reference voltage, pin REST is used to input a reset signal, and pin VS is used to connect to an external current sampling resistor.

[0015] The output of the overcurrent protection unit provides one overcurrent alarm signal and is connected to the ALRM pin; the ALRM pin is used to send out overcurrent alarms.

[0016] The output of the overcurrent protection unit is also connected to the logic gate circuit Gata. The overcurrent protection unit is used to monitor the H-bridge current. When an overcurrent occurs, it shuts down the output of the logic gate circuit Gata, thereby shutting down the output of the H-bridge control signal.

[0017] Preferably, the dead-time control unit includes a delay circuit RC and a flip-flop circuit ST. The input of the delay circuit RC is connected to the output of the logic gate circuit Gata, the output of the delay circuit RC is connected to the input of the flip-flop circuit ST, and the output of the flip-flop circuit ST is connected to the input of the drive output unit.

[0018] Preferably, the overcurrent protection unit includes a voltage sampling circuit SC, a comparator circuit Comp, a flip-flop D-FF, a current isolation circuit CI, and an inverter NOT. The input terminal of the voltage sampling circuit SC is connected to the VS pin, and the output terminal is connected to the positive input terminal of the comparator circuit Comp. The negative input terminal of the comparator circuit Comp is connected to the Vref pin, and the output terminal is connected to the CLK pin of the flip-flop D-FF. The RD pin of the flip-flop D-FF is connected to the REST pin, and the Q pin is connected to the input terminal of the inverter NOT. The output terminal of the inverter NOT is the output terminal of the overcurrent protection unit, which is connected to the logic gate circuit Gata.

[0019] The Q terminal of the trigger D-FF is also connected to the current isolation circuit CI, which is connected to the ALRM pin. The current isolation circuit CI provides an overcurrent alarm signal for the overcurrent protection unit.

[0020] Preferably, the logic gate circuit Gata includes NOT1, NOT2, AND1, AND2, AND3, and AND4. The input of NOT1 is connected to pin A, and its output is connected to one input of AND2. The other input of AND2 is connected to pin B. The input of NOT2 is connected to pin B, and its output is connected to one input of AND1. The other input of AND1 is connected to pin A. The output of AND1 is connected to one input of AND3. The output of AND2 is connected to one pin of AND4. The output of AND3 outputs one of the preliminary H-bridge control signals, HO-CTRL signal, and the output of AND3 outputs another of the preliminary H-bridge control signals, LO-CTRL signal.

[0021] The voltage sampling circuit SC is a voltage sampling circuit composed of resistors RX and RS. Pin 1 of resistor RS is connected to the ground wire through resistor RS, and pin 1 of resistor RS is connected to the VS pin.

[0022] The comparator circuit Comp is comparator Comp1. The positive input terminal of comparator Comp1 is connected to pin 2 of resistor RS, and the negative input terminal is connected to the Vref pin.

[0023] The flip-flop D-FF is a D flip-flop D-FF1. The CLK terminal of the D flip-flop D-FF1 is connected to the output terminal of the comparator Comp1, the D terminal and the SD terminal are both connected to the ground wire, and the RD terminal is connected to the REST pin.

[0024] The inverter NOT is NOT3. The input of NOT3 is connected to the Q terminal of D flip-flop D-FF1, and the output is connected to one input of AND gate AND3 and one input of AND gate AND4, respectively.

[0025] The current isolation circuit CI is a diode D. The positive terminal of diode D is connected to the Q terminal of D flip-flop D-FF1, and the negative terminal is connected to the ALRM pin.

[0026] Preferably, the delay circuit RC includes resistor R1, capacitor C1, resistor R2 and capacitor C2, resistor R1 and capacitor C1 constitute a first RC delay circuit, and resistor R2 and capacitor C2 constitute a second RC delay circuit.

[0027] The trigger circuit ST includes Schmitt trigger ST1 and Schmitt trigger ST2;

[0028] Pin 1 of resistor R1 is connected to the HO-CTRL signal, and pin 2 is connected to the input of Schmitt trigger ST1; one end of capacitor C1 is connected to pin 2 of resistor R1, and the other end is connected to ground.

[0029] Pin 1 of resistor R2 is connected to the LO-CTRL signal, and pin 2 is connected to the input of Schmitt trigger ST2; one end of capacitor C2 is connected to pin 2 of resistor R2, and the other end is connected to ground.

[0030] The drive output unit includes buffer Buffer1 and buffer Buffer2. Buffer Buffer1 includes inverters NOT4 and NOT5, and buffer Buffer2 includes inverters NOT6 and NOT7. The input of inverter NOT4 is connected to the output of Schmitt trigger ST1, and its output is connected to the input of inverter NOT5. The output of inverter NOT5 is connected to the HO pin. The input of inverter NOT6 is connected to the output of Schmitt trigger ST2, and its output is connected to the input of inverter NOT7. The output of inverter NOT7 is connected to the LO pin.

[0031] The integrated circuit described in this invention solves the technical problems of providing stable dead-time control, fast overcurrent protection response, and preventing simultaneous conduction of HO and LO during H-bridge driving. This invention eliminates the need for MCU control, improving system independence. The hardware circuit has a fast response speed, and RC delay + Schmitt trigger ensures stable and reliable dead time, providing efficient dead-time control. Overcurrent detection uses a current sampling resistor + comparator + D flip-flop, resulting in fast response speed. In case of overcurrent, the H-bridge drive signal is immediately cut off to prevent damage. The logic gate design ensures that there is no drive signal when A=1, B=1 or A=0, B=0, avoiding H-bridge shoot-through. Overcurrent alarm is provided through the ALRM pin, facilitating system fault detection. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the present invention.

[0033] Figure 2 This is the equivalent circuit diagram of this utility model. Detailed Implementation

[0034] Depend on Figures 1-2 An integrated circuit is shown, including a logic gate circuit Gata, a dead-time control unit, an overcurrent protection unit, and a drive output unit. The input terminals of the logic gate circuit Gata include pin A and pin B, both of which are used to connect to an external PWM signal. The output terminal of the logic gate circuit Gata is connected to the dead-time control unit.

[0035] The Gata logic gate circuit is used to process external PWM signals and generate initial H-bridge control signals;

[0036] The logic gate circuit Gata includes NOT1, NOT2, AND1, AND2, AND3, and AND4. The input of NOT1 is connected to pin A, and its output is connected to one input of AND2. The other input of AND2 is connected to pin B. The input of NOT2 is connected to pin B, and its output is connected to one input of AND1. The other input of AND1 is connected to pin A. The output of AND1 is connected to one input of AND3. The output of AND2 is connected to one pin of AND4. The output of AND3 outputs one of the initial H-bridge control signals, HO-CTRL, and the other of the initial H-bridge control signals, LO-CTRL.

[0037] The voltage sampling circuit SC is a voltage sampling circuit composed of resistors RX and RS. Pin 1 of resistor RS is connected to the ground wire through resistor RS, and pin 1 of resistor RS is connected to the VS pin.

[0038] The comparator circuit Comp is comparator Comp1. The positive input terminal of comparator Comp1 is connected to pin 2 of resistor RS, and the negative input terminal is connected to the Vref pin.

[0039] The flip-flop D-FF is a D flip-flop D-FF1. The CLK terminal of the D flip-flop D-FF1 is connected to the output terminal of the comparator Comp1, the D terminal and the SD terminal are both connected to the ground wire, and the RD terminal is connected to the REST pin.

[0040] The inverter NOT is NOT3. The input of NOT3 is connected to the Q terminal of D flip-flop D-FF1, and the output is connected to one input of AND gate AND3 and one input of AND gate AND4, respectively.

[0041] The current isolation circuit CI is a diode D. The positive terminal of diode D is connected to the Q terminal of D flip-flop D-FF1, and the negative terminal is connected to the ALRM pin.

[0042] The output of the dead zone control unit is connected to the input of the drive output unit;

[0043] The dead time control unit is used to introduce dead time through a delay circuit to prevent the upper and lower bridge control signals in the H-bridge control signal from being turned on simultaneously.

[0044] The dead-time control unit includes a delay circuit RC and a flip-flop circuit ST. The input of the delay circuit RC is connected to the output of the logic gate circuit Gata, the output of the delay circuit RC is connected to the input of the flip-flop circuit ST, and the output of the flip-flop circuit ST is connected to the input of the drive output unit.

[0045] The delay circuit RC includes resistor R1, capacitor C1, resistor R2 and capacitor C2. Resistor R1 and capacitor C1 constitute the first RC delay circuit, and resistor R2 and capacitor C2 constitute the second RC delay circuit.

[0046] The trigger circuit ST includes Schmitt trigger ST1 and Schmitt trigger ST2;

[0047] Pin 1 of resistor R1 is connected to the HO-CTRL signal, and pin 2 is connected to the input of Schmitt trigger ST1; one end of capacitor C1 is connected to pin 2 of resistor R1, and the other end is connected to ground.

[0048] Pin 1 of resistor R2 is connected to the LO-CTRL signal, and pin 2 is connected to the input of Schmitt trigger ST2; one end of capacitor C2 is connected to pin 2 of resistor R2, and the other end is connected to ground.

[0049] The drive output unit includes buffer Buffer1 and buffer Buffer2. Buffer Buffer1 includes inverters NOT4 and NOT5, and buffer Buffer2 includes inverters NOT6 and NOT7. The input of inverter NOT4 is connected to the output of Schmitt trigger ST1, and its output is connected to the input of inverter NOT5. The output of inverter NOT5 is connected to the HO pin. The input of inverter NOT6 is connected to the output of Schmitt trigger ST2, and its output is connected to the input of inverter NOT7. The output of inverter NOT7 is connected to the LO pin.

[0050] The output terminal of the drive output unit outputs HO and LO pins, both of which are used to connect to the IGBT power transistors in the external H-bridge.

[0051] The input terminals of the overcurrent protection unit include pins Vref, VS, and REST. Pin Vref is used to connect to an external reference voltage, pin REST is used to input a reset signal, and pin VS is used to connect to an external current sampling resistor.

[0052] The output of the overcurrent protection unit provides one overcurrent alarm signal and is connected to the ALRM pin; the ALRM pin is used to send out overcurrent alarms.

[0053] The output of the overcurrent protection unit is also connected to the logic gate circuit Gata. The overcurrent protection unit is used to monitor the H-bridge current. When an overcurrent occurs, it shuts down the output of the logic gate circuit Gata, thereby shutting down the output of the H-bridge control signal.

[0054] The overcurrent protection unit includes a voltage sampling circuit SC, a comparator circuit Comp, a flip-flop D-FF, a current isolation circuit CI, and an inverter NOT. The input terminal of the voltage sampling circuit SC is connected to the VS pin, and the output terminal is connected to the positive input terminal of the comparator circuit Comp. The negative input terminal of the comparator circuit Comp is connected to the Vref pin, and the output terminal is connected to the CLK pin of the flip-flop D-FF. The RD pin of the flip-flop D-FF is connected to the REST pin, and the Q pin is connected to the input terminal of the inverter NOT. The output terminal of the inverter NOT is the output terminal of the overcurrent protection unit, which is connected to the logic gate circuit Gata.

[0055] The Q terminal of the trigger D-FF is also connected to the current isolation circuit CI, which is connected to the ALRM pin. The current isolation circuit CI provides an overcurrent alarm signal for the overcurrent protection unit.

[0056] In this embodiment, the Gata logic gate circuit is used to receive two external PWM signals (A and B) and generate the initial H-bridge control signals HO-CTRL and LO-CTRL; the circuit consists of NOT gates and AND gates, with the following logical relationship:

[0057] NOT1: Invert A (A-);

[0058] NOT2: Invert B (B-);

[0059] AND1: Calculate A and B-;

[0060] AND2: Calculate B and A-;

[0061] AND3: Calculate AND1 and NOT3;

[0062] AND4: Calculate AND2 and NOT3;

[0063] The truth table for the Gata logic gate is shown in Table 1 below:

[0064]

[0065] Table 1

[0066] The overcurrent protection unit is used to monitor the H-bridge current. If the current exceeds the threshold, the protection circuit is triggered to shut down the output and issue an alarm signal. The VS pin is used to connect to the voltage output of the external current acquisition resistor, and the Vref pin is provided with an overcurrent reference comparison voltage by an external reference voltage circuit.

[0067] The external current acquisition resistor is mainly responsible for sampling the H-bridge current, while the resistor RS is responsible for sampling the voltage drop across the current acquisition resistor.

[0068] Compare Vs with the reference voltage Vref:

[0069] If Vs < Vref, it means the current is normal and you can continue working.

[0070] If Vs ≥ Vref, it indicates an overcurrent and triggers protection.

[0071] The D-FF1 flip-flop latches the comparator output, ensuring a stable protection signal. When an overcurrent occurs, the rising edge of its CLK terminal triggers the output, causing the high level of the D terminal (the D terminal is connected to the VCC pin to obtain a high level) to be latched to the Q terminal, thereby generating an overcurrent alarm signal. This signal is inverted by the inverter NOT3 and then input to the logic gate circuit Gate to participate in the logic of the logic gate.

[0072] Diode D provides an alarm signal and is output through the ALRM pin. Diode D is used to prevent backflow of current.

[0073] When Q (protection trigger) is 1, NOT3=0. Regardless of the values ​​of A and B, AND3 and AND4 are both 0, ensuring that HO_CTRL and LO_CTRL are both 0, thus turning off the H-bridge output.

[0074] When Q is not triggered (protection is normal), i.e., NOT3=1, pins A and B are connected to external PWM signals and execute the following logic respectively:

[0075] A=1, B=0:

[0076] AND1 = 1·(¬0)=1; AND2 = 0·(¬1)=0;

[0077] HO_CTRL = 1·1 = 1; LO_CTRL = 0·1 = 0;

[0078] A=0, B=1:

[0079] AND1 = 0·(¬1)=0; AND2 = 1·(¬0)=1;

[0080] HO_CTRL = 0·1 = 0; LO_CTRL = 1·1 = 1;

[0081] A=0, B=0 or A=1, B=1:

[0082] Both AND1 and AND2 are 0;

[0083] Both HO_CTRL and LO_CTRL are 0.

[0084] The drive output unit is responsible for amplifying the signal after dead-time control and driving the IGBT power transistor. In this embodiment, a buffer drive is formed by two inverters, namely, two push-pull drives composed of inverter NOT4 + inverter NOT5 and inverter NOT6 + inverter NOT7, which enhances the driving capability.

[0085] In this embodiment, the integrated circuit also has a VCC pin and a GND pin for connecting to an external power supply to obtain the power supply voltage provided to the integrated circuit.

[0086] In this embodiment, the integrated circuit can be fabricated using wide bandgap semiconductor materials (such as GaN and SiC) or CMOS circuit technology.

[0087] The integrated circuit described in this invention solves the technical problems of providing stable dead-time control, fast overcurrent protection response, and preventing simultaneous conduction of HO and LO during H-bridge driving. This invention eliminates the need for MCU control, improving system independence. The hardware circuit has a fast response speed, and RC delay + Schmitt trigger ensures stable and reliable dead time, providing efficient dead-time control. Overcurrent detection uses a current sampling resistor + comparator + D flip-flop, resulting in fast response speed. In case of overcurrent, the H-bridge drive signal is immediately cut off to prevent damage. The logic gate design ensures that there is no drive signal when A=1, B=1 or A=0, B=0, avoiding H-bridge shoot-through. Overcurrent alarm is provided through the ALRM pin, facilitating system fault detection.

Claims

1. An integrated circuit, characterized in that: It includes a logic gate circuit Gata, a dead-time control unit, an overcurrent protection unit, and a drive output unit. The input terminals of the logic gate circuit Gata include pin A and pin B, both of which are used to connect to an external PWM signal. The output terminal of the logic gate circuit Gata is connected to the dead-time control unit. The Gata logic gate circuit is used to process external PWM signals and generate initial H-bridge control signals; The output of the dead zone control unit is connected to the input of the drive output unit; The dead time control unit is used to introduce dead time through a delay circuit to prevent the upper and lower bridge control signals in the H-bridge control signal from being turned on simultaneously. The output terminal of the drive output unit outputs HO and LO pins, both of which are used to connect to the IGBT power transistors in the external H-bridge. The input terminals of the overcurrent protection unit include pins Vref, VS, and REST. Pin Vref is used to connect to an external reference voltage, pin REST is used to input a reset signal, and pin VS is used to connect to an external current sampling resistor. The output of the overcurrent protection unit provides one overcurrent alarm signal and is connected to the ALRM pin; the ALRM pin is used to send out overcurrent alarms. The output of the overcurrent protection unit is also connected to the logic gate circuit Gata. The overcurrent protection unit is used to monitor the H-bridge current. When an overcurrent occurs, it shuts down the output of the logic gate circuit Gata, thereby shutting down the output of the H-bridge control signal.

2. An integrated circuit as described in claim 1, characterized in that: The dead-time control unit includes a delay circuit RC and a flip-flop circuit ST. The input of the delay circuit RC is connected to the output of the logic gate circuit Gata, the output of the delay circuit RC is connected to the input of the flip-flop circuit ST, and the output of the flip-flop circuit ST is connected to the input of the drive output unit.

3. An integrated circuit as described in claim 1, characterized in that: The overcurrent protection unit includes a voltage sampling circuit SC, a comparator circuit Comp, a flip-flop D-FF, a current isolation circuit CI, and an inverter NOT. The input terminal of the voltage sampling circuit SC is connected to the VS pin, and the output terminal is connected to the positive input terminal of the comparator circuit Comp. The negative input terminal of the comparator circuit Comp is connected to the Vref pin, and the output terminal is connected to the CLK pin of the flip-flop D-FF. The RD pin of the flip-flop D-FF is connected to the REST pin, and the Q pin is connected to the input terminal of the inverter NOT. The output terminal of the inverter NOT is the output terminal of the overcurrent protection unit, which is connected to the logic gate circuit Gata. The Q terminal of the trigger D-FF is also connected to the current isolation circuit CI, which is connected to the ALRM pin. The current isolation circuit CI provides an overcurrent alarm signal for the overcurrent protection unit.

4. An integrated circuit as described in claim 3, characterized in that: The logic gate circuit Gata includes NOT1, NOT2, AND1, AND2, AND3, and AND4. The input of NOT1 is connected to pin A, and its output is connected to one input of AND2. The other input of AND2 is connected to pin B. The input of NOT2 is connected to pin B, and its output is connected to one input of AND1. The other input of AND1 is connected to pin A. The output of AND1 is connected to one input of AND3. The output of AND2 is connected to one pin of AND4. The output of AND3 outputs one of the initial H-bridge control signals, HO-CTRL, and the other of the initial H-bridge control signals, LO-CTRL. The voltage sampling circuit SC is a voltage sampling circuit composed of resistors RX and RS. Pin 1 of resistor RS is connected to the ground wire through resistor RS, and pin 1 of resistor RS is connected to the VS pin. The comparator circuit Comp is comparator Comp1. The positive input terminal of comparator Comp1 is connected to pin 2 of resistor RS, and the negative input terminal is connected to the Vref pin. The flip-flop D-FF is a D flip-flop D-FF1. The CLK terminal of the D flip-flop D-FF1 is connected to the output terminal of the comparator Comp1, the D terminal and the SD terminal are both connected to the ground wire, and the RD terminal is connected to the REST pin. The inverter NOT is NOT3. The input of NOT3 is connected to the Q terminal of D flip-flop D-FF1, and the output is connected to one input of AND gate AND3 and one input of AND gate AND4, respectively. The current isolation circuit CI is a diode D. The positive terminal of diode D is connected to the Q terminal of D flip-flop D-FF1, and the negative terminal is connected to the ALRM pin.

5. An integrated circuit as described in claim 4, characterized in that: The delay circuit RC includes resistor R1, capacitor C1, resistor R2 and capacitor C2. Resistor R1 and capacitor C1 constitute the first RC delay circuit, and resistor R2 and capacitor C2 constitute the second RC delay circuit. The trigger circuit ST includes Schmitt trigger ST1 and Schmitt trigger ST2; Pin 1 of resistor R1 is connected to the HO-CTRL signal, and pin 2 is connected to the input of Schmitt trigger ST1; one end of capacitor C1 is connected to pin 2 of resistor R1, and the other end is connected to ground. Pin 1 of resistor R2 is connected to the LO-CTRL signal, and pin 2 is connected to the input of Schmitt trigger ST2; one end of capacitor C2 is connected to pin 2 of resistor R2, and the other end is connected to ground. The drive output unit includes buffer Buffer1 and buffer Buffer2. Buffer Buffer1 includes inverters NOT4 and NOT5, and buffer Buffer2 includes inverters NOT6 and NOT7. The input of inverter NOT4 is connected to the output of Schmitt trigger ST1, and its output is connected to the input of inverter NOT5. The output of inverter NOT5 is connected to the HO pin. The input of inverter NOT6 is connected to the output of Schmitt trigger ST2, and its output is connected to the input of inverter NOT7. The output of inverter NOT7 is connected to the LO pin.

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