A DMA control system suitable for on-chip network architecture chips

Abstract

The present invention relates to the field of integrated circuit chip design, and in particular to a DMA control system suitable for an on-chip network architecture chip. The system includes a central processing unit module as a core processor, a central processing unit configuration module for configuring PL terminal register parameters, an interrupt management module, a data management module for managing data, a data channel arbitration module for establishing a data transmission channel, an on-chip network architecture chip writing module for writing data to the on-chip network architecture chip, an on-chip network architecture chip output data unpacking module for receiving data output by the on-chip network architecture chip for unpacking and shunting, and a small data processing module for storing and processing data output by the on-chip network architecture chip whose length does not exceed a threshold. The present invention can achieve high-efficiency data interaction between the on-chip network architecture chip and the FPGA chip by optimizing the data transmission channel and the data caching strategy, thereby greatly improving the overall efficiency of the system.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit chip design, and in particular to a DMA control system suitable for an on-chip network architecture chip. Background Art

[0002] The on-chip network is a technology that uses the idea of ​​interconnected networks to design complex on-chip systems, which is used to achieve IP (intellectual property) core interconnection and communication. However, with the development of semiconductor technology, the complexity and integration of on-chip systems have continued to increase, and the traditional bus communication architecture can no longer meet its communication needs. In this case, the on-chip network architecture came into being and became the preferred solution for achieving on-chip multi-core communication. Since the DMA (direct memory access) control system does not require the intervention of the CPU (central processing unit) to complete the access to the memory, the efficiency of data transmission is improved. This technology has a wide range of applications in communications, computers, high-performance computing, embedded systems and other fields, and plays an important role in improving the comprehensive performance and response speed of the processor.

[0003] At present, in order to achieve efficient data interaction between the on-chip network architecture chip and the FPGA chip, a DMA control system based on FPGA can be used. This system uses the parallel processing capability and flexibility of FPGA to quickly and efficiently transmit data after the CPU initializes the task information configuration of the DMA control system.

[0004] However, current FPGA-based DMA control systems have limited data scheduling and management capabilities, which reduces the overall efficiency of the system. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a DMA control system suitable for a network-on-chip architecture chip.

[0006] The system includes:

[0007] The central processing unit module is used to execute programs, manage system resources, and control the work of other modules. When reading or sending data to the on-chip network architecture chip, the central processing unit module sends instructions to the central processing unit configuration module to match the data sender with the data receiver, establish a data transmission channel, and determine whether the data reading is completed based on the interrupt signal of the interrupt management module;

[0008] The CPU configuration module is used to configure the parameters of the PL-side registers and send instructions through the CPU module to achieve control and information interaction with the specified module on the PL side;

[0009] The interrupt management module is used to manage the interrupts sent by the PL end to the central processing unit module;

[0010] A data management module is used to store data required for the operation of the on-chip network architecture chip and the data output by the on-chip network architecture chip, and provide an access interface for controlling the stored data;

[0011] A data channel arbitration module is used to match a data receiver's read data request with a data sender's write data request, so that the data sender and the data receiver establish a data transmission channel;

[0012] The on-chip network architecture chip writing module sends a read request to the data channel arbitration module according to the instruction of the central processor configuration module, and writes data to the on-chip network architecture chip after establishing a data transmission channel with the data sender;

[0013] The on-chip network architecture chip output data unpacking module is used to receive the data packets or network interface information packets output by the on-chip network architecture chip, unpack them and then split them;

[0014] A small data processing module is used to store and process data output by the on-chip network architecture chip whose data length does not exceed a threshold.

[0015] Furthermore, the data management module includes:

[0016] The PS-side data management module is used to store the data required for the operation of the on-chip network architecture chip in the DDR of the PS-side and control its read and write operations;

[0017] The PL-side data management module is used to store data whose length exceeds a threshold value output by the on-chip network architecture chip in the DDR of the PL-side and control its read and write operations;

[0018] Furthermore, the PS end data management module includes:

[0019] PSDDR, used to store data required for the operation of the on-chip network architecture chip;

[0020] PSDDR controller, used to manage and control the data read and write operations of PSDDR;

[0021] MM2S PS, according to the instruction of the CPU configuration module, sends a write request to the data channel arbitration module as the data sending direction, establishes a data transmission channel with the data receiver, and then reads data from PSDDR through PSDDR controller for transmission;

[0022] S2MM PS, according to the instruction of the CPU configuration module, sends a read request to the data channel arbitration module as the data receiving direction, establishes a data transmission channel with the data sender, and writes data to PSDDR through the PSDDR controller.

[0023] Furthermore, the PL-side data management module includes:

[0024] PL DDR, used to store data whose length exceeds the threshold output by the on-chip network architecture chip;

[0025] PL DDR controller, used to manage and control the data read and write operations of PL DDR;

[0026] MM2S PL, according to the instructions of the CPU configuration module, sends a write request to the data channel arbitration module as the data sender, establishes a data transmission channel with the data receiver, and then reads data from the PL DDR through the PL DDR controller for transmission;

[0027] S2MM PL, according to the instructions of the CPU configuration module, sends a read request to the data channel arbitration module as the data receiving direction, establishes a data transmission channel with the data sender, and then writes data to the PL DDR through the PL DDR controller.

[0028] Furthermore, the small data processing module includes:

[0029] Bram, used to cache the data whose length does not exceed the threshold after decompression output by the on-chip network architecture chip;

[0030] Read Result, according to the instructions of the CPU configuration module, sends a write request to the data channel arbitration module, establishes a data transmission channel with the data receiver, and then reads the data stored in Bram for transmission.

[0031] Further, the network interface information packet message fields transmitted in the system include: node address, type, storage unit address, length, command;

[0032] Node address: indicates the address of a destination node in the on-chip network architecture chip;

[0033] Type: indicates the type of data packet, which includes data, control and synchronization.

[0034] Storage unit address: indicates the address of a storage unit inside a node;

[0035] Length: indicates the size of the network interface information packet;

[0036] Command: Indicates the command content carried by the network interface information packet.

[0037] Furthermore, the data sender and the data receiver are determined by a central processing unit module according to the data transmission direction, data type and data length.

[0038] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0039] The present invention provides a DMA control system suitable for an on-chip network architecture chip. The system improves the data scheduling and management capabilities by optimizing data transmission channels and data caching strategies, and can achieve efficient data interaction between the on-chip network architecture chip and the FPGA chip, greatly improving the overall efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A hierarchical diagram of the DMA control system architecture provided by an embodiment of the present invention;

[0041] Figure 2 A module diagram of a DMA control system provided by an embodiment of the present invention;

[0042] Figure 3 The message format of the network interface information packet of the network-on-chip architecture chip provided in the embodiment of the present invention. DETAILED DESCRIPTION

[0043] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. Before describing in detail the technical solutions of each embodiment of the present invention, the nouns and terms involved are explained. In this specification, components with the same name or the same number represent similar or identical structures and are only for illustrative purposes.

[0044] Some terms in this invention are explained as follows:

[0045] ARM: The full name is Advanced RISC Machine, which is a processor architecture. The ARM architecture uses a simple and efficient instruction set to execute and is committed to improving processor performance and efficiency.

[0046] FPGA: The full name is Field Programmable Gate Array. Unlike fixed-function integrated circuits, FPGA allows users to configure its internal logic gates and connections through programming to achieve specific digital circuit functions.

[0047] DMA: The full name is Direct Memory Access, which means that memory can be accessed without CPU intervention, thereby improving data transfer rate and system efficiency.

[0048] PS side: The full name is Processing System, which is the part of the SOC related to the ARM core processor, used to handle routine software computing tasks and peripheral interactions.

[0049] PL side: The full name is Programmable Logic, which includes programmable logic units and programmable input and output resources. The PL side works together with the PS side to provide flexibility and reconfigurability for the system.

[0050] API library: The full name is Application Programming Interface library, which is a collection of predefined functions and routines. The purpose of the API library is to provide developers with a standardized interface so that they can easily integrate existing functions without having to deeply understand the underlying implementation details.

[0051] DDR: The full name is Double Data Rate, which means double data transfer. It is a memory technology used to increase the data transfer rate of memory modules. In this article, DDR refers to the memory that uses this technology.

[0052] The present invention proposes a DMA control system suitable for a network-on-chip architecture chip, which is constructed based on a chip integrating an FPGA and an ARM core processor.

[0053] The DMA control system can be divided into four layers according to the hierarchical structure of the system architecture, such as Figure 1 As shown. The top layer is the user application layer, which is responsible for the main functions and logic that users need to implement; the second layer is the client driver layer, which provides an API library for the user application layer to call. It is mainly divided into two aspects. The first control module controls the execution of the hardware system by transmitting control parameters, and the second data transmission module transmits the data to be processed to the hardware system, so that the hardware system can realize the corresponding functions; the third layer is the kernel driver layer, which is the main logic layer of the driver hardware, realizing the registration of hardware devices, memory allocation mapping, hardware system register configuration, and equipped with an interrupt system and an exception handling system to monitor hardware feedback information and process it, so as to realize the driving and control of the underlying hardware. Except for modifying the underlying FPGA end logic, it generally does not need to be modified; the bottom layer is the hardware system, including FPGA and on-chip network architecture chip. Among the four layers, only the user application layer and the client driver layer are visible to the user.

[0054] In order to realize the driving and control of each hardware module, the present invention provides a set of configurable, customizable and expandable software system API library as the software part, including a control module and a data transmission module. These two software modules can be selectively called by the upper-level application to realize the corresponding functions.

[0055] The control driver module is used to send network interface information packets and obtain the underlying hardware status, such as initializing the status of the on-chip network architecture chip, configuring task parameters and execution flow, starting the chip to execute tasks, and obtaining the execution status of different tasks.

[0056] The data transmission driver module is used to transmit data, such as transmitting the data to be processed to the on-chip network architecture chip.

[0057] 1.DMA control system module

[0058] like Figure 2 As shown, the DMA control system is divided into the following modules according to module functions:

[0059] 1. Central Processing Unit Module, i.e. Figure 2 The ARM in the system is the control center of the entire system, responsible for executing programs, managing system resources, and controlling the work of other modules. When reading or sending data to the on-chip network architecture chip, the CPU module sends instructions to the CPU configuration module to match the data sender and the data receiver, establish a data transmission channel, and determine whether the data reading is completed based on the interrupt signal of the interrupt management module. The data sender and the data receiver are determined by the CPU module based on the data transmission direction, data type, and data length.

[0060] 2.CPU configuration module, i.e. Figure 2 Config in is used to configure the parameters of the PL-side registers and send instructions through the ARM core processor to achieve control and information interaction with the specified module on the PL side.

[0061] 3. Interrupt management module, that is Figure 2 IRQ Manage in is used to manage the interrupts sent by the PL to the central processing unit module, so that the ARM core processor can grasp the working status of each module.

[0062] 4. Data channel arbitration module, that is Figure 2 The Connect in the data receiving side is used to match the data reading request of the data sending side with the data writing request of the data sending side, so that the data sending side and the data receiving side can establish a data transmission channel.

[0063] 5. PS-side data management module, used to store the data required for the operation of the on-chip network architecture chip in the DDR of the PS side and control its read and write operations. The PS-side data management module includes the following sub-modules:

[0064] PSDDR: DDR connected to the PS end, its function is to store data.

[0065] PSDDR controller: used to manage and control the data read and write operations of PSDDR, including providing a standard interface for PSDDR; optimizing the performance of PSDDR memory, improving the speed of data read and write, and reducing latency through reasonable data read and write strategies; and error handling.

[0066] MM2S PS: The logic module that reads data from PSDDR, sends a write request to the data channel arbitration module as the data sending direction according to the instructions of the CPU configuration module, establishes a data transmission channel with the data receiver, and then reads data from PSDDR for transmission through the PSDDR controller.

[0067] S2MM PS: The logic module that writes data into the DDR on the PS side. It sends a read request to the data channel arbitration module as the data receiving direction according to the instructions of the CPU configuration module. After establishing a data transmission channel with the data sender, it writes data into the PSDDR through the PSDDR controller.

[0068] 6. PL-side data management module is used to store large amounts of data. That is, when the data length output by the on-chip network architecture chip exceeds the threshold, all output data will be stored in the DDR of the PL side and its read and write operations will be controlled. The PL-side data management module includes the following submodules:

[0069] PL DDR: DDR connected to the PL end is used to store large amounts of data output by the on-chip network architecture chip.

[0070] PL DDR controller: used to manage and control the data read and write operations of PL DDR, including providing a standard interface for PLDDR; optimizing the performance of PL DDR memory, improving the speed of data read and write, and reducing latency through reasonable data read and write strategies; and error handling.

[0071] MM2S PL: The logic module that reads data from PL DDR. According to the instructions of the CPU configuration module, it sends a write request to the data channel arbitration module as the data sender. After establishing a data transmission channel with the data receiver, it reads data from PL DDR for transmission through PL DDR controller.

[0072] S2MM PL: The logic module that writes data into PL DDR. According to the instructions of the CPU configuration module, it sends a read request to the data channel arbitration module as the data receiving direction. After establishing a data transmission channel with the data sender, it writes data into PL DDR through the PL DDR controller.

[0073] 7.On-chip network architecture chip writing module, that is Figure 2 Req Data in the module is used to send data packets and network interface information packets to the on-chip network architecture chip. Req Data sends a read request to the data channel arbitration module as the data receiving direction according to the instructions of the central processor configuration module. After establishing a data transmission channel with the data sender, it writes data to the on-chip network architecture chip. The types of written data include data packets and network interface information packets.

[0074] 8. On-chip network architecture chip output data unpacking module, that is Figure 2 The Resp Data in it is used to receive the data packets or network interface information packets output by the on-chip network architecture chip, unpack them and then divert them.

[0075] 9. A small data processing module is used to store and process a small amount of data. That is, when the length of the data output by the on-chip network architecture chip does not exceed the threshold, the data will be cached in Bram first. The small data processing module includes the following sub-modules:

[0076] Bram: It is used to cache the data whose length does not exceed the threshold after decompression output by the on-chip network architecture chip.

[0077] Read Result: According to the instructions of the CPU configuration module, the data channel arbitration module sends a write request as the data sending direction, establishes a data transmission channel with the data receiving party, and then reads the data stored in Bram for transmission.

[0078] 2. DMA control system workflow

[0079] Combination Figure 2 The specific working process of the DMA control system provided by the present invention is explained as follows:

[0080] The ARM core processor first starts the DMA read data function in the data transmission driver to transfer the data packet from PSDDR to the on-chip network architecture chip. The steps are as follows: the ARM core processor configures the read data instruction containing the read PSDDR first address and burst length information to the Config module through the S_AXIL bus. The Config module outputs the read data instruction sent by ARM to the MM2S PS module. The MM2S PS module reads data from PSDDR through the PSDDR controller according to the instruction. The ARM core processor configures the MM2S PS module and the Req Data module through the Config module. The MM2S PS module generates a write request as the data sender, and the Req Data module generates a read request as the data receiver. The Connect module matches the read request of the data receiver with the write request of the data sender. The write request of the MM2S PS module matches the read request of the Req Data module. The MM2S PS module and the Req Data module will establish a data transmission channel, and the data packet will be written into the on-chip network architecture chip through the Req Data module. When all the data packets are written into the on-chip network architecture chip, the IRQ Manage interrupt management module will send an interrupt vector to the ARM core processor, indicating that the DMA read data process is completed.

[0081] The ARM core processor also needs to start the control driver to transmit the network interface information packet to the on-chip network architecture chip. The message format of the network interface information packet is as follows: Figure 3 As shown, the network interface information packet consists of five parts: node address, type, storage unit address, length, and command.

[0082] Node address: represents the address of a destination node of the on-chip network architecture chip. The on-chip network architecture chip is composed of several nodes, and each node corresponds to an address.

[0083] Type: indicates the type of data packet, which includes data (data), control (ctrl), and synchronization (sync). For data type data packets, the on-chip network architecture chip will convert the data packets into multi-segment packets for transmission. For sync and ctrl types of data packets, the on-chip network architecture chip will convert the data packets into single-segment packets for transmission.

[0084] Storage unit address: represents the address of a storage unit inside a node. There are many storage units inside each node, and each storage unit corresponds to an address.

[0085] Length: Indicates the size of the network interface information packet, in bytes.

[0086] Command: Indicates the command content carried by the network interface information packet, such as start command, stop command, read command, write command, refresh command, etc.

[0087] The format of the network interface information packet is determined according to the on-chip network architecture chip. The DMA system of the present invention can generate different network interface information packets by changing the control drive of the ARM core processor to meet the requirements of the on-chip network architecture chip.

[0088] When the on-chip network architecture chip receives data packets and network interface information packets, it will output some data packets and network interface information packets. The ARM core processor will start the DMA write data function in the data transmission driver to transfer the data from the on-chip network architecture chip to PSDDR or PL DDR. These data will first be unpacked by a Resp Data module. The RespData module will select different paths to store data according to the size of the returned data packet. The specific situation is as follows:

[0089] When the length of the returned data does not exceed the threshold, the returned data will be cached in the Bram module first, and then the ARM core processor will configure the Read Result module and the S2MM PS module through the Config module. The Read Result module generates a write request as the data sender, and the S2MM PS module generates a read request as the data receiver. After the Connect module matches the write request of the Read Result module and the read request of the S2MM PS module, the Read Result module and the S2MM PS module will establish a data transmission channel. The Read Result module reads the data stored in the Bram module and transmits it to the S2MM PS module. The S2MM PS module writes the data to the PSDDR module through the PSDDR controller and waits for post-processing operations on the PS side.

[0090] When the length of the returned data exceeds the threshold, a PL DDR module needs to be added to store the data. At this time, the data will be directly written into the PL DDR through the S2MM PL module via a high-priority channel. When the ARM core processor needs to process the data in the PLDDR, the ARM core processor will configure the MM2S PL module and the S2MM PS module through the Config module. The MM2S PL module generates a write request as the data sender, and the S2MM PS module generates a read request as the data receiver. The Connect module matches the write request of the MM2S PL module and the read request of the S2MM PS module. The MM2S PL module and the S2MM PS module will establish a data transmission channel. The MM2S PL module reads data from the PL DDR and transmits it to the S2MM PS module through the PL DDR controller. The S2MM PS module writes data to the PSDDR through the PSDDR controller. In this way, the data in the PL DDR module will be transmitted to the PSDDR module, waiting for post-processing operations on the PS side.

[0091] When all data packets are written from the chip of the on-chip network architecture to the DDR, the IRQ Manage interrupt management module will send an interrupt vector to the ARM core processor, indicating that the DMA data writing process is completed. The ARM core processor also needs to start the control driver to obtain the underlying hardware status, such as the working status of the nodes in the on-chip network architecture chip.

[0092] The above-described embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A DMA control system suitable for a network-on-chip architecture chip, characterized in that: include: The CPU module is used to execute programs, manage system resources, and control the work of other modules; When reading or sending data to the on-chip network architecture chip, the CPU module sends instructions to the CPU configuration module to match the data sender with the data receiver, establish a data transmission channel, and determine whether the data reading is completed based on the interrupt signal of the interrupt management module; The CPU configuration module is used to configure the parameters of the PL-side registers, receive instructions sent by the CPU module, and realize control and information interaction with the specified module on the PL side; The interrupt management module is used to manage the interrupts sent by the PL end to the central processing unit module; A data management module is used to store data required for the operation of the on-chip network architecture chip and the data output by the on-chip network architecture chip, and provide an access interface for controlling the stored data; A data channel arbitration module is used to match a data receiver's read data request with a data sender's write data request, so that the data sender and the data receiver establish a data transmission channel; The on-chip network architecture chip writing module sends a read request to the data channel arbitration module according to the instruction of the central processor configuration module, and writes data to the on-chip network architecture chip after establishing a data transmission channel with the data sender; The on-chip network architecture chip output data unpacking module is used to receive the data packets or network interface information packets output by the on-chip network architecture chip, unpack them and then distribute them; A small data processing module is used to store and process data output by the on-chip network architecture chip whose data length does not exceed a threshold.

2. A DMA control system suitable for a network-on-chip architecture chip according to claim 1, characterized in that: The data management module comprises: The PS-side data management module is used to store the data required for the operation of the on-chip network architecture chip in the DDR of the PS-side and control its read and write operations; The PL-side data management module is used to store data whose length exceeds a threshold value output by the on-chip network architecture chip in the DDR of the PL side and control its read and write operations.

3. A DMA control system suitable for a network-on-chip architecture chip according to claim 2, characterized in that: The PS end data management module includes: PSDDR, used to store data required for the operation of the on-chip network architecture chip; PSDDR controller, used to manage and control the data read and write operations of PSDDR; MM2S PS, according to the instruction of the CPU configuration module, sends a write request to the data channel arbitration module as the data sending direction, establishes a data transmission channel with the data receiver, and then reads data from PSDDR through PSDDR controller for transmission; S2MM PS, according to the instruction of the CPU configuration module, sends a read request to the data channel arbitration module as the data receiving direction, establishes a data transmission channel with the data sender, and writes data to PSDDR through the PSDDR controller.

4. A DMA control system suitable for a network-on-chip architecture chip according to claim 2, characterized in that: The PL end data management module includes: PL DDR, used to store data whose length exceeds the threshold output by the on-chip network architecture chip; PL DDR controller, used to manage and control the data read and write operations of PL DDR; MM2S PL, according to the instructions of the CPU configuration module, sends a write request to the data channel arbitration module as the data sender, establishes a data transmission channel with the data receiver, and then reads data from the PL DDR through the PL DDR controller for transmission; S2MM PL, according to the instructions of the CPU configuration module, sends a read request to the data channel arbitration module as the data receiving direction, establishes a data transmission channel with the data sender, and then writes data to the PL DDR through the PL DDR controller.

5. A DMA control system suitable for a network-on-chip architecture chip according to claim 1, characterized in that: The small data processing module comprises: Bram, used to cache the data whose length does not exceed the threshold after decompression output by the on-chip network architecture chip; Read Result, according to the instructions of the CPU configuration module, sends a write request to the data channel arbitration module, establishes a data transmission channel with the data receiver, and then reads the data stored in Bram for transmission.

6. A DMA control system suitable for a network-on-chip architecture chip according to claim 1, characterized in that: The network interface information packet message fields transmitted in the system include: node address, type, storage unit address, length, and command; Node address: indicates the address of a destination node in the on-chip network architecture chip; Type: indicates the type of data packet, which includes data, control and synchronization. Storage unit address: indicates the address of a storage unit inside a node; Length: indicates the size of the network interface information packet; Command: Indicates the command content carried by the network interface information packet.

7. A DMA control system suitable for a network-on-chip architecture chip according to claim 1, characterized in that: The data sender and the data receiver are determined by the central processing unit module according to the data transmission direction, data type and data length.

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