A trench MOSFET device with a junction-controlled diode and a method for manufacturing the same

Abstract

The present invention provides a trench MOSFET device with a junction-controlled diode and a preparation method thereof, belonging to the technical field of semiconductor devices. The device includes a drain, a substrate, an epitaxial layer, and a source which are stacked in sequence from bottom to top; a P-well region and a source N+ region are arranged on the surface of the epitaxial layer, and the P-well region is located below the source N+ region; source trenches and gate trenches in a multi-stage stepped shape are also arranged in the epitaxial layer. A gate dielectric layer is deposited on the inner wall of the gate trench, and a first filling medium is filled inside it as the gate. An interlayer dielectric layer for separating the gate and the source is covered at the opening of the gate trench. A source dielectric layer is deposited on the inner wall of the source trench, and a second filling medium is filled inside it. Source P+ regions are arranged on the side wall and the bottom of the source trench. An ohmic contact metal layer is arranged between the source N+ region and the source. The device structure can significantly reduce the gate trench corner electric field, improve the reverse freewheeling ability of the device, and reduce the switching loss.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a trench MOSFET device with a junction-controlled diode and a preparation method thereof. Background Art

[0002] SiC and GaN are the third-generation wide bandgap semiconductor materials, which have more advantages than Si in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. Power devices prepared with wide bandgap semiconductor materials, such as diodes, transistors, and power modules, have more excellent electrical characteristics, can overcome the defects that silicon-based devices cannot meet the application requirements of high power, high voltage, high frequency, high temperature, etc., and are also one of the breakthrough paths that can transcend Moore's Law. Therefore, they are widely used in the new energy field, for example, in fields such as photovoltaic, energy storage, charging piles, and electric vehicles.

[0003] Ultra-wide bandgap semiconductor materials with a bandgap width greater than that of SiC and GaN mainly include gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), etc. Ultra-wide bandgap semiconductor materials can be applied to more extreme and harsh environments due to their superior optical and electrical properties. For example, in the context of geothermal energy production and oil and gas extraction, higher drilling speeds and lower failure rates can be achieved, enabling higher operating temperatures for electronic sensor-controlled aluminum plants, steel plants, and coal-fired and gas-fired power plants, thereby improving the energy utilization efficiency of these industrial processes.

[0004] However, there are still several problems in the actual manufacturing process and application of trench MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) prepared with wide bandgap semiconductor materials: (1) The high electric field in the material drift region results in a very high electric field on the gate dielectric layer, and this problem is exacerbated at the trench corners, thus causing the gate dielectric layer to break down rapidly under high drain voltages; poor tolerance to electrostatic effects in harsh environments and high voltage spikes in the circuit; (2) The parasitic body diode has a minority carrier storage effect and a long reverse recovery time, increasing the switching loss. Summary of the Invention

[0005] In order to solve at least one of the above problems, the present invention provides a trench MOSFET device with a junction-controlled diode. The device is provided with multi-level stepped source trenches, source P+ regions are arranged on the side walls of the multi-level trenches, and a source ohmic contact region is also provided. The structure of the multi-level trenches can make the source P+ regions have a deeper masking effect, significantly reducing the gate trench corner electric field; the unipolar junction-controlled diode integrated by the source P+ regions and the source ohmic contact region can significantly reduce the switching loss.

[0006] Specifically, the present invention adopts the following technical solutions to achieve the above object:

[0007] A trench MOSFET device with a junction-controlled diode, which includes a drain, a substrate, an epitaxial layer, and a source stacked in sequence from bottom to top; a P-well region and a source N+ region are provided in the surface layer on the side of the epitaxial layer facing away from the substrate, and the P-well region is located below the source N+ region; a plurality of gate trenches and a plurality of source trenches are provided in the epitaxial layer; a gate dielectric layer is deposited on the inner wall of each gate trench, and a first filling medium is filled inside as a gate; an interlayer dielectric layer for separating the gate and the source is covered at the opening of each gate trench; each source trench is a multi-stage trench in a stepped shape, and the number of steps n≥2 and n is an integer; the side wall and the bottom of each source trench are formed with a source P+ region by ion implantation; a source dielectric layer is deposited on the inner wall of each source trench, and a second filling medium is filled inside; an ohmic contact metal layer is provided between the source N+ region and the source.

[0008] In a preferred embodiment, the P-well region covers the surface layer on the side of the epitaxial layer facing away from the substrate, the material of the source dielectric layer is the metal of the ohmic contact metal layer, at least one side wall of at least one sub-trench of at least one source trench is not completely shielded by the source P+ region, and an N+ current guiding region is provided in the unshielded region. The source P+ region, the N+ current guiding region, and the source dielectric layer form at least one junction barrier-controlled unipolar diode at the corner of the step of the source trench.

[0009] In a further preferred embodiment, the N+ current guiding region is formed directly below the source P+ region at the bottom of each source trench.

[0010] In a preferred embodiment, the gate trench is a long strip structure, and along the extending direction of the gate trench, the source trenches are arranged at intervals; along the direction from the source to the drain, the P-well region is provided in the surface layer on one side of the epitaxial layer, and at least one source trench is provided in the region on the other side of the epitaxial layer where the P-well region is not provided. That is, in the surface layer on the side of the epitaxial layer facing away from the substrate, in the direction from the source to the drain, the P-well region is only provided on one side of the epitaxial layer, and the P-well region is not provided on the other side; in the region where the P-well region is not provided, at least one source trench is provided. Therefore, there is no P-well region between this source trench and its adjacent source trench. Therefore, in the region where the P-well region is not provided, the source P+ regions on the side walls of two adjacent source trenches, the source N+ region between two adjacent source trenches, and the ohmic contact metal layer form a junction barrier-controlled unipolar planar diode.

[0011] In a further preferred embodiment, the material of the source dielectric layer is the metal of the ohmic contact metal layer. At least one sidewall of at least one sub-groove of at least one source trench is not completely shielded by the source P+ region, and an N+ current guiding region is provided in the unshielded region. In this solution, in the direction along the gate trench, the P-well region is only provided in the epitaxial layer near one end of the gate trench, and the P-well region is not provided in the epitaxial layer near the other end of the gate trench. Since multiple source trenches are arranged at intervals in sequence and source P+ regions are provided on the sidewalls of adjacent two source trenches, therefore, in the region without the P-well region, the source P+ regions on the sidewalls of adjacent two source trenches, the source N+ region between adjacent two source trenches, and the ohmic contact metal layer form a unipolar planar diode controlled by a junction barrier. In the direction from the source to the drain, since at least one sidewall of at least one sub-groove of at least one source trench is not completely shielded by the source P+ region, an N+ current guiding region is provided in the unshielded region, and the material of the source dielectric layer is metal, therefore, the N+ current guiding region is located between adjacent two source P+ regions on the sidewall of the same source trench, and the source P+ region, the N+ current guiding region, and the source dielectric layer form at least one unipolar diode controlled by a junction barrier at the corner of the step of the source trench.

[0012] In a preferred embodiment, the gate trenches and the source trenches are arranged alternately in the direction along the gate width.

[0013] In a further preferred embodiment, the number and shape of the source trenches on both sides of the gate trench are the same, and the source trenches are symmetrically distributed on both sides of the gate trench.

[0014] In a preferred embodiment, the gate trenches are arranged in a grid pattern, the source trenches are arranged in each grid, and the shape of the grid is a polygon or a circle.

[0015] In a preferred embodiment, the first filling medium is polysilicon; and / or the second filling medium is a source metal or polysilicon or an insulating material.

[0016] In a preferred embodiment, the substrate is at least one of a silicon carbide, gallium oxide, diamond, and aluminum nitride substrate.

[0017] The present invention also provides a method for manufacturing the trench MOSFET device with a junction-controlled diode, including the following steps:

[0018] Growing an epitaxial layer on the substrate, and sequentially forming a P-well region and a source N+ region by ion implantation on the epitaxial layer;

[0019] Etching gate trenches and source trenches in the epitaxial layer;

[0020] A source P+ region is provided on the sidewall and bottom of the source trench;

[0021] A gate dielectric layer is deposited along the wall in the gate trench and a first filling medium is filled therein; an interlayer dielectric layer is deposited, the interlayer dielectric layer at the top of the gate trench is reserved, and the interlayer dielectric layer in the remaining regions is etched away; a source dielectric layer is deposited along the wall in the source trench and a second filling medium is filled therein; an ohmic contact metal layer is deposited on the surface of the source N+ region facing away from the epitaxial layer;

[0022] Finally, a source metal and a drain metal are deposited to obtain a source and a drain respectively.

[0023] In a preferred embodiment, the source P+ region is formed by ion implantation or secondary epitaxy or by growing a P-type oxide.

[0024] In a preferred embodiment, the source P+ region is formed by ion implantation, the depth of the ion implantation is less than the height of the sidewall of each step of the source trench, and an N+ current guiding region is formed between two adjacent source P+ regions by ion implantation.

[0025] In a preferred embodiment, the material of the source dielectric layer is the same as that of the ohmic contact metal layer, and the obtained device structure is annealed at 950 - 1000 °C for 90 - 180 s.

[0026] The present invention has the following beneficial effects: (1) In the present invention, the source of the MOSFET device adopts a multi-level trench structure, and P+ source regions are arranged on the sidewalls and bottom of the trenches. The multi-level trench structure can enable the P+ source regions to have a deeper masking effect, significantly reducing the gate trench corner electric field. (2) In the present invention, a source ohmic contact region is formed between the ohmic contact metal layer of the MOSFET device and the source. The P+ source region, N+ source region and the ohmic contact metal layer form a unipolar planar diode with integrated junction barrier control. The on-state voltage drop of this unipolar planar diode will be lower than that of the body diode of the device, thereby shielding the conduction of the body diode. And since it is a unipolar device, there is no minority carrier storage effect, and thus the freewheeling ability of the device can be improved and the switching loss can be significantly reduced. (3) The present invention further controls the P+ source region to partially shield the sidewalls of the source trenches, and an N+ current guiding region is arranged in the unshielded sidewall region. An ohmic contact metal layer is also deposited on the inner wall of the source trenches, so that the P+ source region, N+ current guiding region and the ohmic contact metal layer on the inner wall of the source trenches form a unipolar diode with integrated junction barrier control at at least one step corner of the source trenches, further reducing the switching loss. (4) The Baliga figure of merit of the MOSFET device of the present invention is basically the same as that of the existing trench MOSFET, but the peak electric field is reduced by 59.0% compared with the existing device, and the reverse on-state voltage drop is also significantly lower than that of the existing device; the current flows out from the junction-controlled diode instead of the body diode. The device of the present invention belongs to a device with junction-controlled diode conduction, and the body diode is shielded. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. is a schematic diagram of one of the structures of the trench MOSFET device with a junction-controlled diode provided in Embodiment 1;

[0028] Figures 2 to 8 FIG. is a cross-sectional view ( Figure 1 cross-section A) of various device structures obtained during the preparation of the trench MOSFET device with a junction-controlled diode in Embodiment 2;

[0029] Figures 9 to 10 FIG. is a cross-sectional view ( Figure 1 cross-section A) of the device structure obtained during the preparation of the trench MOSFET device with a junction-controlled diode in Embodiment 3;

[0030] Figures 11 to 16 FIG. is a top view of the arrangement of the source trenches and gate trenches of the trench MOSFET device with a junction-controlled diode provided by the present invention;

[0031] Figures 17 to 19 FIG. is a schematic diagram of the other three structures of the trench MOSFET device with a junction-controlled diode provided in Embodiment 1;

[0032] Figure 20 Cross-section diagram of one of the structures of the trench MOSFET device with a junction-controlled diode provided for Example 1 (refer to Figure 1 cross-section A in

[0033] Figure 21 Cross-section diagram of one of the structures of the trench MOSFET device with a junction-controlled diode provided for Example 1, different from Figure 20 (refer to Figure 1 cross-section A in

[0034] Figure 22 Schematic diagram of the structure of the trench MOSFET device in the prior art;

[0035] Figure 23 Comparison diagram of the blocking characteristics between the MOSFET device prepared in Example 2 and the existing trench MOSFET;

[0036] Figure 24 Comparison diagram of the forward conduction characteristics between the MOSFET device prepared in Example 2 and the existing trench MOSFET;

[0037] Figure 25 Comparison diagram of the peak electric field distribution of the gate oxide layer when the devices break down between the MOSFET device prepared in Example 2 and the existing trench MOSFET;

[0038] Figure 26 Comparison diagram of the current curves when the devices conduct reversely between the MOSFET device prepared in Example 2 and the existing trench MOSFET;

[0039] Figure 27 Comparison diagram of the current distribution when the devices conduct reversely between the MOSFET device prepared in Example 2 and the existing trench MOSFET.

[0040] In the figure: 1. Substrate; 2. Epitaxial layer; 3. P-well region; 4. Source N+ region; 5. Gate trench; 6. Source trench; 7. Gate dielectric layer; 8. First filling medium; 9. Interlayer dielectric layer; 10. Source P+ region; 11. N+ current guiding region; 12. Source dielectric layer; 13. Second filling medium; 14. Drain; 15. Source; 16. Ohmic contact metal layer; 171. First ion implantation mask; 172. Second ion implantation mask; A. Cross-section. Detailed implementation manners

[0041] The following content describes the technical solution of the present invention clearly and completely in combination with embodiments, so that those skilled in the art can fully understand the present invention. Obviously, the described embodiments are only some preferred embodiments of the present invention, rather than all embodiments. Any equivalent transformation or substitution made to the following embodiments by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0042] The directional terms mentioned in the present invention, such as words like "from bottom to top", "on...", "bottom", etc., refer to the directions in the accompanying drawings of the specification. Therefore, the directional terms are for illustration only and not for limiting the present invention. In the present invention, unless otherwise clearly defined, expressions such as "on", "above", "over", and "upper surface" of the first feature with respect to the second feature mean that the first feature and the second feature can be in direct contact or in indirect contact through an intermediate medium; the first feature can be directly above or obliquely above the second feature, or simply means that the first feature is at a higher horizontal level than the second feature. Expressions such as "under", "below", "beneath", and "lower surface" of the first feature with respect to the second feature mean that the first feature and the second feature can be in direct contact or in indirect contact through an intermediate medium; the first feature can be directly below or obliquely below the second feature, or simply means that the first feature is at a lower horizontal level than the second feature. The ordinal numbers used in the present invention, such as "first", "second", etc., are only for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0043] Embodiment 1

[0044] As Figure 1 shown, this embodiment provides a trench MOSFET device with a junction-controlled diode, including a substrate 1, an epitaxial layer 2 epitaxially grown on the substrate 1, a drain 14 deposited on one surface of the substrate 1 facing away from the epitaxial layer 2, and a source 15. On the surface of the epitaxial layer 2 facing away from the substrate 1, a P-well region 3 and a source N+ region 4 are sequentially arranged. The P-well region 3 covers the entire surface layer of the epitaxial layer 2 and is located below the source N+ region 4. As Figure 1As shown in the middle cross-section A, gate trenches and source trenches are alternately arranged in the epitaxial layer 2. A gate dielectric layer 7 is deposited on the inner wall of the gate trench, and a first filling medium 8 (polycrystalline silicon in this embodiment) is filled therein as the gate. An interlayer dielectric layer 9 is provided at the opening of the gate trench to separate the gate from the source 15. The middle part of the interlayer dielectric layer 9 is in contact with the first filling medium 8, and both sides thereof are in contact with the gate dielectric layer 7. The source trench is stepped, and the number of steps n≥2 and n is an integer. Source P+ regions 10 are formed on the side walls and the bottom of the steps of the source trench by ion implantation. Along the direction from the source 15 to the drain 14, the depth of ion implantation is less than the height of each step. An N+ current guiding region 11 is formed between two adjacent source P+ regions 10 by ion implantation. Ohmic contact metal layers 16 are provided between the inner wall of the source trench, the source N+ region 4 and the source 15, and a second filling medium (source metal in this embodiment) is filled therein. The ohmic contact metal layer 16 on the inner wall of the source trench serves as the source dielectric layer. Both the source N+ region 4 and the source P+ region 10 form ohmic contacts with the ohmic contact metal layer 16. The source P+ region 10, the N+ current guiding region 11 and the ohmic contact metal layer (source dielectric layer) on the inner wall of the source trench form a junction barrier controlled unipolar diode at the corner of each step of the source trench.

[0045] It should be noted that, as Figure 11 shown, in this embodiment, the gate trench 5 is a complete long strip trench along the direction perpendicular to Figure 1 the upper cross-section A, the source trenches 6 are arranged at intervals along the direction perpendicular to Figure 1 the upper cross-section A, and the number and shape of the source trenches 6 on both sides of the gate trench 5 are the same, and the source trenches 6 are symmetrically distributed on both sides of the gate trench 5. In some other embodiments, as Figure 12 shown, the gate trench 5 is a complete long strip trench along the direction perpendicular to Figure 1 the upper cross-section A, the source trenches 6 are arranged at intervals along the direction perpendicular to Figure 1 the upper cross-section A, and the source trenches 6 are asymmetrically distributed on both sides of the gate trench 5. In some embodiments, as Figure 13 shown, the gate trench 5 is a complete long strip trench along the direction perpendicular to Figure 1 the upper cross-section A, the source trenches 6 are complete long strip trenches along the direction perpendicular to Figure 1 the upper cross-section A, and at least two source trenches 6 are provided between adjacent gate trenches 5. In some other embodiments, as Figures 14 to 16 shown, the gate trenches 5 are arranged in a grid pattern, and the source trenches 6 are distributed in each grid. The shape of each grid is a regular or irregular polygon, or the grid shape is circular.

[0046] As Figure 17 shown, in other embodiments, the gate trench is along the direction ofFigure 17 The direction perpendicular to the upper cross-section A is a complete strip-shaped structure or multiple strip-shaped structures arranged at intervals. In the surface layer of the epitaxial layer 2 facing away from the substrate 1, in the direction from the source electrode 15 to the drain electrode 14, a P-well region 3 is formed on one side of the epitaxial layer by ion implantation, and no P-well region 3 is provided on the other side of the epitaxial layer. Only the source N+ region 4 exists in the surface layer on the other side of the epitaxial layer 2. That is, the source N+ region 4 covers the entire surface layer of the epitaxial layer 2. In the epitaxial layer 2 below it, in the direction along the gate trench extension, in a part of the surface layer of the epitaxial layer 2, a P-well region 3 is provided, and in another part of the region, no P-well region 3 is provided. The source trenches are arranged at intervals in the direction perpendicular to Figure 17 the upper cross-section A (i.e., the direction of the gate trench extension). Therefore, in the epitaxial layer 2 where the P-well region 3 is provided, both the source N+ region 4 and the P-well region 3 exist around the source trench; in the epitaxial layer 2 where no P-well region 3 is provided, only the source N+ region 4 exists around the source trench. The source P+ region 10 is formed on the vertical sidewall of the step of the source trench and at the bottom of the trench by ion implantation, and the source P+ region 10 completely shields the sidewall of each sub-trench. An ohmic contact metal layer 16 is provided between the inner wall of the source trench, the source N+ region 4 and the source electrode 15 (i.e., at this time, the source dielectric layer is an ohmic metal contact layer), and the second filling medium 13 filled therein is polysilicon. Between two adjacent source trenches, the source P+ region 10, the source N+ region 4 and the ohmic contact metal layer 16 form a planar junction-controlled diode.

[0047] Further, with reference to Figure 17 and Figure 1 , the source P+ region 10 is formed on the sidewall of the step of the source trench and at the bottom of the trench by ion implantation. In the direction from the source electrode 15 to the drain electrode 14, the depth of ion implantation is less than the height of each step. An N+ current guiding region 11 is formed between two adjacent source P+ regions 10 by ion implantation. At this time, in addition to the fact that between two adjacent source trenches, the source P+ region 10, the source N+ region 4 and the ohmic contact metal layer 16 form a planar junction-controlled diode; the source P+ region 10, the N+ current guiding region 11 and the ohmic contact metal layer (source dielectric layer) on the inner wall of the source trench also form a unipolar diode controlled by a junction barrier at the corner of each step of the source trench.

[0048] When the ohmic contact metal layer 16 is deposited on the inner wall of the source trench and the second filling medium 13 filled therein is metal or polysilicon, the ohmic contact area of the device structure can be increased and the on-resistance can be reduced.

[0049] Such as Figure 18 、 19As shown, in some embodiments, in the surface layer of the epitaxial layer 2 facing away from the substrate 1, in the direction from the source 15 to the drain 14, a P-well region is formed on one side of the epitaxial layer by ion implantation. There is no P-well region on the other side of the epitaxial layer. At least one source trench is provided in the epitaxial layer without a P-well region. The source dielectric layer 12 deposited on the inner wall of the source trench is made of the same material as the gate dielectric layer 7. The second filling medium 13 filled inside the source trench is source metal or polysilicon. At this time, a multi-stage field plate can be formed to optimize the electric field distribution. Between two adjacent source trenches, the source P+ region 10, the source N+ region 4, and the ohmic contact metal layer 16 form a planar junction control diode.

[0050] As Figure 20 shown, in some embodiments, Figure 1 On cross-section A, the gate trenches are arranged at intervals in the left-to-right direction (the direction perpendicular to the source-to-drain direction on cross-section A or the so-called gate width direction). At least two source trenches are provided between two adjacent gate trenches. Along the direction perpendicular to cross-section A, the source trench is a complete elongated structure (see Figure 13 ) or multiple spaced-apart elongated structures. The P-well region 3 surrounds the gate trench. The material of the source dielectric layer on the inner sidewall of the source trench is the same as that of the ohmic contact metal layer 16, and the second filling medium inside the source trench is source metal. There is no P-well region in the epitaxial layer 2 between two adjacent source trenches. Therefore, along the gate width direction, between two adjacent source trenches, the source P+ region 10, the source N+ region 4, and the ohmic contact metal layer 16 integrate to form a planar junction control diode. Along the direction perpendicular to cross-section A, when the source trenches are multiple spaced-apart elongated structures, between two adjacent source trenches, the source P+ region 10, the source N+ region 4, and the ohmic contact metal layer 16 form a planar junction control diode.

[0051] As Figure 21 shown, in some embodiments, Figure 1 On cross-section A, the gate trenches are arranged at intervals in the left-to-right direction. At least two source trenches are provided between two adjacent gate trenches. The P-well region 3 surrounds the gate trench. The material of the source dielectric layer 12 on the inner sidewall of the source trench is the same as that of the gate dielectric layer 7, and the second filling medium inside the source trench is source metal. There is no P-well region in the epitaxial layer 2 between two adjacent source trenches. Therefore, along the gate width direction, between two adjacent source trenches, the source P+ region 10, the source N+ region 4, and the ohmic contact metal layer 16 integrate to form a planar junction control diode.

[0052] The above examples list the embodiments in which the inner sidewalls of each sub-groove of the source trench are completely shielded by the source P+ region 10 or partially shielded by the source P+ region 10. In some other embodiments, the depth of different-level sub-grooves of each source trench can also be adjusted so that the sidewalls of some sub-grooves in the same source trench are completely shielded by the source P+ region, and the sidewalls of the other sub-grooves are partially shielded by the source P+ region. An N+ current-guiding region is formed by ion implantation in the region on the sidewall of the sub-groove that is not shielded by the source P+ region, so that a unipolar diode controlled by a junction barrier is formed at the corners of some steps of each source trench, where the source P+ region, the N+ current-guiding region and the ohmic contact metal layer are involved.

[0053] Example 2

[0054] Taking Figure 1 cross-section A therein as an example for illustration, the present embodiment provides a preparation method of a trench MOSFET device with a junction-controlled diode, including the following steps:

[0055] S1. As Figure 2 shown, an epitaxial layer 2 is grown on a substrate 1, and a P-well region 3 is formed by ion implantation on the surface of the epitaxial layer 2 facing away from the substrate 1. Then, a source N+ region 4 is formed by ion implantation on the surface of the P-well region 3 facing away from the epitaxial layer 2. The material of the substrate 1 is silicon carbide (SiC).

[0056] S2. As Figure 3 shown, a gate trench 5 and a source trench 6 are formed by dry etching. The source trench 6 is a stepped multi-level trench, and the number of its steps n≥2 and is a positive integer. The sidewall heights of each level of trenches in the multi-level trench can be the same or different.

[0057] S3. As Figure 4 shown, a first ion implantation mask 171 is first formed by dry etching, and then a source P+ region 10 is formed on the sidewall and bottom of the source trench 6 by ion implantation. The depth of ion implantation on the sidewall is less than the height of the sidewall of each level of trench, so that all sidewalls of the source trench 6 are partially shielded by the source P+ region 10. Because there is lateral scattering during ion implantation and the ions will have lateral diffusion during the high-temperature activation process, the doped region will have lateral expansion.

[0058] S4. As Figure 5 shown, in Figure 4Deposit a second ion implantation mask 172 on the structure, and form sidewalls on the sidewalls of the source trench 6 by etching. By designing the width of the trench at the bottom of the source trench 6 and the thickness of the sidewalls, the second ion implantation mask 172 fills the trench at the bottom of the source trench 6. Form an N+ current guiding region 11 between two adjacent source P+ regions 10 by N-type ion implantation. Finally, remove the first ion implantation mask 171 and the second ion implantation mask 172 to obtain the structure as shown in Figure 6 shown.

[0059] S5. As shown in Figure 6 , 7 shown, grow a gate dielectric layer 7 and a first filling dielectric 8 in the gate trench 5 in sequence, then deposit an interlayer dielectric layer 9 on the surface of the obtained device structure, retain the interlayer dielectric layer 9 in contact with the gate dielectric layer 7 and the first filling dielectric 8, and etch away the interlayer dielectric layer 9 in the remaining regions. Deposit an ohmic contact metal layer 16 on the obtained device structure and anneal it at 1000 °C for 90 s to obtain the structure as shown in Figure 7 shown. At this time, the source dielectric layer is the ohmic contact metal layer 16. The material of the gate dielectric layer 7 is silicon dioxide. The first filling dielectric 8 is polysilicon. The material of the interlayer dielectric layer 9 is silicon dioxide. The material of the ohmic contact metal layer 16 is titanium.

[0060] S6. As shown in Figure 7 , 8 shown, deposit source metal on the surface of the Figure 7 structure to obtain the source 15. At this time, the second filling dielectric 13 filled in the source trench 6 is the source metal. Deposit drain metal on the surface of the side of the substrate 1 away from the epitaxial layer 2 to obtain the drain 14. The cross-sectional schematic diagram of the finally obtained device structure is as shown in Figure 8 shown.

[0061] It should be noted that, in step S3, the method of forming the source P+ region can also adopt the secondary epitaxy method or the method of growing P-type oxide in addition to the ion implantation method.

[0062] Embodiment 3

[0063] In this embodiment, a preparation method of a trench MOSFET device with a junction control diode is provided. This method is basically the same as that in Embodiment 2, except that:

[0064] S4. As shown in Figure 9 shown, in Figure 4A second ion implantation mask 172 is deposited on the structure, and sidewalls are formed on the sidewalls of the source trench 6 by etching. When the width of the trench at the bottom of the source trench 6 is greater than the sum of the thicknesses of the sidewalls on both sides, an N+ current guiding region 11 is formed between two adjacent source P+ regions 10 by N-type ion implantation. At the same time, an N+ current guiding region 11 is formed directly below the source P+ region 10 at the bottom of the source trench 6. Finally, the first ion implantation mask 171 and the second ion implantation mask 172 are removed to obtain the structure as shown in Figure 10 shown.

[0065] In step S5, annealing is performed at 950 °C for 180 s.

[0066] It should be noted that the material of the substrate 1 can also be a gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or aluminum nitride (AlN) substrate. The material of the gate dielectric layer 7 can also be hafnium oxide (HfO2). The material of the interlayer dielectric layer 9 can also be borophosphosilicate glass (BPSG) or silicon nitride (Si3N4). The material of the ohmic contact metal layer 16 can also be nickel (Ni) or aluminum (Al). Annealing the ohmic contact metal layer 16 at 950 - 1000 °C for 90 - 180 s can meet the requirements of device performance.

[0067] The preparation method of the MOSFET device with other structures in Example 1 is the same as that in Example 2 or 3, and will not be elaborated one by one. When the material of the source dielectric layer is the same as that of the gate dielectric layer in step S5, the source dielectric layer and the gate dielectric layer are deposited simultaneously, and the ohmic contact metal layer is deposited on the surface of the source N+ region facing away from the epitaxial layer.

[0068] Performance Test

[0069] The MOSFET device prepared in Example 2 is simulated and compared with an existing device (the trench MOSFET of Infineon, see Figure 22 ). The blocking characteristics and forward conduction characteristics are respectively as shown in Figure 23 and Figure 24 shown. It can be seen from the figure that although the breakdown voltage (BV) of the MOSFET structure prepared in Example 2 is slightly lower than that of the existing device, the specific on-resistance (R on,sp ) is also lower than that of the existing device. Through calculation, the Baliga figure of merit of the two is basically the same. The peak electric field distribution of the gate oxide layer when the device breaks down is as shown in Figure 25 shown, Figure 25 in the left figure is the existing device, and the right figure is the MOSFET prepared in Example 2. It can be seen from the figure that the peak electric field of the MOSFET device prepared in Example 2 is reduced by 59.0% compared with the existing device. The current curve and current distribution when the device conducts in the reverse direction are respectively as shown in Figure 26 and Figure 27 shown.Figure 27 The left figure in the middle is the existing device, and the right figure is the MOSFET device prepared in Example 2. From Figure 26 and Figure 27 it can be seen that the reverse conduction voltage drop (V F ) of this structure is significantly lower than that of the existing device, and the current flows out from the junction-controlled diode instead of the body diode, belonging to the conduction of the junction-controlled diode and the body diode being shielded, while it is obvious that the existing device conducts through the body diode.

[0070] The above are only the preferred embodiments of the present invention and are not used to limit the protection scope of the present invention. For any person skilled in the art, the present invention can have various changes and modifications. Any simple equivalent changes and modifications made according to the protection scope of the present invention application and the content of the specification shall be included in the protection scope of the present invention.

Claims

1. A trench MOSFET device with a junction-controlled diode, characterized in that, It includes a drain, a substrate, an epitaxial layer, and a source that are sequentially stacked from bottom to top; A P-well region and a source N+ region are provided in the surface layer on the side of the epitaxial layer facing away from the substrate, and the P-well region is located below the source N+ region; A plurality of gate trenches and a plurality of source trenches are provided in the epitaxial layer; A gate dielectric layer is deposited on the inner wall of each gate trench, and a first filling medium is filled therein as a gate; an interlayer dielectric layer for separating the gate and the source is covered at the opening of each gate trench; each source trench is a multi-stage trench in a stepped shape, the number of steps n≥2 and n is an integer; the side wall and the bottom of each source trench are formed with a source P+ region by ion implantation; a source dielectric layer is deposited on the inner wall of each source trench, and a second filling medium is filled therein; an ohmic contact metal layer is provided between the source N+ region and the source; The P-well region covers the surface layer on the side of the epitaxial layer facing away from the substrate, the material of the source dielectric layer is the metal of the ohmic contact metal layer, at least one side wall of at least one sub-trench of at least one source trench is not completely shielded by the source P+ region, and an N+ current guiding region is provided in the unshielded region.

2. The trench MOSFET device with a junction-controlled diode according to claim 1, wherein The N+ current guiding region is formed directly below the source P+ region at the bottom of each source trench.

3. The trench MOSFET device with a junction-controlled diode according to claim 1, wherein The gate trench is a long strip structure, and the source trenches are arranged at intervals along the extending direction of the gate trench; Along the direction from the source to the drain, the P-well region is provided in the surface layer on one side of the epitaxial layer, and at least one source trench is provided in the region on the other side of the epitaxial layer where the P-well region is not provided.

4. The trench MOSFET device with a junction-controlled diode according to claim 3, wherein, The material of the source dielectric layer is the metal of the ohmic contact metal layer, at least one side wall of at least one sub-trench of at least one source trench is not completely shielded by the source P+ region, and an N+ current guiding region is provided in the unshielded region.

5. The trench MOSFET device with a junction-controlled diode according to claim 1, characterized in that, The gate trenches and the source trenches are arranged alternately along the direction of the gate width.

6. The trench MOSFET device with a junction-controlled diode according to claim 5, characterized in that, The number and shape of the source trenches on both sides of the gate trench are the same, and the source trenches are symmetrically distributed on both sides of the gate trench.

7. The trench MOSFET device with a junction-controlled diode according to claim 1, wherein The gate trenches are arranged in a grid pattern, the source trenches are provided in each grid, and the shape of the grid is a polygon or a circle.

8. The trench MOSFET device with a junction-controlled diode according to claim 1, characterized in that, The first filling medium is polysilicon; and / or the second filling medium is source metal or polysilicon or insulating material.

9. The manufacturing method of the trench MOSFET device with a junction control diode according to any one of claims 1 to 8, characterized in that, It includes the following steps: Growing an epitaxial layer on a substrate, and sequentially forming a P-well region and a source N+ region on the epitaxial layer by ion implantation; Etching gate trenches and source trenches in the epitaxial layer; Providing a source P+ region on the side wall and the bottom of the source trench; Forming an N+ current guiding region by ion implantation between two adjacent source P+ regions; Depositing a gate dielectric layer along the wall in the gate trench and filling a first filling medium therein; depositing an interlayer dielectric layer, retaining the interlayer dielectric layer at the top of the gate trench, and etching away the interlayer dielectric layer in the remaining regions; Deposit a source dielectric layer along the wall inside the source trench and fill the inside thereof with a second filling medium; deposit an ohmic contact metal layer on the surface of the source N+ region facing away from the epitaxial layer; Finally, deposit source metal and drain metal to obtain a source and a drain respectively.

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