A high-order temperature-compensated bandgap reference circuit based on BCD technology

Abstract

This invention claims protection for a high-order temperature-compensated bandgap reference circuit based on BCD technology, comprising a bias circuit, a temperature compensation circuit, and a first-order bandgap reference circuit. This invention utilizes the difference between the base-emitter voltages of two NPN transistors and the base-emitter voltage of NPN transistor Q3 to generate positive and negative temperature coefficient currents across resistors R1 and R2, respectively, providing bias to the temperature compensation circuit. The invention uses the base-emitter voltages of NPN transistors Q7 and Q8, along with clamping technology from amplifier A1, to generate a first-order bandgap reference voltage. Furthermore, it employs linear loop technology and base-emitter clamping technology from NPN transistors Q4 and Q5 to generate a high-order temperature nonlinear current to compensate for the high-order temperature nonlinearity of the first-order bandgap reference voltage, improving the temperature drift performance of the bandgap reference voltage, thereby realizing a high-order temperature-compensated bandgap reference circuit based on BCD technology.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a high-order temperature-compensated bandgap reference circuit based on BCD technology. Background Technology

[0002] With the development of integrated circuit technology, more and more functional modules are integrated onto the same chip, which places increasingly higher demands on reference circuits. Bandgap reference circuits, which are insensitive to process technology, temperature, and power supply voltage, are widely used in integrated circuit systems to provide high-performance reference voltages.

[0003] Figure 1 This is a traditional bandgap reference circuit, mainly composed of an error amplifier A1, PMOS transistors M1, M2, and M3, resistors R1, R2, R3, and R4, and PNP transistors Q1 and Q2. PMOS transistors M1, M2, and M3 are identical. The emitter area of ​​PNP transistor Q1 is n times that of PNP transistor Q2. The circuit output voltage... Where R2 is the resistance of resistor R2, R3 is the resistance of resistor R3, R4 is the resistance of resistor R4, V T For thermal voltage, V EB1 This is the emitter-base voltage of the PNP transistor Q1. Regardless, this reference voltage V... REF As a first-order bandgap reference voltage, it has high temperature drift characteristics, which limits the application of bandgap reference circuits in high-performance systems. Summary of the Invention

[0004] This invention aims to solve the problems of the prior art mentioned above. It proposes a high-order temperature-compensated bandgap reference circuit based on BCD technology. The technical solution of this invention is as follows:

[0005] A high-order temperature-compensated bandgap reference circuit based on BCD technology includes: a bias circuit, a temperature compensation circuit, and a first-order bandgap reference circuit; wherein, the signal output terminal of the bias circuit is connected to the signal input terminal of the temperature compensation circuit, and the signal output terminal of the temperature compensation circuit is connected to the signal input terminal of the first-order bandgap reference circuit; the bias circuit provides a positive temperature coefficient current and a negative temperature coefficient current to the temperature compensation circuit, and the temperature compensation circuit generates a high-order temperature nonlinear current and compensates for the high-order temperature nonlinearity of the first-order bandgap reference voltage generated by the first-order bandgap reference circuit, thereby obtaining a bandgap reference voltage with low temperature drift characteristics.

[0006] Furthermore, the bias circuit includes: PMOS transistors MS1, MS2, MS3, MS4, MS5, MS6, MS7, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M18, NPN transistors Q1, Q2, Q3, R1, and R2, resistors R1 and R2, wherein the source of PMOS transistor MS1 is connected to P... The sources of MOSFET M1, PMOS transistors M2, M7, M9, and M10 are connected to the external power supply VDD. The gate of PMOS transistor MS1 is connected to the drain of PMOS transistor MS1 and the source of PMOS transistor MS2. The gate of PMOS transistor MS2 is connected to the drain of PMOS transistor MS2 and the source of PMOS transistor MS3. The gate of PMOS transistor MS3 is connected to the drain of PMOS transistor MS3, the gate of NMOS transistor MS6, the gate of NMOS transistor MS7, and the drain of NMOS transistor MS4. The source of NMOS transistor MS4 is connected to the drain of NMOS transistor MS5. The gate of PMOS transistor M1 is connected to the source of NMOS transistor MS6, the source of NMOS transistor MS7, the emitter of NPN transistor Q1, the emitter of NPN transistor Q2, the emitter of NPN transistor Q3, one end of resistor R2, the source of NMOS transistor M18, and the external ground GND. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M1, the gate of PMOS transistor M2, the gate of PMOS transistor M7, the gate of PMOS transistor M14, the drain of NMOS transistor MS6, and the source of PMOS transistor M3. The gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, the gate of PMOS transistor M4, the gate of PMOS transistor M8, the gate of PMOS transistor M15, and the gate of PMOS transistor M22. The drain of NMOS transistor M2 is connected to the drain of NMOS transistor M4, the source of NMOS transistor M5 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the collector and base of NPN transistor Q1. The drain of PMOS transistor M2 is connected to the source of PMOS transistor M4, the gate of NMOS transistor MS5, the gate of NMOS transistor M5, the gate of NMOS transistor M6, and the drain of NMOS transistor M6. The source of NMOS transistor M6 is connected to the collector and base of NPN transistor Q2. The drain of PMOS transistor M7 is connected to the source of PMOS transistor M8.The drain of PMOS transistor M8 is connected to the collector of NPN transistor Q3 and the gate of NMOS transistor M13. The gate of PMOS transistor M9 is connected to the drain of PMOS transistor M9, the gate of PMOS transistor M10, and the source of PMOS transistor M11. The gate of PMOS transistor M11 is connected to the drain of PMOS transistor M11, the gate of PMOS transistor M12, and the drain of NMOS transistor M13. The source of NMOS transistor M13 is connected to the base of NPN transistor Q3 and the other end of resistor R2. The drain of PMOS transistor M10 is connected to the source of PMOS transistor M12. The drain of PMOS transistor M12 is connected to the drain of NMOS transistor M18, the gate of NMOS transistor M18, and the gate of NMOS transistor M19.

[0007] Furthermore, in the bias circuit, PMOS transistors M1 and M2 are identical, PMOS transistors M3 and M4 are identical, and NMOS transistors M5 and M6 are identical. The emitter area of ​​NPN transistor Q1 is n times that of NPN transistor Q2, and the current I1 of PMOS transistor M1 has... Furthermore, it is a current with a positive temperature characteristic, where R1 is the resistance value of resistor R1, V T The thermal voltage is proportional to temperature; PMOS transistors M9 and M10 are identical, PMOS transistors M11 and M12 are identical, and the current I of NMOS transistor M18 is... 18 for Furthermore, it is a current with a negative temperature characteristic, where R2 is the resistance of resistor R2, V BE3 This is the base-emitter circuit for NPN transistor Q3.

[0008] Furthermore, the temperature compensation circuit includes: PMOS transistors M14, M15, M16, M17, M19, M20, M21, and M22; NPN transistors Q4, Q5, and Q6; and resistor R3. The source of PMOS transistor M14 is connected to the drain of NMOS transistor M17, the source of PMOS transistor M20, the source of PMOS transistor M21, and the external power supply VDD. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M16, the gate of NMOS transistor M16, and the gate of NMOS transistor M17. The source of M16 is connected to the collector of NPN transistor Q4, the base of NPN transistor Q4, and the base of NPN transistor Q5. The emitter of NPN transistor Q4 is connected to the emitter of NPN transistor Q5, the source of NMOS transistor M19, the emitter of NPN transistor Q6, and the external ground GND. The source of NMOS transistor M17 is connected to the collector of NPN transistor Q5, the base of NPN transistor Q6, and the drain of NMOS transistor M19. The gate of PMOS transistor M20 is connected to the drain of PMOS transistor M20, the gate of PMOS transistor M21, and the collector of NPN transistor Q6. The drain of PMOS transistor M21 is connected to the source of PMOS transistor M22. The drain of PMOS transistor M22 is connected to one end of resistor R3.

[0009] Furthermore, in the temperature compensation circuit, NMOS transistors M16 and M17, NPN transistors Q4 and Q5 form a linear loop. NMOS transistors M16 and M17 are identical. The emitter area of ​​NPN transistor Q4 is m times that of NPN transistor Q5. NPN transistor Q6 is identical to NPN transistor Q4. The current amplification of NPN transistors Q4, Q5, and Q6 is much greater than 1. The channel width-to-length ratio of PMOS transistor M14 is K1 times that of PMOS transistor M1. The channel width-to-length ratio of PMOS transistor M15 is K1 times that of PMOS transistor M3. The channel width-to-length ratio of NMOS transistor M19 is K2 times that of NMOS transistor M18. PMOS transistors M21 and M20 are identical. The current I of PMOS transistor M21 is... 21 have And current I 21 Let μ be a high-order nonlinear current at temperature T, where μ n For electron mobility, C ox The capacitance of the gate oxide layer per unit area (W / L) 16 This is the channel width-to-length ratio of the NMOS transistor M16.

[0010] Furthermore, the first-order bandgap reference circuit includes: PMOS transistors M23, MS8, MS9, MS10, MS11, MS12, amplifier A1, resistors R4, R5, and R6, NPN transistor Q7, and NPN transistor Q8. The source of PMOS transistor M23 is connected to the source of PMOS transistor MS8 and the external power supply VDD. The drain of PMOS transistor M23 is connected to one end of resistor R5, the base of NPN transistor Q7, one end of resistor R6, the gate of NMOS transistor MS11, and the circuit output terminal VREF. The other end of resistor R5 is connected to the collector of NPN transistor Q7, the base of NPN transistor Q8, and the inverting input terminal of amplifier A1. The other end of resistor R6 is connected to the collector of NPN transistor Q8. The electrodes are connected to the non-inverting input terminal of amplifier A1. The output terminal of amplifier A1 is connected to the gate of PMOS transistor M23 and the drain of NMOS transistor MS12. The emitter of NPN transistor Q7 is connected to the emitter of NPN transistor Q8, the other end of resistor R3, and one end of resistor R4. The other end of resistor R4 is connected to the source of NMOS transistor MS12, the source of NMOS transistor MS11, and the external ground GND. The gate of PMOS transistor MS8 is connected to the drain of PMOS transistor MS8 and the source of PMOS transistor MS9. The drain of PMOS transistor MS9 is connected to the gate of PMOS transistor MS9 and the source of PMOS transistor MS10. The gate of PMOS transistor MS10 is connected to the drain of PMOS transistor MS10, the gate of NMOS transistor MS12, and the drain of NMOS transistor MS11.

[0011] Furthermore, in the first-order bandgap reference circuit, the DC gain A of amplifier A1 is... d There is A d >>1, it forces the collector voltage of NPN transistor Q7 to be equal to the collector voltage of NPN transistor Q8, resistors R5 and R6 are exactly the same, and the emitter area of ​​NPN transistor Q8 is β times that of NPN transistor Q7, then the current I flowing through resistor R5 is... R5 With the current I flowing through resistor R6 R6 for The output voltage V at the circuit output terminal VREF ref for Where V BE7 R is the base-emitter voltage of NPN transistor Q7, R4 is the resistance of resistor R4, and R5 is the resistance of resistor R5; factor V BE7 It is a voltage with a negative temperature characteristic, factor It is a voltage with a positive temperature characteristic. By optimizing the values ​​of resistor R4 and resistor R5, as well as the factor β, the factor can be improved. The first-order bandgap reference voltage, factor I 21 R4 compensation V BE7 The higher-order temperature nonlinearity is used to obtain the bandgap reference voltage V for low temperature drift. ref .

[0012] The advantages and beneficial effects of this invention are as follows:

[0013] This invention provides a high-order temperature-compensated bandgap reference circuit based on BCD technology. It utilizes the base-emitter voltage difference between NPN transistors Q1 and Q2 to generate a positive temperature coefficient current across resistor R1, and the base-emitter voltage of NPN transistor Q3 to generate a negative temperature coefficient current across resistor R2 to provide bias for the temperature compensation circuit. It employs the base-emitter voltages of NPN transistors Q7 and Q8, along with clamping technology from amplifier A1, to generate a first-order bandgap reference voltage. Furthermore, it uses a linear loop technique composed of NMOS transistors M16 and M17, NPN transistors Q4 and Q5, and the base-emitter clamping technology of NPN transistors Q4 and Q5 to generate a high-order temperature nonlinear current to compensate for the high-order temperature nonlinearity of the first-order bandgap reference voltage, thereby improving the temperature drift performance of the bandgap reference voltage. This achieves a high-order temperature-compensated bandgap reference circuit based on BCD technology. Attached Figure Description

[0014] Figure 1 It is a traditional bandgap reference circuit schematic;

[0015] Figure 2 A schematic diagram of a high-order temperature-compensated bandgap reference circuit based on BCD technology, according to a preferred embodiment of the present invention;

[0016] Figure 3 A simulation diagram of the temperature characteristics of the output voltage of a high-order temperature-compensated bandgap reference circuit based on BCD technology, according to a preferred embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0018] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0019] In this embodiment, the base-emitter voltage difference between NPN transistors Q1 and Q2 generates a positive temperature coefficient current across resistor R1, and the base-emitter voltage of NPN transistor Q3 generates a negative temperature coefficient current across resistor R2 to provide bias for the temperature compensation circuit. The base-emitter voltages of NPN transistors Q7 and Q8, along with the clamping technique of amplifier A1, generate a first-order bandgap reference voltage. A linear loop technique consisting of NMOS transistors M16 and M17, NPN transistors Q4 and Q5, and the base-emitter clamping technique of NPN transistors Q4 and Q5 generate a high-order nonlinear current for temperature to compensate for the high-order temperature nonlinearity of the first-order bandgap reference voltage, thereby improving the temperature drift performance of the bandgap reference voltage. This realizes a high-order temperature-compensated bandgap reference circuit based on BCD technology.

[0020] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0021] Example

[0022] A high-order temperature-compensated bandgap reference circuit based on BCD technology, such as Figure 2 As shown, it includes a bias circuit 1, a temperature compensation circuit 2, and a first-order bandgap reference circuit 3;

[0023] The signal output terminal of the bias circuit 1 is connected to the signal input terminal of the temperature compensation circuit 2, and the signal output terminal of the temperature compensation circuit 2 is connected to the signal input terminal of the first-order bandgap reference circuit 3. The bias circuit 1 provides a positive temperature coefficient current and a negative temperature coefficient current to the temperature compensation circuit 2. The temperature compensation circuit 2 generates a high-order temperature nonlinear current and compensates for the high-order temperature nonlinearity of the first-order bandgap reference voltage generated by the first-order bandgap reference circuit 3, thereby obtaining a bandgap reference voltage with low temperature drift characteristics.

[0024] As a preferred technical solution, such as Figure 2As shown, the bias circuit 1 includes: PMOS transistors MS1, MS2, MS3, MS4, MS5, MS6, MS7, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M18, NPN transistors Q1, Q2, Q3, R1, and R2, resistors R1 and R2, wherein the source of PMOS transistor MS1 is connected to PMOS transistor MS4, MS5, MS6, MS7, M8, M9, M10, M11, M12, M13, and M18, NPN transistors Q1, Q2, and Q3, and resistors R1 and R2. The source of transistor M1, the source of PMOS transistors M2, M7, M9, and M10, and the external power supply VDD are connected. The gate of PMOS transistor MS1 is connected to the drain of PMOS transistor MS1 and the source of PMOS transistor MS2. The gate of PMOS transistor MS2 is connected to the drain of PMOS transistor MS2 and the source of PMOS transistor MS3. The gate of PMOS transistor MS3 is connected to the drain of PMOS transistor MS3, the gate of NMOS transistor MS6, the gate of NMOS transistor MS7, and the drain of NMOS transistor MS4. The source of NMOS transistor MS4 is connected to the drain of NMOS transistor MS5. The gate of PMOS transistor M1 is connected to the source of NMOS transistor MS6, the source of NMOS transistor MS7, the emitter of NPN transistor Q1, the emitter of NPN transistor Q2, the emitter of NPN transistor Q3, one end of resistor R2, the source of NMOS transistor M18, and the external ground GND. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M1, the gate of PMOS transistor M2, the gate of PMOS transistor M7, the gate of PMOS transistor M14, the drain of NMOS transistor MS6, and the source of PMOS transistor M3. The gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, the gate of PMOS transistor M4, the gate of PMOS transistor M8, the gate of PMOS transistor M15, and the gate of PMOS transistor M22. The drain of NMOS transistor M2 is connected to the drain of NMOS transistor M4, the source of NMOS transistor M5 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the collector and base of NPN transistor Q1. The drain of PMOS transistor M2 is connected to the source of PMOS transistor M4, the gate of NMOS transistor MS5, the gate of NMOS transistor M5, the gate of NMOS transistor M6, and the drain of NMOS transistor M6. The source of NMOS transistor M6 is connected to the collector and base of NPN transistor Q2. The drain of PMOS transistor M7 is connected to the source of PMOS transistor M8.The drain of PMOS transistor M8 is connected to the collector of NPN transistor Q3 and the gate of NMOS transistor M13. The gate of PMOS transistor M9 is connected to the drain of PMOS transistor M9, the gate of PMOS transistor M10, and the source of PMOS transistor M11. The gate of PMOS transistor M11 is connected to the drain of PMOS transistor M11, the gate of PMOS transistor M12, and the drain of NMOS transistor M13. The source of NMOS transistor M13 is connected to the base of NPN transistor Q3 and the other end of resistor R2. The drain of PMOS transistor M10 is connected to the source of PMOS transistor M12. The drain of PMOS transistor M12 is connected to the drain of NMOS transistor M18, the gate of NMOS transistor M18, and the gate of NMOS transistor M19.

[0025] The temperature compensation circuit 2 includes: PMOS transistors M14, M15, M16, M17, M19, M20, M21, and M22; NPN transistors Q4, Q5, and Q6; and resistor R3. The source of PMOS transistor M14 is connected to the drain of NMOS transistor M17, the source of PMOS transistor M20, the source of PMOS transistor M21, and the external power supply VDD. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M16, the gate of NMOS transistor M16, and the gate of NMOS transistor M17. NMOS transistor M1... The source of transistor 6 is connected to the collector of NPN transistor Q4, the base of NPN transistor Q4, and the base of NPN transistor Q5. The emitter of NPN transistor Q4 is connected to the emitter of NPN transistor Q5, the source of NMOS transistor M19, the emitter of NPN transistor Q6, and the external ground GND. The source of NMOS transistor M17 is connected to the collector of NPN transistor Q5, the base of NPN transistor Q6, and the drain of NMOS transistor M19. The gate of PMOS transistor M20 is connected to the drain of PMOS transistor M20, the gate of PMOS transistor M21, and the collector of NPN transistor Q6. The drain of PMOS transistor M21 is connected to the source of PMOS transistor M22. The drain of PMOS transistor M22 is connected to one end of resistor R3.

[0026] The first-order bandgap reference circuit 3 includes: PMOS transistors M23, MS8, MS9, MS10, MS11, MS12, amplifier A1, resistors R4, R5, and R6, NPN transistors Q7 and Q8. The source of PMOS transistor M23 is connected to the source of PMOS transistor MS8 and the external power supply VDD. The drain of PMOS transistor M23 is connected to one end of resistor R5, the base of NPN transistor Q7, one end of resistor R6, the gate of NMOS transistor MS11, and the circuit output terminal VREF. The other end of resistor R5 is connected to the collector of NPN transistor Q7, the base of NPN transistor Q8, and the inverting input terminal of amplifier A1. The other end of resistor R6 is connected to the collector of NPN transistor Q8. The non-inverting input of amplifier A1 is connected to the output of amplifier A1. The gate of PMOS transistor M23 and the drain of NMOS transistor MS12 are connected to the output of amplifier A1. The emitter of NPN transistor Q7 is connected to the emitter of NPN transistor Q8, the other end of resistor R3 and one end of resistor R4. The other end of resistor R4 is connected to the source of NMOS transistor MS12, the source of NMOS transistor MS11 and the external ground GND. The gate of PMOS transistor MS8 is connected to the drain of PMOS transistor MS8 and the source of PMOS transistor MS9. The drain of PMOS transistor MS9 is connected to the gate of PMOS transistor MS9 and the source of PMOS transistor MS10. The gate of PMOS transistor MS10 is connected to the drain of PMOS transistor MS10, the gate of NMOS transistor MS12 and the drain of NMOS transistor MS11.

[0027] In the bias circuit 1, PMOS transistors M1 and M2 are identical, PMOS transistors M3 and M4 are identical, and NMOS transistors M5 and M6 are identical. The emitter area of ​​NPN transistor Q1 is n times that of NPN transistor Q2. Therefore, the current I1 of PMOS transistor M1 and the current I2 of PMOS transistor M2 have the following relationship:

[0028]

[0029] In the formula, R1 is the resistance value of resistor R1, V T Since the thermal voltage is proportional to temperature, PMOS transistors M9 and M10 are identical, and PMOS transistors M11 and M12 are identical, then the current I of NMOS transistor M18 is... 18 for

[0030]

[0031] In the formula, R2 is the resistance value of resistor R2, V BE3This is the base-emitter circuit for NPN transistor Q3, with voltage V. BE3 It has a negative temperature characteristic, therefore the current I 18 This refers to a current with negative temperature characteristics.

[0032] In the temperature compensation circuit 2, NMOS transistors M16, M17, Q4, and Q5 form a linear loop. NMOS transistors M16 and M17 are identical. The emitter area of ​​NPN transistor Q4 is m times that of NPN transistor Q5. NPN transistor Q6 is identical to NPN transistor Q4. The current amplification of NPN transistors Q4, Q5, and Q6 is much greater than 1. The gate-source voltage V of NMOS transistor M16 is... GS16 The gate-source voltage V of NMOS transistor M17 GS17 have

[0033]

[0034] In the formula, I 20 I is the current of PMOS transistor M20. 16 The current of NMOS transistor M16 is given. The channel width-to-length ratio of PMOS transistor M14 is K1 times that of PMOS transistor M1, and the channel width-to-length ratio of PMOS transistor M15 is K1 times that of PMOS transistor M3. The current I of NMOS transistor M16 is given. 16 There is I 16 =K1I1, then the current I of PMOS transistor M20 20 for

[0035]

[0036] In the formula, μ n For electron mobility, C ox The capacitance of the gate oxide layer per unit area (W / L) 16 I is the channel width-to-length ratio of NMOS transistor M16. 19 Let I be the current of NMOS transistor M19. The channel width-to-length ratio of NMOS transistor M19 is K2 times that of NMOS transistor M18. PMOS transistor M21 is exactly the same as PMOS transistor M20. Then the current I of PMOS transistor M21 is... 21 have

[0037]

[0038] In the formula, V T It is a voltage with a positive temperature coefficient, V BE3 It is a voltage with a negative temperature coefficient. Therefore, by optimizing parameters K1, K2, m, n, the resistance values ​​of resistor R1 and R2, the current I can be increased. 21Let be a high-order nonlinear current at a temperature T.

[0039] In the first-order bandgap reference circuit 3, the DC gain A of amplifier A1 is... d There is A d >>1, it forces the collector voltage of NPN transistor Q7 to be equal to the collector voltage of NPN transistor Q8, resistors R5 and R6 are exactly the same, and the emitter area of ​​NPN transistor Q8 is β times that of NPN transistor Q7, then the current I flowing through resistor R5 is... R5 With the current I flowing through resistor R6 R6 for

[0040]

[0041] Where R5 is the resistance value of resistor R5, then the output voltage V at the circuit output terminal VREF is... ref for

[0042]

[0043] In the formula, V BE7 R is the base-emitter voltage of NPN transistor Q7, and R4 is the resistance value of resistor R4, where the factor V BE7 It is a voltage with a negative temperature characteristic, factor It is a voltage with a positive temperature characteristic. By optimizing the values ​​of resistor R4 and resistor R5, as well as the factor β, the factor can be improved. The first-order bandgap reference voltage, factor I 21 R4 compensation V BE7 The higher-order temperature nonlinearity is used to obtain the bandgap reference voltage V for low temperature drift. ref .

[0044] Figure 3 This is a simulation curve of the temperature characteristics of a high-order temperature-compensated bandgap reference circuit based on BCD technology according to the present invention, where the horizontal axis represents temperature T and the vertical axis represents the output voltage of the bandgap reference. The simulation results show that, within the temperature range of -40℃ to 125℃, the output voltage V of the high-order temperature-compensated bandgap reference circuit based on BCD technology... ref The temperature coefficient is 2.63 ppm / ℃.

[0045] In the above embodiments of this application, a high-order temperature-compensated bandgap reference circuit based on BCD technology includes a bias circuit, a temperature compensation circuit, and a first-order bandgap reference circuit. This application embodiment uses the difference between the base-emitter voltages of NPN transistors Q1 and Q2 to generate a positive temperature coefficient current across resistor R1, and the base-emitter voltage of NPN transistor Q3 to generate a negative temperature coefficient current across resistor R2 to provide bias for the temperature compensation circuit. It uses the base-emitter voltages of NPN transistors Q7 and Q8, along with the clamping technique of amplifier A1, to generate a first-order bandgap reference voltage. It employs a linear loop technique consisting of NMOS transistors M16 and M17, NPN transistors Q4 and Q5, and the base-emitter clamping technique of NPN transistors Q4 and Q5 to generate a high-order nonlinear current at temperature to compensate for the high-order temperature nonlinearity of the first-order bandgap reference voltage, thereby improving the temperature drift performance of the bandgap reference voltage. This realizes a high-order temperature-compensated bandgap reference circuit based on BCD technology.

[0046] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0047] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-order temperature-compensated bandgap reference circuit based on BCD technology, characterized in that, It includes: a bias circuit (1), a temperature compensation circuit (2), and a first-order bandgap reference circuit (3); wherein, the signal output terminal of the bias circuit (1) is connected to the signal input terminal of the temperature compensation circuit (2), and the signal output terminal of the temperature compensation circuit (2) is connected to the signal input terminal of the first-order bandgap reference circuit (3); the bias circuit (1) is used to provide a positive temperature coefficient current and a negative temperature coefficient current to the temperature compensation circuit (2), and the temperature compensation circuit (2) is used to generate a high-order temperature nonlinear current and compensate for the high-order temperature nonlinearity of the first-order bandgap reference voltage generated by the first-order bandgap reference circuit (3), thereby obtaining a bandgap reference voltage with low temperature drift characteristics; The bias circuit (1) includes: PMOS transistors MS1, MS2, MS3, MS4, MS5, MS6, MS7, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M18, NPN transistors Q1, Q2, Q3, R1, R2, R2, R3, R4, Q5, R5, R6, R3, R1, R2, R3, R1, R2, R2, R3, R1, R2, R2, R3, R1, R2, R1, R2, R1, R18, and external power supply VDD. The gate of PMOS transistor MS1 is connected to the drain of PMOS transistor MS1 and the source of PMOS transistor MS2. The gate of PMOS transistor MS2 is connected to the drain of PMOS transistor MS2 and the source of PMOS transistor MS3. The gate of PMOS transistor MS3 is connected to the drain of PMOS transistor MS3, the gate of NMOS transistor MS6, the gate of NMOS transistor MS7, and the drain of NMOS transistor MS4. The source of NMOS transistor MS4 is connected to the drain of NMOS transistor MS5. The source of NMOS transistor MS5 is connected to the source of NMOS transistor MS6, the source of NMOS transistor MS7, the emitter of NPN transistor Q1, and the NPN transistor MS5. The emitter of NPN transistor Q2, the emitter of NPN transistor Q3, one end of resistor R2, the source of NMOS transistor M18, and external ground GND are connected. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M1, the gate of PMOS transistor M2, the gate of PMOS transistor M7, the gate of PMOS transistor M14, the drain of NMOS transistor MS6, and the source of PMOS transistor M3. The gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, the gate of PMOS transistor M4, the gate of PMOS transistor M8, the gate of PMOS transistor M15, the gate of PMOS transistor M22, the drain of NMOS transistor MS7, and the source of NMOS transistor M18. The drain of transistor M5 is connected to the source of transistor M4. The other end of resistor R1 is connected to the collector and base of NPN transistor Q1. The drain of PMOS transistor M2 is connected to the source of PMOS transistor M4. The drain of PMOS transistor M4 is connected to the gates of NMOS transistors MS4, MS5, M5, and M6, as well as the drain of NMOS transistor M6. The source of NMOS transistor M6 is connected to the collector and base of NPN transistor Q2. The drain of PMOS transistor M7 is connected to the source of PMOS transistor M8.The drain of PMOS transistor M8 is connected to the collector of NPN transistor Q3 and the gate of NMOS transistor M13. The gate of PMOS transistor M9 is connected to the drain of PMOS transistor M9, the gate of PMOS transistor M10, and the source of PMOS transistor M11. The gate of PMOS transistor M11 is connected to the drain of PMOS transistor M11, the gate of PMOS transistor M12, and the drain of NMOS transistor M13. The source of NMOS transistor M13 is connected to the base of NPN transistor Q3 and the other end of resistor R2. The drain of PMOS transistor M10 is connected to the source of PMOS transistor M12. The drain of PMOS transistor M12 is connected to the drain of NMOS transistor M18, the gate of NMOS transistor M18, and the gate of NMOS transistor M19.

2. The high-order temperature-compensated bandgap reference circuit based on BCD technology according to claim 1, characterized in that, In the bias circuit (1), PMOS transistors M1 and M2 are identical, PMOS transistors M3 and M4 are identical, and NMOS transistors M5 and M6 are identical. The emitter area of ​​NPN transistor Q1 is n times that of NPN transistor Q2. The current I1 of PMOS transistor M1 has... Furthermore, it is a current with a positive temperature characteristic, where R1 is the resistance value of resistor R1, V T The thermal voltage is proportional to temperature; PMOS transistors M9 and M10 are identical, PMOS transistors M11 and M12 are identical, and the current I of NMOS transistor M18 is... 18 for Furthermore, it is a current with a negative temperature characteristic, where R2 is the resistance of resistor R2, V BE3 This is the base-emitter circuit for NPN transistor Q3.

3. The high-order temperature-compensated bandgap reference circuit based on BCD technology according to claim 1, characterized in that, The temperature compensation circuit (2) includes: PMOS transistors M14, M15, M16, M17, M19, M20, M21, and M22; NPN transistors Q4, Q5, and Q6; and resistor R3. The source of PMOS transistor M14 is connected to the drain of NMOS transistor M17, the source of PMOS transistor M20, the source of PMOS transistor M21, and the external power supply VDD. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M16, the gate of NMOS transistor M16, and the gate of NMOS transistor M17. NMOS transistor M14... The source of transistor M16 is connected to the collector of NPN transistor Q4, the base of NPN transistor Q4, and the base of NPN transistor Q5. The emitter of NPN transistor Q4 is connected to the emitter of NPN transistor Q5, the source of NMOS transistor M19, the emitter of NPN transistor Q6, and the external ground GND. The source of NMOS transistor M17 is connected to the collector of NPN transistor Q5, the base of NPN transistor Q6, and the drain of NMOS transistor M19. The gate of PMOS transistor M20 is connected to the drain of PMOS transistor M20, the gate of PMOS transistor M21, and the collector of NPN transistor Q6. The drain of PMOS transistor M21 is connected to the source of PMOS transistor M22. The drain of PMOS transistor M22 is connected to one end of resistor R3.

4. The high-order temperature-compensated bandgap reference circuit based on BCD technology according to claim 3, characterized in that, In the temperature compensation circuit (2), NMOS transistors M16, M17, Q4, and Q5 form a linear loop. NMOS transistors M16 and M17 are identical. The emitter area of ​​NPN transistor Q4 is m times that of NPN transistor Q5. NPN transistor Q6 is identical to NPN transistor Q4. The current amplification of NPN transistors Q4, Q5, and Q6 is much greater than 1. The channel width-to-length ratio of PMOS transistor M14 is K1 times that of PMOS transistor M1. The channel width-to-length ratio of PMOS transistor M15 is K1 times that of PMOS transistor M3. The channel width-to-length ratio of NMOS transistor M19 is K2 times that of NMOS transistor M18. PMOS transistors M21 and M20 are identical. The current I of PMOS transistor M21 is... 21 have And current I 21 Let V be a high-order nonlinear current at temperature T, where V T Where is the thermal voltage, n is the ratio of the emitter areas of NPN transistor Q1 to NPN transistor Q2, R1 is the resistance of resistor R1, and μ is the thermal voltage. n For electron mobility, C ox The capacitance of the gate oxide layer per unit area (W / L) 16 V is the channel width-to-length ratio of NMOS transistor M16. BE3 R1 is the base-emitter voltage of NPN transistor Q3, and R2 is the resistance value of resistor R2.

5. A high-order temperature-compensated bandgap reference circuit based on BCD technology according to claim 1, characterized in that, The first-order bandgap reference circuit (3) includes: PMOS transistors M23, MS8, MS9, MS10, MS11, MS12, amplifier A1, resistors R4, R5, and R6, NPN transistor Q7, and NPN transistor Q8. The source of PMOS transistor M23 is connected to the source of PMOS transistor MS8 and the external power supply VDD. The drain of PMOS transistor M23 is connected to one end of resistor R5, the base of NPN transistor Q7, one end of resistor R6, the gate of NMOS transistor MS11, and the circuit output terminal VREF. The other end of resistor R5 is connected to the collector of NPN transistor Q7, the base of NPN transistor Q8, and the inverting input terminal of amplifier A1. The other end of resistor R6 is connected to the collector of NPN transistor Q8. The gate of the PMOS transistor M23 is connected to the non-inverting input of the amplifier A1. The output of the amplifier A1 is connected to the gate of the PMOS transistor M23 and the drain of the NMOS transistor MS12. The emitter of the NPN transistor Q7 is connected to the emitter of the NPN transistor Q8, the other end of the resistor R3, and one end of the resistor R4. The other end of the resistor R4 is connected to the source of the NMOS transistor MS12, the source of the NMOS transistor MS11, and the external ground GND. The gate of the PMOS transistor MS8 is connected to the drain of the PMOS transistor MS8 and the source of the PMOS transistor MS9. The drain of the PMOS transistor MS9 is connected to the gate of the PMOS transistor MS9 and the source of the PMOS transistor MS10. The gate of the PMOS transistor MS10 is connected to the drain of the PMOS transistor MS10, the gate of the NMOS transistor MS12, and the drain of the NMOS transistor MS11.

6. A high-order temperature-compensated bandgap reference circuit based on BCD technology according to claim 5, characterized in that, In the first-order bandgap reference circuit (3), the DC gain A of amplifier A1 is... d There is A d >>1, it forces the collector voltage of NPN transistor Q7 to be equal to the collector voltage of NPN transistor Q8, resistors R5 and R6 are exactly the same, the emitter area of ​​NPN transistor Q8 is β times that of NPN transistor Q7, and the current I flowing through resistor R5 is... R5 With the current I flowing through resistor R6 R6 For equal and Where R5 is the resistance value of resistor R5, V T Thermoelectric voltage is proportional to temperature.

7. A high-order temperature-compensated bandgap reference circuit based on BCD technology according to any one of claims 2-6, characterized in that, The output voltage V at the output terminal VREF of the first-order bandgap reference circuit (3) is... ref for V BE7 V is the base-emitter voltage of NPN transistor Q7. T The thermal voltage is proportional to temperature; R4 is the resistance of resistor R4; R5 is the resistance of resistor R5; β is the ratio of the emitter area of ​​NPN transistor Q8 to that of NPN transistor Q7; I 21 The current of PMOS transistor M21; factor V BE7 It is a voltage with a negative temperature characteristic, factor It is a voltage with a positive temperature characteristic. By optimizing the values ​​of resistor R4, resistor R5, and factor β, the factor [V] is improved. BE7 + [I] is the first-order bandgap reference voltage, factor I 21 R4 compensation V BE7 The higher-order temperature nonlinearity is used to obtain the bandgap reference voltage V for low temperature drift. ref .

Images