An output rate optimization device and optimization method for a pulsed many-to-one output system

Abstract

The present invention provides an output rate optimization device for a pulsed many-to-one output system, the pulsed many-to-one output system includes a plurality of processing units and an arbitration module, the output rate optimization device includes: a plurality of first-level selectors, used to obtain continuous output results of the processing units and perform alternating gapless output, the input ends of every two first-level selectors are coupled to two processing units; a plurality of asynchronous FIFO memories, the input ends of the asynchronous FIFO memories are respectively coupled to the output ends of the first-level selectors, and the output ends of the asynchronous FIFO memories are all coupled to the arbitration module. The present invention realizes output continuity by adopting synchronous FIFO; realizes continuous gapless output by adopting a first-level selector and its selection strategy, and realizes alternating output of two processing units at the same time, which can reduce the total instantaneous bandwidth of the output and improve the output continuity; and realizes that the output can be continuously received by adopting asynchronous FIFO.

Description

Technical Field

[0001] The present invention relates to the technical field of frequent multi-party data interaction, and specifically but not limited to, relates to an output rate optimization device and optimization method for a pulsed many-to-one output system. Background Art

[0002] The existing pulsed many-to-one output solutions can basically be abstractly represented as follows: Figure 1 The model shown in FIG. 1 includes several processing units and a memory or buffer. The model distributes the data to be processed to multiple processing units, and after the processing is completed, the processing results are aggregated and stored in the memory or buffer. The output of several processing units to a memory or buffer presents a many-to-one feature, such as Figure 1 For a single processing unit, there is a common design scheme, such as Figure 2 As shown, after the processing unit receives a batch of data to be processed, it outputs after a period of internal processing. This type of output data presents a pulse-like feature, namely: {…}{processing gap, output}{processing gap, output}{…}, so the pulse-like feature is used to refer to the solution of this type of processing unit.

[0003] In the existing pulsed many-to-one output solution, due to the different data access queues and processing branches, the outputs of multiple processing units cannot be synchronized, which will form the following problems in the output channel: Figure 3 The "transmission bubble" shown Figure 3 The existence of "transmission cavitation" causes the overall output bandwidth to fail to reach the theoretical maximum value, where the theoretical maximum value of output bandwidth = output channel data bit width * number of output channels * output clock frequency.

[0004] In view of this, it is necessary to provide a new structure or control method to solve at least part of the above problems. Summary of the invention

[0005] In response to one or more problems in the prior art, the present invention proposes an output rate optimization device and optimization method for a pulsed many-to-one output system, which can effectively squeeze the use of "transmission cavitation" so that the output efficiency can reach the theoretical limit.

[0006] The technical solution to achieve the purpose of the present invention is:

[0007] An output rate optimization device for a pulsed many-to-one output system, the pulsed many-to-one output system comprising n processing units and an arbitration module, n being a positive integer, the output rate optimization device comprising:

[0008] n first-level selectors, used for obtaining continuous output results of the processing units and outputting them alternately without gaps, wherein the input ends of the 2a-1th and 2ath first-level selectors are both coupled to the 2a-1th and 2ath processing units, a∈[1,n / 2];

[0009] There are n asynchronous FIFO memories, the input ends of the n asynchronous FIFO memories are respectively coupled to the output ends of the n first-level selectors, and the output ends of the n asynchronous FIFO memories are all coupled to the arbitration module.

[0010] Furthermore, the output rate optimization device for a pulsed many-to-one output system of the present invention comprises:

[0011] n groups of synchronous FIFO memories are used to obtain discontinuous output results of processing units and output them continuously; the input ends of the n groups of synchronous FIFO memories are respectively coupled to the output ends of the n processing units, and the output ends of the 2a-1 group and the 2a group of synchronous FIFO memories are coupled to the input ends of the 2a-1 and 2a first-level selectors, a∈[1,n / 2].

[0012] Furthermore, the output rate optimization device for a pulsed many-to-one output system of the present invention comprises:

[0013] 2n synchronous FIFO memories are used to obtain discontinuous output results of the processing units and output them continuously; wherein, every 2 synchronous FIFO memories form a group of synchronous FIFO memories, the input ends of the n groups of synchronous FIFO memories are respectively coupled to the output ends of the n processing units, and the output ends of the 2a-1 group and the 2a group of synchronous FIFO memories are coupled to the input ends of the 2a-1 and 2a first-level selectors, a∈[1,n / 2].

[0014] Furthermore, in the output rate optimization device for a pulsed many-to-one output system of the present invention, the depths of the synchronous FIFO memories are all the same, and the depths are set according to the total output volume and interval time of the processing unit.

[0015] Furthermore, in the output rate optimization device for a pulsed many-to-one output system of the present invention, the first-level selector includes a first AND gate, a second AND gate, a NOT gate, an output flag module, a third AND gate, an OR gate and an output module, wherein the first input and the second input of the first AND gate, and the first input and the second input of the output module are respectively coupled to the outputs of two synchronous FIFO memories, the output of the first AND gate is coupled to the input of the output flag module, the input of the NOT gate and the first input of the third AND gate, the output of the output flag module is coupled to the second input of the third AND gate, the output of the NOT gate is coupled to the first input of the second AND gate, the second input of the second AND gate is coupled to the output of the first synchronous FIFO memory, the output of the second AND gate and the output of the third AND gate are respectively coupled to the first input and the second input of the OR gate, the output of the OR gate is coupled to the control end of the output module, and the output of the output module is coupled to the asynchronous FIFO memory.

[0016] A pulsed many-to-one output system comprises n processing units, an arbitration module, a memory and an output rate optimization device as described above, wherein the output ends of the processing units are respectively coupled to the synchronous FIFO memories of the output rate optimization device, the output ends of the output rate optimization device are coupled to the input ends of the arbitration module, and the output ends of the arbitration module are coupled to the memory.

[0017] An output rate optimization method for a pulsed many-to-one output system, the pulsed many-to-one output system comprising n processing units and an arbitration module, the output rate optimization method comprising:

[0018] S1: Obtain the continuous output data and output flag signal of the processing unit, and output the continuous output data of each processing unit alternately to its corresponding two first-level selectors, wherein every two processing units correspond to two first-level selectors;

[0019] S2: Each first-level selector selects its two groups of inputs according to the output flag signal and outputs them to the corresponding asynchronous FIFO memory;

[0020] S3: The asynchronous FIFO memory outputs to the arbitration module in a first-in, first-out order.

[0021] Furthermore, in the output rate optimization method for a pulsed many-to-one output system of the present invention, obtaining continuous output data of the processing unit in S1 includes:

[0022] S1-1: Determine whether the processing data of the processing unit is continuous. If it is continuous, directly output it as continuous output data. If it is not continuous, go to step S1-2;

[0023] S1-2: The processing data of each processing unit are output alternately and stored in two synchronous FIFO memories of the same depth. When a certain amount of processing data is stored in the synchronous FIFO memories, the two synchronous FIFO memories begin to output data to the corresponding two first-level selectors respectively. The output data of each synchronous FIFO memory is continuous output data.

[0024] Furthermore, in the output rate optimization method for a pulsed many-to-one output system of the present invention, the depth of the synchronous FIFO memory is set according to the total amount of output data and the interval time of the processing unit.

[0025] Furthermore, in the output rate optimization method for a pulsed many-to-one output system of the present invention, the selection strategy of the first-level selector in S2 is:

[0026] When one and only one of the two inputs of the first-level selector is valid, the first-level selector selects the valid input for sequential output;

[0027] When both sets of inputs of the first-level selector are valid, the first set of valid inputs will be output sequentially first, and after all of the inputs in that set have been output, the other set of valid inputs will be output sequentially.

[0028] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0029] 1. The output rate optimization device for a pulsed many-to-one output system of the present invention realizes output continuity by adopting a synchronous FIFO.

[0030] 2. The output rate optimization device for a pulsed many-to-one output system of the present invention realizes continuous gapless output by adopting a first-level selector and its selection strategy, and realizes alternating output of two processing units at the same time, which can reduce the total instantaneous bandwidth of the output and improve the output continuity.

[0031] 3. The output rate optimization device for a pulsed many-to-one output system of the present invention uses an asynchronous FIFO to achieve output that can be continuously received. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the present invention and are used together with the description to explain the embodiments of the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0033] Figure 1 A schematic diagram of an existing pulsed many-to-one output solution is shown.

[0034] Figure 2 The output schematic diagram of a single processing unit in an existing pulsed many-to-one output solution is shown.

[0035] Figure 3 A schematic diagram of output channels of an existing pulsed many-to-one output solution is shown.

[0036] Figure 4 A schematic diagram of a synchronous FIFO is shown.

[0037] Figure 5 A schematic diagram of an asynchronous FIFO is shown.

[0038] Figure 6 A schematic diagram of an output rate optimization device for a pulsed many-to-one output system of the present invention is shown.

[0039] Figure 7 The schematic diagram of the structure of the primary selector of the output rate optimization device for the pulsed many-to-one output system of the present invention is shown.

[0040] Figure 8 The schematic diagram of input and output of the synchronous FIFO of the output rate optimization device for the pulsed many-to-one output system of the present invention is shown.

[0041] Fig. 9 The output schematic diagram is shown when only one processing unit outputs.

[0042] Fig.10 A schematic diagram of an output channel of an output rate optimization device for a pulsed many-to-one output system of the present invention is shown.

[0043] Fig.11 The output schematic diagram when both processing units have outputs is shown. DETAILED DESCRIPTION

[0044] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0045] The description in this section is only for typical embodiments, and the present invention is not limited to the scope of the embodiments. The combination of different embodiments, the mutual replacement of some technical features in different embodiments, and the mutual replacement of the same or similar prior art means with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0046] FIFO, also known as synchronous FIFO, is a common basic design (such as Figure 4As shown in the figure, the FIFO has a storage space of a certain capacity (also recorded as depth). Data is written from one end and read from the other end. The read order is consistent with the write order. This is the first-in-first-out principle (First In First Out). When working, read and write requests can be continuous or spaced arbitrarily, but reading cannot be done when the FIFO is empty, and writing cannot be done when the FIFO is full.

[0047] Asynchronous FIFO, that is, asynchronous FIFO (such as Figure 5 As shown in the figure, based on the synchronous FIFO, the read and write interfaces use different clocks respectively, and the usage follows the same method as the synchronous FIFO, first-in first-out. You cannot read when the FIFO is empty, and write when the FIFO is full.

[0048] The present invention proposes an output rate optimization device for a pulsed many-to-one output system, which can effectively squeeze out the design scheme of using 'transmission cavitation' so that the output efficiency can reach the theoretical limit.

[0049] Based on the existing pulsed many-to-one output solution, the present invention adds a synchronous fifo (added when the processing unit outputs discontinuously), a first-level selector and an asynchronous fifo before each processing unit outputs the result to the output arbitration.

[0050] Synchronous fifo is used to ensure continuous output. The principle is to use the capacity of fifo to absorb the output gap. When the processing unit outputs discontinuously, by adding two synchronous fifos with the same depth for each processing unit, when the processing unit starts to output, it does not directly output to the asynchronous fifo, but accumulates alternately in the synchronous fifo. After the synchronous FIFO reaches a certain amount, it starts to output to the asynchronous FIFO. In this way, the data of the processing unit can be continuously output. Figure 8 As shown. The depth of the synchronous Fifo is set according to the total output and interval time of the processing unit to ensure continuous output. In the output interval background, let the total output of T clock cycles be x, that is, the cumulative interval time is Tx, then the depth of the synchronous fifo is Tx, and when the synchronous fifo is 1 less than full, the output from the synchronous fifo output end can achieve x data continuous output. For example: the total number of processing unit outputs is 8, one data is operated per cycle, the output order is to output 4 continuously first, then wait for 4 cycles, and then continuously output the last 4. At this time, it is necessary to wait until both synchronous fifos have 3 data to achieve continuous output.

[0051] The first-level selector is used to achieve alternating gapless output. The processing unit is grouped into 2 groups each time, and the output is simultaneously connected to the asynchronous fifo corresponding to the N-way processing unit, thereby forming an N-to-1 selector at each asynchronous fifo entry. The internal implementation of the selector is as follows Figure 7As shown, let the processing units be A and B. If only one of A and B is valid, the valid one is selected as the output. If both A and B are valid, the flag sel_flag (initial value is 0) is designed. Each time A and B are valid at the same time, the flag sel_flag value 0 / 1 is inverted once, and then the output is determined according to the flag value (output A if 0, output B if 1), thereby realizing the arbitration principle of "first come first out, same come alternately out". According to this arbitration principle, when only one of the two processing units is outputting, the idle asynchronous fifo next to it can be used to achieve the effect of halving the output overhead (such as Fig. 9 In addition, the output flag signal out_vld is extracted from the processing unit (the flag signal out_vld is 1 to indicate validity), which indicates that the output link of the processing-output cycle is in progress and remains valid during the output process. Arbitration based on out_vld can achieve that once the arbitration is granted, it will be exclusively used until the output is completed, thereby further supplementing the arbitration principle as "first come first out, same come alternately, and one arbitration is maintained until the output of a processing unit is completed".

[0052] Asynchronous FIFO is used to ensure smooth output. First, the storage space inside the asynchronous FIFO absorbs the pulse output gap of the processing unit and converts it into continuous output, thereby realizing the direct squeezing and utilization of the "output bubble". Secondly, by setting the output frequency higher than the input frequency, it can be combined with the capacity to amplify the capacity effect, thereby realizing continuous reception of the output results.

[0053] The output ID marks the output order. For designs that are sensitive to order, the output order or other key information can be encoded in the output result to form an ID and concatenate it with the data before outputting it together. In subsequent processing, the data can be restored based on the ID. It needs to be specified that the above processing will not excessively change the original order.

[0054] In summary, the combination of the continuous output of the synchronous FIFO, the first-level selector and the asynchronous FIFO can achieve a gapless and double-widened output channel for continuous data output, reaching the theoretical output limit.

[0055] Example 1

[0056] This embodiment proposes an output rate optimization device for a pulsed many-to-one output system, such as Figure 6 As shown, the pulsed many-to-one output system includes four processing units, an arbitration module and a storage / cache module.

[0057] The output rate optimization device includes 4 first-level selectors and 4 asynchronous FIFO memories, wherein:

[0058] The first-level selector is used to obtain the continuous output results of the processing unit and output them alternately without gaps. The input ends of the first and second first-level selectors are coupled to the first and second processing units, and the input ends of the third and fourth first-level selectors are coupled to the third and fourth processing units.

[0059] Input ends of the four asynchronous FIFO memories are respectively coupled to output ends of the four first-level selectors, output ends of the four asynchronous FIFO memories are all coupled to the arbitration module, and an output end of the arbitration module is coupled to the storage / cache module.

[0060] like Figure 7 As shown, the first-level selector includes a first AND gate 1, a second AND gate 2, a NOT gate 4, an output flag module 6, a third AND gate 3, an OR gate 5 and an output module 7, wherein the first input terminal and the second input terminal of the first AND gate 1, and the first input terminal and the second input terminal of the output module 7 are respectively coupled to the output terminals of two synchronous FIFO memories, the output terminal of the first AND gate 1 is coupled to the input terminal of the output flag module 6, the input terminal of the NOT gate 4 and the first input terminal of the third AND gate 3, the output terminal of the output flag module 6 is coupled to the second input terminal of the third AND gate 3, the output terminal of the NOT gate 4 is coupled to the first input terminal of the second AND gate 2, the second input terminal of the second AND gate 2 is coupled to the output terminal of the first synchronous FIFO memory, the output terminal of the second AND gate 2 and the output terminal of the third AND gate 3 are respectively coupled to the first input terminal and the second input terminal of the OR gate 5, the output terminal of the OR gate 5 is coupled to the control terminal of the output module 7, and the output terminal of the output module 7 is coupled to the asynchronous FIFO memory.

[0061] Based on the above output rate optimization device, if only one of the two processing units is outputting, and the output requires T cycles to output N data, the above output rate optimization device can be applied to allow the output of the processing unit to be output in advance with the help of the idle channel next to it, so that N data outputs can be completed in T / 2 time. If two processing units are outputting at the same time, one output is given priority, and then the second is output. In this way, the working time of the two processing units is staggered, which means that the data required and the output data at the same time present serial queuing characteristics, and the peak window time of the output is shortened, reducing the external memory access pressure.

[0062] Based on the above output rate optimization device, this embodiment also proposes a pulsed many-to-one output system, such as Figure 6 As shown, it includes 4 processing units, 1 arbitration module, 1 memory and the above-mentioned output rate optimization device, the output ends of the 4 processing units are respectively coupled to the first-level selector of the output rate optimization device, the output end of the output rate optimization device is coupled to the input end of the arbitration module, and the output end of the arbitration module is coupled to the memory.

[0063] Based on the above output rate optimization device, this embodiment further proposes an output rate optimization method for a pulsed many-to-one output system, wherein the pulsed many-to-one output system includes four processing units and an arbitration module, and the output rate optimization method includes:

[0064] S1: Acquire continuous output data of the processing unit, and output the processing data of each processing unit alternately to its corresponding two first-level selectors, wherein every two processing units correspond to two first-level selectors.

[0065] S2: Each first-level selector selects its two inputs and outputs them to its corresponding asynchronous FIFO memory. The selection strategy of the first-level selector is:

[0066] When one and only one of the two inputs of the first-level selector is valid, the first-level selector selects the valid input for sequential output;

[0067] When both sets of inputs of the first-level selector are valid, the first set of valid inputs will be output sequentially first, and after all of the inputs in that set have been output, the other set of valid inputs will be output sequentially.

[0068] S3: The asynchronous FIFO memory outputs in a first-in, first-out order.

[0069] Example 2

[0070] This embodiment proposes an output rate optimization device for a pulsed many-to-one output system, such as Figure 6 As shown, the pulsed many-to-one output system includes four processing units, an arbitration module and a storage / cache module.

[0071] The output rate optimization device includes 4 groups of synchronous FIFO memories, 4 first-level selectors and 4 asynchronous FIFO memories.

[0072] The four groups of synchronous FIFO memories are used to obtain discontinuous output results of the processing units and output them continuously, and the depths of the synchronous FIFO memories are the same, and the depths are set according to the total output amount and interval time of the processing units. The input ends of the four groups of synchronous FIFO memories are respectively coupled to the output ends of the four processing units, the output ends of the first and second groups of synchronous FIFO memories are both coupled to the input ends of the first and second first-level selectors, and the output ends of the third and fourth groups of synchronous FIFO memories are both coupled to the input ends of the third and fourth first-level selectors.

[0073] Four first-level selectors are used to obtain the continuous output results of the synchronous FIFO memory and output them alternately without gaps.

[0074] Input ends of the four asynchronous FIFO memories are respectively coupled to output ends of the four first-level selectors, output ends of the four asynchronous FIFO memories are all coupled to the arbitration module, and an output end of the arbitration module is coupled to the storage / cache module.

[0075] like Figure 6 As shown, each group of synchronous FIFO memories includes 2 synchronous FIFO memories, that is, a total of 8 synchronous FIFO memories. Among them, the input ends of the 1st and 2nd synchronous FIFO memories are coupled to the output end of the 1st processing unit, and the output ends of the 1st and 2nd synchronous FIFO memories are coupled to the input ends of the 1st and 2nd first-level selectors; the input ends of the 3rd and 4th synchronous FIFO memories are coupled to the output end of the 2nd processing unit, and the output ends of the 3rd and 4th synchronous FIFO memories are coupled to the input ends of the 1st and 2nd first-level selectors; the input ends of the 5th and 6th synchronous FIFO memories are coupled to the output end of the 3rd processing unit, and the output ends of the 5th and 6th synchronous FIFO memories are coupled to the input ends of the 3rd and 4th first-level selectors; the input ends of the 7th and 8th synchronous FIFO memories are coupled to the output end of the 4th processing unit, and the output ends of the 7th and 8th synchronous FIFO memories are coupled to the input ends of the 3rd and 4th first-level selectors.

[0076] like Figure 7 As shown, the first-level selector includes a first AND gate 1, a second AND gate 2, a NOT gate 4, an output flag module 6, a third AND gate 3, an OR gate 5 and an output module 7, wherein the first input terminal and the second input terminal of the first AND gate 1, and the first input terminal and the second input terminal of the output module 7 are respectively coupled to the output terminals of two synchronous FIFO memories, the output terminal of the first AND gate 1 is coupled to the input terminal of the output flag module 6, the input terminal of the NOT gate 4 and the first input terminal of the third AND gate 3, the output terminal of the output flag module 6 is coupled to the second input terminal of the third AND gate 3, the output terminal of the NOT gate 4 is coupled to the first input terminal of the second AND gate 2, the second input terminal of the second AND gate 2 is coupled to the output terminal of the first synchronous FIFO memory, the output terminal of the second AND gate 2 and the output terminal of the third AND gate 3 are respectively coupled to the first input terminal and the second input terminal of the OR gate 5, the output terminal of the OR gate 5 is coupled to the control terminal of the output module 7, and the output terminal of the output module 7 is coupled to the asynchronous FIFO memory.

[0077] Based on the above output rate optimization device, this embodiment also proposes a pulsed many-to-one output system, such as Figure 6 As shown, it includes 4 processing units, 1 arbitration module, 1 memory and the above-mentioned output rate optimization device. The output ends of the 4 processing units are respectively coupled to the synchronous FIFO memory of the output rate optimization device, the output end of the output rate optimization device is coupled to the input end of the arbitration module, and the output end of the arbitration module is coupled to the memory.

[0078] Based on the above output rate optimization device, this embodiment further proposes an output rate optimization method for a pulsed many-to-one output system, wherein the pulsed many-to-one output system includes four processing units and an arbitration module, and the output rate optimization method includes:

[0079] S1: Obtain the continuous output data of the processing unit, and output the processing data of each processing unit alternately to its corresponding two first-level selectors, wherein every two processing units correspond to two first-level selectors. Obtaining the continuous output data of the processing unit includes:

[0080] S1-1: Determine whether the processing data of the processing unit is continuous. If it is continuous, directly output it as continuous output data. If it is not continuous, go to step S1-2;

[0081] S1-2: The processed data of each processing unit are output alternately and stored in two synchronous FIFO memories of the same depth. When a certain amount of processed data is stored in the synchronous FIFO memory, the two synchronous FIFO memories begin to output data to the corresponding two first-level selectors respectively, and the output data of each synchronous FIFO memory is continuous output data. The depth of the synchronous FIFO memory is set according to the total output data and interval time of the processing unit. Specifically, in the context of the output interval, assuming that the total output of T clock cycles is x, that is, the accumulated interval time of Tx is accumulated, then the depth of the synchronous fifo is Tx, and when the synchronous fifo is almost full, the output from the synchronous fifo output end can achieve x data continuous output.

[0082] S2: Each first-level selector selects its two inputs and outputs them to its corresponding asynchronous FIFO memory. The selection strategy of the first-level selector is:

[0083] When one and only one of the two inputs of the first-level selector is valid, the first-level selector selects the valid input for sequential output;

[0084] When both sets of inputs of the first-level selector are valid, the first set of valid inputs will be output sequentially first, and after all of the inputs in that set have been output, the other set of valid inputs will be output sequentially.

[0085] S3: The asynchronous FIFO memory outputs in a first-in, first-out order.

[0086] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the specification may not be reflected in the actual experimental examples due to the uncertainty of specific condition parameters or other factors, and the effects or advantages are not used to limit the scope of the invention. The deformation and change of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent parts are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. An output rate optimization device for a pulsed many-to-one output system, characterized in that: The pulsed many-to-one output system includes n processing units and arbitration modules, where n is a positive integer, and the output rate optimization device includes: 2n synchronous FIFO memories, used to obtain discontinuous output results of the processing units and output them continuously; wherein, every two synchronous FIFO memories form a group of synchronous FIFO memories, the input ends of the n groups of synchronous FIFO memories are respectively coupled to the output ends of the n processing units, and the output ends of the 2a-1 group and the 2a group of synchronous FIFO memories are coupled to the input ends of the 2a-1 and 2a first-level selectors, a∈[1,n / 2]; n first-level selectors are used to obtain continuous output results of the processing unit and output them alternately without gaps, wherein the input ends of the 2a-1th and 2ath first-level selectors are coupled to the 2a-1th and 2ath processing units, a∈[1,n / 2]; wherein the selection strategy of the first-level selector is: when one and only one of the two sets of inputs of the first-level selector is valid, the first-level selector selects the valid input for sequential output; when both sets of inputs of the first-level selector are valid, the first set of valid inputs is sequentially output first, until all the inputs of the first set have been output, and then the other set of valid inputs is sequentially output; There are n asynchronous FIFO memories, the input ends of the n asynchronous FIFO memories are respectively coupled to the output ends of the n first-level selectors, and the output ends of the n asynchronous FIFO memories are all coupled to the arbitration module.

2. The output rate optimization device for a pulsed many-to-one output system according to claim 1, characterized in that: The depths of the synchronous FIFO memories are all the same, and the depths are set according to the total output volume and the interval time of the processing unit.

3. The output rate optimization device for a pulsed many-to-one output system according to claim 1, characterized in that: The first-level selector includes a first AND gate, a second AND gate, a NOT gate, an output flag module, a third AND gate, an OR gate and an output module, wherein the first input terminal and the second input terminal of the first AND gate, and the first input terminal and the second input terminal of the output module are respectively coupled to the output terminals of two synchronous FIFO memories, the output terminal of the first AND gate is coupled to the input terminal of the output flag module, the input terminal of the NOT gate and the first input terminal of the third AND gate, the output terminal of the output flag module is coupled to the second input terminal of the third AND gate, the output terminal of the NOT gate is coupled to the first input terminal of the second AND gate, the second input terminal of the second AND gate is coupled to the output terminal of the first synchronous FIFO memory, the output terminal of the second AND gate and the output terminal of the third AND gate are respectively coupled to the first input terminal and the second input terminal of the OR gate, the output terminal of the OR gate is coupled to the control terminal of the output module, and the output terminal of the output module is coupled to the asynchronous FIFO memory.

4. A pulsed many-to-one output system, characterized in that: It includes n processing units, an arbitration module, a memory and an output rate optimization device as described in any one of claims 1-3, the output ends of the processing units are respectively coupled to the synchronous FIFO memories of the output rate optimization device, the output ends of the output rate optimization device are coupled to the input ends of the arbitration module, and the output ends of the arbitration module are coupled to the memory.

5. A method for optimizing output rate of a pulsed many-to-one output system, characterized in that: The pulsed many-to-one output system includes n processing units and an arbitration module, where n is a positive integer. The output rate optimization method includes: S1: Obtaining continuous output data and output flag signals of the processing units, and outputting the continuous output data of each processing unit alternately to its corresponding two first-level selectors, wherein every two processing units correspond to two first-level selectors; wherein obtaining the continuous output data of the processing units includes: S1-1: Determine whether the processing data of the processing unit is continuous. If it is continuous, directly output it as continuous output data. If it is not continuous, go to step S1-2; S1-2: The processed data of each processing unit are alternately output and stored in two synchronous FIFO memories with the same depth. When a certain amount of processed data is stored in the synchronous FIFO memories, the two synchronous FIFO memories start to output data to the corresponding two first-level selectors respectively. The output data of each synchronous FIFO memory is continuous output data. S2: Each first-level selector selects its two sets of inputs according to the output flag signal and outputs them to its corresponding asynchronous FIFO memory; wherein the selection strategy of the first-level selector is: When one and only one of the two inputs of the first-level selector is valid, the first-level selector selects the valid input for sequential output; When both inputs of the first-level selector are valid, the first valid input is output in sequence, and then the other valid input is output in sequence after all the inputs of the first-level selector have been output. S3: The asynchronous FIFO memory outputs to the arbitration module in a first-in, first-out order.

6. The output rate optimization method for a pulsed many-to-one output system according to claim 5, characterized in that: The depth of the synchronous FIFO memory is set according to the total amount and interval time of output data of the processing unit.

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