Semiconductor device and method of manufacturing the same
By increasing the height of the first passivation layer in the semiconductor device and using a reflow process to cover the passivation layer on both sides of the ridge, the leakage problem caused by overlay deviation was solved, the process success rate was improved and the cost was reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN BRIGHT DIODE LASER TECH CO LTD
- Filing Date
- 2023-12-26
- Publication Date
- 2026-07-07
AI Technical Summary
In the fabrication of narrow-linewidth semiconductor laser ridges, conventional photolithography equipment cannot be precisely aligned, leading to overlay deviations and leakage. Existing high-precision equipment is costly and has a high probability of process failure. The thermal reflow process has high requirements for exposure light intensity and a low success rate.
By forming multiple spaced first passivation layers on the substrate surface and increasing their height so that the total height of the ridge and the first passivation layer is greater than a height threshold, a reflow process is used to reflow the photoresist layer along the sidewall of the ridge to cover the second passivation layer, thus protecting the passivation layers on both sidewalls of the ridge.
It improves the success rate of the hot reflow process, is applicable to semiconductor devices with different ridge heights, avoids the etching of the passivation layer on both sides of the ridge, achieves insulation effect, and reduces production costs.
Smart Images
Figure CN117878718B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] In the fabrication of narrow-linewidth semiconductor laser ridges, the width of the central emitting ridge is relatively small (usually around a few micrometers), and the overlay requirement is generally around 100nm. However, conventional lithography equipment cannot achieve precise alignment due to its low alignment accuracy. Any misalignment can easily lead to leakage and chip failure. Therefore, the main process methods currently used are high-precision lithography equipment (such as stepper lithography machines and electron beam lithography machines) for overlay operations, and thermal reflow. The first method has high equipment costs, low efficiency, and high production costs. The second method, thermal reflow, has lower requirements for overlay but higher requirements for the intensity of the exposed light, and the possibility of process failure is higher. Summary of the Invention
[0003] Therefore, it is necessary to provide a semiconductor device and its fabrication method to address the above problems. By increasing the height through a first passivation layer, the success rate of the reflow process can be improved, making it suitable for the thermal reflow process of semiconductor devices with different ridge heights.
[0004] In a first aspect, this application provides a method for fabricating a semiconductor device, comprising:
[0005] Provide substrate;
[0006] A plurality of first passivation layers are formed on the surface of the substrate at intervals;
[0007] A plurality of ridges are formed within the substrate, each ridge comprising a portion of the substrate, and each ridge having two sidewalls formed as grooves in the substrate; wherein, the first passivation layer is located on the ridge, and the total height of the first passivation layer and the ridge is greater than a height threshold;
[0008] A second passivation layer is formed on the surface of the substrate and on the surface of each of the first passivation layers;
[0009] A first photoresist layer is formed on the surface of the second passivation layer;
[0010] The first photoresist layer is patterned to expose the second passivation layer away from the first passivation layer and the second passivation layer on the ridge;
[0011] A reflow process is used to reflow the first photoresist layer in each of the grooves along the sidewalls of the ridges to cover the second passivation layer on both sidewalls of the ridges.
[0012] In one embodiment, the total height of the ridge and the first passivation layer is 1 micrometer to 3 micrometers.
[0013] In one embodiment, forming a plurality of spaced-apart first passivation layers on the surface of the substrate includes:
[0014] An initial passivation layer is formed on the surface of the substrate;
[0015] The initial passivation layer is etched to form a plurality of first passivation layers spaced apart on the surface of the substrate.
[0016] In one embodiment, etching the initial passivation layer to form a plurality of spaced-apart first passivation layers on the surface of the substrate includes:
[0017] The initial passivation layer is etched to form a plurality of spaced sub-passivation layers on the surface of the substrate, wherein the width of the sub-passivation layers is greater than the width of the ridge;
[0018] The sub-passivation layer is etched to form a plurality of first passivation layers spaced apart on the surface of the substrate, the width of the first passivation layer being equal to the width of the ridge.
[0019] In one embodiment, etching the initial passivation layer to form a plurality of spaced-apart sub-passivation layers on the surface of the substrate includes:
[0020] A second photoresist layer is formed on the side of the initial passivation layer away from the substrate;
[0021] The second photoresist layer is patterned, and the initial passivation layer is etched using a reactive ion etching process to form a plurality of spaced sub-passivation layers on the surface of the substrate.
[0022] Remove the second photoresist layer.
[0023] In one embodiment, etching the sub-passivation layer to form a plurality of spaced-apart first passivation layers on the surface of the substrate includes:
[0024] A third photoresist layer is formed on the surface of the substrate and on the side of each of the sub-passivation layers away from the substrate;
[0025] The third photoresist layer is patterned, and each of the sub-passivation layers is etched using reactive ion etching to form a plurality of spaced first passivation layers on the surface of the substrate.
[0026] In one embodiment, forming a plurality of ridges within the substrate includes:
[0027] The substrate is etched using an inductively coupled plasma process to form a plurality of ridges within the substrate;
[0028] Remove the third photoresist layer.
[0029] In one embodiment, after using a reflow process to reflow the first photoresist layer within each of the grooves along the sidewalls of the ridge to cover the second passivation layer on both sidewalls of the ridge, the method further includes:
[0030] Remove the first passivation layer and the second passivation layer on the side of the first passivation layer away from the ridge;
[0031] Remove the first photoresist layer.
[0032] In one embodiment, the material of the first passivation layer is silicon nitride, silicon oxide, or chromium metal.
[0033] On the other hand, this application provides a semiconductor device, including:
[0034] The substrate includes a plurality of spaced-apart ridges and grooves formed on the side walls of each of the ridges;
[0035] Multiple first passivation layers are provided, each of which is located on a corresponding ridge; wherein the total height of the ridge and the first passivation layers is greater than a height threshold.
[0036] The second passivation layer is located on the surface of the substrate and on the surface of each of the first passivation layers;
[0037] A first photoresist layer is located on the surface of the second passivation layer away from the substrate; wherein the first photoresist layer covering the surface of the second passivation layer on both sides of each ridge is formed by a reflow process.
[0038] The aforementioned semiconductor device and its fabrication method provide a substrate, and form a plurality of first passivation layers spaced apart on the surface of the substrate. Then, a plurality of ridges are formed within the substrate. Next, second passivation layers are formed on the surface of the substrate and on the surface of each of the first passivation layers, respectively. A first photoresist layer is formed on the surface of the second passivation layer. The first photoresist layer is then patterned to expose the second passivation layers away from the first and second passivation layers on the ridges. A reflow process is then used to reflow the first photoresist layer within each groove along the sidewalls of the ridges to cover the second passivation layers on both sidewalls of the ridges. Since the total height of the ridges and the first passivation layers is greater than a height threshold, i.e., the surface of the first passivation layer and the sidewalls are... The height difference between the bottoms of the grooves is greater than a height threshold, ensuring that the grooves on both sides of the ridge can accommodate sufficient photoresist. This allows the photoresist in the grooves to reflow and cover the second passivation layer on both sides of the ridge, thus protecting the second passivation layer on both sides of the ridge from the first photoresist layer. This avoids the problem of etching the second passivation layer on both sides of the ridge during the subsequent fabrication of the ridge passivation layer window, thereby preserving the second passivation layer on both sides of the ridge to achieve insulation. This method can ensure the success rate of the reflow process by adjusting the height of the first passivation layer to ensure that the total height of the ridge and the first passivation layer is greater than the height threshold. It is applicable to the reflow process of semiconductor devices with different ridge heights. Attached Figure Description
[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0040] Figure 1 A schematic diagram of the cross-sectional structure of the ridge strip after adhesive coating is provided in the related technology;
[0041] Figure 2 This is a top view of the ridge window structure provided in related technologies;
[0042] Figure 3 A flowchart illustrating a method for fabricating a semiconductor device according to one embodiment;
[0043] Figure 4 This is a schematic cross-sectional view of the structure obtained in step S302 of the semiconductor device fabrication method provided in one embodiment;
[0044] Figure 5 This is a schematic cross-sectional view of the structure obtained in step S304 of the semiconductor device fabrication method provided in one embodiment;
[0045] Figure 6This is a schematic cross-sectional view of the structure obtained in step S306 of the semiconductor device fabrication method provided in one embodiment;
[0046] Figure 7 This is a schematic cross-sectional view of the structure obtained in step S308 of the semiconductor device fabrication method provided in one embodiment;
[0047] Figure 8 This is a schematic cross-sectional view of the structure obtained in step S310 of the semiconductor device fabrication method provided in one embodiment;
[0048] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S312 of the semiconductor device fabrication method provided in one embodiment;
[0049] Figure 10 Provided in one embodiment Figure 9 The diagram shows an enlarged view of the structure of region D1.
[0050] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S314 of the semiconductor device fabrication method provided in one embodiment;
[0051] Figure 12 Provided in one embodiment Figure 11 A magnified structural diagram of region D2 is shown below;
[0052] Figure 13 This is a flowchart illustrating step S304 in a method for fabricating a semiconductor device according to an embodiment.
[0053] Figure 14 This is a schematic cross-sectional view of the structure obtained in step S1302 of the semiconductor device fabrication method provided in one embodiment;
[0054] Figure 15 This is a flowchart illustrating step S1304 in a method for fabricating a semiconductor device according to an embodiment.
[0055] Figure 16 This is a schematic cross-sectional view of the structure obtained in step S1502 of the semiconductor device fabrication method provided in one embodiment;
[0056] Figure 17 This is a flowchart illustrating step S1502 in a method for fabricating a semiconductor device according to an embodiment.
[0057] Figure 18 This is a schematic cross-sectional view of the structure obtained in step S1702 of the semiconductor device fabrication method provided in one embodiment;
[0058] Figure 19This is a schematic cross-sectional view of the structure obtained in step S1704 of the semiconductor device fabrication method provided in one embodiment;
[0059] Figure 20 This is a flowchart illustrating step S1504 in a method for fabricating a semiconductor device according to an embodiment.
[0060] Figure 21 This is a schematic cross-sectional view of the structure obtained in step S2002 of the semiconductor device fabrication method provided in one embodiment;
[0061] Figure 22 This is a schematic cross-sectional view of the structure obtained in step S2004 of the semiconductor device fabrication method provided in one embodiment;
[0062] Figure 23 This is a schematic diagram of a cross-sectional structure after removing the first passivation layer and the second passivation layer on the side of the first passivation layer away from the ridge, as provided in one embodiment.
[0063] Figure 24 This is a schematic diagram of the cross-sectional structure after removing the first photoresist layer in one embodiment;
[0064] Figure 25 A flowchart illustrating a method for fabricating a semiconductor device according to another embodiment;
[0065] Figure 26 This is a schematic diagram of the cross-sectional structure after step S2524, obtained using a scanning electron microscope (SEM) according to one embodiment.
[0066] Figure 27 This is a schematic diagram of the cross-sectional structure after execution step S2528, obtained based on SEM, provided as an embodiment.
[0067] Explanation of reference numerals in the attached figures:
[0068] Substrate 1, photoresist 2, ridge 3, groove 4, ridge sidewall 5, substrate 10, first passivation layer 20, ridge 110, groove 120, second passivation layer 30, first photoresist layer 40, initial passivation layer 50, sub-passivation layer 60, second photoresist layer 70, third photoresist layer 80, ridge window 90. Detailed Implementation
[0069] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0071] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0072] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0073] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0074] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0075] like Figure 1 and Figure 2 As shown, a hot reflow process is adopted. This process mainly involves etching a deep groove 4 on the substrate 1 on both sides of the ridge 3. During the coating process, the adhesive 2 on the surface of the middle ridge 3 flows into the grooves 4 on both sides, creating a large difference between the adhesive thickness H2 on the surface of the ridge 3 and the adhesive thickness H1 in the groove 4. Then, by controlling the exposure intensity, the adhesive 2 on the ridge 3 is fully exposed and can be developed cleanly. However, there is still adhesive 2 remaining in the grooves 4 on both sides of the ridge 3 after development. This is then baked at high temperature to soften and melt the adhesive 2. Through the surface capillary principle, the adhesive 2 can climb upwards along the edge of the ridge 3 (reflow), thereby protecting the adhesive 2 on the sides of the ridge 3. This prevents the sides of the ridge 3 from being etched during subsequent etching, achieving the goal of removing only the passivation layer on the surface of the ridge 3. However, in actual operation, it was found that when the depth of the grooves 4 etched on both sides of the ridge 3 was <1um, the height difference of the photoresist 2 on the surface of the ridge 3 and in the grooves 4 on both sides was small. After exposure, the remaining thickness of the photoresist 2 in the grooves 4 on both sides of the ridge 3 was too small to achieve high-temperature reflow, thus causing the process to fail. In actual operation, due to the requirements of epitaxial structure design, it is not possible to etch the grooves 4 on both sides of the ridge 3 to be too deep. If this method is used again, the experiment will fail, and the passivation layer of the ridge sidewall 5 will be etched away, failing to achieve the insulating effect.
[0076] In response, this application provides a semiconductor device and its fabrication method, which increases the height by using a first passivation layer to improve the success rate of the reflow process, making it suitable for the thermal reflow process of semiconductor devices with different ridge heights.
[0077] In one embodiment, such as Figure 3 As shown, a method for fabricating a semiconductor device is provided, the method comprising the steps S302 to S314.
[0078] S302: Provides a substrate.
[0079] like Figure 4 As shown, a substrate is provided. Exemplarily, the substrate can be an epitaxial substrate. The substrate material can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can also be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc., which are not limited in this embodiment.
[0080] S304: A first passivation layer with multiple spaced layers is formed on the surface of the substrate.
[0081] like Figure 5As shown, a plurality of first passivation layers are formed on the surface of a substrate at intervals. Exemplarily, the material of the first passivation layers includes silicon nitride (SiNx), silicon oxide (such as SiO2), or chromium metal (Ge). Exemplarily, the first passivation layers can be formed on the surface of the substrate using a deposition technique, wherein the deposition technique may include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD), etc., and this embodiment is not limited thereto.
[0082] S306: Multiple ridges are formed within the substrate.
[0083] like Figure 6 As shown, each ridge includes a portion of the substrate, and each ridge has two sidewalls formed by grooves in the substrate. The grooves on the sidewalls of the ridge are symmetrically arranged along the ridge. A first passivation layer is located on the ridge, and the total height of the first passivation layer and the ridge is greater than a height threshold. The height of the ridge is the depth of the groove, meaning the height between the surface of the first passivation layer and the bottom of the groove is greater than the height threshold. The height threshold is preset and can be determined based on factors such as the groove depth, the ridge height, and the reflow process. For example, if the height threshold is greater than or equal to 1 micrometer, then the height of the first passivation layer and the ridge is greater than 1 micrometer. For example, multiple ridges can be formed in the substrate using etching techniques. These etching techniques can include sputtering and ion beam milling, plasma etching, high-pressure plasma etching, high-density plasma (HDP) etching, reaction ion etching (RIE), or inductively coupled plasma (ICP) etching, etc., and are not limited to these methods in this embodiment.
[0084] S308: A second passivation layer is formed on the surface of the substrate and on the surface of each first passivation layer.
[0085] like Figure 7As shown, a second passivation layer is formed on the surface of the substrate and on the surface of each first passivation layer. Exemplarily, the material of the second passivation layer is the same as that of the first passivation layer. Exemplarily, the material of the second passivation layer includes silicon nitride (SiNx), silicon oxide (such as SiO2), or chromium metal. Chromium metal is heat-resistant, easily etched, and does not corrode the process passivation layer or the surface material of the epitaxial wafer during etching. Exemplarily, a coating technique can be used to form the second passivation layer on the surface of the substrate, the bottom and walls of each groove, and the surface and sides of each first passivation layer. The coating technique can include any of the aforementioned deposition processes, which will not be elaborated further here.
[0086] S310: A first photoresist layer is formed on the surface of the second passivation layer. See also Figure 8 .
[0087] S312: Pattern the first photoresist layer to expose the second passivation layer away from the first and second passivation layers on the ridge. See also Figure 9 .
[0088] In application, after coating the surface of the second passivation layer with the first photoresist layer, the first photoresist layer can be overlaid and exposed. By controlling the exposure amount, the first photoresist layer on the second passivation layer away from the first passivation layer is fully exposed, thereby completely exposing the first and second passivation layers on the ridge away from the second passivation layer. It is understood that after exposing and developing the first photoresist layer, portions of the second passivation layer on both sides of the ridge will also be exposed, such as... Figure 10 As shown, Figure 10 for Figure 9 A magnified structural diagram of region D1 in the middle.
[0089] S314: A reflow process is used to reflow the first photoresist layer in each groove along the sidewall of the ridge to cover the second passivation layer on both sides of the ridge.
[0090] like Figure 11 and Figure 12 As shown, for example, a thermal reflow process can be used to reflow the first photoresist layer within each groove along the sidewalls of the ridge, thereby covering the second passivation layer on both sidewalls of the ridge. The temperature and time of the reflow process can be set according to the actual application scenario. For example, the reflow temperature can be 155°C, and the reflow time can be 5 minutes. Figure 12 for Figure 11 An enlarged schematic diagram of region D2 in the middle, from Figure 12 It can be seen that Y is the first photoresist layer that has been reflowed, and this first photoresist layer covers the second passivation layer on both sides of the ridge.
[0091] The above-described method for fabricating a semiconductor device involves providing a substrate and forming multiple first passivation layers spaced apart on the surface of the substrate. Multiple ridges are then formed within the substrate. Second passivation layers are formed on the surface of the substrate and on the surface of each of the first passivation layers. A first photoresist layer is formed on the surface of the second passivation layer. The first photoresist layer is then patterned to expose the second passivation layers away from the first and second passivation layers on the ridges. A reflow process is then used to reflow the first photoresist layer within each groove along the sidewalls of the ridges to cover the second passivation layers on both sidewalls of the ridges. Since the total height of the ridges and the first passivation layers is greater than a height threshold, i.e., the surface of the first passivation layer is close to the sidewalls of the ridges... The height difference between the bottoms of the grooves is greater than a height threshold, ensuring that the grooves on both sides of the ridge can accommodate sufficient photoresist. This allows the photoresist in the grooves to reflow and cover the second passivation layer on both sides of the ridge, thus protecting the second passivation layer on both sides of the ridge from the first photoresist layer. This avoids the problem of etching the second passivation layer on both sides of the ridge during the subsequent fabrication of the ridge passivation layer window, thereby preserving the second passivation layer on both sides of the ridge to achieve insulation. This method can ensure the success rate of the reflow process by adjusting the height of the first passivation layer to ensure that the total height of the ridge and the first passivation layer is greater than the height threshold. It is applicable to the reflow process of semiconductor devices with different ridge heights.
[0092] In one embodiment, the total height of the ridge and the first passivation layer is 1 micrometer (μm) to 3 micrometers (μm). Based on this, the height difference between the surface of the first passivation layer and the bottom of each groove is greater than 1 micrometer, ensuring that sufficient photoresist can be accommodated within the grooves on both sides of the ridge. This allows the photoresist within the grooves to flow back and cover the second passivation layer on both sides of the ridge, thus protecting the second passivation layer on both sides of the ridge from the first photoresist layer. This avoids the problem of etching the second passivation layer on both sides of the ridge during the subsequent fabrication of the ridge passivation layer window, preserving the second passivation layer on both sides of the ridge to achieve insulation. Furthermore, the total height of the ridge and the first passivation layer is less than 3 micrometers to control process costs.
[0093] In one embodiment, such as Figure 13 As shown, step S304, forming a plurality of spaced first passivation layers on the surface of the substrate, may include steps S1302 and S1304.
[0094] S1302: An initial passivation layer is formed on the surface of the substrate. See also Figure 14 The height of the initial passivation layer is the same as the height of the first passivation layer.
[0095] S1304: The initial passivation layer is etched to form multiple spaced-apart first passivation layers on the surface of the substrate. The cross-sectional structure obtained after performing step S1304 can be found in [reference needed]. Figure 5As shown, the first passivation layer can be understood as the portion remaining after the initial passivation layer is etched. Any of the aforementioned etching processes can be used to etch the initial passivation layer, such as RIE etching, etc., and no limitation is made here. Based on this, the first passivation layer is formed on the substrate by etching the initial passivation layer to increase the height difference between the ridge surface and the bottom of the groove, thereby ensuring that the first photoresist layer reflows to cover the second passivation layer on both sides of the ridge.
[0096] In one embodiment, such as Figure 15 As shown, step S1304: Etching the initial passivation layer to form a plurality of spaced first passivation layers on the surface of the substrate may include the following steps S1502 and S1504.
[0097] S1502: The initial passivation layer is etched to form multiple spaced sub-passivation layers on the surface of the substrate. The cross-sectional structure obtained after performing step S1502 can be found in [reference needed]. Figure 16 As shown, the sub-passivation layer can be understood as the portion remaining after the initial passivation layer is etched. The width of the sub-passivation layer is greater than the width of the ridge. For example, the width of the sub-passivation layer is less than the width between two adjacent sub-passivation layers. For example, the initial passivation layer can be etched using a RIE process.
[0098] S1504: The sub-passivation layer is etched to form multiple spaced-apart first passivation layers on the surface of the substrate. The cross-sectional structure obtained after performing step S1504 can be found in [reference needed]. Figure 5 As shown, the width of the first passivation layer is equal to the width of the ridge. Based on this, a sub-passivation layer is formed by etching the initial passivation layer onto the substrate, and then the sub-passivation layer is etched onto the substrate to form the first passivation layer. This increases the height difference between the ridge surface and the bottom of the groove through the first passivation layer, thereby ensuring that the first photoresist layer reflows to cover the second passivation layer on both sides of the ridge.
[0099] In one embodiment, such as Figure 17 As shown, step S1502, etching the initial passivation layer to form a plurality of spaced sub-passivation layers on the surface of the substrate, may include steps S1702 to S1706.
[0100] S1702: A second photoresist layer is formed on the side of the initial passivation layer away from the substrate. The cross-sectional structure obtained after performing step S1702 can be found in [reference needed]. Figure 18 As shown.
[0101] S1704: The second photoresist layer is patterned, and the initial passivation layer is etched using reactive ion etching to form multiple spaced sub-passivation layers on the surface of the substrate.
[0102] See Figure 19 After applying a second photoresist layer to the surface of the initial passivation layer, it is exposed. The width of the exposed pattern is the width of the sub-passivation layer. The width of the exposed pattern is greater than the width of the ridge, and the width of the exposed pattern is less than the width of the side walls of the ridge to be etched.
[0103] S1706: Remove the second photoresist layer. The cross-sectional structure obtained after step S1504 can be found in [reference needed]. Figure 16 As shown. Based on this, the initial passivation layer is patterned using photolithography to form a sub-passivation layer on the substrate. The sub-passivation layer is then etched onto the substrate to form a first passivation layer. This first passivation layer increases the height difference between the ridge surface and the bottom of the groove, thereby ensuring that the first photoresist layer reflows to cover the second passivation layer on both sides of the ridge.
[0104] In one embodiment, such as Figure 20 As shown, step S1504, etching the sub-passivation layer to form a plurality of spaced first passivation layers on the surface of the substrate, may include steps S2002 and S2004.
[0105] S2002: A third photoresist layer is formed on the surface of the substrate and on the side of each sub-passivation layer away from the substrate. The cross-sectional structure obtained after performing step S1504 can be found in [reference needed]. Figure 21 As shown.
[0106] S2004: The third photoresist layer is patterned, and each sub-passivation layer is etched using reactive ion etching to form multiple spaced first passivation layers on the surface of the substrate.
[0107] See Figure 22 After the third photoresist layer is applied to the surface of the initial passivation layer, it is exposed and developed to expose part of the sub-passivation layer and part of the substrate. The remaining third photoresist layer is located in the middle of the side of the sub-passivation layer away from the substrate and on the surface of the substrate. The width of the remaining third photoresist layer on the sub-passivation layer is the width of the ridge.
[0108] Based on this, the sub-passivation layer is patterned using photolithography to form a first passivation layer on the substrate. This first passivation layer increases the height difference between the ridge surface and the bottom of the groove, thereby ensuring that the first photoresist layer reflows to cover the second passivation layer on both sides of the ridge.
[0109] In one embodiment, based on Figures 20 to 22 Step S306, forming multiple ridges within the substrate, may include: etching the substrate using an inductively coupled plasma process to form multiple ridges within the substrate, and removing the third photoresist layer. A schematic diagram of the cross-sectional structure after removing the third photoresist layer can be found in [reference needed]. Figure 6 As shown.
[0110] In one embodiment, see Figures 23 to 26 In step S314, after the first photoresist layer in each groove is reflowed along the sidewall of the ridge to cover the second passivation layer on both sidewalls of the ridge, the semiconductor device fabrication method may further include: removing the first passivation layer and the second passivation layer on the side of the first passivation layer away from the ridge, and removing the first photoresist layer. For example, reactive ion etching (RIE) can be used to etch the first passivation layer and the second passivation layer on the side of the first passivation layer away from the ridge. A schematic diagram of the cross-sectional structure after removing the first passivation layer and the second passivation layer on the side of the first passivation layer away from the ridge can be found in [reference needed]. Figure 23 As shown, the ridge window is exposed after removing the first passivation layer and the second passivation layer on the side of the first passivation layer away from the ridge. A schematic diagram of the cross-sectional structure after removing the first photoresist layer can be found in [reference needed]. Figure 24 As shown. Based on this, the fabrication of the ridge window was realized, which can be applied to related semiconductor devices such as narrow linewidth semiconductor lasers. Since the second passivation layer on both sides of the ridge is covered by the first photoresist layer, the second passivation layer on both sides of the ridge can be effectively protected by the first photoresist layer during the etching of the first and second passivation layers. Therefore, the problem of the second passivation layer on both sides of the ridge being etched away is avoided, and the second passivation layer on both sides of the ridge plays an insulating role.
[0111] In one embodiment, such as Figure 25 As shown, a method for fabricating a semiconductor device is provided, the method comprising the steps S2502 to S2528.
[0112] S2502: Provides a substrate. See also Figure 4 The substrate is an epitaxial substrate.
[0113] S2504: An initial passivation layer is formed on the surface of the substrate. See also Figure 14 For example, the material of the initial passivation layer is the same as that of the first passivation layer, which is SiNx or SiO2. In another example, the material of the initial passivation layer is chromium metal.
[0114] S2506: A second photoresist layer is formed on the side of the initial passivation layer furthest from the substrate. See also Figure 18 .
[0115] S2508: The second photoresist layer is patterned, and the initial passivation layer is etched using reactive ion etching to form multiple spaced sub-passivation layers on the substrate surface. See also Figure 19 .
[0116] S2510: Remove the second photoresist layer. See also Figure 16 .
[0117] S2512: A third photoresist layer is formed on the surface of the substrate and on the side of each sub-passivation layer away from the substrate. See also Figure 21 .
[0118] S2514: The third photoresist layer is patterned, and reactive ion etching is used to etch each sub-passivation layer to form multiple spaced-apart first passivation layers on the substrate surface. See also Figure 22 .
[0119] S2516: The substrate is etched using an inductively coupled plasma process to form multiple ridges within the substrate and remove the third photoresist layer. See also Figure 6 Each ridge includes a portion of the substrate, and grooves are formed on both side walls of each ridge. Furthermore, each first passivation layer is located on each ridge, and the height of the first passivation layer and the ridge is between 1 micrometer and 3 micrometers.
[0120] S2518: A second passivation layer is formed on the surface of the substrate and on the surface of each of the first passivation layers. See also Figure 7 .
[0121] S2520: A first photoresist layer is formed on the surface of the second passivation layer. See also Figure 8 .
[0122] S2522: Pattern the first photoresist layer to expose the second passivation layer away from the first and second passivation layers on the ridge. See also Figure 9 .
[0123] S2524: A reflow process is used to reflow the first photoresist layer in each groove along the sidewalls of the ridge, thereby covering the second passivation layer on both sidewalls of the ridge. See also Figure 11 and Figure 26 ,in, Figure 26 This is a schematic diagram of the cross-sectional structure after step S2524, obtained based on SEM. The reflow process temperature was 155℃, and the reflow time was 5 minutes.
[0124] S2526: The first passivation layer and the second passivation layer on the side of the first passivation layer away from the ridge are removed using reactive ion etching. See also Figure 23 .
[0125] S2528: Remove the first photoresist layer. See also Figure 24 and Figure 27 ,in, Figure 27 This is a schematic diagram of the cross-sectional structure after execution step S2528, obtained based on SEM.
[0126] The aforementioned semiconductor device fabrication method, because the total height of the ridge and the first passivation layer is greater than a height threshold (i.e., the height difference between the surface of the first passivation layer and the bottom of the sidewall grooves is greater than the height threshold), allows sufficient photoresist to be accommodated within the sidewall grooves of the ridge. This ensures that the photoresist within the grooves can flow back to cover the second passivation layer on both sides of the ridge, achieving protection of the second passivation layer on both sides of the ridge by the first photoresist layer. This avoids the problem of etching the second passivation layer on both sides of the ridge during the subsequent fabrication of the ridge passivation layer window, thus preserving the second passivation layer on both sides of the ridge and achieving [the desired effect]. For the purpose of insulation, this method can ensure the success rate of the reflow process by adjusting the height of the first passivation layer to ensure that the total height of the ridge and the first passivation layer is greater than the height threshold. It is applicable to the reflow process of semiconductor devices with different ridge heights. Furthermore, the material of the first passivation layer can be the same as that of the second passivation layer, which is beneficial to the etching process of the passivation layer in the window area. In addition, the material of the first passivation layer can be a high-temperature resistant, easily etchable material that will not corrode the process passivation layer and the surface material of the epitaxial wafer during etching, such as chromium, which is beneficial to the etching process of the passivation layer in the window area.
[0127] It should be understood that although the steps in each flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in each diagram may include multiple steps or stages, which are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.
[0128] Based on the same inventive concept, this application also provides a semiconductor device. The solution provided by this semiconductor device is similar to the solution described in the above method. Therefore, the specific limitations of one or more semiconductor device embodiments provided below can be found in the limitations of the semiconductor device fabrication method described above, and will not be repeated here.
[0129] Please continue reading. Figure 11 This application also provides a semiconductor device, comprising: a substrate including a plurality of spaced ridges and grooves formed on the side walls of each ridge; a plurality of first passivation layers, each first passivation layer being respectively located on each ridge; wherein the total height of the ridges and the first passivation layers is greater than a height threshold; a second passivation layer located on the surface of the substrate and the surface of each first passivation layer; a first photoresist layer located on the surface of the second passivation layer away from the substrate; wherein the first photoresist layer covering the surface of the second passivation layer on the side walls of each ridge is formed by a reflow process.
[0130] For example, the total height of the first passivation layer and the ridge is 1 micrometer to 3 micrometers. For example, the material of the first passivation layer is the same as the material of the second passivation layer. For example, the material of the first passivation layer includes silicon nitride (SiNx), silicon oxide (such as SiO2), or chromium metal.
[0131] In the aforementioned semiconductor device, because the total height of the ridge and the first passivation layer is greater than the height threshold (i.e., the height difference between the surface of the first passivation layer and the bottom of the grooves on both sides of the ridge is greater than the height threshold), sufficient photoresist can be accommodated in the grooves on both sides of the ridge. This ensures that the photoresist in the grooves can be reflowed to cover the second passivation layer on both sides of the ridge, thus protecting the second passivation layer on both sides of the ridge from the problem of etching the second passivation layer on both sides of the ridge during the subsequent fabrication of the ridge passivation layer window. This preserves the second passivation layer on both sides of the ridge to achieve the purpose of insulation. This method can ensure the success rate of the reflow process by adjusting the height of the first passivation layer to ensure that the total height of the ridge and the first passivation layer is greater than the height threshold. It is applicable to the reflow process of semiconductor devices with different ridge heights.
[0132] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0134] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A plurality of first passivation layers are formed on the surface of the substrate at intervals; A plurality of ridges are formed within the substrate, each ridge comprising a portion of the substrate, and each ridge having two sidewalls formed as grooves in the substrate; wherein, the first passivation layer is located on the ridge, and the total height of the first passivation layer and the ridge is greater than a height threshold; A second passivation layer is formed on the surface of the substrate and on the surface of each of the first passivation layers; A first photoresist layer is formed on the surface of the second passivation layer; The first photoresist layer is patterned to expose the second passivation layer away from the first passivation layer and the second passivation layer on the ridge; A reflow process is used to reflow the first photoresist layer in each of the grooves along the sidewalls of the ridges to cover the second passivation layer on both sidewalls of the ridges.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The total height of the ridge and the first passivation layer is 1 micrometer to 3 micrometers.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a plurality of spaced-apart first passivation layers on the surface of the substrate includes: An initial passivation layer is formed on the surface of the substrate; The initial passivation layer is etched to form a plurality of first passivation layers spaced apart on the surface of the substrate.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The etching of the initial passivation layer to form a plurality of spaced-apart first passivation layers on the surface of the substrate includes: The initial passivation layer is etched to form a plurality of spaced sub-passivation layers on the surface of the substrate, wherein the width of the sub-passivation layers is greater than the width of the ridge; The sub-passivation layer is etched to form a plurality of first passivation layers spaced apart on the surface of the substrate, the width of the first passivation layer being equal to the width of the ridge.
5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The etching of the initial passivation layer to form a plurality of spaced sub-passivation layers on the surface of the substrate includes: A second photoresist layer is formed on the side of the initial passivation layer away from the substrate; The second photoresist layer is patterned, and the initial passivation layer is etched using a reactive ion etching process to form a plurality of spaced sub-passivation layers on the surface of the substrate. Remove the second photoresist layer.
6. The method for fabricating a semiconductor device according to claim 4, characterized in that, The etching of the sub-passivation layer to form a plurality of spaced-apart first passivation layers on the surface of the substrate includes: A third photoresist layer is formed on the surface of the substrate and on the side of each of the sub-passivation layers away from the substrate; The third photoresist layer is patterned, and each of the sub-passivation layers is etched using reactive ion etching to form a plurality of spaced first passivation layers on the surface of the substrate.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The formation of a plurality of ridges within the substrate includes: The substrate is etched using an inductively coupled plasma process to form a plurality of ridges within the substrate; Remove the third photoresist layer.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, After employing a reflow process to reflow the first photoresist layer within each of the grooves along the sidewalls of the ridge to cover the second passivation layer on both sidewalls of the ridge, the method further includes: Remove the first passivation layer and the second passivation layer on the side of the first passivation layer away from the ridge; Remove the first photoresist layer.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the first passivation layer is silicon nitride, silicon oxide, or chromium metal.
10. A semiconductor device, characterized in that, include: The substrate includes a plurality of spaced-apart ridges and grooves formed on the side walls of each of the ridges; Multiple first passivation layers are provided, each of which is located on a corresponding ridge; wherein the total height of the ridge and the first passivation layers is greater than a height threshold. The second passivation layer is located on the surface of the substrate and on the surface of each of the first passivation layers; A first photoresist layer is located on the surface of the second passivation layer away from the substrate; wherein the first photoresist layer covering the surface of the second passivation layer on both sides of each ridge is formed by a reflow process.