Method for assigning width to target signal line, wiring substrate, light emitting substrate, and display device

Abstract

A method for allocating width to target signal lines, a wiring substrate, a light-emitting substrate, and a display device. The method includes: numbering the target signal lines (S101); performing the following steps at least once until the number of target signal lines in the set is 0 (S102): determining a set of target signal lines (S103); determining a region R based on a condition satisfied by a voltage drop V, a temperature rise T, and a width W of the target signal lines, the voltage drop V being a function V(L, W), a length L and a width W each being a length and a width of each target signal line in a sub-portion of a fan-out region (S104); determining a number i of a target signal line having a maximum voltage drop in the set (S105); substituting the known length L i of the target signal line numbered i into V(L, W) to obtain V(L i , W), obtaining W i based on an intersection of V(L i , W) and a boundary of the region R (S106); and removing the target signal line having the width W i from the set (S107).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a method for allocating width for a target signal line, a wiring substrate, a light-emitting substrate including the wiring substrate, and a display device. Background Technology

[0002] Display devices are generally classified into two main categories: liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. LCDs are widely used due to their advantages such as thinness, shock resistance, wide viewing angles, and high contrast. An LCD typically consists of a display panel and a backlight. The backlight is usually located on the non-display side of the display panel to provide light for the display. The contrast ratio, brightness uniformity, and stability of an LCD are related to the structure and performance of the backlight. In recent years, mini-LEDs have received widespread attention due to their superior performance and are increasingly being used in backlights. Summary of the Invention

[0003] According to one aspect of this disclosure, a method for assigning width to target signal lines is provided, comprising: numbering at least one target signal line; performing the following steps at least once until the number of target signal lines to be assigned width in the set is 0: determining a set of target signal lines to be assigned width; determining a planar region R based on a voltage drop V and a temperature rise T of each of the target signal lines to be assigned width and a condition satisfied by the width W of the target signal lines to be assigned width, wherein the voltage drop V is a function of length L and width W, wherein the length L refers to the length of a sub-portion of each target signal line located in the fan-out region and extending along a first direction along the first direction, and the width W refers to the width of a sub-portion of each target signal line located in the fan-out region and extending along the first direction along a second direction, the second direction intersecting the first direction; determining the number i of the target signal line with the largest voltage drop among the target signal lines to be assigned width in the set; and assigning the known length L of the target signal line numbered i to the target signal line. i Substitute into V(L, W) to obtain V(L) i W), based on V(L) i The intersection of W) and the boundary of the region R is obtained by W. i The W i The width of the sub-portion of target signal line i, located in the fan-out region and extending along the first direction, along the second direction; and the removal of the allocated width W from the set. i The target signal line.

[0004] In some embodiments, the number of target signal lines is N, where N is a positive integer greater than or equal to 2, the N target signal lines have N widths, and the width of the target signal line with the largest voltage drop among the N target signal lines is the maximum value among the N widths.

[0005] In some embodiments, the temperature rise T is a function T(L, W) of the length L and the width W. The step of determining the planar region R based on the voltage drop V and temperature rise T of each of the target signal lines to be allocated width and the width W of the target signal lines to be allocated width includes: determining the planar region R based on a set of inequalities consisting of the voltage drop V(L, W) of each of the target signal lines to be allocated width being less than a voltage drop threshold, the temperature rise T(L, W) of each of the target signal lines to be allocated width being less than a temperature rise threshold, and the sum of the widths W of the target signal lines to be allocated width being less than a dynamic width threshold.

[0006] In some embodiments, the step of determining the number i of the target signal line with the largest voltage drop among the target signal lines to be allocated width in the set includes: substituting W0 into V(L, W) to obtain V(L, W0), where W0 is associated with the dynamic width threshold; substituting the known length of each of the target signal lines to be allocated width in the set into V(L, W0) to obtain a set of different voltage drops; selecting the largest voltage drop from the set of different voltage drops; and determining the number i of the target signal line with the largest voltage drop based on the known length corresponding to the largest voltage drop.

[0007] In some embodiments, the voltage drop V(L, W) of each target signal line satisfies the following formula: V(L, W) = E + F * L / W, where E and F are constants.

[0008] In some embodiments, The target signal line is also arranged in a functional area, which includes multiple partitions arranged in an array, R pixel The resistance of each target signal line segment within a single partition, where k is the number of rows in the partition, and I... j =j*I0,I k =k*I0, where I0 is the current in a single partition.

[0009] In some embodiments, R(L, W) = R s *L / W, R s The sheet resistance of the target signal line is E = k*(k+1) / 2*I0*R pixel F=k*I0*R s .

[0010] In some embodiments, the temperature rise T(L, W) of each target signal line satisfies the following formula:

[0011] T(L, W) = [(1 / (L*W*X)] Y ) / (I / C)] 1 / Q Where I is the current transmitted on each target signal line, and X, Y, C, and Q are all constants.

[0012] According to another aspect of this disclosure, a wiring substrate is provided, comprising: a substrate including a fan-out region; at least one target signal line located on the substrate and at least within the fan-out region, each of the at least one target signal line having a sub-portion located in the fan-out region and extending along a first direction having a length L along the first direction, each of the at least one target signal line having a sub-portion located in the fan-out region and extending along the first direction having a width W along a second direction intersecting the first direction, the width W of each target signal line being determined according to the method described in any of the preceding embodiments.

[0013] In some embodiments, the number of target signal lines is N, where N is a positive integer greater than or equal to 2, the N target signal lines have N widths, and the width of the target signal line with the largest voltage drop among the N target signal lines is the maximum value among the N widths.

[0014] In some embodiments, the wiring substrate further includes bonding electrodes disposed within the fan-out area, with each target signal line electrically connected to at least two bonding electrodes.

[0015] In some embodiments, the target signal line includes at least one of a drive voltage signal line, a common voltage signal line, and a power supply voltage signal line.

[0016] According to another aspect of this disclosure, a light-emitting substrate is provided, the light-emitting substrate comprising: a wiring substrate as described in any of the preceding embodiments, the substrate further comprising a functional region including a plurality of partitions arranged in an array; a plurality of light-emitting elements disposed within the plurality of partitions in the functional region; and a circuit board disposed within the fan-out region.

[0017] In some embodiments, the plurality of partitions are arranged in multiple rows and columns, the number of target signal lines is N, where N is a positive integer greater than or equal to 2, the N target signal lines are also arranged in the functional area along the second direction, and the N target signal lines are located in the same column partition or in adjacent M column partitions, where M is a positive integer greater than or equal to 2.

[0018] In some embodiments, the circuit board includes a flip-chip film, and the N target signal lines are electrically connected to the same circuit board via bonding electrodes.

[0019] In some embodiments, each of the plurality of light-emitting elements includes a sub-millimeter light-emitting diode.

[0020] According to another aspect of this disclosure, a display device is provided, which includes a wiring substrate or a light-emitting substrate described in any of the preceding embodiments. Attached Figure Description

[0021] To more clearly describe the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This illustrates the arrangement of signal lines in the fan-out area in related technologies;

[0023] Figure 2 A flowchart of a method for allocating width to a target signal line according to an embodiment of the present disclosure is shown;

[0024] Figure 3 The arrangement of the target signal line in the fan-out region according to an embodiment of the present disclosure is shown;

[0025] Figure 4 A partial plan view of a wiring substrate according to an embodiment of the present disclosure is shown;

[0026] Figure 5 A partial plan view of a wiring substrate according to another embodiment of the present disclosure is shown;

[0027] Figure 6 A partial planar schematic diagram of a light-emitting substrate according to an embodiment of the present disclosure is shown; and

[0028] Figure 7 A block diagram of a display device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0029] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0030] Wiring substrates typically have multiple signal lines arranged to transmit signals, such as electrical signals. Since each signal line has resistance, a voltage drop occurs between the two ends of the signal line when an electrical signal is transmitted through it. To ensure that the voltage drop between the two ends of the signal line does not exceed a safe threshold, there are usually certain requirements for the resistance value of the signal line. In related technologies, to reduce the resistance of signal lines, due to limitations in the size of the wiring substrate and to avoid signal crosstalk caused by adjacent signal lines being too close together, a certain width of spacing must be maintained between adjacent signal lines. Therefore, there is an upper limit to the linewidth of each signal line. Thus, it is common practice to increase the thickness of the signal lines to increase their cross-sectional area, thereby reducing the resistance. Multiple signal lines located on the same layer can be formed simultaneously through patterning in a single film deposition process, but the thickness of multiple signal lines on the same layer is limited by the signal line with the greatest thickness requirement.

[0031] The wiring substrate includes functional areas and fan-out areas. The functional areas consist of multiple partitions arranged in an array, while the fan-out areas may house bonding electrodes and circuit boards. Each signal line in the fan-out area receives electrical signals from the circuit board via bonding electrodes and extends into the functional areas to transmit corresponding electrical signals to each partition. To meet the requirements of narrow bezels or even bezel-less products, the fan-out areas of the wiring substrate typically have a smaller size along the signal line extension direction. Multiple signal lines converge within the fan-out area, and the spacing between these lines changes from a state where they can be relatively large to a state where they are relatively uniform and small. Therefore, compared to the portion of the signal line located in the functional area, the portion in the fan-out area has greater limitations in terms of dimensional parameters related to voltage drop, such as line width and line length, often necessitating an increase in the thickness of the conductive layer. However, a thicker conductive layer places more stringent requirements on the manufacturing process, often leading to decreased product yield and increased production costs.

[0032] Figure 1 A schematic diagram of the signal lines arranged in the fan-out region of a wiring board 10 in the related art is shown. For example... Figure 1As shown, the fan-out region includes multiple signal lines, such as signal line 11, signal line 12, and signal line 13. Within the fan-out region, the portion of signal line 11 along the first direction D1 has a dimension of S1 along the first direction D1 and a dimension of G1 along the second direction D2, with the second direction D2 intersecting the first direction D1; the portion of signal line 12 along the first direction D1 has a dimension of S2 along the first direction D1 and a dimension of G2 along the second direction D2; the portion of signal line 13 along the first direction D1 has a dimension of S3 along the first direction D1 and a dimension of G3 along the second direction D2. Dimensions S1 and S2 are much smaller than dimension S3, but dimensions G1, G2, and G3 are essentially equal. This results in the voltage drop of signal line 13 being much greater than that of signal lines 11 and 12, exceeding the safety threshold. Consequently, the overall voltage drop level of the wiring substrate 10 is limited by the voltage drop of signal line 13, resulting in poor electrical performance of the wiring substrate 10.

[0033] To address the technical problems existing in related technologies, embodiments of this disclosure provide a method for allocating width to a target signal line. Figure 2 A flowchart of method 100 is shown. (Reference) Figure 2 The method 100 includes:

[0034] Step S101: Number at least one target signal line;

[0035] Step S102: Execute steps S103-S107 at least once until the number of target signal lines with unallocated widths in the set is 0;

[0036] Step S103: Determine the set of target signal lines whose widths to be allocated;

[0037] Step S104: Determine the planar region R based on the voltage drop V and temperature rise T of each target signal line with the width to be allocated and the conditions satisfied by the width W of the target signal line with the width to be allocated. The voltage drop V is a function of length L and width W, V(L, W). The length L refers to the length of the sub-section of each target signal line located in the fan-out region and extending along the first direction along the first direction. The width W refers to the width of the sub-section of each target signal line located in the fan-out region and extending along the first direction along the second direction. The second direction intersects the first direction.

[0038] Step S105: Determine the number i of the target signal line with the largest voltage drop among the target signal lines to be allocated width in the set;

[0039] Step S106: The known length L of the target signal line numbered i i Substitute into V(L, W) to obtain V(L) i W), based on V(L) iThe intersection of W) with the boundary of the planar region R yields W. i W i The width of the sub-section of the target signal line numbered i, located in the fan-out region and extending along the first direction, along the second direction;

[0040] Step S107: Remove the allocated width W from the set. i The target signal line.

[0041] It should be noted that the term "voltage drop" refers to voltage or potential difference. When current flows through a target signal line, a certain voltage drop will be generated in each segment of the target signal line. The voltage drop represents the potential difference caused by the movement of charge from one end of a segment of the signal line to the other. The term "temperature rise" refers to the increase in temperature of the target signal line when it operates with non-zero fixed electrical power over a period of time, compared to the temperature when it operates with zero electrical power.

[0042] Additionally, it should be noted that the term "fan-out area" refers to the area used to connect signal lines to the circuit board. The fan-out area typically contains structures such as signal lines, bonding electrodes, and circuit boards. For example, the portion of the signal line located in the fan-out area is connected to the circuit board via bonding electrodes, thereby receiving signals from the circuit board.

[0043] It should be noted that the term "width to be allocated" refers to the linewidth of the sub-section of the target signal line located in the fan-out region and extending along the first direction. The term "planar region R" is a two-dimensional planar region defined by L and W, which can be understood as a mathematical set composed of L and W.

[0044] By using method 100, after each execution of steps S101-S107, the width can be allocated to the fan-out region and the sub-part extending along the first direction of the target signal line with the largest voltage drop in the set, until the width is allocated to the fan-out region and the sub-part extending along the first direction of each target signal line in the set. Compared to related technologies where the sub-parts of each signal line extending along the first direction in the fan-out region have different lengths but essentially the same linewidth, in the method 100 provided in the embodiments of this disclosure, the width allocated to the fan-out region and the sub-part extending along the first direction of each target signal line is related to the length, voltage drop, and temperature rise of the sub-part extending along the first direction in the fan-out region of that signal line, thus achieving dynamic allocation of the width of each target signal line. In addition, by dynamically allocating the width of each target signal line by method 100, the voltage drop of all target signal lines, especially the maximum voltage drop, is less than the voltage drop threshold, and the voltage drop of all target signal lines is less than the voltage drop of the signal line 13 of the wiring substrate 10, thereby improving the overall voltage drop level of the wiring substrate.

[0045] Figure 3A schematic diagram showing the arrangement of a portion of the signal lines in the fan-out region of the wiring board 200 according to an embodiment of the present disclosure is shown. Figure 4 A partial planar schematic diagram of the wiring substrate 200 is shown below. Figures 2 to 4 The steps of method 100 are described in detail.

[0046] Step S101: Number at least one target signal line.

[0047] Within the fan-out region of the wiring substrate 200, multiple signal lines are typically arranged. Among these multiple signal lines, some signal lines, due to the transmission of digital signals, have low resistance requirements. The size design of such signal lines in the fan-out region is not within the scope of discussion in this disclosure embodiment, and is thus referred to as "non-target signal lines." On the other hand, another portion of the multiple signal lines, due to the transmission of electrical signals with constant amplitude, such as constant voltage or constant current signals, have a significant impact on the overall voltage drop level of the wiring substrate 200 due to the design of their size parameters. The width of these signal lines in the fan-out region is within the scope of discussion in this disclosure embodiment, and these signal lines are referred to as "target signal lines" herein.

[0048] In other words, the target signal line refers to a signal line that transmits an electrical signal of constant amplitude and includes multiple sequentially connected sub-sections in the fan-out region. Of the multiple sub-sections of the target signal line, only one sub-section extends along a first direction D1, and at most two sub-sections extend along a second direction D2. One end of the sub-section extending along the second direction D2 is connected to one end of the sub-section extending along the first direction D1 to form an integral structure, and the other end is connected to at least one bonding electrode in the bonding region. Specifically, refer to... Figure 3 Signal line 103 transmits a voltage signal of constant amplitude and includes three sequentially connected sub-sections 1031, 1032, and 1033 in the fan-out region. Only one sub-section 1032 extends along a first direction D1, while two other sub-sections 1031 and 1033 extend along a second direction D2. Sub-sections 1031 and 1033 are connected to the two parts of sub-section 1032 to form an integral structure. Therefore, signal line 103 is a target signal line; similarly, signal lines 101 and 102 are also target signal lines. It should also be noted that within the fan-out region, signal lines with only sub-sections extending along the second direction D2 are non-target signal lines.

[0049] The signal line or sub-section of the signal line extending in a certain direction means that the signal line or sub-section of the signal line has a generally strip-shaped structure, and the direction of extension of the longer side of the strip-shaped structure is parallel to that direction. The direction of extension of the signal line or sub-section of the signal line can be considered to be parallel to the direction of extension of the side with the longest length in the strip-shaped structure.

[0050] Specifically, refer to Figure 3 The signal line 201 has a generally strip-shaped structure in its sub-section 2011 located in the fan-out region and extending along the first direction. The side 202 with the maximum length in this strip-shaped structure extends only along the second direction D2. Therefore, the sub-section 2011 of the signal line 201 located in the fan-out region and extending along the first direction can be considered to extend only along the second direction D2. Thus, the signal line 201 is not the target signal line referred to herein, but a non-target signal line.

[0051] Figure 3 As an example, eight signal lines are shown, including target signal line 101, target signal line 102, target signal line 103, and other non-target signal lines. These eight signal lines are electrically connected in the bonding area to the same circuit board 106 (e.g., a flip-chip film), which includes multiple gold finger structures that correspond one-to-one with and are electrically connected to multiple bonding electrodes in the bonding area. Figure 3 As shown, using the center line of circuit board 106 parallel to the second direction D2 as a reference line, all target signal lines (including target signal lines 101, 102, and 103) located on the first side of the reference line are electrically connected to circuit board 106 on the first side of the reference line, and all signal lines located on the second side of the reference line are electrically connected to circuit board 106 on the second side of the reference line. In some embodiments, since the orthographic projections of multiple target signal lines located on one side of the reference line on a plane parallel to the first direction D1 overlap, and the multiple target signal lines located on one side of the reference line are spaced apart from each other, the width of the fan-out area along the second direction D2 is positively correlated with the sum of the widths of the target signal lines on either side of the reference line. Since the width of the fan-out area along the second direction D2 is positively correlated with the sum of the widths of the target signal lines on either side of the reference line, the set of target signal lines targeted by method 100 refers to the set of all target signal lines located on one side of the reference line. For example, in Figure 3 In the example, the set of target signal lines is the set of target signal lines 101, 102, and 103 located on the first side of the reference line. The three target signal lines 101, 102, and 103 are numbered respectively; for example, target signal line 101 can be numbered 1, target signal line 102 can be numbered 2, and target signal line 103 can be numbered 3. In some embodiments, target signal lines 101 and 103 can be drive voltage signal lines VLED, which are configured to transmit a first constant voltage signal; target signal line 102 can be a common voltage signal line GND, which is configured to transmit a second constant voltage signal.

[0052] Step S102: Execute steps S103-S107 at least once until the number of target signal lines with unallocated widths in the set is 0.

[0053] The number of times steps S103-S107 are executed is equal to the number of target signal lines. Figure 3 In this embodiment, the number of target signal lines is 3. Therefore, steps S103-S107 are executed 3 times, resulting in 0 target signal lines in the final set to be allocated width. In other words, by repeating steps S103-S107 three times, a corresponding width can be allocated to each of the 3 target signal lines 101, 102, and 103. As explained above, the term "width to be allocated" refers to the line width of the sub-section of the target signal line located in the fan-out region and extending along the first direction D1. For example, in Figure 3 In this context, the width to be allocated for the target signal line 103 refers to the line width of the sub-section 1032 of the target signal line 103 located in the fan-out region and extending along the first direction D1.

[0054] The following describes the operations corresponding to each execution of steps S103-S107.

[0055] First execution of steps S103-S107:

[0056] Step S103: Determine the set of target signal lines whose widths are to be allocated.

[0057] The set of target signal lines whose width is to be allocated is the set consisting of target signal line 101, target signal line 102 and target signal line 103.

[0058] Step S104: Determine the planar region R based on the voltage drop V and temperature rise T of each target signal line with the width to be allocated and the conditions satisfied by the width W of the target signal line with the width to be allocated. The voltage drop V is a function of length L and width W, V(L, W). The length L refers to the length of each target signal line in the sub-section of the fan-out region along the first direction D1, and the width W refers to the width of each target signal line in the sub-section of the fan-out region along the second direction D2. The second direction D2 intersects the first direction D1.

[0059] The target signal line 101 has a length L1 along a first direction D1 and a width W1 to be allocated along a second direction D2 in its fan-out region. The second direction D2 intersects the first direction D1, for example, the second direction D2 is perpendicular to the first direction D1. The target signal line 102 has a length L2 along the first direction D1 and a width W2 to be allocated along the second direction D2 in its fan-out region. The target signal line 103 has a length L3 along the first direction D1 and a width W3 to be allocated along the second direction D2 in its fan-out region. The lengths L1, L2, and L3 are known, while the widths W1, W2, and W3 are unknown and to be allocated. The lengths L1, L2, and L3 can have various suitable values, and the embodiments of this disclosure do not impose specific limitations on them. In some embodiments, the length L1 of the target signal line 101 is approximately 12882 μm, the length L2 of the target signal line 102 is approximately 13010 μm, and the length L3 of the target signal line 103 is approximately 23380 μm.

[0060] refer to Figure 4 It should be noted that the known length L of the target signal line i (i=1, 2, 3) refers to the maximum length of the sub-section of the target signal line located in the fan-out region and extending along the first direction D1 in the first direction D1. The sub-section of the target signal line located in the fan-out region and extending along the first direction D1 is directly connected to the sub-section of the target signal line closest to the bonding region and extending along the second direction D2. The sub-section of the target signal line closest to the bonding region and extending along the second direction D2 is in direct contact and electrically connected to at least one corresponding bonding electrode 104, which extends along the second direction D2. Specifically, with... Figure 4 Taking the target signal line 103 as an example, the length L3 of the sub-part of the target signal line 103 located in the fan-out area and extending along the first direction in the first direction D1 refers to the distance between the first side 1034 and the second side 1035 of the sub-part 1032 of the target signal line 103 located in the fan-out area and extending along the first direction.

[0061] The voltage drop V is a function of length L and width W, V(L, W), and the temperature rise T is also a function of length L and width W, T(L, W). In some embodiments, the step of determining the planar region R based on the voltage drop V and temperature rise T of each of the target signal lines to be allocated width and the condition satisfied by the width W of the target signal lines to be allocated width may include the following sub-step: based on the voltage drop V(L, W) of each of the target signal lines 101, 102, 103 being less than a voltage drop threshold V limit The temperature rise T(L, W) of each of the target signal lines 101, 102, and 103 is less than the temperature rise threshold T. limitThe sum of the widths W of the target signal lines 101, 102, and 103 is less than the dynamic width threshold W. allow1 The system of inequalities constitutes the planar region R. This system of inequalities can be expressed as follows: It can be seen that the planar region R defined by this system of inequalities is a two-dimensional planar region bounded by L and W, which are regions defined by L and W within a certain numerical range. In this system of inequalities, i takes the values ​​1, 2, and 3, and j takes the values ​​1, 2, and 3. i (L i W i The values ​​(L1, W1) represent the temperature rise of target signal line i. For example, T1(L1, W1) represents the temperature rise of target signal line i (i.e., target signal line 101), T2(L2, W2) represents the temperature rise of target signal line i (i.e., target signal line 102), and T3(L3, W3) represents the temperature rise of target signal line i (i.e., target signal line 103). Similarly, V1(L1, W1) represents the voltage drop of target signal line i (i.e., target signal line 101), V2(L2, W2) represents the voltage drop of target signal line i (i.e., target signal line 102), and V3(L3, W3) represents the voltage drop of target signal line i (i.e., target signal line 103).

[0062] The temperature rise T(L, W) involves numerous electrical and thermal parameters, and its physical model is quite complex. In some embodiments, the temperature rise T(L, W) of each target signal line satisfies the following formula: T(L, W) = {(1 / (L*W*X)} Y ) / (I / C)} 1 / Q Where I is the current transmitted through each target signal line, in mA, and X, Y, C, and Q are all constants. Temperature rise threshold T limit This indicates the upper limit of the allowable temperature rise. Its value is related to factors such as structural thermal expansion and product specifications, and may vary in different projects. Temperature rise threshold T limit The temperature range is typically 10–20°C. In some embodiments, T limit It equals 15℃.

[0063] In some embodiments, the voltage drop V(L, W) of each target signal line satisfies the following formula: V(L, W) = E + F * L / W, where E and F are constants. Figure 4As shown, the wiring substrate 200 also includes a functional area, which comprises multiple partitions arranged in an array. These partitions are arranged in a multi-row, multi-column configuration. Each partition can contain a light-emitting element and a driving circuit electrically connected to that light-emitting element. Each of the target signal lines 101, 102, and 103 is arranged in both the functional area and the fan-out area. Within the functional area, at least one target signal line 101, 102, or 103 is arranged in each column of partitions. Furthermore, the voltage drop V(L, W) of each target signal line can satisfy the following formula: R(L, W) is the resistance of the target signal line in the fan-out region. In some embodiments, R(L, W) = R s *L / W, I j =j*I0,I k =k*I0. Let R(L, W) = R s *L / W、I j =j*I0、I k Substituting k*I0 into V(L, W), we get V(L, W) = k*(k+1) / 2*I0*R pixel +k*I0*R s *L / W. R pixel This represents the resistance of the segment corresponding to a single partition on each target signal line, k is the row number of the partition, I0 is the current flowing through a single partition during operation, and R... s Let I be the sheet resistance of each target signal line, which is a measured value. The wiring substrate 200 includes k rows of partitions. The portion of each target signal line located in the functional area extends along the second direction D2 from the first row partition to the kth row partition. Therefore, the portion of each target signal line located in the functional area can be divided into k segments according to the dimensions of a single partition along the second direction D2. The segment corresponding to the first row partition is the first segment, and the segment corresponding to the kth row partition is the kth segment. The current transmitted on each segment is I0, and the segments are connected in parallel with each other. Therefore, I... j This represents the sum of the currents transmitted on the first j segments of each target signal line. Given that the model of the wiring board 200 is already determined, R... pixel ,k,I0,R s All of these can be considered constants. In this case, E = k*(k+1) / 2*I0*R pixel F=k*I0*R s .

[0064] Voltage drop threshold This indicates the upper limit of the permissible voltage drop, the magnitude of which is related to the amplitude of the signal transmitted by the target signal line and its purpose. Different target signal lines may have different limits. For example, the drive voltage signal line VLED and the common voltage signal line GND. Typically, it is approximately 0.5 mV. In some embodiments, It equals 0.45mV.

[0065] In inequalities In the middle, the dynamic width threshold W allow1 This represents the threshold for the sum of the total widths that can be allocated to the three target signal lines 101, 102, and 103, and this threshold needs to be greater than W1 + W2 + W3. allow1 The value is related to factors such as the frame size of the wiring substrate 200, the distance between the light-emitting element and the fan-out area, and the minimum distance between each target signal line. (Reference) Figure 4 W allow1 =H-H1-H2-(H3+H4+H5)-H6, where H represents the distance between the center of the light-emitting element 305 closest to the bonding area in the last row (i.e., the k-th row) partition of the wiring substrate 200 and the side edge 1051 of the substrate 105; H1 represents the length of the bonding electrode 104 along the second direction D2; H2 represents the distance between the first end of the bonding electrode 104 near the side edge 1051 and the side edge 1051; and H3 represents the distance between the sub-part of the target signal line 101 located in the fan-out region and extending along the first direction D1 and the adjacent target signal line 102. The distances between the sub-parts located in the fan-out region and extending along the first direction D1 are as follows: H4 represents the distance between the sub-part of target signal line 102 located in the fan-out region and extending along the first direction D1 and the sub-part of adjacent target signal line 103 located in the fan-out region and extending along the first direction D1; H5 represents the distance between the sub-part of target signal line 103 located in the fan-out region and extending along the first direction D1 and the second end of bonding electrode 104 opposite to the first end; and H6 represents the distance between the center of the light-emitting element 305 in the k-th row partition of the wiring substrate 200 and the boundary of the fan-out region. By setting the spacing between adjacent target signal lines 101 and 102 by distance H3 and between adjacent target signal lines 102 and 103 by distance H4, crosstalk between the signals of each target signal line can be avoided. Furthermore, by setting the spacing between the center of the light-emitting element 305 in the k-th row partition and the boundary of the fan-out region by distance H6, crosstalk between the signals of the target signal lines in the fan-out region and the signals of the light-emitting element 305 can be avoided. allow1 The value of W can be flexibly changed according to product design requirements, and the embodiments disclosed herein do not impose specific limitations on it. In one example, W allow1 It equals 2.8 mm.

[0066] Step S105: Determine the number i of the target signal line with the largest voltage drop among the target signal lines to be allocated width in the set.

[0067] Specifically, step S105 may include the following sub-steps:

[0068] a: Substitute W0 into V(L, W) to obtain V(L, W0), where W0 is the dynamic width threshold W. allow1 Related. In embodiments of this disclosure, W0 can be reasonably valued based on the amplitude of the signal transmitted by the target signal line whose width needs to be allocated and its purpose. Generally, W0 = W allow1 / N, where N is the number of target signal lines of width to be allocated in the set, here N=3. When W0=W allow1 When the value is N, V(L, W0) = k*(k+1) / 2*I0*R pixel +k*I0*R s *L*3 / W allow1 .

[0069] b: Substitute the known length of each target signal line in the set whose width is to be allocated into V(L, W0) to obtain a set of different voltage drops.

[0070] As mentioned earlier, the lengths L1 of the sub-section of target signal line 101 located in the fan-out region and extending along the first direction D1, L2 of the sub-section of target signal line 102 located in the fan-out region and extending along the first direction D1, and L3 of the sub-section of target signal line 103 located in the fan-out region and extending along the first direction D1 are all known. The values ​​of L1, L2, and L3 can be determined based on the amplitude of the signal transmitted by the target signal line, its application, and the design requirements of the product. In this embodiment, L1 is approximately 12882 μm, L2 is approximately 13010 μm, and L3 is approximately 23380 μm. Substituting the values ​​of L1, L2, and L3 into V(L, W0), we can obtain...

[0071] V1(L1, W0) = k*(k+1) / 2*I0*R pixel +k*I0*R s *12882*3 / W allow1 ,

[0072] V2(L2, W0) = k*(k+1) / 2*I0*R pixel +k*I0*R s *13010*3 / W allow1 ,

[0073] V3(L3, W0) = k*(k+1) / 2*I0*R pixel +k*I0*R s *23380*3 / W allow1 .

[0074] In other words, the set includes three different voltage drops, namely V1(L1, W0), V2(L2, W0), and V3(L3, W0).

[0075] c: Select the maximum voltage drop from the set of different voltage drops.

[0076] By comparing V1(L1, W0), V2(L2, W0), and V3(L3, W0), it can be seen that V3(L3, W0) has the largest voltage drop.

[0077] d: Determine the target signal line number i with the maximum voltage drop based on the known length corresponding to the maximum voltage drop.

[0078] The known length corresponding to V3(L3, W0) is L3. Since each target signal line has been assigned a number in step S101, and the length of the fan-out region of each target signal line with the corresponding number is known, the number of the corresponding target signal line can be known through the known length L3. That is, the target signal line with the maximum voltage drop is the target signal line 103 with the number 3.

[0079] Step S106: Substitute the known length L3 of the target signal line numbered 3 into V(L, W) to obtain V(L3, W), that is, V(L3, W) = k*(k+1) / 2*I0*R pixel +k*I0*R s *23380 / W, W3 is obtained based on the intersection of V(L3, W) and the boundary of the planar region R. W3 is the width of the target signal line 103 numbered 3 in the sub-region along the second direction D2 in the fan-out area. In this embodiment, W3 is equal to 1036 μm.

[0080] Step S107: Remove the target signal line 103 with allocated width W3 from the set.

[0081] By executing steps S103-S107 for the first time, the width W3 can be dynamically allocated to the target signal line 103 with the largest voltage drop among the three target signal lines, so that the allocated width W3 is equal to 1036 μm.

[0082] Second execution steps S103-S107:

[0083] Step S103: Determine the set of target signal lines to be allocated width. Since the target signal line 103 with allocated width W3 was removed from the set during the first execution of step S107, the updated set in this step S103 consists of target signal lines 101 and 102.

[0084] Step S104: Determine the updated planar region R' based on the following set of inequalities: Compared to the first execution of step S104, i, j, and W allow1 In this execution of step S104, the values ​​of i are 1 and 2, and the values ​​of j are 1 and 2. allow2 =W allow1 -W1, while keeping the values ​​of other parameters unchanged. This is due to the dynamic width threshold W. allow2 Compared to the dynamic width threshold W allow1 Since changes have occurred, the updated planar region R' determined in step S104 this time has also changed compared to the planar region R determined in step S104 last time. Accordingly, the horizontal and vertical coordinate values ​​(L and W) corresponding to the boundary of the updated planar region R' determined in step S104 this time have also changed compared to the horizontal and vertical coordinate values ​​corresponding to the boundary of the planar region R determined in step S104 last time.

[0085] Step S105: Determine the number i of the target signal line with the maximum voltage drop among target signal lines 101 and 102.

[0086] Specifically, step S105 may include the following sub-steps:

[0087] a: W0 ' Substituting into V(L, W) yields V(L, W0) ' ), W0 ' With dynamic width threshold W allow2 Related, W0 ' =W allow2 / (N-1), i.e., W0 ' =W allow2 / 2. Move W0 ' =W allow2 Substituting / 2 into V(L, W), we can obtain V(L, W0). ' )=k*(k+1) / 2*I0*R pixel +k*I0*R s *L*2 / W allow2 .

[0088] b: Substitute the known length L1 of target signal line 101 and the known length L2 of target signal line 102 into V(L, W0) respectively. ' The set of different voltage drops is obtained by substituting the values ​​of L1 and L2 into V(L, W0) and W0 respectively. L1 is approximately 12882 μm, and L2 is approximately 13010 μm. ' From ), we can obtain

[0089] V1(L1, W0) ')=k*(k+1) / 2*I0*R pixel +k*I0*R s *12882*2 / W allow2 ,

[0090] V2(L2, W0) ' )=k*(k+1) / 2*I0*R pixel +k*I0*R s *13010*2 / W allow2 In other words, the set includes two different voltage drops, namely V1(L1, W0). ' ) and V2(L2, W0 ' ).

[0091] c: By comparing V1(L1, W0) ' ) and V2(L2, W0 ' It can be deduced that V2(L2, W0) is the largest of the two. ' The voltage drop is the largest.

[0092] d: Based on the maximum voltage drop V2(L2, W0) ' The known length L2 corresponding to the target signal line is used to determine that the target signal line with the largest voltage drop is number 2. That is, among the target signal lines 101 and 102, the target signal line with the largest voltage drop is the target signal line 102 numbered 2.

[0093] Step S106: Substitute the known length L2 of the target signal line 102 (numbered 2) into V(L, W) to obtain V2(L2, W), that is...

[0094] V2(L2, W) = k*(k+1) / 2*I0*R pixel +k*I0*R s *13010 / W, W2 is obtained based on the intersection of V2(L2, W) and the boundary of the updated planar region R'. W2 is the width of the sub-section of target signal line 102 numbered 2, located in the fan-out region and extending along the first direction, along the second direction D2. In this embodiment, W2 is equal to 710 μm.

[0095] Step S107: Remove the target signal line 102 with allocated width W2 from the set.

[0096] By executing steps S103-S107 for the second time, the width W2 can be dynamically allocated to the target signal line 102 with the largest voltage drop among the remaining two target signal lines 101 and 102 in the set, so that the allocated width W2 is equal to 710 μm.

[0097] The third execution steps S103-S107:

[0098] Step S103: Determine the set of target signal lines to be allocated width. Since the target signal line 102 with allocated width W2 was removed from the set during the second execution of step S107, the updated set in this step S103 only includes target signal line 101.

[0099] Step S104: Determine the updated planar region R'' based on the following set of inequalities: Compared to the first execution of step S104, i, j, and W allow1 In the current execution of step S104, the value of i is 1, the value of j is 1, and the value of W is... allow3 =W allow1 -W1-W2, while the values ​​of other parameters remain unchanged. This is due to the dynamic width threshold W. allow3 Compared to the dynamic width threshold W allow1 and W allow2 All of these have changed. Therefore, the updated planar region R'' determined in step S104 this time has changed compared to the planar region R determined in the first step S104 and the planar region R' determined in the second step S104. Correspondingly, the horizontal and vertical coordinate values ​​(L and W) corresponding to the boundaries of the updated planar region R'' determined in step S104 this time have also changed compared to the horizontal and vertical coordinate values ​​corresponding to the boundaries of the planar region R determined in the first step S104 and the planar region R' determined in the second step S104. It can be seen that the dynamic width threshold is a dynamic value associated with the number of times method 100 is executed (or the number of target signal lines), rather than a constant. During the first execution of steps S103-S107, W allow1 It equals the initial value of 2.8 mm. During the second execution of steps S103-S107, W... allow2 =W allow1 -W1. During the third execution of steps S103-S107, W allow3 =W allow1 -W1-W2, and so on. Where n is a positive integer greater than or equal to 1 and less than or equal to N, N is the number of target signal lines, and W allown This represents the dynamic width threshold selected when executing step S104 for the nth time.

[0100] Step S105: Determine the number i of the target signal line 101.

[0101] Specifically, step S105 may include the following sub-steps:

[0102] a: W0 '' Substituting into V(L, W) yields V(L, W0) ''), W0 '' With dynamic width threshold W allow3 Related, W0 '' =W allow3 / (N-2), i.e., W0 '' =W allow3 W0 '' =W allow3 Substituting into V(L, W), we can obtain V(L, W0). '' )=k*(k+1) / 2*I0*R pixel +k*I0*R s *L / W allow3 .

[0103] b: Substitute the known length L1 of the target signal line 101 into V(L, W0) '' The voltage drop set is obtained from the input, L1 is approximately 12882 μm. Substituting the value of L1 into V(L, W0)... '' From this, we can obtain V1(L1, W0). '' )=k*(k+1) / 2*I0*R pixel +k*I0*R s *12882 / W allow3 In other words, the set includes only one voltage drop, namely V1(L1, W0). ''' ).

[0104] d: Based on the voltage drop V1(L1, W0) ''' The known length L1 corresponding to the target signal line determines the target signal line number as 1, that is, the target signal line to be allocated width is the target signal line 101 numbered 1.

[0105] Step S106: Substitute the known length L1 of the target signal line 101 (numbered 1) into V(L, W) to obtain V1(L1, W), i.e., V(L1, W) = k*(k+1) / 2*I0*R pixel +k*I0*R s *12882 / W, W1 is obtained based on the intersection of V1(L1, W) and the boundary of the updated planar region R'', where W1 is the width of the sub-section of target signal line 101 numbered 1 located in the fan-out region and extending along the first direction along the second direction D2. In this embodiment, W1 is equal to 710 μm.

[0106] Step S107: Remove the target signal line 101 with allocated width W1 from the set.

[0107] By executing steps S103-S107 for the third time, the width W1 can be dynamically allocated to the remaining target signal lines 101 in the set, such that the allocated width W1 is equal to 710 μm.

[0108] At this point, the number of target signal lines with unassigned widths in the set becomes 0, and the step ends.

[0109] refer to Figure 1 In related technologies, the width G1 of the fan-out portion of signal line 11 in the second direction D2 is equal to 810 μm, the width G2 of the fan-out portion of signal line 12 in the second direction D2 is equal to 810 μm, and the width G3 of the fan-out portion of signal line 13 in the second direction D2 is equal to 836 μm. G1, G2, and G3 are approximately equal, and G1 + G2 + G3 = 2456 μm. The voltage drop of signal line 13 is much greater than that of signal lines 11 and 12 and exceeds the voltage drop threshold. The overall voltage drop level of the wiring substrate 10 is limited by the voltage drop of the signal line 13. However, the method 100 provided in this embodiment dynamically allocates widths for the three target signal lines 101, 102, and 103, such that the width W3 of the sub-part of the target signal line 103 with the largest voltage drop, located in the fan-out region and extending along the first direction, in the second direction D2 is equal to 1036 μm; the width W2 of the sub-part of the target signal line 102 with the intermediate voltage drop, located in the fan-out region and extending along the first direction, in the second direction D2 is equal to 710 μm; and the width W3 of the sub-part of the target signal line 101 with the smallest voltage drop, located in the fan-out region and extending along the first direction, in the second direction D2 is equal to 710 μm. W1 + W2 + W3 = 2456 μm, which is the same as the sum of G1 + G2 + G3 in the related art. Compared to related technologies, without increasing the width of the fan-out area, widening the border, or increasing the thickness of the target signal lines, the widths of the sub-sections of the three target signal lines 101, 102, and 103 located in the fan-out area and extending along the first direction vary according to their respective lengths and voltage drops, and the three no longer have uniform widths. Through this method 100, the width W3 of the target signal line 103 with the largest voltage drop is significantly increased. Compared to the signal line 13 in related technologies, the voltage drop of the target signal line 103 is significantly reduced and falls below the voltage drop threshold. Additionally, it should be noted that, compared to related technologies, although the voltage drop of target signal lines 101 and 102 is slightly increased due to the slightly increased width of the fan-out region, the overall voltage drop level of the wiring substrate 200 is limited by the maximum voltage drop. The voltage drop value of target signal line 103, which has the maximum voltage drop, is lower than that of signal line 13 in related technologies and is below the voltage drop threshold. Therefore, the overall voltage drop level of the wiring board 200 has been significantly improved.

[0110] In some embodiments, the linewidth of the sub-section of the target signal line extending along the first direction D1 in the fan-out region is positively correlated with the distance between the sub-section of the target signal line located in the fan-out region and extending along the second direction D2, and closest to the functional area, and the reference line. In an alternative embodiment, among multiple target signal lines located on the same side of the reference line, at least two target signal lines exist, wherein the distance between the first target signal line located at the boundary between the functional area and the fan-out region and the reference line is greater than the distance between the second target signal line located at the boundary between the functional area and the fan-out region and the reference line, and the linewidth of the sub-section of the first target signal line extending along the first direction D1 in the fan-out region is at least 1.5 times the linewidth of the sub-section of the second target signal line extending along the first direction D1 in the fan-out region, for example, it can be 1.8 times, 2 times, 3 times, 3.5 times, etc. Specifically, taking target signal lines 102 and 103 as examples, the distance between the position of target signal line 103 at the junction of the functional area and the fan-out area and the reference line is greater than the distance between the position of target signal line 102 at the junction of the functional area and the fan-out area and the reference line. The line width W3 of the sub-section of target signal line 103 extending along the first direction D1 in the fan-out area is equal to 1036 μm, and the line width W2 of the sub-section of target signal line 102 extending along the first direction D1 in the fan-out area is equal to 710 μm. W3 is about 1.5 times that of W2.

[0111] Figure 3 and Figure 4 The steps of method 100 are described using the example of the number of target signal lines N equal to 3. However, as mentioned above, the number of target signal lines N can be any suitable value, and the embodiments of this disclosure do not specifically limit this.

[0112] Figure 5 A partial planar schematic diagram of the wiring substrate 300 is shown, illustrating multiple target signal lines that transmit electrical signals to four columns of partitions. These target signal lines are connected to the same circuit board 106 in a bonding area, which contains multiple spaced bonding electrodes. Figure 5 The diagram shows four columns of partitions in a wiring substrate 300. In some embodiments, the wiring substrate 300 includes multiple such repeating units, with each of these four columns considered as a repeating unit. Figure 5As shown, the center line of circuit board 106 parallel to the second direction D2 is used as a reference line. The first side of the reference line has a C-th partition and a C+1-th partition, and the second side has a C+2-th partition and a C+3-th partition. Signal lines located on the first side of the reference line are electrically connected to circuit board 106 on the first side, and signal lines located on the second side of the reference line are electrically connected to circuit board 106 on the second side. Since the width of the fan-out area along the second direction D2 is positively correlated with the sum of the widths of the target signal lines on either side of the reference line, the set of target signal lines targeted by method 100 refers to the set of all target signal lines located on one side of the reference line. For example, in... Figure 5 In the example, the set of target signal lines is the set of target signal lines 301, 302, 303, and 304 located on the first side of the reference line. It should be noted that, as... Figure 5As shown, although six signal lines are arranged on the first side of the reference line, signal lines 305 and 306, located in column C+1, are very close to the reference line. Therefore, signal lines 305 and 306 are connected to the circuit board 106 in a nearly straight line manner. That is, signal lines 305 and 306 have almost no sub-sections extending along the first direction D1 in the fan-out area. Therefore, it can be considered that the length of the sub-section of signal line 305 extending along the first direction D1 in the fan-out area is 0, and the length of the sub-section of signal line 306 extending along the first direction D1 in the fan-out area is also 0. Therefore, according to the previous definition, signal lines 305 and 306 are non-target signal lines. Signal lines 301-304, on the other hand, each include sequentially connected sub-sections extending along the first direction D1 and sub-sections extending along the second direction D2 in the fan-out area, and all signal lines 301-304 transmit electrical signals of constant amplitude. Therefore, signal lines 301-304 are target signal lines. Target signal lines 301, 302, and 303 are arranged in column C, and target signal line 304 is arranged in column C+1. That is, there are four target signal lines arranged on the first side of the reference line. These four target signal lines 301, 302, 303, and 304 are numbered respectively. For example, target signal line 301 can be numbered 1, target signal line 302 can be numbered 2, target signal line 303 can be numbered 3, and target signal line 304 can be numbered 4. In some embodiments, target signal lines 301 and 304 may be drive voltage signal lines VLED, target signal line 301 is configured to provide a first constant voltage to the light-emitting unit 601 in the Cth column partition, and target signal line 304 is configured to provide a third constant voltage to the light-emitting unit 601 in the C+1th column partition; target signal line 302 may be a power supply voltage signal line Pwr, and target signal line 302 is electrically connected to the power supply terminal of the drive circuit (not shown) in the Cth column partition; target signal line 303 may be a common voltage signal line GND, and target signal line 303 is configured to provide a second constant voltage (e.g., ground voltage) to the drive circuit in the Cth column partition.

[0113] Method 100 is also applicable to... Figure 5 The target signal lines are shown to be assigned widths. For example, the widths of target signal lines 301-304 can be assigned respectively by the following steps:

[0114] Step S101: Number the four target signal lines 301-304 as 1-4 respectively;

[0115] Step S102: Execute steps S103-S107 four times until the number of target signal lines with unallocated widths in the set is 0;

[0116] Step S103: Determine the set of target signal lines whose widths to be allocated;

[0117] Step S104: Determine the planar region R based on the voltage drop V and temperature rise T of each target signal line with the width to be allocated and the conditions satisfied by the width W of the target signal line with the width to be allocated. The voltage drop V is a function of length L and width W, V(L, W). The length L refers to the length of each target signal line in the sub-section of the fan-out region along the first direction D1, and the width W refers to the width of each target signal line in the sub-section of the fan-out region along the second direction D2. The second direction D2 intersects the first direction D1.

[0118] Step S105: Determine the number i of the target signal line with the largest voltage drop among the target signal lines to be allocated width in the set;

[0119] Step S106: The known length L of the target signal line numbered i i Substitute into V(L, W) to obtain V(L) i W), based on V(L) i The intersection of W) with the boundary of the planar region R yields W. i W i The width of the sub-section of the target signal line numbered i, located in the fan-out region and extending along the first direction, along the second direction D2;

[0120] Step S107: Remove the allocated width W from the set. i The target signal line.

[0121] For detailed instructions on each step in steps S103-S107, please refer to the relevant documentation. Figure 2-4 For the sake of brevity, the description will not be repeated here. It is important to note that... Figure 5 The initial dynamic width threshold W corresponding to the embodiment allow1 It equals 3.4 mm.

[0122] like Figure 5As shown, the sub-section of target signal line 301 located in the fan-out region and extending along the first direction has a known length L4 along the first direction D1, which is 20100 μm; the sub-section of target signal line 302 located in the fan-out region and extending along the first direction has a known length L5 along the first direction D1, which is 9730 μm; the sub-section of target signal line 303 located in the fan-out region and extending along the first direction has a known length L6 along the first direction D1, which is 11840 μm; and the sub-section of target signal line 304 located in the fan-out region and extending along the first direction has a known length L7 along the first direction D1, which is 9720 μm. The method 100 described above allocates widths to the fan-out regions and extending along the first direction of the target signal lines 301-304, such that the width W4 of the fan-out region and extending along the first direction of target signal line 301 in the second direction D2 is equal to 996 μm, the width W5 of the fan-out region and extending along the first direction of target signal line 302 in the second direction D2 is equal to 200 μm, the width W6 of the fan-out region and extending along the first direction of target signal line 303 in the second direction D2 is equal to 776 μm, and the width W7 of the fan-out region and extending along the first direction of target signal line 304 in the second direction D2 is equal to 690 μm. Among the target signal lines 301-304, target signal line 301 has the largest voltage drop, therefore its allocated width W4 is the maximum value among W1-W4.

[0123] Compared to related technologies, without increasing the width of the fan-out area, widening the border, or increasing the thickness of the target signal lines, this method allows the widths of the sub-sections of the four target signal lines 301, 302, 303, and 304 located in the fan-out area and extending along the first direction to have differentiated values ​​based on their respective lengths and voltage drops, instead of having uniform widths. Through this method 100, the width W4 of the target signal line 301 with the largest voltage drop is significantly increased, thereby significantly reducing the voltage drop of the target signal line 301 and bringing it below the voltage drop threshold. This significantly improves the overall voltage drop level of the wiring board 300.

[0124] In other embodiments not described, there may be situations where two adjacent columns share one (or several) signal lines. In this case, the number of target signal lines will be reduced accordingly.

[0125] According to another aspect of this disclosure, a wiring substrate is provided, with reference to Figures 3-5The wiring substrate includes: a substrate 105 including a fan-out region; at least one target signal line located on the substrate 105 and at least within the fan-out region, each of the at least one target signal line having a sub-portion located in the fan-out region and extending along a first direction having a length L along the first direction D1, each of the at least one target signal line having a sub-portion located in the fan-out region and extending along the first direction having a width W along a second direction D2, the second direction D2 intersecting the first direction D1, and the width W of each target signal line being determined according to the method 100 described in any of the preceding embodiments.

[0126] Within the fan-out region of the wiring substrate 200, multiple signal lines are typically arranged. Among these signal lines, some transmit digital signals and have low resistance requirements; the dimensional design of these signal lines within the fan-out region is outside the scope of this disclosure, and they are termed "non-target signal lines." Other signal lines, transmitting electrical signals with constant amplitude (e.g., constant voltage or constant current), have dimensional parameters that significantly impact the overall voltage drop level of the wiring substrate 200; the width of these signal lines within the fan-out region is within the scope of this disclosure, and they are termed "target signal lines" herein. In some embodiments, such as... Figure 3 and Figure 4 As shown, the target signal lines include a drive voltage signal line VLED and a common voltage signal line GND. For example, target signal lines 101 and 103 can be drive voltage signal lines VLED, and target signal line 102 can be the common voltage signal line GND. Target signal lines 101 and 102 can be located within the same column partition, and target signal line 103 can be located within a partition of an adjacent column. In alternative embodiments, such as... Figure 5 As shown, the target signal lines include a drive voltage signal line VLED, a power supply voltage signal line PWR, and a common voltage signal line GND. For example, target signal line 301 can be the drive voltage signal line VLED, target signal line 302 can be the power supply voltage signal line PWR, and target signal line 303 can be the common voltage signal line GND. Target signal lines 301, 302, and 303 are located within the C-th column partition. Target signal line 304 can be the drive voltage signal line VLED, and target signal line 304 is located within the C+1-th column partition. Target signal line 301 is configured to provide a first constant voltage to the light-emitting unit 601 within the C-th column partition, and target signal line 304 is configured to provide a first constant voltage to the light-emitting unit 601 within the C+1-th column partition. Target signal line 302 is connected to the power supply terminal of the drive circuit (not shown) within the C-th column partition. Target signal line 303 is configured to provide a second constant voltage (e.g., ground voltage) to the drive circuit within the C-th column partition.

[0127] like Figure 4As shown, in some embodiments, the wiring substrate further includes bonding electrodes 104 disposed in the fan-out region, and the portion of each target signal line located in the fan-out region is electrically connected to at least two bonding electrodes 104.

[0128] The number of target signal lines is N, where N is a positive integer greater than or equal to 2. The fan-out regions of these N target signal lines, extending along the first direction D1, have N linewidths. As described earlier, the largest of the N linewidths corresponds to the target signal line with the largest voltage drop among the N target signal lines. Since the overall voltage drop level of the wiring substrate is limited by the maximum voltage drop, by making the target signal line with the largest voltage drop have the largest linewidth in its fan-out region, the voltage drop of that target signal line can be significantly reduced, causing its voltage to drop below the voltage drop threshold. This can significantly improve the overall voltage drop level of the wiring board.

[0129] The technical effects of the wiring substrate can be referred to the technical effects of the method 100 described in the previous embodiments. For the sake of brevity, the technical effects of the wiring substrate will not be described again here.

[0130] According to another aspect of this disclosure, a light-emitting substrate is provided. Figure 6 A planar schematic diagram of a light-emitting substrate 600 is shown. The light-emitting substrate 600 includes: a wiring substrate as described in any of the preceding embodiments, the substrate 105 of the wiring substrate further including a functional region, the functional region including a plurality of partitions P arranged in an array, the term "functional region" refers to an area on the substrate 105 used for arranging functional components (e.g., light-emitting elements); a plurality of light-emitting elements arranged in the plurality of partitions P within the functional region; and a circuit board 603 arranged in the fan-out region.

[0131] like Figure 6As shown, the functional area of ​​the light-emitting substrate 600 is arranged with multiple partitions, each dashed rectangle representing a partition P. Each partition P contains a light-emitting unit 601, and optionally, a driving circuit 602 electrically connected to the light-emitting unit 601. The driving circuit 602 can control the light-emitting performance of the light-emitting unit 601. In some embodiments, each light-emitting unit 601 may include multiple light-emitting units, which can be connected in series, in parallel, or in a series-parallel combination. Each light-emitting unit may be composed of at least one light-emitting element such as a light-emitting diode (LED), a sub-millimeter light-emitting diode (Mini LED), or a micro light-emitting diode (Micro LED). When the light-emitting element is a Mini LED or a Micro LED, it has a smaller size than an LED, thus allowing each partition P of the light-emitting substrate 600 to have a smaller size or more space for signal line wiring on the light-emitting substrate 600. Each light-emitting unit 601 within each partition P can be individually addressed and powered, thereby making the light-emitting brightness of the light-emitting substrate 600 more precise. Compared to traditional light-emitting substrates, the light-emitting substrate 600 using Mini LEDs or Micro LEDs as the light source can achieve local dimming within a smaller area, thereby achieving better brightness uniformity, higher color contrast, and a thinner and lighter product form. When this wiring substrate 600 is applied to a display device, the display effect of the display device is comparable to that of an OLED display device, but the cost is only about 60% of that of an OLED display device, while the product's lifespan is significantly improved compared to an OLED display device.

[0132] Figure 6 The example shown is a k-row * 3-column partition, which is only a partial schematic diagram of the light-emitting substrate 600. In fact, as those skilled in the art will know, the light-emitting substrate 600 should include multi-row * multi-column partitions. Figure 6As shown, each column partition has two target signal lines. The first column partition has target signal lines 108 and 109. Target signal line 108 is electrically connected to all light-emitting units 601 within the first column partition; target signal line 108 can be a driving voltage signal line VLED. Target signal line 109 is electrically connected to all driving circuits 602 within the first column partition; target signal line 109 can be a common voltage signal line GND. Similarly, the second column partition has target signal lines 101 and 107. Target signal line 101 is electrically connected to all light-emitting units 601 within the second column partition; target signal line 101 can be a driving voltage signal line VLED. Target signal line 107 is electrically connected to all driving circuits 602 within the second column partition; target signal line 107 can be a common voltage signal line GND. The third column partition contains target signal lines 102 and 103. Target signal line 103 is electrically connected to all light-emitting units 601 within the third column partition, and target signal line 103 can be a driving voltage signal line VLED. Target signal line 102 is electrically connected to all driving circuits 602 within the third column partition, and target signal line 102 can be a common voltage signal line GND. Each of target signal lines 101, 102, 103, 107, 108, and 109 is arranged within the functional area and the fan-out area. Within the functional area, each of the target signal lines 101, 102, 103, 107, 108, and 109 extends substantially in a straight line along the second direction D2; within the fan-out area, each of the target signal lines 101, 102, 103, 107, 108, and 109 includes a sub-section extending along the first direction D1, and each sub-section of the target signal line has a length L along the first direction and a width W along the second direction D2 as described above. For example, the length L1 of the sub-part of target signal line 101 located in the fan-out region and extending along the first direction D1 in the first direction D1 is approximately 12882 μm, and the width W1 of the sub-part of target signal line 101 located in the fan-out region and extending along the first direction D1 in the second direction D2 is approximately 710 μm; the length L2 of the sub-part of target signal line 102 located in the fan-out region and extending along the first direction D1 in the first direction D1 is approximately 13010 μm, and the width W2 of the sub-part of target signal line 102 located in the fan-out region and extending along the first direction D1 in the second direction D2 is approximately 710 μm; the length L3 of the sub-part of target signal line 103 located in the fan-out region and extending along the first direction D1 in the first direction D1 is approximately 23380 μm, and the width W3 of the sub-part of target signal line 103 located in the fan-out region and extending along the first direction D1 in the second direction D2 is approximately 1036 μm.Compared to related technologies, without increasing the width of the fan-out area, widening the border, or increasing the thickness of the target signal lines, the widths of the three target signal lines 101, 102, and 103 in the fan-out area vary depending on their respective lengths and voltage drops within the fan-out area, instead of having uniform widths. The width W3 of the target signal line 103 with the largest voltage drop is the maximum value among W1, W2, and W3. Compared to related technologies, the voltage drop of the target signal line 103 is significantly reduced and falls below the voltage drop threshold V. limit Furthermore, since the overall voltage drop level of the light-emitting substrate 600 is limited by the maximum voltage drop, while the voltage drop of the target signal line 103 has been significantly reduced, the overall voltage drop level of the light-emitting substrate 600 has actually been significantly improved.

[0133] like Figure 6 As shown, target signal lines 101, 102, 103, 107, 108, and 109 are electrically connected to the same circuit board 603 via multiple bonding electrodes 104. In some embodiments, the circuit board 603 may be a chip-on-film (COP) film. Using the center line of the circuit board 603 parallel to the second direction D2 as a reference line, target signal lines 101, 102, and 103 located on the first side of the reference line are electrically connected to the circuit board 603 via bonding electrodes 104 on the first side of the reference line, and target signal lines 107, 108, and 109 located on the second side of the reference line are electrically connected to the circuit board 603 via bonding electrodes 104 on the second side of the reference line. Although... Figure 6 Although not shown in the diagram, the fan-out area of ​​the light-emitting substrate 600 may also include a flexible printed circuit board (FPC) and a printed circuit board (PCBA). One end of the FPC is connected to the circuit board 603, and the other end of the FPC is connected to the PCBA. Control signals from the IC on the PCBA are transmitted to the bonding electrode 104 via the FPC and the circuit board 603. The sub-parts of multiple target signal lines (e.g., target signal lines 101, 103, 108) on the light-emitting substrate 600 located in the fan-out area are bonded to the bonding electrode 104, and the portions of the multiple target signal lines (e.g., target signal lines 101, 103, 108) on the light-emitting substrate 600 located in the functional area are electrically connected to the light-emitting unit 601. Therefore, control signals from the IC on the PCBA can be transmitted to the light-emitting unit 601 via the target signal lines to control the light-emitting unit 601 to emit light.

[0134] Although Figure 6 The example described is that target signal line 101 is located in the second column partition while target signal lines 102 and 103 are located in the adjacent third column partition. However, this is just an example. The position of the target signal line can be flexibly changed according to the product design requirements and the amplitude and purpose of the signal transmitted by the target signal line.

[0135] Other technical effects of the light-emitting substrate 600 can be referred to the previous section on the technical effects of method 100. For the sake of brevity, the technical effects of the light-emitting substrate 600 will not be described again here.

[0136] According to another aspect of this disclosure, a display device is provided. Figure 7 A block diagram of a display device 700 is shown, which includes a wiring substrate or a light-emitting substrate as described in any of the preceding embodiments. In some embodiments, the display device 700 may be a liquid crystal display device, which includes a liquid crystal panel and a backlight disposed on the non-display side of the liquid crystal panel. The backlight includes the wiring substrate described in any of the preceding embodiments, and the backlight may be used to implement HDR dimming for display operation. The liquid crystal display device may have more uniform backlight brightness and better display contrast. The display device 700 may be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, navigators, e-readers, and any other products or components with display functions.

[0137] Since the display device 700 can have essentially the same technical effects as the wiring substrate or light-emitting substrate described in the preceding embodiments, for the sake of brevity, the technical effects of the display device 700 will not be described again here.

[0138] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed above may be referred to as a second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0139] Spatial relative terms such as “row,” “column,” “below,” “above,” “left,” “right,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary term “below” can cover both orientations above and below. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as “between two layers,” it may be the only layer between those two layers, or there may be one or more intermediate layers.

[0140] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. In the description of this specification, references to the terms “one embodiment,” “another embodiment,” etc., mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. The illustrative expressions of the foregoing terms in this specification do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples, without contradiction.

[0141] It will be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," it may be directly on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or directly adjacent to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "directly adjacent to another component or layer," no intermediate components or layers exist. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

[0142] Embodiments of this disclosure are described herein with reference to illustrative illustrations (and intermediate structures) of idealized embodiments. Therefore, variations in the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations due to manufacturing processes. Thus, the regions illustrated are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of this disclosure.

[0143] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0144] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for allocating width to a target signal line, comprising: Each target signal line is numbered individually. Perform the following steps at least once until the number of target signal lines of unassigned width in the set is 0: Determine the set of target signal lines whose widths are to be allocated; The planar region R is determined based on a set of inequalities consisting of the voltage drop V of each of the target signal lines to be allocated being less than a voltage drop threshold, the temperature rise T of each of the target signal lines to be allocated being less than a temperature rise threshold, and the sum of the widths W of the target signal lines to be allocated being less than a dynamic width threshold. The voltage drop V is a function of length L and width W, namely V(L, W), and the temperature rise T is a function of length L and width W, namely T(L, W). The length L refers to the length of the sub-section of each target signal line located in the fan-out region and extending along the first direction along the first direction, and the width W refers to the width of the sub-section of each target signal line located in the fan-out region and extending along the first direction along the second direction, which intersects the first direction. Substitute W0 into V(L, W) to obtain V(L, W0), where W0 is associated with the dynamic width threshold. Substitute the known length of each target signal line in the set whose width is to be allocated into V(L, W0) to obtain a set of different voltage drops; Select the largest voltage drop from the set of different voltage drops; The number i of the target signal line with the maximum voltage drop is determined based on the known length corresponding to the maximum voltage drop. The known length L of the target signal line numbered i i Substitute into V(L, W) to obtain V(L) i W), based on V(L) i The intersection of W) with the boundary of the planar region R is obtained by... i The W i The width of the sub-section of the target signal line numbered i, located in the fan-out region and extending along the first direction, along the second direction; as well as Remove the allocated width W from the set. i The target signal line.

2. The method according to claim 1, wherein, The number of target signal lines is N, where N is a positive integer greater than or equal to 2. The N target signal lines have N widths, and the width of the target signal line with the largest voltage drop among the N target signal lines is the maximum value among the N widths.

3. The method according to claim 1 or 2, wherein, The voltage drop V(L, W) of each target signal line satisfies the following formula: V(L, W) = E + F * L / W, where E and F are constants.

4. The method according to claim 3, wherein, ， The target signal line is also arranged in a functional area, which includes multiple partitions arranged in an array, R pixel For each target signal line, the resistance of the corresponding segment of a single partition is given, where k is the number of rows in the partition, and I... j =j*I0,I k =k*I0, where I0 is the current in a single partition.

5. The method according to claim 4, wherein, R(L, W) = R s *L / W, R s The sheet resistance of the target signal line is E = k*(k+1) / 2*I0*R pixel F=k*I0*R s .

6. The method according to claim 1 or 2, wherein, The temperature rise T(L, W) of each target signal line satisfies the following formula: T(L, W) = [(1 / (L*W*X)] Y ) / (I / C)] 1 / Q Where I is the current transmitted on each target signal line, and X, Y, C, and Q are all constants.

7. A wiring substrate, comprising: Substrate, including the fan-out region; At least one target signal line is located on the substrate and at least within the fan-out region. Each of the at least one target signal line has a sub-portion located in the fan-out region and extending along a first direction having a length L along the first direction. The sub-portion located in the fan-out region and extending along the first direction has a width W along a second direction, which intersects the first direction. The width W of each target signal line is determined by the method according to any one of claims 1-6.

8. The wiring substrate according to claim 7, wherein, The number of target signal lines is N, where N is a positive integer greater than or equal to 2. The N target signal lines have N widths, and the width of the target signal line with the largest voltage drop among the N target signal lines is the maximum value among the N widths.

9. The wiring substrate according to claim 7, further comprising bonding electrodes disposed within the fan-out region, wherein, Each target signal line is electrically connected to at least two bonded electrodes.

10. The wiring substrate according to any one of claims 7-9, wherein, The target signal line includes at least one of the following: a drive voltage signal line, a common voltage signal line, and a power supply voltage signal line.

11. A light-emitting substrate, comprising: The wiring substrate according to any one of claims 7-10, wherein the substrate further includes a functional region, the functional region comprising a plurality of partitions arranged in an array; Multiple light-emitting elements are arranged in multiple partitions within the functional area; and The circuit board is arranged within the fan-out area.

12. The light-emitting substrate according to claim 11, wherein, The multiple partitions are arranged in multiple rows and columns. The number of target signal lines is N, where N is a positive integer greater than or equal to 2. The N target signal lines are also arranged in the functional area along the second direction. The N target signal lines are located in the same column partition or in adjacent M column partitions, where M is a positive integer greater than or equal to 2.

13. The light-emitting substrate according to claim 12, wherein, The circuit board includes a flip-chip film, and the N target signal lines are electrically connected to the same circuit board via bonding electrodes.

14. The light-emitting substrate according to any one of claims 11-13, wherein, Each of the plurality of light-emitting elements includes a sub-millimeter light-emitting diode.

15. A display device comprising a wiring substrate according to any one of claims 7-10 or a light-emitting substrate according to any one of claims 11-14.

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