A method for rapid data exchange between real-time and time-sharing systems

Abstract

A method for rapid data exchange between real-time and time-sharing systems. Different cores on a single processor work together to share hardware resources equally, improving overall system performance and efficiency. This not only meets real-time requirements and a large number of application computing requirements, but also reduces investment costs. A simple shared memory and signal notification mechanism is used between multi-core systems to increase data transmission bandwidth and efficiency, while also taking into account real-time and large data volume requirements. Real-time data processing and high-bandwidth data transmission are met. Through address bus communication, FPGAs can process large amounts of data in parallel and in real time, accelerating the data transmission process. The number of memory copies from kernel mode to user mode is reduced, eliminating unnecessary duplication during data transmission, thereby improving performance and reducing resource usage. A high-speed, large-capacity, real-time data interaction method is designed for the entire process, from data reception to processor processing, operating from the same memory area from start to finish.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a method for rapid data exchange between real-time and time-sharing systems. Background Art

[0002] Currently, in a wide range of applications, such as industry and power generation, transient and steady-state responses require real-time control and application computing, which are respectively hosted by the real-time system of the real-time core and the time-sharing system of the computing core. However, bottlenecks and shortcomings exist in the data transmission and exchange performance between the real-time system (task preemption) and the time-sharing system (task non-preemption), which restricts the real-time processing. The shortcomings are as follows:

[0003] Communication bottlenecks between systems: The communication network between systems is limited by the communication architecture and protocols. Network congestion, routing issues, and distance can cause delays and jitter, impacting the real-time nature of interactions. Protocol serialization, deserialization, and parsing operations require significant computing resources and time, and can also become a bottleneck for system communication.

[0004] Processing bottlenecks in real-time systems: Microprocessor-based real-time systems typically encounter communication bottlenecks if a low-speed interface between them and the application system is insufficient to handle the data flow. Using a high-speed interface increases hardware costs. A small microprocessor buffer can lead to data loss or the need for frequent interrupt processing.

[0005] Processing bottleneck of time-sharing system: In general time-sharing system, data interaction between user state and kernel state is realized through system calls. When data is received from the driver layer and processed by the application, it needs to be copied from one buffer to another. There are repeated memory requests and data duplication losses, which increase resource overhead and load occupancy.

[0006] Communication bottlenecks with peripherals: The bottleneck in communication with controlled devices depends on factors such as the peripheral type and transmission protocol requirements. TCP / IP, which balances both reliability and transmission speed, can suffer from congestion handling issues. Ethernet devices can also experience hardware or compatibility issues, leading to communication failures. Transmission between the peripheral communication interface and the processor is limited by buffer settings, interrupt handling efficiency, or the speed and bandwidth limitations of DMA (Direct Memory Access). Summary of the Invention

[0007] In order to overcome the shortcomings in the above-mentioned data transmission and exchange process, a method for fast data exchange between real-time and time-sharing systems is proposed. A data exchange method based on the symbiosis of real-time and time-sharing systems with multi-core processors is designed. At the same time, a peripheral reading and writing method based on FPGA parallel computing is designed. This not only greatly increases the efficiency of data exchange between systems, but also reduces the number of copies in the data transfer process between user state and kernel state of the time-sharing system.

[0008] A method for quickly exchanging data between a real-time and a time-sharing system comprises the following steps:

[0009] Step 1: Run the real-time system and the time-sharing system on different cores of a multi-core processor, respectively carrying the real-time scheduling system and the polling scheduling time-sharing system. Memory resources are shared equally among the multiple cores.

[0010] Step 2: Divide the shared memory area as the data exchange area, configure it into a two-way chain structure, and complete the setting of the shared memory node chain;

[0011] Step 3: After the FPGA completes parallel processing by carrying the communication protocol through the communication interface, the real-time system core applies for and writes to the shared memory node chain, and notifies the time-sharing system core to receive it through inter-core communication;

[0012] Step 4: After receiving the address in kernel state, the time-sharing system core maps the shared memory node chain address to user state.

[0013] Step 5: After the user state processing is completed, the shared memory node chain is returned and the state is reset, thus completing the data exchange.

[0014] The beneficial effects achieved by the present invention are:

[0015] (1) Multi-core system symbiosis: Two systems work together on different cores of a processor. Multi-core systems share hardware resources equally, such as memory, cache, bus, etc., which improves the performance and efficiency of the overall system. It not only meets the real-time requirements and a large number of application computing requirements, but also reduces investment costs.

[0016] (2) Simple inter-core communication: Multi-core systems use simple shared memory and signal notification mechanisms to improve data transmission bandwidth and efficiency, while taking into account the requirements of real-time performance and large data volumes.

[0017] (3) Shorten the peripheral read and write time of the real-time system: meet the requirements of real-time data processing and high-bandwidth data transmission. Through address bus communication, FPGA can process large amounts of data in parallel and process them immediately, accelerating the data transmission process.

[0018] (4) Efficient data transfer within the time-sharing system: reduces the number of memory copies from kernel state to user state, and reduces unnecessary copying during data transmission, thereby improving performance and reducing resource usage.

[0019] (5) Extreme real-time data exchange throughout the entire process: From data reception to processor processing, the entire process is designed with a high-speed, large-capacity, and real-time data exchange method. The same memory area is used for operation from beginning to end. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a diagram of the overall system architecture in an embodiment of the present invention.

[0021] Figure 2 This is a diagram of a shared memory node chain structure in an embodiment of the present invention.

[0022] Figure 3 This is a flowchart of the overall data exchange in an embodiment of the present invention.

[0023] Figure 4 It is an illustration of inter-core communication in an embodiment of the present invention.

[0024] Figure 5 This is a flowchart of the memory mapping between kernel state and user state in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0026] In this method, the real-time system and the time-sharing system coexist on a multi-core processor without the need for physical separation, respectively carrying the real-time scheduling system and the polling scheduling time-sharing system. Since memory resources are shared and equal for multiple cores, the systems achieve efficient and large-capacity data exchange by designing an inter-core shared memory communication method and notifying through interrupt signals.

[0027] Real-time systems connect to peripherals through an FPGA. FPGA resources (such as registers, memory, and peripherals) are mapped into the CPU's address space. The CPU communicates with the FPGA by accessing specific addresses. The CPU can communicate using memory read and write instructions (e.g., read and write), significantly reducing processing speed mismatches.

[0028] The time-sharing system designs memory pools mapped in user mode and kernel mode, and allocates dynamic memory pools and shared memory node chains from the memory area shared between cores in advance. The driver applies for memory through a simple mark bit. After the application is finished using it, the node chain is released and the mark bit is reset, completing zero copy of memory during data exchange. The same memory area is always operated from the real-time system to the time-sharing system.

[0029] The characteristics of this method are as follows:

[0030] ① The peripheral communication interface is mounted to the bus of the real-time core through FPGA, and data information is quickly read through IO reading and writing.

[0031] ② The real-time core communicates with the application core in a large and efficient manner through a simple shared memory and signal mechanism.

[0032] ③ The time-sharing system completes the transfer from kernel state to application state processing through memory mapping.

[0033] ④ Divide the shared memory area for peripheral data storage, inter-core communication, and user-mode kernel-mode mapping to achieve zero-transfer in the data exchange process.

[0034] Figure 1 For the overall system architecture, a heterogeneous dual-core design was developed. The time-sharing system, which requires large-scale application computing, runs on Core 0, while the real-time control system runs on Core 1. Core 0 and Core 1 share peripherals and memory, allowing inter-core communication to exchange large amounts of data. A shared memory area is designated for data exchange. The FPGA connects to a high-speed optical port, carrying fast and reliable Layer 3 communication protocols such as GOOSE, and is directly mounted on the CPU bus, bypassing intermediate forwarding. After Core 0 receives data, kernel and user states read directly from the previously allocated shared memory area, also known as the inter-core communication memory area. This eliminates repeated memory allocation and transfer at different layers, ultimately achieving millisecond-level real-time processing.

[0035] Figure 2 This is a shared memory node chain structure. The shared memory area consists of a configuration area and a data area. The configuration area contains information such as the data area description, verification, and synchronization. All systems can directly read and write to the data area in a ring-shaped chain. The size of each node in the shared memory pool is the sum of the frame size and the node header size. The node header contains valid status information and user information for the node space. The frame corresponds to the pbuf space. The pbuf frame header includes information such as the actual size of the data buffer. The actual storage buffer for interactive data corresponds to the payload space in the pbuf.

[0036] Figure 3 For the overall data exchange process, a shared memory area is pre-allocated as the data exchange area and configured as a bidirectional ring chain structure. The GOOSE Layer 3 fast protocol is carried over an optical fiber interface. After the FPGA completes parallel processing, real-time core 1 requests and writes to the node chain. This is notified to core 0 via inter-core communication. Application core 0 receives the node chain address in kernel mode and maps it to user mode. After user mode processing is complete, the node chain address is returned and reset, completing the data exchange.

[0037] Figure 4 To illustrate inter-core communication, after core1 receives data from a peripheral, it applies for a shared memory node chain, sets the node header to valid, sets the user to core1, and then writes the data to the communication area. Upon completion, it enables an interrupt to core0. Upon receiving the interrupt notification, core0 retrieves the shared memory data, rewrites the user to core0, and completes the data reception process. It then sends an interrupt to core1, notifying it of the completion of the reception and clearing the status and user information to restore resources.

[0038] Figure 5 The memory mapping process between kernel and user mode involves aligning the frame size during initialization. The memory request type and cache refresh flag are set based on the enable bit. The sending space is directly associated with the upper-level pbuf space, while the receiving space retrieves the pbufs of each node in the node list. Before sending, the pbuf->payload to be sent by the upper layer is associated with the sending node. After sending, the clean operation releases the pbuf space. Before receiving, the content pointed to by the receiving node (stored in the memory pool) is retrieved, and the node is cleared upon completion. If the node pool is insufficient, static receiving space is used. After the upper-level receive processing is complete, the upper-level release actually re-adds the space to the shared memory pool list. After receiving, since the node was retrieved and cleared before receiving, the node is re-associated from the shared memory pool.

[0039] The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. Any equivalent modifications or changes made by ordinary technicians in this field based on the contents disclosed in the present invention should be included in the protection scope recorded in the claims.

Claims

1. A method for rapid data exchange between real-time and time-sharing systems, characterized by: The method comprises the following steps: Step 1: Run the real-time system and the time-sharing system on different cores of a multi-core processor, respectively carrying the real-time scheduling system and the polling scheduling time-sharing system. Memory resources are shared equally among the multiple cores. Step 2: Divide the shared memory area as the data exchange area, configure it into a two-way chain structure, and complete the setting of the shared memory node chain; Step 3: After the FPGA completes parallel processing by carrying the communication protocol through the communication interface, the real-time system core applies for and writes to the shared memory node chain, and notifies the time-sharing system core to receive it through inter-core communication; In step 3, the FPGA connects to the communication interface, which carries the communication protocol and is directly mounted on the CPU bus, skipping intermediate forwarding. The peripheral communication interface is mounted on the bus of the real-time system core through the FPGA, and data information is read and written through IO. In inter-core communication, after receiving peripheral data, the real-time system core applies for a shared memory node chain, sets the node header to valid, and the user is the real-time system core. It fills in and sends data to the shared memory area serving as the communication area. After completion, it enables interrupt transmission to the time-sharing system core. After receiving the interrupt notification, the time-sharing system core takes out the shared memory data in the communication area and rewrites the user to the time-sharing system core. After completing the data reception and processing, the interrupt notifies the real-time system core that the reception is complete, clears the status and user information, and restores the resources. Step 4: After receiving the address in kernel state, the time-sharing system core maps the shared memory node chain address to user state. In step 4, the mapping process between kernel state and user state is as follows: in the initialization phase, the frame size is aligned and converted, the memory application type and cache refresh mark are set according to the enable bit, the sending space is directly associated with the upper-layer pbuf space, and the receiving space obtains the pbuf of each node in the node list; before sending, the pbuf->payload to be sent by the upper layer is associated with the sending node, and after sending, the pbuf space is released by clean; before receiving, the content pointed to by the receiving node, that is, the content stored in the memory pool, is taken out, and the node is assigned to zero after completion; if the node pool is insufficient, the receiving static space is used; after the upper-layer receiving process is completed, the upper-layer release is to re-add the space to the shared memory pool list; after receiving, since the node is taken out before receiving and assigned to zero, the node is re-associated from the shared memory pool; Step 5: After the user state processing is completed, the shared memory node chain is returned and the state is reset, thus completing the data exchange.

2. A method for rapid data exchange between real-time and time-sharing systems according to claim 1, characterized in that: In step 1, the real-time system connects to peripherals through the FPGA. The resources on the FPGA are mapped to the address space of the CPU, and the CPU communicates with the FPGA by accessing specific addresses.

3. The method for rapid data exchange between real-time and time-sharing systems according to claim 2, characterized in that: Resources on FPGA include registers, memory, and peripherals.

4. The method for rapid data exchange between real-time and time-sharing systems according to claim 1, characterized in that: In step 2, the shared memory area consists of a configuration area and a data area. The configuration area contains the description, verification, and synchronization information of the data area. Each system directly reads and writes the data area space, forming a shared memory node chain according to a bidirectional ring chain.

5. A method for rapid data exchange between real-time and time-sharing systems according to claim 4, characterized in that: The size of each node in the shared memory area is the frame size plus the node header size. The node header contains the valid status information and user information of the node space. The frame corresponds to the pbuf space. The pbuf frame header includes data description information, and the actual storage buffer of the interactive data corresponds to the payload space in the pbuf.

6. The method for rapid data exchange between real-time and time-sharing systems according to claim 1, characterized in that: In step 5, the time-sharing system designs the memory pool mapped in user mode and kernel mode, allocates the dynamic memory pool and shared memory node chain from the memory area shared between cores in advance, applies for receiving memory through the mark bit, releases the shared memory node chain and resets the mark bit after use, completes the zero copy of memory during data exchange, and always operates on the same memory area from the real-time system to the time-sharing system.

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