Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel. The array substrate comprises a substrate; a thin-film transistor disposed on the substrate, comprising a gate insulating layer and an active layer stacked along the thickness of the array substrate; and a first barrier layer disposed between the gate insulating layer and the active layer, the first barrier layer having oxygen vacancies. The first barrier layer of the array substrate can prevent hydrogen-containing substances in the gate insulating layer from being injected into the active layer, thereby ensuring stable operation of a display panel using the array substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Array substrates based on active layers can be used as active driver devices in the field of display panel technology. In particular, thin-film transistors formed from amorphous oxide semiconductors offer advantages such as high transparency, high mobility, a high current switching ratio, low process temperature, and a simple fabrication process, making them suitable for use in high-performance TFT-LCD or AMOLED display panels. However, amorphous oxide semiconductors are sensitive to substances containing hydrogen. Injecting this hydrogen into the active layer can cause the threshold voltage of the thin-film transistor to shift significantly negatively. Therefore, preventing hydrogen from being injected into the active layer is crucial to the proper operation of the display panel. Summary of the Invention

[0003] The embodiment of the present application provides an array substrate and a display panel, wherein the first barrier layer of the array substrate can prevent the substance containing hydrogen from being injected into the internal structure of the array substrate such as the active layer, so that the display panel using the array substrate can operate stably.

[0004] An embodiment of the present application provides an array substrate, comprising:

[0005] substrate;

[0006] a thin film transistor, the thin film transistor being disposed on the substrate, the thin film transistor comprising a gate insulating layer and an active layer stacked along a thickness direction of the array substrate;

[0007] A first barrier layer is provided between the gate insulating layer and the active layer, and the first barrier layer has oxygen vacancies.

[0008] In some embodiments, the resistivity of the first barrier layer is greater than 10 4 Ω·m.

[0009] In some embodiments, the first barrier layer and the active layer include oxide semiconductor materials.

[0010] In some embodiments, the first barrier layer and the active layer are both indium gallium zinc oxide.

[0011] In some embodiments, a second barrier layer and a passivation layer are further included. The passivation layer is arranged on a side of the thin film transistor away from the substrate, and the second barrier layer is arranged between the active layer of the thin film transistor and the passivation layer; the second barrier layer has oxygen vacancies.

[0012] In some embodiments, the resistivity of the second barrier layer is greater than 10 4 Ω·m

[0013] In some embodiments, the thin film transistor has a top-gate structure or a bottom-gate structure.

[0014] In some embodiments, the number of oxygen vacancies in the first barrier layer is greater than the number of oxygen vacancies in the active layer.

[0015] In some embodiments, the active layer is divided into a channel region and a source region and a drain region formed on both sides of the channel region; the source is connected to the source region of the active layer, and the drain is connected to the drain region of the active layer.

[0016] The present application also provides a display panel, including:

[0017] The above-mentioned array substrate;

[0018] The packaging component is connected to the array substrate.

[0019] An array substrate and display panel provided in embodiments of the present application include a substrate, a thin-film transistor (TFT), and a first barrier layer. The TFT is disposed on the substrate and includes a gate insulating layer and an active layer stacked along the thickness of the array substrate. The first barrier layer is disposed between the gate insulating layer and the active layer and contains oxygen vacancies that prevent hydrogen from being injected into the active layer, thereby ensuring stable operation of a display panel using the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0021] Figure 1 The figure is a schematic structural diagram of an array substrate in the prior art.

[0022] Figure 2 This is a schematic diagram of the first structure of the array substrate provided in an embodiment of the present application.

[0023] Figure 3 This is a schematic diagram of the second structure of the array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0025] See also Figure 1 , Figure 1 The figure is a schematic structural diagram of an array substrate in the prior art.

[0026] The array substrate 1 in the prior art includes a substrate 101, a gate 102, a gate insulating layer 103, an active layer 104, a source electrode 105, a drain electrode 106, a first passivation layer 107, a planarization layer 108, a first electrode 110, a second passivation layer 109, and a second electrode 111. The gate 102 is disposed on the substrate 101, the gate insulating layer 103 is stacked on the gate 102, the active layer 104 is formed on the gate insulating layer 103, and the source electrode 105 and the drain electrode 106 are both formed on the active layer 104. The first passivation layer 107 and the planarization layer 108 are stacked on the source electrode 105 and the drain electrode 106. The first electrode 110 is formed on the planarization layer 108. The second passivation layer 109 is formed on the first electrode 110. The second electrode 111 is formed on the second passivation layer 109. The first passivation layer 107, the planar layer 108, and the second passivation layer 109 are provided with through-holes, through which the drain electrode 106 is exposed. The second electrode 111 is formed on the second passivation layer 109. The second electrode 111 is electrically connected to the drain electrode 106 through the through-hole and can be the anode of the organic light-emitting diode of the display panel. The gate 102, the source electrode 105, and the drain electrode 106 together with the active layer 104 form a thin film transistor. The gate 102, the source electrode 105, and the drain 106 are the control electrode, the input electrode, and the output electrode of the thin film transistor, respectively.

[0027] The array substrate 1 includes some films with high hydrogen content, such as those made of silicon nitride (which contains a large number of hydrogen bonds). During high-temperature processes or operating conditions, the hydrogen in these films can easily diffuse into the active layer 104 (or channel region) of the thin-film transistor in the form of hydrogen ions. This can cause the active layer 104 (or channel region) of the thin-film transistor to exhibit a conductive effect, resulting in a negative bias in the threshold voltage Vth of the thin-film transistor, and thus poor electrical performance and reliability of the thin-film transistor. Therefore, preventing hydrogen from being injected into the active layer 104 is crucial to the smooth operation of the display panel.

[0028] The present invention provides an array substrate and a display panel. The first barrier layer of the array substrate can prevent hydrogen from being injected into the internal structure of the array substrate, such as the active layer, so that the display panel using the array substrate can operate stably.

[0029] See also Figure 2 , Figure 2 This is a schematic diagram of the first structure of the array substrate provided in an embodiment of the present application.

[0030] An embodiment of the present application provides an array substrate 100 , which includes a substrate 10 , a thin film transistor, and a first barrier layer 70 .

[0031] The substrate 10 can be divided into a hard substrate 10 and a flexible substrate 10. The hard substrate 10 can be a traditional glass substrate 10, and the flexible substrate 10 can be a polyimide (PI) substrate 10. The preparation process of the flexible substrate 10 generally uses a glass substrate as a hard base, prepares the flexible substrate 10 on the glass substrate, and then separates the flexible substrate 10 from the glass substrate to finally obtain the flexible substrate 10.

[0032] The thin film transistor can be an N-type transistor or a P-type transistor. Alternatively, the thin film transistor can be a top-gate thin film transistor, a bottom-gate thin film transistor, or other types of thin film transistors. The gate insulating layer 30 and the active layer 40 in the thin film transistor are stacked along the thickness direction of the array substrate 100. The thin film transistor also includes a gate 20, a source 50, and a drain 60. Taking the bottom-gate thin film transistor as an example, along the thickness direction of the array substrate 100, the gate 20 is arranged on the substrate 10, the gate insulating layer 30 is arranged on the side of the gate 20 away from the substrate 10, the active layer 40 is arranged on the side of the gate insulating layer 30 away from the substrate 10, and the source 50 and the drain 60 are arranged on the side of the active layer 40 away from the substrate 10.

[0033] Along the thickness direction of the array substrate 100 , the first barrier layer 70 is disposed between the gate insulating layer 30 and the active layer 40 , and the orthographic projection of the first barrier layer 70 on the substrate 10 at least partially overlaps with the orthographic projection of the active layer 40 on the substrate 10 .

[0034] The first barrier layer 70 has oxygen vacancies, which can better absorb hydrogen-containing substances generated in the gate insulating layer 30, blocking the diffusion of hydrogen from the source, preventing the hydrogen generated in the gate insulating layer 30 from diffusing into the active layer 40, and thereby improving the reliability of the array substrate 100.

[0035] Furthermore, the orthographic projection of the active layer 40 on the substrate 10 is located within the orthographic projection of the first barrier layer 70 on the substrate 10. In other words, the orthographic projection area of ​​the first barrier layer 70 on the substrate 10 is larger than the orthographic projection area of ​​the active layer 40 on the substrate 10, which can completely separate the active layer 40 from the gate insulating layer 30, thereby blocking the diffusion of hydrogen elements and improving the reliability of the array substrate 100.

[0036] The gate 20 is provided on the substrate 10. The material of the gate 20 includes one or more combinations of Mo (molybdenum), Al (aluminum), Ti (titanium) and Cu (copper).

[0037] The gate insulating layer 30 is sequentially stacked on the substrate 10 and the gate 20. The material of the gate insulating layer 30 includes one or more combinations of silicon nitride, silicon oxynitride, and silicon oxide. Since the gate insulating layer 30 includes silicon, SiH4 (silicon tetrahydrogen) is inevitably present. The hydrogen-containing substance in the gate insulating layer 30 may be injected into the active layer 40, resulting in a significant negative threshold voltage shift.

[0038] The material of the active layer 40 is an amorphous oxide semiconductor. For example, the material of the active layer 40 includes at least one of ZnO (zinc oxide), ITZO (indium tin zinc oxide), ITZTO (indium tin zinc tin oxide), IZO (indium tin oxide), ZTO (zinc tin oxide), and IGZO (indium gallium zinc oxide). In this embodiment, the material of the active layer 40 is IGZO.

[0039] The active layer 40 is divided into a channel region 41 and a source region 42 and a drain region 43 formed on both sides of the channel region 41. The source electrode 50 is connected to the source region 42 of the active layer 40, and the drain electrode 60 is connected to the drain region 43 of the active layer 40. The material of the source electrode 50 and the drain electrode 60 includes one or more combinations of Mo (molybdenum), Al (aluminum), Ti (titanium) and Cu (copper).

[0040] The gate electrode 20 , the source electrode 50 , and the drain electrode 60 are respectively a control electrode, an input electrode, and an output electrode of the thin film transistor, and together with the active layer 40 , form the thin film transistor.

[0041] In order to prevent the substance containing hydrogen in the gate insulating layer 30 from being injected into the active layer 40, the array substrate 100 includes at least a first barrier layer 70. The first barrier layer 70 is arranged between the active layer 40 and the gate insulating layer 30. The first barrier layer 70 has oxygen vacancies, which can better adsorb the substance containing hydrogen produced in the gate insulating layer 30, block the diffusion of hydrogen from the source, and prevent the substance containing hydrogen produced in the gate insulating layer 30 from diffusing into the active layer 40, thereby improving the reliability of the array substrate 100.

[0042] The material of the first barrier layer 70 may be an oxide semiconductor material. The material of the first barrier layer 70 includes at least one of ZnO (zinc oxide), ITZO (indium tin zinc oxide), ITZTO (indium tin zinc tin oxide), IZO (indium tin oxide), ZTO (zinc tin oxide), and IGZO (indium gallium zinc oxide).

[0043] Furthermore, in the preparation of the array substrate 100 , the first barrier layer 70 and the active layer 40 are made of the same material, for example, IGZO (indium gallium zinc oxide), so no new material needs to be added, which is beneficial to simplifying the production process and reducing production costs.

[0044] For example, a layer of indium gallium zinc oxide (IGZO) is formed on the gate insulating layer 30, and the IGZO is ion-bombarded to increase the oxygen vacancies in the IGZO, so that the number of oxygen vacancies in the first barrier layer 70 is greater than the number of oxygen vacancies in the active layer 40, and the ability to adsorb hydrogen-containing substances is enhanced, thereby forming the first barrier layer 70. Since the number of oxygen vacancies is positively correlated with the resistivity, the resistivity is a macroscopic expression of the number of oxygen vacancies. The resistivity of the first barrier layer 70 is greater than 10 4 A layer of indium gallium zinc oxide (IGZO) is formed on the first barrier layer 70 , and the IGZO layer serves as the active layer 40 .

[0045] See also Figure 3 , Figure 3 This is a schematic diagram of the second structure of the array substrate provided in an embodiment of the present application.

[0046] In some embodiments, the array substrate 100 further includes a second barrier layer 80 and a passivation layer 90. The passivation layer is disposed on a side of the thin film transistor away from the substrate, and the second barrier layer is disposed between the active layer of the thin film transistor and the passivation layer. The second barrier layer has oxygen vacancies to prevent substances containing hydrogen from entering the active layer 40.

[0047] Taking a bottom-gate thin film transistor as an example, the active layer 40 is disposed on the side of the gate insulating layer 30 away from the substrate 10, and the source electrode 50 and the drain electrode 60 are disposed on the side of the active layer 40 away from the substrate 10. The second barrier layer 80 is disposed between the active layer 40 and the source electrode 50 and the drain electrode 60. The passivation layer 90 is disposed on the side of the source electrode 50 and the drain electrode 60 away from the active layer 40. The second barrier layer 80 has oxygen vacancies, which can effectively adsorb hydrogen-containing substances generated in the passivation layer 90, blocking the diffusion of hydrogen at the source, preventing the hydrogen-containing substances generated in the passivation layer 90 from diffusing into the active layer 40, thereby improving the reliability of the array substrate 100.

[0048] The orthographic projection of the second barrier layer 80 on the substrate 10 at least partially overlaps with the orthographic projection of the active layer 40 on the substrate 10 .

[0049] Furthermore, the orthographic projection of the active layer 40 on the substrate 10 is located within the orthographic projection of the second barrier layer 80 on the substrate 10. In other words, the orthographic projection area of ​​the second barrier layer 80 on the substrate 10 is larger than the orthographic projection area of ​​the active layer 40 on the substrate 10, which can completely separate the active layer 40 from the passivation layer 90, thereby blocking the diffusion of hydrogen elements and improving the reliability of the array substrate 100.

[0050] The material of the passivation layer 90 includes one or more combinations of tetraethyl orthosilicate (TEOS), silicon nitride, and silicon oxide. Since the passivation layer 90 includes silicon, SiH4 (silicon tetrahydride) is inevitably present. The hydrogen-containing substance in the passivation layer 90 may be injected into the active layer 40, causing the threshold voltage of the thin film transistor to be significantly negatively biased.

[0051] The material of the second barrier layer 80 may be an oxide semiconductor material. The material of the second barrier layer 80 includes at least one of ZnO (zinc oxide), ITZO (indium tin zinc oxide), ITZTO (indium tin zinc tin oxide), IZO (indium tin oxide), ZTO (zinc tin oxide), and IGZO (indium gallium zinc oxide).

[0052] Furthermore, in the preparation of the array substrate 100 , the second barrier layer 80 and the active layer 40 are made of the same material, for example, IGZO (indium gallium zinc oxide), which can save steps, improve production efficiency, and reduce costs.

[0053] For example, the source electrode 50 and the drain electrode 60 are disposed on the active layer 40, a layer of indium gallium zinc oxide (IGZO) is formed on the active layer 40, and the IGZO is ion-bombarded to increase the oxygen vacancies in the IGZO, so that the number of oxygen vacancies in the second barrier layer 80 is greater than the number of oxygen vacancies in the active layer 40, and the resistivity of the IGZO is greater than 10 4 Ω·m, to form a second barrier layer 80; and then a passivation layer 90 is formed on the second barrier layer 80.

[0054] An embodiment of the present application further provides a display panel, comprising the array substrate 100 of the above embodiment and a package, wherein the package is connected to the array substrate 100 and is used to encapsulate the array substrate 100. The display panel may be a TFT-LCD (Thin film transistor liquid crystal display) or an AMOLED (Active-matrix organic light-emitting diode) display panel.

[0055] An array substrate 100 and a display panel provided in an embodiment of the present application include: the array substrate 100 includes a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, a source electrode 50, a drain electrode 60, and a first barrier layer 70; the gate 20, the gate insulating layer 30, the active layer 40, the source electrode 50, and the drain electrode 60 are arranged on the substrate 10; the first barrier layer 70 is arranged between the gate insulating layer 30 and the active layer 40; the first barrier layer 70 has oxygen vacancies, which can block hydrogen elements in the gate insulating layer 30 from entering the active layer 40, and can prevent the hydrogen elements from being injected into the internal structure of the array substrate 100, such as the active layer 40, so that the display panel using the array substrate 100 can operate stably.

[0056] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0057] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more features.

[0058] The above describes in detail the array substrate and display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is intended only to facilitate understanding of the present application. Furthermore, those skilled in the art will appreciate that variations in the specific implementation methods and scope of application may occur based on the concepts of the present application. In summary, the contents of this specification should not be construed as limiting the present application.

Claims

1. An array substrate, characterized in that: include: substrate; a thin film transistor, the thin film transistor being disposed on the substrate, the thin film transistor comprising a gate insulating layer and an active layer stacked along a thickness direction of the array substrate; a first barrier layer, wherein the first barrier layer is disposed between the gate insulating layer and the active layer, an orthographic projection of the first barrier layer on the substrate at least partially overlaps with an orthographic projection of the active layer on the substrate, and the first barrier layer has oxygen vacancies; The first barrier layer and the active layer are both made of oxide semiconductor materials, and the number of oxygen vacancies in the first barrier layer is greater than the number of oxygen vacancies in the active layer.

2. The array substrate according to claim 1, wherein: The resistivity of the first barrier layer is greater than 10 4 Ω·m.

3. The array substrate according to claim 1, wherein: The first barrier layer and the active layer are both indium gallium zinc oxide.

4. The array substrate according to any one of claims 1 to 3, wherein: It also includes a second barrier layer and a passivation layer. The passivation layer is arranged on a side of the thin film transistor away from the substrate, and the second barrier layer is arranged between the active layer of the thin film transistor and the passivation layer. The second barrier layer has oxygen vacancies.

5. The array substrate according to claim 4, wherein: The resistivity of the second barrier layer is greater than 10 4 Ω·m.

6. The array substrate according to any one of claims 1 to 3, characterized in that: The thin film transistor has a top-gate structure or a bottom-gate structure.

7. The array substrate according to any one of claims 1 to 3, characterized in that: The orthographic projection of the active layer on the substrate is located within the orthographic projection of the first barrier layer on the substrate.

8. The array substrate according to any one of claims 1 to 3, characterized in that: The active layer is divided into a channel region and a source region and a drain region formed on both sides of the channel region; the source electrode is connected to the source region of the active layer, and the drain electrode is connected to the drain region of the active layer.

9. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 8; The packaging component is connected to the array substrate.

Images