Switching devices, switching methods and switching equipment

Abstract

This application discloses a switching device, switching method, and switching equipment, relating to the field of communications, for preventing uneven heating in a switching device. The switching device includes: multiple switching blocks and corresponding input / output ports; the multiple switching blocks are used to receive data through their corresponding input / output ports, forward data to a target switching block within the multiple switching blocks, and transmit data through the input / output ports corresponding to the target switching block; the multiple switching blocks include a first switching block that is not a target switching block for data; the multiple switching blocks are divided into at least two groups, each switching block including a first switching interface and a second switching interface, the first switching interface being used to exchange data with switching blocks in the same group, and the second interface being used to exchange data with switching blocks in different groups; the switching device also includes a control circuit for: when the first switching block receives data through its corresponding input / output port or the second switching interface, causing the first switching block to select the first switching interface to forward the data.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a switching device, switching method, and switching equipment. Background Technology

[0002] In switched network communication, the switching chips in the switching equipment often have to handle a large number of data packet switching services. The processing complexity of each circuit in the switching chip is different, which makes the power consumption (heat generation) of each circuit different. This causes the temperature of some areas of the switching chip to be much higher than that of other areas, which brings difficulties to the power supply design and heat dissipation design of the switching chip. Summary of the Invention

[0003] This application provides a switching device, a switching method, and a switching equipment to prevent uneven heating of the switching device.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a switching device is provided, comprising: a plurality of switching blocks, and a plurality of input / output ports corresponding to the plurality of switching blocks; the plurality of switching blocks are configured to receive data through corresponding input / output ports, forward the data to a target switching block among the plurality of switching blocks, and send data through an input / output port corresponding to the target switching block; wherein the plurality of switching blocks includes a first switching block, which is not a target switching block for the data; the plurality of switching blocks are divided into at least two groups of switching blocks, each switching block including a first switching interface and a second switching interface, the first switching interface being used to exchange data with switching blocks in the same group, and the second interface being used to exchange data with switching blocks in different groups; the switching device further includes a control circuit configured to: when the first switching block receives data through a corresponding input / output port or a second switching interface, control the first switching block to select the first switching interface to forward the data.

[0006] The switching device provided in this application divides the switching blocks into at least two groups. Switching blocks within a group exchange data through a first switching interface, while switching blocks between groups exchange data through a second switching interface. For data received from inter-group exchanges via the second switching interface, or for data received from external exchanges via input / output ports, the switching blocks perform intra-group switching through the first switching interface. This achieves load balancing and similar power consumption among the switching blocks within the same group, preventing some areas of the switching device from having significantly higher temperatures than others, and reducing the difficulty of power supply and heat dissipation design.

[0007] In one possible implementation, the control circuit is further configured to: when the first switching block receives data through the corresponding input / output port or the second switching interface, control the first switching block to simultaneously select the first switching interface and the second switching interface to forward the data. For data received through the second switching interface from inter-group exchange, or for data received through the input / output port from external exchange, the switching block performs intra-group exchange through the first switching interface and inter-group exchange through the second switching interface. This achieves load balancing and similar power consumption for each switching block within the same group. Switching blocks in different groups also participate in data exchange with similar power consumption, preventing the temperature in some areas of the switching device from being significantly higher than in others, thus reducing the difficulty of power supply and heat dissipation design.

[0008] In one possible implementation, the control circuit is further configured to: when the first switching block receives data through the first switching interface, control the first switching block to select the second switching interface or the corresponding input / output port to forward the data. For data received from intra-group switching through the first switching interface, the switching block performs inter-group switching through the second switching interface, or forwards it directly through the input / output port, thereby enabling switching blocks in different groups to participate in data exchange with similar power consumption, avoiding the temperature in some areas of the switching device being much higher than in other areas, and reducing the difficulty of power supply and heat dissipation design.

[0009] In one possible implementation, the switching block further includes a switching circuit coupled to corresponding input / output ports, a first switching interface, and a second switching interface. The switching circuit is used to exchange data with other switching blocks via the first and second switching interfaces, and to exchange data with corresponding input / output ports. The switching circuit can be used for communication between the switching device and external devices, as well as for communication between switching blocks within the switching device, allowing for a more compact switching block structure.

[0010] In one possible implementation, the switching block further includes coupled switching circuitry and routing circuitry. The switching circuitry is coupled to corresponding input / output ports and is used to exchange data with the routing circuitry and corresponding input / output ports. The routing circuitry is coupled to a first switching interface and a second switching interface and is used to exchange data with other switching blocks through the first and second switching interfaces. The switching circuitry is used for communication between the switching device and external devices, and the routing circuitry is used for communication between switching blocks within the switching device. This decoupling of circuits with different functions simplifies software and hardware design.

[0011] In one possible implementation, the target switching block outputs multiple data points through corresponding input / output ports in the order they are received from multiple switching blocks. This is because load-balanced data is exchanged between different switching blocks before reaching the target switching block, and due to varying processing latency across blocks, data may arrive later than expected. Whether reordering is necessary and the difficulty of reordering depends on the load balancing algorithm employed.

[0012] In one possible implementation, the same set of switching blocks are located on different dies. This allows for coupling between more switching devices, facilitates the expansion of the switching system, improves system switching capacity, and ensures that the communication method between switching blocks across dies is consistent with the communication method between switching blocks on the same die, simplifying software and hardware design.

[0013] In one possible implementation, different groups of switching blocks are located on different dies. This allows for greater coupling between switching devices, facilitates expansion of the switching system, improves system switching capacity, and ensures that the communication method between switching blocks across dies is consistent with the communication method between switching blocks on the same die, simplifying software and hardware design.

[0014] In one possible implementation, the first switching interfaces of the same group of switching blocks are coupled via a fan-out bus, and the second switching interfaces of different groups of switching blocks are coupled via a fan-out bus. This connection method allows any switching block to send a load directly to another coupled switching block without having to be forwarded by other switching blocks.

[0015] In one possible implementation, the switching device is a switching chip. The switching device can also be a switch, switching equipment, etc.

[0016] In one possible implementation, a switching block refers to a circuit that has data switching functionality.

[0017] In a second aspect, a switching method is provided, applied to a switching apparatus as described in the first aspect and any embodiment thereof, the method comprising: when a first switching block receives data through a corresponding input / output port or a second switching interface, controlling the first switching block to select a first switching interface to forward the data.

[0018] In one possible implementation, when the first switching block receives data through the corresponding input / output port or the second switching interface, controlling the first switching block to select the first switching interface to forward the data includes: when the first switching block receives data through the corresponding input / output port or the second switching interface, controlling the first switching block to simultaneously select the first switching interface and the second switching interface to forward the data.

[0019] In one possible implementation, the method further includes: when the first switching block receives data through the first switching interface, controlling the first switching block to select the second switching interface or the corresponding input / output port to forward the data.

[0020] Thirdly, a switching device is provided, including a switching device as described in any of the first aspects and a memory coupled to the switching device, the switching device being a switching chip.

[0021] Fourthly, a computer-readable storage medium is provided for storing one or more programs, the one or more programs including instructions that, when executed by a switching device, cause the switching device to perform the method as described in the second aspect and any embodiment thereof.

[0022] Fifthly, a computer program product including instructions is provided, characterized in that, when the instructions are executed by a switching device, the switching device performs the method as described in the second aspect and any embodiment thereof.

[0023] The technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any of its embodiments. Attached Figure Description

[0024] Figure 1 A schematic diagram of the Kloss architecture provided in this application embodiment;

[0025] Figure 2 A schematic diagram of a spine structure provided for an embodiment of this application;

[0026] Figure 3 A schematic diagram of the architecture of a switching node in a switching network provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the structure of a switching chip provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the structure of a switching device provided in an embodiment of this application;

[0029] Figure 6 A schematic diagram of another switching device provided in an embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the structure of another switching device provided in an embodiment of this application;

[0031] Figure 8 This is a schematic diagram of the structure of a swap block provided in an embodiment of this application;

[0032] Figure 9 This is a schematic diagram of another swap block structure provided in an embodiment of this application;

[0033] Figure 10 A schematic diagram of the architecture of a switching node in another switching network provided in an embodiment of this application;

[0034] Figure 11 A schematic diagram of the architecture of a switching node in another switching network provided in an embodiment of this application;

[0035] Figure 12 A schematic diagram illustrating the connection of various switching blocks via a fan-out bus, provided in an embodiment of this application;

[0036] Figure 13 A flowchart illustrating an exchange method provided in an embodiment of this application;

[0037] Figure 14 This is a schematic diagram of another switching device provided in an embodiment of this application;

[0038] Figure 15 A schematic diagram illustrating a switching device performing a switching method according to an embodiment of this application;

[0039] Figure 16 This is a schematic diagram of the structure of a switching device provided in an embodiment of this application. Detailed Implementation

[0040] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0041] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0042] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0043] First, let me describe some of the concepts involved in this application:

[0044] Clos architecture: a structure describing multi-level circuit-switched networks, such as... Figure 1As shown, the system includes multiple ingress nodes 11, multiple intermediate nodes 12, and multiple egress nodes 13. Ingress nodes 11, intermediate nodes 12, and egress nodes 13 can be switches or switching chips. Each ingress node 11 includes multiple input ports, and each egress node 13 includes multiple output ports. Each ingress node 11 is connected to each intermediate node 12 (i.e., fully connected), and each intermediate node 12 is connected to each egress node 13 (i.e., fully connected). The advantage of this architecture is that it can achieve load balancing.

[0045] In real-world products, data flow is not unidirectional. Depending on the direction of data flow, a switch or switching chip can be used simultaneously as both an ingress and egress node in a switching network, thus forming a spine-leaf architecture.

[0046] Spinal lobe structure: such as Figure 2 As shown, by treating the entry node 11 and exit node 13 as leaf nodes 21 and the intermediate node 12 as spine nodes 22 in the Clos architecture, a spine-leaf architecture can be obtained. Compared to the Clos architecture, this architecture offers advantages such as more reliable network connectivity, the failure of any node not affecting the overall operation, and higher exchange efficiency between the leaf nodes 21. Assuming the number of leaf nodes 21 is N (…),… Figure 2 The number of ridge nodes 22 is M (6 in the middle). Figure 2 If the middle is 3), then M ridge nodes 22 can achieve NxN ( Figure 2 In this case, all swaps are performed in a 6x6 array, where N is a positive integer.

[0047] The bandwidth between leaf node 21 and ridge node 22 can be greater than, equal to, or less than the bandwidth (external bandwidth) of the input / output ports of leaf node 21. Figure 2 For example, assuming the bandwidth of the input / output ports of each leaf node 21 is 9.6Tbps, each leaf node 21 can be connected to each spine node 22 through three 3.2Tbps lines. In this case, the bandwidth between leaf node 21 and spine node 22 is equal to the bandwidth of the input / output ports of leaf node 21. Alternatively, each leaf node 21 can be connected to each spine node 22 through three 1.6Tbps lines. In this case, the bandwidth between leaf node 21 and spine node 22 is less than the bandwidth of the input / output ports of leaf node 21, and cost can be reduced through bandwidth convergence. Alternatively, each leaf node 21 can be connected to each spine node 22 through three 4.8Tbps lines. In this case, the bandwidth between leaf node 21 and spine node 22 is greater than the bandwidth of the input / output ports of leaf node 21, and transmission performance can be improved through speedup.

[0048] Non-blocking switching: If a switching device can successfully establish any route request to any idle output port without interfering with other data being switched, it is called non-blocking switching, and the switching device is called a non-blocking switching device.

[0049] like Figure 3 As shown, each switching node in the switching network (e.g., leaf node 21 and spine node 22 mentioned above) may include: a first media access control (MAC) 31, an ingress packet processing (PP) circuit 32, a switch / traffic manager (SW / TM) circuit 33, an egress PP circuit 34, and a second MAC 35. The first MAC 31 couples multiple input ports, and the second MAC 35 couples multiple output ports. The first MAC 31 and the second MAC 35 can be the same MAC or different MACs, and the input ports and output ports can be the same port or different ports.

[0050] Input and output ports are used to provide high-speed interfaces for communication with other switching devices, such as 50Gbps serializer / deserializer (SerDes) interfaces and optical interfaces.

[0051] The first MAC 31 and the second MAC 35 are used to provide standard Ethernet protocol interfaces to process data packets according to the Ethernet protocol, such as data verification, frame delimitation, and sending and receiving.

[0052] The transmission path of a single data packet can be called a pipeline. Figure 3Two pipelines are illustrated exemplarily. Each pipeline may include an ingress pipeline and an egress pipeline. The circuitry for data processing in the ingress pipeline is the ingress PP circuit 32, and the circuitry for data processing in the egress pipeline is the egress PP circuit 34. The ingress PP circuit 32 processes the received data packets to obtain the payload and header data, and sends the payload and header data to the SW / TM circuit 33. The data packet processing includes parsing the data packets to obtain the payload and header data, finding the destination port of the data packets through a table lookup, and editing the header data, etc. The egress PP circuit 34 processes the payload and header data to obtain the data packets, and implements the reverse process of the ingress PP circuit 32, such as editing the header data and re-encapsulating the payload based on the header data to obtain the data packets, etc.

[0053] The input PP circuit 32 and the output PP circuit 34 may include multiple-stage match action (MA) circuits. The more stages of the MA circuits, the more complex the functions supported by the pipeline. The input PP circuit 32 and the output PP circuit 34 may be programmable to implement other functions.

[0054] The TM function in SW / TM circuit 33 is used to add the payload and header data in the data packet to a queue according to the data in the packet header (e.g., the 5-tuple of transmission control protocol / internet protocol (TCP / IP), destination port, etc.), and to schedule these queues according to a certain quality of service (QoS) policy.

[0055] The SW function in the SW / TM circuit 33 is used to write the payload and header data of the received data packet into the buffer, and according to the scheduling result of the TM function, to exchange the payload and header data of the data packet to the destination output port.

[0056] like Figure 4 As shown, a method based on Figure 3The switch chip shown has a star topology. The switch chip 40 includes, in sequence according to the data flow direction, input / output ports 41, a MAC 42, a PP circuit 43, and an SW / TM circuit 44. Input / output ports 41 are used to implement… Figure 3 The MAC 42 is used to implement the functions of input and output ports. Figure 3 The functions of the first MAC 31 and the second MAC 35 are implemented by the PP circuit 43. Figure 3 The functions of the inlet PP circuit 32 and the outlet PP circuit 34 are implemented by the SW / TM circuit 44. Figure 3 The function of the SW / TM circuit 33.

[0057] The layout of the aforementioned switching chip is based on the data packet processing flow: after the data packet is input from the input / output port 41, the MAC 42 processes the data packet according to the Ethernet protocol, the uplink PP circuit in the PP circuit 43 processes the data packet to obtain the payload and the data in the header, and sends it to the SW / TM circuit 44 for scheduling and switching; the switched payload and the data in the header are then processed by the downlink PP circuit in the PP circuit 43, re-encapsulated to obtain the data packet, and the MAC 42 sends the data packet out through the input / output port 41.

[0058] This reveals the following problems with this type of switching chip:

[0059] Poor feasibility: Each circuit is often developed independently and then integrated, which makes the top-level design of the switching chip (such as the layout of each circuit and the interconnections between them) difficult. Furthermore, due to the different processing complexities of each circuit, the power consumption of each circuit is also different, causing the temperature of some areas of the switching chip to be much higher than that of other areas, which brings difficulties to power supply design and heat dissipation design.

[0060] Large latency: All data packets exchanged between input / output ports 41 need to be transmitted sequentially through MAC 42 and PP circuit 43 to the innermost SW / TM circuit 44 of the chip, and then sequentially through PP circuit 43 and MAC 42 before being transmitted out. In other words, even data packets sent and received by a certain input / output port 41 itself need to go through such forwarding to complete, making the exchange latency between any input / output ports very long.

[0061] Poor scalability: When two or more switching chips need to be interconnected to expand functionality, a communication protocol between the switching chips also needs to be defined to coordinate the functions of the circuits in different switching chips.

[0062] This application provides a switching device, which may be a switching chip, a switch, a switching device, etc. Figure 5 As shown, the switching device 50 includes: multiple switching blocks 51, multiple input / output ports 52 respectively coupled to (or corresponding to) the multiple switching blocks 51, and a control circuit 55, wherein a switching block refers to a circuit with data switching function. The multiple switching blocks 51 can receive data (one or more) through their corresponding input / output ports 52, forward the data to a target switching block among the multiple switching blocks 51, and output the data through the corresponding input / output port 52 of the target switching block. The control circuit 55 is used to control the switching blocks 51 to forward data; the control circuit 55 can be located in the switching device 50 or in each switching block 51.

[0063] Multiple switching blocks 51 are divided into at least two groups of switching blocks. For example, suppose the switching device 50 includes M*N switching blocks 51, which can be arranged in an M row, N column configuration, where M and N are positive integers. Figure 5 In this case, M = N = 3. A row of switching blocks 51 can be considered as a group of switching blocks 51, then a column of switching blocks 51 can be considered as different groups of switching blocks 51; conversely, a column of switching blocks 51 can be considered as a group of switching blocks 51, then a row of switching blocks 51 can be considered as different groups of switching blocks 51. Switching blocks 51 in the same group are coupled through the first bus 53, and switching blocks 51 in different groups are coupled through the second bus 54.

[0064] Taking this switching device as an example of a switching chip, multiple switching blocks 51 can be mounted on the same die, and multiple input / output ports 52 can be located around the die and coupled to the multiple switching blocks 51. With technological advancements, such as the use of three-dimensional (3D) stacking technology, multiple switching blocks 51 can also be mounted on multiple dies. Figure 6 As shown, the same group of switching blocks can be disposed in switching devices 50 located on different dies, and the switching blocks 51 located in switching devices 50 on different dies can be coupled to each other through the first bus 53. Figure 7 As shown, different groups of switching blocks (e.g., the first and second groups of switching blocks mentioned later) can be located in switching devices 50 on different dies, and the switching blocks 51 located in the switching devices 50 on different dies can be coupled to each other via the second bus 54. It should be noted that... Figure 6 and Figure 7 The coupling methods in the process are combined to enable coupling between more switching devices 50, which can easily expand the scale of the switching system and improve the system switching capacity. Furthermore, the communication method between switching blocks 51 across the die is consistent with the communication method between switching blocks 51 on the same die, which simplifies software and hardware design.

[0065] like Figure 8 As shown, each switching block 51 includes at least an SW circuit 514, multiple first switching interfaces 517, and multiple second switching interfaces 518 to implement data switching functions. The switching block 51 may also include a MAC 511, a PP circuit 512, a TM circuit 513, and a buffer 515. The first switching interfaces 517 are coupled to a first bus 53 for exchanging data with switching blocks 51 in the same group; the second switching interfaces 518 are coupled to a second bus 54 for exchanging data with switching blocks 51 in different groups. Optionally, such as... Figure 9 As shown, each switching block 51 also includes a routing circuit 516.

[0066] It should be noted that each switching block 51, in addition to the SW circuit 514, may include some or all of the circuits from MAC 511, PP circuit 512, and TM circuit 513. The remaining circuits can be located on the periphery of the switching block 51. For example, each switching block 51 may include PP circuit 512, TM circuit 513, and SW circuit 514, while MAC 511 can be located on the periphery of the switching block 51. Furthermore, each switching block 51 may include more circuits to implement more functions, such as circuits supporting statistical, computational, data processing, telemetry, and in-network computing functions.

[0067] Input / output port 52 is used to implement Figure 3 The MAC 511 is used to implement the functions of input and output ports. Figure 3 The functions of the first MAC 31 and the second MAC 35 are implemented by the PP circuit 512. Figure 3 The functions of the inlet PP circuit 32 and the outlet PP circuit 34 are implemented by the TM circuit 513. Figure 3 The TM function of the SW / TM circuit 33 is implemented by the SW circuit 514. Figure 3 The SW function of the SW / TM circuit 33. It should be noted that the TM circuit 513 and the SW circuit 514 can also be combined into an SW / TM circuit.

[0068] For each switching block 51, MAC 511 is coupled to input / output port 52. MAC 511 is also coupled to PP circuit 512. PP circuit 512 is further coupled to TM circuit 513 and SW circuit 514. SW circuit 514 is also coupled to buffer 515, where buffer 515 is used to buffer the payload in data packets. That is, input / output port 52 is coupled to SW circuit 514 via MAC 511 and PP circuit 512. Figure 8In this circuit, the SW circuit 514 can also be coupled to multiple first switching interfaces 517 and multiple second switching interfaces 518. The SW circuit 514 can not only exchange data with the corresponding input / output ports 52, but also exchange data with other switching blocks 51 through the multiple first switching interfaces 517 and multiple second switching interfaces 518. Figure 9 In this circuit, routing circuit 516 is coupled to multiple first switching interfaces 517 and multiple second switching interfaces 518. SW circuit 514 is coupled to multiple first switching interfaces 517 and multiple second switching interfaces 518 through routing circuit 516. At this time, SW circuit 514 is used to exchange data with routing circuit 516 and corresponding input / output ports 52. Routing circuit 516 is used to exchange data with other switching blocks 51 through multiple first switching interfaces 517 and multiple second switching interfaces 518.

[0069] exist Figure 3 Based on the exchange nodes shown, Figure 8 The switching device shown can correspond to Figure 10 The exchange node shown Figure 9 The switching device shown can correspond to Figure 11 The shown switching node. Assuming the input / output port bandwidth of this switching device is 51.2 Tbps, and it includes 16 switching blocks arranged in 4 rows and 4 columns, then the bandwidth of the input / output ports coupled to each switching block is 51.2 / 16 = 3.2 Tbps. Figure 10 and Figure 11 In this architecture, each switching block can include two pipelines, each processing 1.6Tbps packets, with distinction between uplink and downlink pipelines. Alternatively, each switching block can employ other architectures, such as a single 3.2Tbps pipeline without distinguishing between uplink and downlink pipelines.

[0070] Figure 10 In addition to providing data forwarding functionality between the input / output ports, the SW / TM circuit 33 (corresponding to TM circuit 513 and SW circuit 514) can also provide data forwarding functionality between various switching blocks 51 through the first switching interface 517 and the second switching interface 518. In this case, the bandwidth of the first switching interface 517 and the bandwidth of the second switching interface 518 can be greater than, less than, or equal to the bandwidth of the input / output ports coupled to the SW / TM circuit 33.

[0071] Figure 11The SW / TM circuit 33 (corresponding to TM circuit 513 and SW circuit 514) not only provides data forwarding functionality between the input / output ports, but also provides data forwarding functionality between the various switching blocks 51 through the routing circuit 516 and the coupled first switching interface 517 and second switching interface 518. In this case, the bandwidth between the SW / TM circuit 33 and the routing circuit 516, the bandwidth of the first switching interface 517, and the bandwidth of the second switching interface 518 can be greater than, less than, or equal to the bandwidth of the input / output ports coupled to the SW / TM circuit 33. For example, all bandwidths should be the same (e.g., 3.2 Tbps) to ensure non-blocking packet forwarding between the various switching blocks.

[0072] The switching block 51 (e.g., the buffer 515 of the switching block 51) stores a switching table. The control circuit 55 can modify each entry in the switching table to control the switching block 51 to execute the switching method provided in this embodiment to forward the received data. The entries in the switching table are used to indicate the mapping relationship between the destination port of the data and the first switching interface 517, the second switching interface 518, or the input / output port 52 coupled to the switching block 51, so that the SW circuit 514 or the routing circuit 516 in the switching block 51 can determine whether to forward the data to the first switching interface 517, the second switching interface 518, or the corresponding input / output port 52 based on the destination port of the received data and the mapping relationship.

[0073] For example, for a switching block 51 that is not the target switching block for data, when this switching block 51 receives data through the corresponding input / output port 52 or the second switching interface 518, this switching block 51 can select the first switching interface 517 to forward the data according to the switching table. That is, for data received through inter-group switching via the second switching interface 518, or for data received through external switching via the input / output port 52, the switching block 51 performs intra-group switching through the first switching interface 517, achieving load balancing and similar power consumption among the switching blocks 51 in the same group. This avoids the temperature in some areas of the switching device being much higher than in other areas, reducing the difficulty of power supply and heat dissipation design.

[0074] For example, when the switching block 51 receives data through the corresponding input / output port 52 or the second switching interface 518, the switching block 51 can simultaneously select the first switching interface 517 and the second switching interface 518 to forward the data according to the switching table. That is, for data received through inter-group switching via the second switching interface 518, or for data received through external switching via the input / output port 52, the switching block 51 performs intra-group switching through the first switching interface 517 and inter-group switching through the second switching interface 518. This achieves load balancing and similar power consumption for each switching block 51 in the same group, and also ensures that each switching block 51 in different groups participates in data switching with similar power consumption. This avoids the temperature in some areas of the switching device being much higher than in other areas, reducing the difficulty of power supply and heat dissipation design.

[0075] For example, when the switching block 51 receives data through the first switching interface 517, it can select the second switching interface 518 or the corresponding input / output port 52 to forward the data according to the switching table. That is, for data received from intra-group switching through the first switching interface 517, the switching block 51 can perform inter-group switching through the second switching interface 518, or directly forward the data through the input / output port 52. This allows switching blocks 51 in different groups to participate in data exchange with similar power consumption, avoiding the temperature in some areas of the switching device being much higher than in other areas, and reducing the difficulty of power supply and heat dissipation design.

[0076] The following describes the coupling methods between the various switching blocks and the data exchange methods.

[0077] The first bus 53 and the second bus 54 between the various switching blocks 51 can be collectively referred to as the inter-block bus (IBB). The inter-block bus can also be used for the connection between each switching block 51 and the input / output port 52.

[0078] For any group (e.g., any row) of N switching blocks 51, the SW circuit 514 of any switching block 51 is coupled to the first switching interfaces 517 of the remaining N-1 switching modules through multiple first switching interfaces 517, that is, the first switching interfaces 517 of the same group of switching blocks 51 are coupled together. For different groups (e.g., any column) of M switching blocks 51, the SW circuit 514 of any switching block 51 is coupled to the second switching interfaces 518 of the remaining M-1 switching blocks 51 through multiple second switching interfaces 518, that is, the second switching interfaces 518 of different groups of switching blocks 51 are coupled together. In other words, the N switching blocks 51 of the same group are coupled to each other through the first switching interfaces 517, and the M switching blocks 51 of different groups are coupled to each other through the second switching interfaces 518, so as to realize the non-blocking transmission of data packets between the switching blocks 51.

[0079] Data packet transmission between switching blocks is directional. For three switching blocks 51 in the same group, the first switching interface 517 of each switching block 51 is coupled to the first switching interfaces 517 of the other two switching blocks 51 in the same group via a first bus 53. For three switching blocks 51 in different groups, the second switching interface 518 of each switching block 51 is coupled to the second switching interfaces 518 of the other two switching blocks 51 via a second bus 54. The first bus 53 and the second bus 54 can be referred to as fanout buses. Figure 12 The first bus 53 and the second bus 54 are 1-to-2 fan-out buses. This connection method allows any switching block 51 to directly send the load to another coupled switching block 51.

[0080] The first bus 53 and the second bus 54 can also be connected in other ways. For example, a data packet sent from switching block a1 to switching block c1 can be forwarded via switching block b1. Alternatively, a crossbar matrix independent of each switching block can be used to switch data packets between the switching blocks. This application does not limit the connection method between the switching blocks 51.

[0081] Before exchanging data packets with the target switching block 51, the source switching block 51 may request authorization from the target switching block 51. When the input / output port coupled to the target switching block 51 is blocked, the target switching block 51 may refuse authorization. In this case, the source switching block 51 will not exchange data packets with the target switching block 51 temporarily, thereby reducing the buffering pressure of the new data packets on the buffer 515 in the target switching block 51.

[0082] In addition, after completing the uplink data packet processing, the PP circuit 34 in the source switching block 51 can generate meta data and send it to the PP circuit 34 in the target switching block 51. The PP circuit 34 in the target switching block 51 then performs further processing on the downlink data packet based on the meta data.

[0083] The request-authorization communication between each switching block 51, and the transmission of metadata between the PP circuits 34 in each switching block 51, can either share the bus with the payload transmission, or they can be independent of the bus for transmitting the payload. That is, the first bus 53 and the second bus 54 can include different types of buses; for example, some buses are used for payload transmission, some buses are used for metadata transmission, and some buses are used for request-authorization communication.

[0084] The following example demonstrates... Figure 13 The switching method shown illustrates the data forwarding process of the aforementioned switching device. For example... Figure 13 As shown, the switching method performed by the switching device provided in this application embodiment includes:

[0085] S101, the source switching block in the first group of switching blocks inputs multiple data through the first input / output port among multiple input / output ports.

[0086] Multiple data may include header data from multiple data packets and payload data from multiple data packets.

[0087] In this embodiment of the application, each switching block 51 in the above-mentioned switching device can achieve Figure 2 The vertebral structure in [the text]. For example... Figure 14 As shown (the bus between the switching block 51 and the input / output port 52 is omitted), for a switching device including 6*3 switching blocks 51, the three switching blocks 51 in each group can be logically used as Figure 2 In a leaf node 21, the six swap blocks 51 from different groups are logically treated as Figure 2 A ridge node 22 is used to achieve this. Figure 2 A spine-leaf architecture with three spine nodes and six leaf nodes can be called a distributed spine-leaf (DSL) architecture, where each switching block 51 belongs to both a leaf node and a spine node. Furthermore, one or more groups of switching blocks 51 can be logically considered as... Figure 2 In a leaf node 21, more swap blocks 51 from different groups are logically treated as Figure 2 One of the ridge nodes 22. This application does not limit the correspondence between leaf nodes or ridge nodes and swap blocks 51.

[0088] For example, such as Figure 15 As shown, assuming a row (within a leaf node 21) of switching blocks 51 is considered as a group of switching blocks, the first group of switching blocks includes switching block a1, switching block b1, and switching block c1, where switching block a1 is the source switching block 51. Switching block a1 receives multiple first data packets through a first input / output port 52 coupled to switching block a1. These multiple first data packets include payload and header data, meaning the multiple data packets include the payload and header data from the multiple first data packets. The MAC circuit 511 in switching block a1 processes the multiple first data packets according to the Ethernet protocol, and the PP circuit 512 in switching block a1 processes the multiple first data packets to obtain the payload and header data from the multiple first data packets, and sends them to the TM circuit 513 and SW circuit 514 in switching block a1. The TM circuit 513 in switching block a1 adds the payload and header data from the multiple first data packets to queues according to the data in the headers of the multiple first data packets, and schedules these queues according to a certain QoS policy.

[0089] S102, The source switching block distributes multiple data in the first group of switching blocks through the first switching interface.

[0090] For example, such as Figure 15 As shown, the SW circuit 514 in switching block a1 writes the payload and header data from multiple first data packets into buffer 515, and distributes the payload and header data from the multiple first data packets to the SW circuits 514 in the first group of switching blocks a1, b1, and c1 through the first switching interface 517, according to the scheduling result of the TM circuit 513. For example, assuming the multiple first data packets are data packet A, data packet B, and data packet C, the SW circuit 514 in switching block a1 obtains the payload and header data from data packet A, the SW circuit 514 in switching block b1 obtains the payload and header data from data packet B, and the SW circuit 514 in switching block c1 obtains the payload and header data from data packet C. This can achieve load balancing (LB) between different spine nodes 22.

[0091] There are many specific load balancing algorithms. For example, multiple data packets can be exchanged to different switching blocks 51 within the same group of switching blocks in a round-robin manner. Alternatively, multiple data packets can be exchanged to different switching blocks 51 within the same group of switching blocks based on data in the packet header (such as source port, destination port, etc.). In addition, the load balancing strategy can be adjusted according to the load of each ridge node 22.

[0092] S103, The first group of switching blocks exchanges multiple data to the second group of switching blocks through the second switching interface.

[0093] For example, such as Figure 15 As shown, assume the second set of switching blocks includes switching block a3, switching block b3, and switching block c3. The SW circuit 514 in switching block a1, based on the destination port of the packet header in packet A, exchanges the payload and data in the packet header of packet A to the SW circuit 514 in switching block a3 via the second switching interface 518. Similarly, the SW circuit 514 in switching block b1, based on the destination port of the packet header in packet B, exchanges the payload and data in the packet header of packet B to the SW circuit 514 in switching block b3 via the second switching interface 518. Likewise, the SW circuit 514 in switching block c1, based on the destination port of the packet header in packet C, exchanges the payload and data in the packet header of packet C to the SW circuit 514 in switching block c3 via the second switching interface 518. This allows for independent switching of multiple data packets between different leaf nodes 21 within the same ridge node 22. Since load balancing is achieved among the ridge nodes 22, blocking issues can be avoided, achieving non-blocking switching.

[0094] S104. The second group of switching blocks aggregates multiple data into the target switching block in the second group of switching blocks through the first switching interface.

[0095] For example, such as Figure 15 As shown, assuming that switching block c1 in the second group of switching blocks is the target switching block 51, the SW circuit 514 in switching block a3 exchanges the payload and header data in data packet A to the SW circuit 514 in switching block c3, and the SW circuit 514 in switching block b3 exchanges the payload and header data in data packet B to the SW circuit 514 in switching block c3, that is, the payload and header data in multiple first data packets are converged to the target switching block 51.

[0096] It should be noted that if it is a multicast service, there can be multiple target switching blocks 51.

[0097] S105, the target switching block outputs multiple data through the second input / output port among multiple input / output ports.

[0098] The target switching block 51 can output multiple data packets through its corresponding second input / output port in the order in which they are received from multiple switching blocks 51 (specifically, the source switching block 51). That is, the target switching block 51 can encapsulate the payloads in the multiple first data packets based on the data in their headers to obtain multiple second data packets, and then send these second data packets in the order in which they are received from the first data packets.

[0099] The reason why target switching block 51 reorders multiple data is that multiple data after load balancing will be exchanged to target switching block 51 through different switching blocks 51. Due to the different processing delays of each switching block 51, multiple data may arrive before the last ones. Whether reordering is necessary or the difficulty of reordering depends on the load balancing algorithm used.

[0100] For example, such as Figure 15As shown, the SW circuit 514 in switching block c1 sends the payload and header data of multiple first data packets to the PP circuit 512 in switching block c1. The PP circuit 512 in switching block c1 processes the payload and header data of the multiple first data packets to obtain multiple second data packets, and sends them to the MAC circuit 511 in switching block c1. The MAC circuit 511 in switching block c1 determines the second input / output port 52 according to the destination port in the header of the multiple first data packets, and outputs the multiple second data packets through the second input / output port 52 according to the receiving order of the multiple first data packets. For example, the target switching block 51 couples 12 800Gbps input / output ports 52, that is, the bandwidth of the input / output ports 52 coupled to the target switching block 51 is 9.6Tbps. The target switching block 51 determines the second input / output port 52 among the 12 input / output ports 52 according to the destination port of the payload.

[0101] The switching apparatus, switching method, and switching device provided in this application embodiment implement data packet switching processing through multiple switching blocks with identical structures, and the multiple switching blocks form a DSL structure, which has the following technical effects:

[0102] Good feasibility: Chips with different bandwidths can include different numbers of switching blocks, avoiding the difficulties of top-level design of the switching device. For example, in a traditional spine-leaf architecture design, if a switching device with a bandwidth of 25.6Tbps includes four leaf nodes with a bandwidth of 6.4Tbps and four spine nodes with a bandwidth of 6.4Tbps, the design of the leaf nodes and spine nodes needs to be completed separately and then connected to form a spine-leaf architecture. However, in the embodiment of this application, a 4x4 DSL matrix can be built based on 16 switching blocks with a bandwidth of 1.6Tbps. Furthermore, the connection method of each switching block is consistent, for example, all use fan-out bus connection, simplifying bus design. In addition, since the switching blocks are divided into at least two groups, the switching blocks within the same group exchange data through the first switching interface, and the switching blocks between groups exchange data through the second switching interface. For data received from inter-group switching via the second switching interface, or for data received from external switching via the input / output ports, the switching block performs intra-group switching via the first switching interface. This achieves load balancing and similar power consumption among the switching blocks in the same group, preventing the temperature in some areas of the switching device from being much higher than in other areas, and reducing the difficulty of power supply and heat dissipation design.

[0103] Reduced latency: Each switching block can independently exchange data packets. For example, in a switching device with 16 switching blocks, each block is coupled with four input / output ports, and each input / output port has a bandwidth of 400Gbps. Therefore, each switching block has a bandwidth of 1.6Tbps, and the switching device has a bandwidth of 25.6Tbps. Data packet exchange between these four input / output ports of each switching block can be completed within the same switching block. Data packet exchange between any two switching blocks requires at most one forwarding. Furthermore, data packet exchange only needs to pass through the switch circuit or routing circuit, without needing to pass through other circuits, thus reducing latency.

[0104] It has good scalability. For example... Figure 6 and Figure 7 As described, switching blocks located in switching devices on different dies can be coupled together via a first bus and a second bus, which facilitates the expansion of the scale of the switching device 50 and improves the system switching capacity.

[0105] like Figure 16 As shown, this application embodiment also provides a switching device 160, which can be a switch. The switching device 160 includes at least one switching unit 50 as described above, and a memory 161 coupled to the switching unit 50. The switching unit 50 can be a switching chip. The switching unit 50 is used to exchange data packets with other communication devices.

[0106] This application provides a computer-readable storage medium for storing one or more programs, wherein the one or more programs include instructions that, when executed by a switching device, cause the switching device to perform actions such as... Figure 13 The method shown.

[0107] This application provides a computer program product including instructions, which, when executed by a switching device, cause the switching device to perform actions such as... Figure 13 The method shown.

[0108] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0109] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0110] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0111] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0112] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0113] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0114] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0115] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A switching device, characterized by include: Multiple switching blocks, and multiple input / output ports corresponding to the multiple switching blocks; The plurality of switching blocks are configured to receive data through corresponding input / output ports, forward the data to a target switching block of the data in the plurality of switching blocks, and send the data through the input / output port corresponding to the target switching block; wherein, the plurality of switching blocks includes a first switching block; The plurality of switching blocks are divided into at least two groups of switching blocks. Each switching block includes a first switching interface and a second switching interface. The first switching interface is used to exchange data with switching blocks in the same group, and the second switching interface is used to exchange data with switching blocks in different groups. The switching device further includes a control circuit for: when the first switching block receives the data through the corresponding input / output port or the second switching interface, controlling the first switching block to select the first switching interface to forward the data.

2. The switching device of claim 1, wherein The control circuit is further configured to: when the first switching block receives the data through the corresponding input / output port or the second switching interface, control the first switching block to simultaneously select the first switching interface and the second switching interface to forward the data.

3. The exchange device according to claim 1 or 2, characterized in that The control circuit is further configured to: when the first switching block receives the data through the first switching interface, control the first switching block to select the second switching interface or the corresponding input / output port to forward the data.

4. The exchange device according to any of claims 1-3, characterized in that The switching block further includes a switching circuit coupled to the corresponding input / output port, the first switching interface, and the second switching interface. The switching circuit is used to exchange data with other switching blocks through the first switching interface and the second switching interface, and to exchange data with the corresponding input / output port.

5. The switching device according to any one of claims 1-3, characterized in that, The switching block further includes coupled switching circuits and routing circuits. The switching circuits are coupled to the corresponding input / output ports and are used to exchange data with the routing circuits and the corresponding input / output ports. The routing circuits are coupled to the first switching interface and the second switching interface and are used to exchange data with other switching blocks through the first switching interface and the second switching interface.

6. The switching device according to any one of claims 1-5, characterized in that, The target switching block is used to output the data through the corresponding input / output port in the order in which the data is received from the plurality of switching blocks.

7. The switching device according to any one of claims 1-6, characterized in that, The same set of swap blocks are set on different dies.

8. The switching device according to any one of claims 1-7, characterized in that, Different groups of swap blocks are set on different dies.

9. The switching device according to any one of claims 1-8, characterized in that, The first switching interfaces of the same group of switching blocks are coupled through a fan-out bus, and the second switching interfaces of different groups of switching blocks are coupled through a fan-out bus.

10. The switching device according to any one of claims 1-9, characterized in that, The switching device is a switching chip.

11. The switching device according to any one of claims 1-9, characterized in that, The switching block refers to a circuit with data exchange functionality.

12. An exchange method, characterized in that, Applied to a switching device as described in any one of claims 1-11, the method comprises: When the first switching block receives data through the corresponding input / output port or the second switching interface, it controls the first switching block to select the first switching interface to forward the data.

13. The method according to claim 12, characterized in that, When the first switching block receives data through the corresponding input / output port or the second switching interface, controlling the first switching block to select the first switching interface to forward the data includes: When the first switching block receives the data through the corresponding input / output port or the second switching interface, it controls the first switching block to simultaneously select the first switching interface and the second switching interface to forward the data.

14. The method according to claim 12 or 13, characterized in that, Also includes: When the first switching block receives the data through the first switching interface, it controls the first switching block to select the second switching interface or the corresponding input / output port to forward the data.

15. A switching device, characterized in that, It includes a switching device as described in any one of claims 1-11 and a memory coupled to the switching device, wherein the switching device is a switching chip.

16. A computer-readable storage medium for storing one or more programs, characterized in that, The one or more programs include instructions that, when executed by the switching device, cause the switching device to perform the method as described in any one of claims 12-14.

17. A computer program product comprising instructions, characterized in that, When the instruction is executed by the switching device, the switching device performs the method as described in any one of claims 12-14.

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