Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure relates to the field of semiconductor technology, and provides a semiconductor structure and a method for manufacturing the same. The manufacturing method includes: providing a substrate, the substrate including a first region and a second region; sequentially forming a gate dielectric layer, a gate material layer and a barrier material layer on the substrate; doping the barrier material layer with a first type of element so that the first type of element is gathered in the barrier material layer, and the barrier material layer can block the first type of element from entering the gate material layer; at least removing the barrier material layer directly above the second region, and at least retaining the barrier material layer directly above the first region; doping the gate material layer directly above the second region with a second type of element; performing a heating treatment so that the first type of element gathered in the barrier material layer diffuses to the gate material layer on the square of the first region. The semiconductor manufacturing method has a relatively simple process.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the related art, semiconductor structures usually need to integrate N-type transistors and P-type transistors at the same time. In the polysilicon gate transistor process, different types of doping are required for the polysilicon gates of the N-type transistors and the P-type transistors to reduce the threshold voltage of the transistors.

[0003] However, in the related art, the process of performing different types of doping on the polysilicon gates of the N-type transistor and the P-type transistor is relatively complicated.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0006] Providing a substrate, the substrate comprising a first region and a second region;

[0007] forming a gate dielectric layer, a gate material layer and a barrier material layer in sequence on the substrate;

[0008] doping the barrier material layer with a first type of element, so that the first type of element is gathered in the barrier material layer, and the barrier material layer can block the first type of element from entering the gate material layer;

[0009] removing at least the barrier material layer directly above the second region, and retaining at least the barrier material layer directly above the first region;

[0010] doping the gate material layer directly above the second region with a second type of element;

[0011] A heating process is performed to diffuse the first type elements gathered in the barrier material layer into the gate material layer on the square of the first region.

[0012] In an exemplary embodiment of the present disclosure, the substrate is a semiconductor substrate, at least a portion of the structure of the first region is used to form a channel region of a first type transistor, and at least a portion of the structure of the second region is used to form a channel region of a second type transistor;

[0013] The first type transistor is a P type transistor, the second type transistor is an N type transistor, the first type element is a P type doping element, and the second type element is an N type doping element;

[0014] Or, the first type transistor is an N-type transistor, the second type transistor is a P-type transistor, the first type element is an N-type doped element, and the second type element is a P-type doped element.

[0015] In an exemplary embodiment of the present disclosure, the gate material layer is a polysilicon material layer;

[0016] The barrier material layer is a polysilicon material layer doped with carbon atoms.

[0017] In an exemplary embodiment of the present disclosure, doping the barrier material layer with a first type element includes:

[0018] doping the barrier material layer with a first type of element by an ion implantation process;

[0019] Doping the gate material layer directly above the second region with a second type of element comprises:

[0020] The gate material layer directly above the second region is doped with a second type element by using an ion implantation process.

[0021] In an exemplary embodiment of the present disclosure, the doping concentration of carbon atoms in the barrier material layer is 10 20 / cm 3 -10 21 / cm 3 .

[0022] In an exemplary embodiment of the present disclosure, the thickness of the gate material layer is h1, the thickness of the barrier material layer is h2, and h1 / h2 is greater than or equal to 3 and less than or equal to 9.

[0023] In an exemplary embodiment of the present disclosure, the thickness of the blocking material layer is 3nm-8nm, and the thickness of the gate material layer is 23nm-28nm.

[0024] In an exemplary embodiment of the present disclosure, at least the barrier material layer directly above the second region is removed, and at least the barrier material layer directly above the first region is retained, comprising:

[0025] Forming a patterned photoresist layer by a photolithography process to expose at least the barrier material layer directly above the second region and to cover at least the barrier material layer directly above the first region;

[0026] The blocking material layer directly above the exposed second region is removed by etching using the patterned photoresist layer as a mask.

[0027] In an exemplary embodiment of the present disclosure, doping the gate material layer directly above the second region with a second type of element includes:

[0028] The patterned photoresist layer is used as a mask to dope the gate material layer directly above the second region with a second type of element.

[0029] In an exemplary embodiment of the present disclosure, the manufacturing method further includes:

[0030] forming at least one metal material layer on a side of the barrier material layer facing away from the substrate;

[0031] forming a passivation material layer on a side of the metal material layer facing away from the substrate;

[0032] forming at least one mask layer on a side of the passivation material layer facing away from the substrate;

[0033] The mask layer, passivation material layer, metal material layer, barrier material layer, gate material layer, and gate dielectric layer are patterned so that the gate material layer, the metal material layer, and a partial structure of the barrier material layer directly above the first region form a first gate portion, and the gate material layer and a partial structure of the metal material layer directly above the second region form a second gate portion.

[0034] In an exemplary embodiment of the present disclosure, the present invention further includes:

[0035] removing the mask layer;

[0036] Performing lightly doped drain treatment on the first region and the second region;

[0037] Forming a sidewall structure on the sidewalls of the first gate portion and the second gate portion, wherein the sidewall structure includes a single layer or multiple layers of insulating material;

[0038] The first region and the second region are heavily doped with source and drain.

[0039] In an exemplary embodiment of the present disclosure, a heating process is performed, including:

[0040] A rapid thermal treatment is performed, wherein the temperature range of the rapid thermal treatment is 800° C. to 1000° C., and the time range of the rapid thermal treatment is 1 minute to 7 minutes.

[0041] According to one aspect of the present disclosure, a semiconductor structure is provided, which includes: a substrate, a first gate structure, and a second gate structure, wherein the substrate includes a first region and a second region; the first gate structure is located on the surface of the first region, the first gate structure includes a first gate dielectric layer and a first gate conductive layer, wherein the first gate conductive layer includes a gate layer and a barrier layer, the barrier layer is located on a side of the gate layer away from the substrate, the first gate conductive layer is located on a side of the first gate dielectric layer away from the substrate, and the gate layer and the barrier layer are doped with a first type of element; the second gate structure is located on the surface of the second region, the second gate structure includes a second gate dielectric layer and a second gate conductive layer, the second gate conductive layer is located on a side of the second gate dielectric layer away from the substrate, and the second gate conductive layer is doped with a second type of element.

[0042] In an exemplary embodiment of the present disclosure, the substrate is a semiconductor substrate, at least a portion of the structure of the first region is used to form a channel region of a first type transistor, and at least a portion of the structure of the second region is used to form a channel region of a second type transistor;

[0043] The first type transistor is a P-type transistor, and the second type transistor is an N-type transistor;

[0044] Alternatively, the first type transistor is an N-type transistor, and the second type transistor is a P-type transistor.

[0045] In an exemplary embodiment of the present disclosure, the second gate conductive layer includes a polysilicon material layer doped with a second type element;

[0046] The gate layer includes a polysilicon material layer doped with a first type element.

[0047] In an exemplary embodiment of the present disclosure, the blocking layer includes: a semiconductor layer, a first type element, and blocking particles, wherein the first type element is doped into the semiconductor layer; and the blocking particles are doped into the semiconductor layer.

[0048] In an exemplary embodiment of the present disclosure, the blocking particles include carbon atoms, and the semiconductor layer includes a polysilicon material layer.

[0049] In an exemplary embodiment of the present disclosure, the doping concentration of carbon atoms in the barrier layer is 10 20 / cm 3 -10 21 / cm 3 .

[0050] In an exemplary embodiment of the present disclosure, the thickness of the gate layer is h1, the thickness of the barrier layer is h2, and h1 / h2 is greater than or equal to 3 and less than or equal to 9.

[0051] In an exemplary embodiment of the present disclosure, the thickness of the barrier layer is 3nm-8nm, and the thickness of the gate layer is 23nm-28nm.

[0052] In an exemplary embodiment of the present disclosure, the substrate further includes:

[0053] A shallow trench isolation structure is located between the first region and the second region.

[0054] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0056] Figure 1-5 A schematic diagram of a manufacturing process of a semiconductor structure in the related art;

[0057] Figure 6 A flowchart of an exemplary embodiment of a semiconductor manufacturing method disclosed in the present invention;

[0058] Figure 7-18 A schematic diagram of a manufacturing process in an exemplary embodiment of a semiconductor structure manufacturing method disclosed in the present invention;

[0059] Fig.19 It is a structural schematic diagram of an exemplary embodiment of the semiconductor structure disclosed in the present invention. DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0061] The terms "a", "an", and "the" are used to indicate the presence of one or more elements / component distinctions / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / component distinctions / etc. may exist in addition to the listed elements / component distinctions / etc.

[0062] In the related art, semiconductor structures usually need to integrate N-type transistors and P-type transistors at the same time. In the polysilicon gate transistor process, different types of doping are required for the polysilicon gates of the N-type transistors and the P-type transistors to reduce the threshold voltage of the transistors.

[0063] like Figure 1-5 As shown in FIG. , it is a schematic diagram of the manufacturing process of the semiconductor structure in the related art. Figure 1 As shown, the semiconductor structure manufacturing method in the related art may include: providing a semiconductor substrate 1, the semiconductor substrate 1 may include a first region 11, a second region 12, and a shallow trench isolation structure 13, the shallow trench isolation structure 13 is located between the first region 11 and the second region 12, and the shallow trench isolation structure 13 can be used to isolate semiconductor devices in the first region 11 and the second region 12. The first region 11 may be an N-type semiconductor material, and a portion of the structure of the first region may be used to form a P-type transistor channel region; the second region 12 may be a P-type semiconductor material, and a portion of the structure of the second region 12 may be used to form an N-type transistor channel region. The semiconductor structure manufacturing method may also include: forming a gate dielectric layer 2 on one side of the semiconductor substrate 1, and the gate dielectric layer 2 may be formed integrally with the shallow trench isolation structure 13 when the shallow trench isolation structure 13 is formed. As shown Figure 2 As shown, the semiconductor structure manufacturing method may further include: forming a polysilicon gate layer 3 on the side of the gate dielectric layer 2 away from the semiconductor substrate 1. Figure 3 As shown, the semiconductor structure manufacturing method may also include: forming a patterned first photoresist layer PR1 on the side of the polysilicon gate layer 3 away from the semiconductor substrate, the orthographic projection of the first photoresist layer PR1 on the substrate covers the first area 11, and the orthographic projection of the first photoresist layer PR1 on the substrate does not overlap with the second area 12; then N-type doping may be performed on the polysilicon gate layer 3 exposed outside the first photoresist layer PR1, for example, phosphorus ion doping may be performed on the polysilicon gate layer 3 exposed outside the first photoresist layer PR1 by an ion implantation process. Figure 4 As shown, the semiconductor structure manufacturing method may also include: removing the first photoresist layer PR1, forming a patterned second photoresist layer PR2 on the side of the polysilicon gate layer 3 away from the semiconductor substrate, the orthographic projection of the second photoresist layer PR2 on the substrate covers the second area 12, and the orthographic projection of the second photoresist layer PR2 on the substrate does not overlap with the first area 11; then, the polysilicon gate layer 3 exposed outside the second photoresist layer PR2 may be doped with P-type, for example, the polysilicon gate layer 3 exposed outside the second photoresist layer PR2 may be doped with boron ions by an ion implantation process. Figure 5As shown, the semiconductor structure manufacturing method may further include: diffusing and activating the impurity ions in the polysilicon gate layer 3 by RTP (rapid thermal processing).

[0064] However, in the related art, when ion doping is performed on the polysilicon gate layer, two patterned photoresist layers need to be formed: a first photoresist layer and a second photoresist layer. Therefore, the manufacturing process of the semiconductor structure in the related art is relatively complicated.

[0065] Based on this, this exemplary embodiment provides a semiconductor manufacturing method, such as Figure 6 As shown, it is a flow chart of an exemplary embodiment of the semiconductor manufacturing method disclosed in the present invention. The semiconductor structure may include a first type transistor and a second type transistor, and the manufacturing method may include:

[0066] Step S1: providing a substrate, wherein the substrate comprises a first region and a second region;

[0067] Step S2: forming a gate dielectric layer, a gate material layer and a barrier material layer in sequence on the substrate;

[0068] Step S3: doping the barrier material layer with a first type of element, so that the first type of element is gathered in the barrier material layer, and the barrier material layer can block the first type of element from entering the gate material layer;

[0069] Step S4: removing at least the barrier material layer directly above the second region, and retaining at least the barrier material layer directly above the first region;

[0070] Step S5: doping the gate material layer directly above the second region with a second type of element;

[0071] Step S6: performing a heating process to diffuse the first type elements gathered in the barrier material layer into the gate material layer on the square of the first region.

[0072] The semiconductor manufacturing method provided by this exemplary embodiment has a relatively simple process flow, and the following exemplary embodiment describes the above steps in detail:

[0073] like Figure 7-18 , which is a process diagram of an exemplary embodiment of the semiconductor structure manufacturing method disclosed in the present invention.

[0074] like Figure 7As shown, step S1 may include: providing a substrate 1, which may be a semiconductor substrate, and the substrate 1 may include a first region 11 and a second region 12. The semiconductor structure may include a first type transistor and a second type transistor. At least a portion of the structure of the first region 11 may be used to form a channel region of the first type transistor, and at least a portion of the structure of the second region 12 may be used to form a channel region of the second type transistor. In this exemplary embodiment, one of the first type transistor and the second type transistor is an N-type transistor, and the other transistor is a P-type transistor. This exemplary embodiment is described by taking the first type transistor as a P-type transistor and the second type transistor as an N-type transistor as an example. Accordingly, in this exemplary embodiment, the first region 11 may be an N-type semiconductor material, and the second region 12 may be a P-type semiconductor material. In this exemplary embodiment, the substrate 1 may be directly formed by a wafer, or may be formed by a semiconductor epitaxial layer on a wafer. The substrate 1 may be a flat plate structure, and the shape of the substrate 1 may be circular, rectangular, elliptical, etc. The material of the substrate 1 may be a silicon semiconductor material. It should be understood that in other exemplary embodiments, the material of the substrate 1 may also be a semiconductor material such as chromium or gallium arsenide.

[0075] In this exemplary embodiment, Figure 7 As shown, the substrate 1 may further include a shallow trench isolation structure 13. The shallow trench isolation structure 13 may be located between the first region 11 and the second region 12. The shallow trench isolation structure 13 may be used to isolate semiconductor devices in the first region 11 and the second region 12. The formation method of the shallow trench isolation structure 13 may include: forming an isolation trench on the substrate 1 using an etching process; depositing a silicon oxide material layer on the side of the substrate 1 where the isolation trench is provided using a deposition process; and flattening the surface of the silicon oxide material using a chemical mechanical polishing process. Among them, the silicon oxide material filled in the isolation trench forms a shallow trench isolation structure 13. The silicon oxide material formed on the surface of the substrate 1 may form a gate dielectric layer 2. It should be understood that in other exemplary embodiments, the shallow trench isolation structure 13 and the gate dielectric layer 2 may also be formed by other methods. For example, the shallow trench isolation structure 13 and the gate dielectric layer 2 may be formed by different deposition processes. As Figure 7 As shown, the substrate 1 may further include a silicon nitride layer 14 , and the silicon nitride layer 14 may conformally cover the inner side of the isolation trench, that is, the silicon nitride layer 14 is isolated between the shallow trench isolation structure 13 and the first region 11 and the second region 12 .

[0076] like Figure 8 , 9As shown, step S2 may also include: sequentially forming a gate material layer 3 and a barrier material layer 4 on the substrate 1. The gate material layer 3 may be formed of a semiconductor material, and the gate material layer 3 may include a first semiconductor portion 31 and a second semiconductor portion 32, wherein the orthographic projection of the first semiconductor portion 31 on the substrate 1 covers the first region 11, and the orthographic projection of the second semiconductor portion 32 on the substrate 1 covers the second region 12. The partial structure of the first semiconductor portion 31 after doping may be used to form a gate of a first type transistor, and the partial structure of the second semiconductor portion 32 after doping may be used to form a gate of a second type transistor. In this exemplary embodiment, the gate material layer 3 may be a polycrystalline silicon layer. It should be understood that in other exemplary embodiments, the gate material layer 3 may also be other semiconductor material layers. As Figure 8 As shown, the orthographic projection of the first semiconductor portion 31 on the substrate 1 can also cover part of the shallow trench isolation structure 13, and the orthographic projection of the second semiconductor portion 32 on the substrate 1 can also cover part of the shallow trench isolation structure 13. The gate material layer 3 formed by the first semiconductor portion 31 and the second semiconductor portion 32 can cover the entire semiconductor substrate. Figure 9-12 As shown, the barrier material layer 4 may cover the entire gate material layer 3. The barrier material layer 4 may include a first barrier portion 41 and a second barrier portion 42, wherein the orthographic projection of the first barrier portion 41 on the substrate 1 may cover the first region 11, and the orthographic projection of the second barrier portion 42 on the substrate 1 may cover the second region 12. For example, the orthographic projection of the first barrier portion 41 on the substrate 1 may coincide with the orthographic projection of the first semiconductor portion 31 on the substrate 1, and the orthographic projection of the second barrier portion 42 on the substrate 1 may coincide with the orthographic projection of the second semiconductor portion 32 on the substrate 1. In this exemplary embodiment, the silicon oxide material layer, the gate material layer 3, and the barrier material layer 4 may be formed by deposition processes such as an electrochemical deposition process, a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process.

[0077] like Fig. 9 As shown, in this exemplary embodiment, the barrier material layer 4 may include: a semiconductor layer, a first type element, and barrier particles, wherein the first type element is doped in the semiconductor layer, and the barrier particles are doped in the semiconductor layer. For example, the barrier particles may include carbon atoms, and the semiconductor layer may include a polysilicon material layer. The doping concentration of carbon atoms in the polysilicon material layer may be 10 20 / cm 3 -10 21 / cm 3 For example, the doping concentration of carbon atoms in the polysilicon material layer can be 10 20 / cm 3 , 3*10 20 / cm3 , 5*10 20 / cm 3 ,7*10 20 / cm 3 , 10 21 / cm 3 The barrier material layer 4 may be formed by mixing gaseous carbon into the gaseous raw material for forming polycrystalline silicon, thereby forming a polycrystalline silicon layer doped with carbon atoms through a vapor deposition process. The barrier material layer 4 may also be formed by first forming a polycrystalline silicon layer, and then doping carbon atoms into the polycrystalline silicon layer through a diffusion process. It should be understood that in other exemplary embodiments, the semiconductor layer may also be a layer of other semiconductor materials, for example, the semiconductor layer may also be a semiconductor material such as chromium or gallium arsenide. The barrier particles may also be other atoms or molecules.

[0078] The thickness of the gate material layer 3 is h1, the thickness of the barrier material layer 4 is h2, and h1 / h2 may be greater than or equal to 3 and less than or equal to 9. For example, h1 / h2 may be equal to 3, 5, 6, 7, 8, 9, etc. In this exemplary embodiment, the thickness of the barrier material layer 4 may be 3nm-8nm, for example, the thickness of the barrier material layer 4 may be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, etc. The thickness of the gate material layer 3 is 23nm-28nm, for example, the thickness of the gate material layer 3 may be 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, etc.

[0079] like Fig.10 As shown, step S3 may include: doping the barrier material layer 4 with a first type element so that the first type element is gathered in the barrier material layer 4, and the barrier material layer 4 can block the first type element from entering the gate material layer 3. In this exemplary embodiment, the first type element is a P-type doping element, and the P-type doping element can be understood as a material required for doping an intrinsic semiconductor into a P-type semiconductor. In this exemplary embodiment, the semiconductor material of the substrate 1 can be a 4-valent element, and correspondingly, the P-type doping element can be a trivalent element, for example, the P-type doping element can be boron, gallium, etc. In this exemplary embodiment, the barrier material layer 4 can be doped with the first type element by an ion implantation process, and the ion implantation process can be performed at a lower temperature, so that carbon atoms can gather the first type element in the barrier material layer. It should be understood that in other exemplary embodiments, when the first type transistor is an N-type transistor and the second type transistor is a P-type transistor, the first type element can be an N-type doping element, and the N-type doping element can be understood as a material required for doping an intrinsic semiconductor into an N-type semiconductor. In addition, in other exemplary embodiments, the barrier material layer 4 can also be other materials.

[0080] like Fig.11 , 12 As shown, step S4 may include: removing at least the barrier material layer directly above the second region 12, and retaining at least the barrier material layer directly above the first region 11. The barrier material layer directly above the second region 12 may refer to: a barrier material layer whose orthographic projection on the substrate coincides with the second region; the barrier material layer directly above the first region 11 may refer to: a barrier material layer whose orthographic projection on the substrate coincides with the first region. For example, step S4 may include: removing the second blocking portion 42. Removing the second blocking portion 42 may include: forming a whole-surface photoresist material layer on the side of the barrier material layer 4 facing away from the substrate 1; performing photolithography and development on the photoresist material layer through a photolithography process to form a patterned first photoresist layer PR1, the orthographic projection of the first photoresist layer PR1 on the substrate 1 covers the first region 11, and the orthographic projection of the first photoresist layer PR1 on the substrate 1 does not overlap with the second region 12. For example, the orthographic projection of the first photoresist layer PR1 on the substrate 1 may coincide with the orthographic projection of the first barrier portion 41 on the substrate 1. As Fig.12 As shown, removing the second blocking portion 42 may further include: using the first photoresist layer PR1 as a mask to etch the blocking material layer 4 to remove the second blocking portion 42. The blocking material layer 4 may be etched to remove the second blocking portion 42 by a dry etching process.

[0081] like Fig.13 As shown, step S5: doping the gate material layer directly above the second region 12 with a second type of element, wherein the gate material layer directly above the second region 12 may be a gate material layer whose orthographic projection on the substrate coincides with the second region 12. For example, step S5 may include: doping the second semiconductor portion 32 with a second type of element. Wherein, in this exemplary embodiment, the second type of element may be an N-type doping element. When the substrate 1 is a tetravalent semiconductor material, correspondingly, the second type of element may be a pentavalent semiconductor material, for example, the second type of element may be phosphorus, arsenic, etc. It should be understood that in other exemplary embodiments, when the first type of transistor is an N-type transistor and the second type of transistor is a P-type transistor, the second type of element may be a P-type doping element. As Fig.13As shown, in this exemplary embodiment, the second semiconductor portion 32 may be doped with the second type element by an ion implantation process using the first photoresist layer PR1 as a mask. It should be understood that in other exemplary embodiments, the second semiconductor portion 32 may be doped with the second type element by other processes, for example, the second semiconductor portion 32 may be doped with the second type element by a diffusion process. This exemplary embodiment only requires one patterning process of the photoresist layer, that is, different types of doping of the first semiconductor portion 31 and the second semiconductor portion 32 can be achieved.

[0082] like Fig.14 As shown, after doping the second semiconductor portion 32 with the second type element, the manufacturing method may further include: ashing and cleaning the first photoresist layer PR1 to remove the first photoresist layer.

[0083] like Fig.15 As shown, step S6 may include: performing a heating treatment so that the first type elements gathered in the barrier material layer 4 diffuse into the gate material layer on the square of the first region 11. That is, the first type elements in the first barrier portion 41 are diffused into the first semiconductor portion 31. Among them, this exemplary embodiment can be heat treated by RTP (rapid thermal processing, rapid thermal processing) process. At the same time, the RTP process can also activate the impurity ions in the gate material layer 3. In addition, the RTP process can also eliminate defects such as semiconductor lattice damage caused by ion implantation. The RTP process can complete annealing of the heating target in a shorter time by means of pulsed laser, pulsed electron beam, incoherent light source, etc. The temperature range of rapid thermal treatment can be 800℃~1000℃, for example, 800℃, 900℃, 1000℃, etc.; the time range of the rapid thermal treatment is 1 minute to 7 minutes, for example, 1 minute, 3 minutes, 5 minutes, 7 minutes.

[0084] like Fig.16 As shown, a heat treatment is performed, after which the manufacturing method may further include: forming a first metal material layer 5 on the side of the barrier material layer 4 facing away from the substrate 1, forming a second metal material layer 6 on the side of the first metal material layer 5 facing away from the substrate 1, forming a passivation material layer 7 on the side of the second metal material layer 6 facing away from the substrate 1, forming a first mask layer 8 on the side of the passivation material layer 7 facing away from the substrate 1, forming a second mask layer 9 on the side of the first mask layer 8 facing away from the substrate 1, and forming a second photoresist layer PR2 on the side of the second mask layer 9 facing away from the substrate 1.

[0085] In this exemplary embodiment, the first metal material layer 5 may be a tungsten layer, the second metal material layer 6 may be a titanium nitride layer, the passivation material layer 7 may be a silicon nitride layer, the first mask layer 8 may be a spin-on hard mask, and the second mask layer 9 may be a silicon oxynitride layer. In this exemplary embodiment, the first metal material layer 5, the second metal material layer 6, the passivation material layer 7, the first mask layer 8, and the second mask layer 9 may be formed by deposition processes such as an electrochemical deposition process, a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process. Forming a second photoresist layer PR2 on the side of the second mask layer 9 facing away from the substrate 1 may include: forming a whole-surface photoresist material layer on the side of the second mask layer 9 facing away from the substrate 1, and the photoresist material layer may be formed by a coating process; performing photolithography and development on the photoresist material layer by a photolithography process to form a second photoresist layer PR2, and the second photoresist layer PR2 may include a first photoresist portion PR21 and a second photoresist portion PR22, and the orthographic projection of the first photoresist portion PR21 on the substrate 1 may be located in the first region 11, and the orthographic projection of the second photoresist portion PR22 on the substrate 1 may be located in the second region 12.

[0086] like Fig.17As shown, the manufacturing method may also include: etching the second mask layer 9 using the second photoresist layer PR2 as a mask to transfer the pattern of the second photoresist layer PR2 to the second mask layer 9; etching the first mask layer 8 using the second mask layer 9 as a mask to transfer the pattern of the second mask layer 9 to the first mask layer 8; etching the passivation material layer 7, the second metal material layer 6, the first metal material layer 5, the barrier material layer 4, the gate material layer 3, and the gate dielectric layer 2 using the first mask layer 8 as a mask; and then removing the second photoresist layer PR2, the second mask layer 9, and the first mask layer 8. Among them, after being etched, the gate dielectric layer 2 may include a first gate insulating portion 21 and a second gate insulating portion 22, the orthographic projection of the first gate insulating portion 21 on the substrate 1 is located in the first area 11, and the orthographic projection of the second gate insulating portion 22 on the substrate 1 is located in the second area 12; after being etched, the first semiconductor portion 31 may include a first sub-gate portion 311, and after being etched, the second semiconductor portion 32 may include a second sub-gate portion 322, the orthographic projection of the first sub-gate portion 311 on the substrate 1 is located on the orthographic projection of the first gate insulating portion 21 on the substrate 1, and the orthographic projection of the second sub-gate portion 322 on the substrate 1 is located on the orthographic projection of the second gate insulating portion 22 on the substrate 1; after being etched, the first blocking portion 41 may include a sub-blocking portion 411, and the orthographic projection of the sub-blocking portion 411 on the substrate 1 is located on the orthographic projection of the first sub-gate portion 311 on the substrate 1; after being etched, the first metal material layer 5 may include a It includes a first conductive portion 51 and a second conductive portion 52, wherein the orthographic projection of the first conductive portion 51 on the substrate 1 is located on the orthographic projection of the sub-blocking portion 411 on the substrate 1, and the orthographic projection of the second conductive portion 52 on the substrate 1 is located on the orthographic projection of the second sub-gate portion 322 on the substrate 1; after being etched, the second metal material layer 6 includes a third conductive portion 63 and a fourth conductive portion 64, wherein the orthographic projection of the third conductive portion 63 on the substrate 1 is located on the orthographic projection of the first conductive portion 51 on the substrate 1, and the orthographic projection of the fourth conductive portion 64 on the substrate 1 is located on the orthographic projection of the second conductive portion 52 on the substrate 1; after being etched, the passivation material layer 7 may include: a first passivation portion 71 and a second passivation portion 72, wherein the orthographic projection of the first passivation portion 71 on the substrate 1 is located on the orthographic projection of the third conductive portion 63 on the substrate 1, and the orthographic projection of the second passivation portion 72 on the substrate 1 is located on the orthographic projection of the fourth conductive portion 64 on the substrate 1.Among them, the partial structure of the first region 11 located directly below the first sub-gate portion 311 can be used to form a channel region of the first type transistor; the first gate insulating portion 21 can be used to form a gate insulating layer of the first type transistor; the first sub-gate portion 311, the sub-blocking portion 411, the first conductive portion 51, and the third conductive portion 63 can form a first gate portion, and the first gate portion can be used to form a gate of the first type transistor. The first passivation portion 71 can be used to protect the surface of the third conductive portion 63 to avoid damage to the surface of the third conductive portion 63. At the same time, the first passivation portion 71 can also serve as an insulating layer to isolate the third conductive portion 63 from other structures to avoid a short circuit between the third conductive portion 63 and other structures. The partial structure of the second region 12 located directly below the second sub-gate portion 322 can be used to form a channel region of a second type transistor; the second gate insulating portion 22 can be used to form a gate insulating layer of the second type transistor; the second sub-gate portion 322, the second conductive portion 52, and the fourth conductive portion 64 can form a second gate portion, which is used to form a gate of the second type transistor, and the second passivation portion 72 can be used to protect the surface of the fourth conductive portion 64 to avoid damage to the surface of the fourth conductive portion 64; at the same time, the second passivation portion 72 can also serve as an insulating layer to isolate the fourth conductive portion 64 from other structures to avoid a short circuit between the fourth conductive portion 64 and other structures.

[0087] It should be understood that in other exemplary embodiments, the semiconductor manufacturing method may also form other numbers of metal material layers and mask layers on the side of the barrier material layer 4 facing away from the substrate 1. Before forming the metal material layer on the side of the barrier material layer 4 facing away from the substrate 1, the barrier material layer 4 may also be removed.

[0088] like Fig.18 As shown, the semiconductor structure manufacturing method may also include: performing lightly doped drain treatment on the first type transistor and the second type transistor. The lightly doped drain treatment may include: performing P-type light doping on the first region 11 on both sides of the channel region of the first type transistor, and performing N-type light doping on the second region 12 on both sides of the channel region of the second type transistor. The semiconductor structure manufacturing method may also include: performing P-type heavy doping on part of the first region 11 on both sides of the channel region of the first type transistor to form the source S1 and drain D1 of the first type transistor, wherein the source S1 and drain D1 of the first type transistor and the channel region of the first type transistor are separated by a P-type lightly doped region of a certain size. Similarly, the semiconductor structure manufacturing method may also include: performing N-type heavy doping on part of the second region 12 on both sides of the channel region of the second type transistor to form the source S2 and drain D2 of the second type transistor, wherein the source S2 and drain D2 of the second type transistor and the channel region of the second type transistor are separated by a N-type lightly doped region of a certain size. Lightly doped drain treatment can effectively improve hot carrier effect and short channel effect.

[0089] like Fig.18 As shown, the semiconductor structure manufacturing method may also include: forming a first sidewall structure 81 on the sidewalls of the first gate insulating portion 21 and the first gate portion, and forming a second sidewall structure 82 on the sidewalls of the second gate insulating portion 22 and the second gate portion. The first sidewall structure 81 and the second sidewall structure 82 may both include a single layer or multiple layers of insulating material. The first sidewall structure 81 may protect the side of the first gate portion, and at the same time may strengthen the insulation effect of the first gate portion and other structures, reduce the coupling effect of the first gate portion and other surrounding structures, and improve the product yield. Similarly, the second sidewall structure 82 may protect the side of the second gate portion, and at the same time may strengthen the insulation effect of the second gate portion and other structures, reduce the coupling effect of the second gate portion and other surrounding structures, and improve the product yield. The materials of the first sidewall structure 81 and the second sidewall structure 82 may be the same as the materials of the gate dielectric layer 2, and the first sidewall structure 81, the second sidewall structure 82, and the gate dielectric layer 2 may be formed of silicon oxide material.

[0090] This exemplary embodiment also provides a semiconductor structure, which can be formed by the above-mentioned semiconductor manufacturing method. Fig.19 The figure is a schematic diagram of the structure of an exemplary embodiment of the semiconductor structure of the present disclosure. The semiconductor structure includes: a substrate 1, a first gate structure X1, and a second gate structure X2. The substrate 1 includes a first region 11 and a second region 12; the first gate structure X1 is located on the surface of the first region 11, the first gate structure X1 includes a first gate dielectric layer 21 and a first gate conductive layer X11, the first gate conductive layer X11 includes a gate layer 311 and a barrier layer 411, the first gate conductive layer X11 is located on the side of the first gate dielectric layer 21 away from the substrate 1, the barrier layer 411 is located on the side of the gate layer 311 away from the substrate 1, and the barrier layer 411 is located on the gate layer 311 and has a doping of the first type element. The second gate structure X2 is located on the surface of the second region 12, the second gate structure X2 includes a second gate dielectric layer 22 and a second gate conductive layer 322, the second gate conductive layer 322 is located on the side of the second gate dielectric layer 22 away from the substrate 1, and the second gate conductive layer 322 has a doping of the second type element.

[0091] like Fig.19 As shown, the semiconductor structure includes a first type transistor M1 and a second type transistor M2, the first region 11 includes a first channel region 111, the second region includes a second channel region 122, the first channel region 111 is used to form a channel region of the first type transistor M1, and the second channel region 122 is used to form a channel region of the second type transistor M2.

[0092] In this exemplary embodiment, the first type transistor is a P-type transistor, and the second type transistor is an N-type transistor. It should be understood that in other exemplary embodiments, the first type transistor may be an N-type transistor, and the second type transistor may be a P-type transistor.

[0093] In this exemplary embodiment, the second gate conductive layer 322 is a polysilicon material layer doped with the second type element; the gate layer 311 is a polysilicon material layer doped with the first type element; and the blocking layer 411 is a polysilicon material layer doped with the first type element and doped with carbon atoms.

[0094] The blocking layer 411 may include: a semiconductor layer, a first type element, and blocking particles, wherein the first type element is doped into the semiconductor layer, and the blocking particles are doped into the semiconductor layer. For example, the blocking particles may include carbon atoms, and the semiconductor layer may include a polysilicon material layer. The doping concentration of carbon atoms in the blocking layer 411 may be 10 20 / cm 3 -10 21 / cm 3 For example, the doping concentration of carbon atoms in the barrier layer 411 may be 10 20 / cm 3 , 3*10 20 / cm 3 , 5*10 20 / cm 3 ,7*10 20 / cm 3 , 10 21 / cm 3 It should be understood that in other exemplary embodiments, the semiconductor layer may also be a layer of other semiconductor materials, for example, the semiconductor layer may also be a semiconductor material such as chromium, gallium arsenide, etc. The blocking particles may also be other atoms or molecules.

[0095] The thickness of the gate layer 311 is h1, the thickness of the barrier layer 411 is h2, and h1 / h2 is greater than or equal to 3 and less than or equal to 9. For example, h1 / h2 may be equal to 3, 5, 6, 7, 8, 9, etc. In this exemplary embodiment, the thickness of the barrier layer 411 may be 3nm-8nm, for example, the thickness of the barrier layer 411 may be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, etc. The thickness of the gate layer 311 is 23nm-28nm, for example, the thickness of the gate layer 311 may be 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, etc.

[0096] In this exemplary embodiment, Fig.19As shown, the semiconductor substrate further includes: a shallow trench isolation structure 13 , and the shallow trench isolation structure 13 may be located between the first region 11 and the second region 12 .

[0097] In this exemplary embodiment, Fig.19 As shown, the semiconductor structure may further include: a first conductive portion 51 and a second conductive portion 52, wherein the first conductive portion 51 is located on the barrier layer 411, and the second conductive portion 52 is located on the second gate conductive layer 322. The semiconductor structure may further include: a third conductive portion 63 and a fourth conductive portion 64, wherein the third conductive portion 63 is located on the first conductive portion 51, and the fourth conductive portion 64 is located on the second conductive portion 52. The first conductive portion 51, the third conductive portion 63, and the first gate conductive layer X11 are used to form the gate of the first type transistor M1, and the second conductive portion 52, the fourth conductive portion 64, and the second gate conductive layer 322 are used to form the gate of the second type transistor M2.

[0098] In this exemplary embodiment, Fig.19 As shown, the semiconductor structure may further include: a first passivation portion 71 and a second passivation portion 72, wherein the orthographic projection of the first passivation portion 71 on the substrate 1 is located on the orthographic projection of the third conductive portion 63 on the substrate 1, and the orthographic projection of the second passivation portion 72 on the substrate 1 is located on the orthographic projection of the fourth conductive portion 64 on the substrate 1. The semiconductor structure may further include a first spacer structure 81 and a second spacer structure 82. The first spacer structure 81 covers the sidewalls of the first gate dielectric layer 21, the gate layer 311, the barrier layer 411, the first conductive portion 51, and the third conductive portion 63, and the second spacer structure 82 covers the sidewalls of the second gate dielectric layer 22, the second gate conductive layer 322, the second conductive portion 52, and the fourth conductive portion 64.

[0099] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0100] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures may refer to the usual design. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those of ordinary skill in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and should be included in the scope of the claims of the present disclosure.

[0101] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region; forming a gate dielectric layer, a gate material layer and a barrier material layer in sequence on the substrate; doping the barrier material layer with a first type of element, so that the first type of element is gathered in the barrier material layer, and the barrier material layer can block the first type of element from entering the gate material layer; removing at least the barrier material layer directly above the second region, and retaining at least the barrier material layer directly above the first region; doping the gate material layer directly above the second region with a second type of element; A heating process is performed to diffuse the first type elements gathered in the barrier material layer into the gate material layer on the square of the first region.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The substrate is a semiconductor substrate, at least a portion of the structure of the first region is used to form a channel region of a first type transistor, and at least a portion of the structure of the second region is used to form a channel region of a second type transistor; The first type transistor is a P type transistor, the second type transistor is an N type transistor, the first type element is a P type doping element, and the second type element is an N type doping element; Or, the first type transistor is an N-type transistor, the second type transistor is a P-type transistor, the first type element is an N-type doped element, and the second type element is a P-type doped element.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The gate material layer is a polysilicon material layer; The barrier material layer is a polysilicon material layer doped with carbon atoms.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Doping the barrier material layer with a first type element comprises: doping the barrier material layer with a first type of element by an ion implantation process; Doping the gate material layer directly above the second region with a second type of element comprises: The gate material layer directly above the second region is doped with a second type element by using an ion implantation process.

5. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The doping concentration of carbon atoms in the barrier material layer is 10 20 / cm 3 -10 21 / cm 3 .

6. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The thickness of the gate material layer is h1, the thickness of the barrier material layer is h2, and h1 / h2 is greater than or equal to 3 and less than or equal to 9.

7. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The thickness of the barrier material layer is 3nm-8nm, and the thickness of the gate material layer is 23nm-28nm.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: At least removing the barrier material layer directly above the second region and at least retaining the barrier material layer directly above the first region, comprising: Forming a patterned photoresist layer by a photolithography process to expose at least the barrier material layer directly above the second region and to cover at least the barrier material layer directly above the first region; The blocking material layer directly above the exposed second region is removed by etching using the patterned photoresist layer as a mask.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: Doping the gate material layer directly above the second region with a second type of element comprises: The patterned photoresist layer is used as a mask to dope the gate material layer directly above the second region with a second type of element.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The production method further comprises: forming at least one metal material layer on a side of the barrier material layer facing away from the substrate; forming a passivation material layer on a side of the metal material layer facing away from the substrate; forming at least one mask layer on a side of the passivation material layer facing away from the substrate; The mask layer, passivation material layer, metal material layer, barrier material layer, gate material layer, and gate dielectric layer are patterned so that the gate material layer, the metal material layer, and a partial structure of the barrier material layer directly above the first region form a first gate portion, and the gate material layer and a partial structure of the metal material layer directly above the second region form a second gate portion.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: Also includes: removing the mask layer; Performing lightly doped drain treatment on the first region and the second region; Forming a sidewall structure on the sidewalls of the first gate portion and the second gate portion, wherein the sidewall structure includes a single layer or multiple layers of insulating material; The first region and the second region are heavily doped with source and drain.

12. The method for manufacturing a semiconductor structure according to any one of claims 1 to 11, characterized in that: Perform heat treatment, including: A rapid thermal treatment is performed, wherein the temperature range of the rapid thermal treatment is 800° C. to 1000° C. and the time range of the rapid thermal treatment is 1 minute to 7 minutes.

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