A single bjt branch mismatched voltage mode bandgap reference circuit

Abstract

This invention discloses a single-BJT branch offset voltage-mode bandgap reference circuit, belonging to the field of integrated circuits. It includes a DC bias circuit, a PTAT operational amplifier, a single BJT branch structure, and a bias current generation circuit. The DC bias circuit outputs a reference voltage V. IB1 V IB2 V IB3 The signal is transmitted to the PTAT operational amplifier; the PTAT operational amplifier generates a signal V. ctrl To control the output bandgap reference voltage V of the single BJT branch structure BG Furthermore, the single BJT branch structure also outputs a signal V. A The DC bias circuit outputs a signal V. B The bias current generating circuit receives the bandgap reference voltage V from the PTAT operational amplifier. BG and reference voltage V IB1 This generates the bandgap reference current I. bias This invention features high precision and small size, requires fewer BJTs and passive components, has a simple circuit structure, and offers better energy efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-digital hybrid circuit, in particular to a single BJT branch offset type voltage mode bandgap reference circuit. BACKGROUND

[0002] In recent years, the rapid development of digital technology has led to the increasing demand for bandgap reference in various electronic products. Due to the rapid development of the Internet of Things system, the power consumption of the system is required to be lower and lower, and low power consumption has become a hot research topic. New type of bandgap reference circuit is emerging.

[0003] The bandgap reference circuit is a key core circuit in low power consumption application devices, which mainly include biomedical, Internet of Things (IOT) and passive RFID devices. The traditional bandgap structure cannot meet this requirement because it needs a huge resistance of several mega ohms in low power consumption design, and occupies a large area. The resolution of biomedical transceiver depends on the ADC accuracy of the operational amplifier, and the operational amplifier depends on the accuracy performance of the bandgap reference.

[0004] Therefore, it is urgent to provide a single BJT branch offset type voltage mode bandgap reference circuit based on a PTAT operational amplifier, which has better energy utilization than the traditional bandgap reference. SUMMARY

[0005] The purpose of the present application is to provide a single BJT branch offset type voltage mode bandgap reference circuit to solve the problems in the background art.

[0006] To solve the above technical problems, the present application provides a single BJT branch offset type voltage mode bandgap reference circuit, which comprises a DC bias circuit, a PTAT operational amplifier, a single BJT branch structure, a bias current generating circuit and a PSRR high frequency improvement capacitor C O ;

[0007] The DC bias circuit outputs reference voltages V IB1 , V IB2 , V IB3 to the PTAT operational amplifier;

[0008] The PTAT operational amplifier generates a signal V ctrl to control the single BJT branch structure to output a bandgap reference voltage V BG , and the PSRR high frequency improvement capacitor C O is connected to the bandgap reference voltage V BG ;

[0009] And the single BJT branch structure also outputs a signal V A to the DC bias circuit, and the output signal VB to the PTAT operational amplifier;

[0010] The bias current generating circuit receives a bandgap reference voltage V BG and a reference voltage V IB1 , and generates a bandgap reference current I bias .

[0011] In an embodiment, the DC bias circuit comprises a current generating branch and a bias output branch;

[0012] The current generating branch comprises NMOS transistor MN1, NMOS transistor MN3 and PMOS transistor MP1; the NMOS transistor MN1 is in MOS diode connection, converting current into voltage to generate a reference voltage V IB1 ;

[0013] The bias output branch comprises PMOS transistor MP2, PMOS transistor MP3 and NMOS transistor MN2; the PMOS transistor MP2 and the PMOS transistor MP3 are in MOS diode connection, generating a bias reference voltage V IB2 , V IB3 ;

[0014] The input control signal of the DC bias circuit is the output signal V A generated by the single BJT branch structure, connected to the gate of the NMOS transistor MN3.

[0015] In an embodiment, the single BJT branch structure comprises bipolar transistor Q1, NMOS transistor MN4, and resistors R1, R2 and R3; by linear superposition in the single BJT branch structure, a reference voltage V BG is obtained; the input control signal of the single BJT branch structure is the V ctrl signal, connected to the gate of the NMOS transistor MN4.

[0016] In an embodiment, the PTAT operational amplifier comprises a transconductance operational amplifier with positive feedback load, a common-source amplifier, and a compensation capacitor C C between the two-stage operational amplifier; wherein,

[0017] The transconductance operational amplifier with positive feedback load comprises NMOS tubes MN5, MN6, MN7, MN8, MN9, MN10, MN11, PMOS tubes MP4, MP5, MP6, MP7, MP9, MP10, MP11, MP12, MP13 and MP14; the PMOS tubes MP11 and MP12 are cross-coupled load pairs serving as positive feedback load, the cross-coupled positive feedback load is added on the basis of MOS diode, the static current of MOS diode is reduced, and the gain is further improved;

[0018] The common-source amplifier comprises NMOS tube MN12 and PMOS tubes MP8 and MP15, and the compensation capacitor C C The output end of the common-source amplifier is directly connected to the output end of the transconductance operational amplifier with positive feedback load.

[0019] In an embodiment, the bias current generation circuit comprises NMOS tubes MN13, MN14, MN15, MN16, MN17, PMOS tubes MP16, MP17, MP18, MP19, MP20, MP21, MP22, MP23, MP24 and a resistor R4, which is used for outputting a reference current I bias ;V BG is an input reference voltage of the bias current generation circuit, IB1 is a bias voltage input of the bias current generation circuit.

[0020] The application provides a single-BJT branch offset type voltage mode bandgap reference circuit, which comprises a direct current biasing circuit, a PTAT operational amplifier, a single-BJT branch structure, a bias current generation circuit and a PSRR high-frequency improvement capacitor C O ; has the characteristics of high precision and small area, has fewer BJT and passive elements, has a simple circuit structure and has better energy utilization. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The application provides a single-BJT branch offset type voltage mode bandgap reference circuit.

[0022] Figure 2 The application provides a direct current biasing circuit principle diagram.

[0023] Figure 3A single BJT branch structure schematic diagram provided by the present application.

[0024] Figure 4 A PTAT operational amplifier schematic diagram provided by the present application.

[0025] Figure 5 A bias current generating circuit schematic diagram provided by the present application. DETAILED DESCRIPTION

[0026] The present application provides a single BJT branch offset type voltage mode bandgap reference circuit, which has the structure as shown in the figure.

[0027] The present application provides a single BJT branch offset type voltage mode bandgap reference circuit, which has the structure as shown in the figure. Figure 1 The single BJT branch offset type voltage mode bandgap reference circuit is composed of a DC bias circuit, a PTAT operational amplifier, a single BJT branch structure, a PSRR high frequency improving capacitor C O and a bias current generating circuit, wherein the PTAT operational amplifier is composed of a transconductance operational amplifier with positive feedback load, a common source amplifier and a compensation capacitor C C between operational amplifier stages.

[0028] Figure 2 The figure is a principle schematic diagram of the DC bias circuit, which has the characteristics of reference voltage generation stability, simple structure and area saving, and is composed of a current generating branch and a bias output branch. The current generating branch includes NMOS tube MN1, NMOS tube MN3 and PMOS tube MP1; the bias output branch includes PMOS tube MP2, PMOS tube MP3 and NMOS tube MN2. The DC bias circuit is used to generate the reference voltage required by the PTAT operational amplifier and the bias current generating circuit. The input control signal of the DC bias circuit is V A , which is connected to the gate of NMOS tube MN3, and NMOS tube MN1, PMOS tube MP2 and PMOS tube MP3 are MOS diode connection, which outputs reference voltages V IB1 , V IB2 and V IB3 at the gates respectively, which is more area saving compared with the traditional resistance voltage dividing branch or resistance and MOS diode form.

[0029] Figure 3 The figure is a single BJT branch structure principle diagram, which includes bipolar transistor Q1, NMOS tube MN4 and resistors R1, R2 and R3, and is used to generate negative temperature coefficient voltages V BE and VBE This is the base-emitter voltage of Q1, and the entire circuit achieves linear superposition through a single BJT branch structure. The input control signal of the circuit is V. ctrl The signal is input through the gate of NMOS transistor MN4, and its output signals are V. A V B V BG etc., due to operational amplifier misalignment, V PTAT A voltage is applied to resistor R1, resulting in a current of V flowing through the BJT branch structure. PTAT / R1, therefore, a zero-temperature coefficient reference voltage can be obtained by adjusting the value of the resistor. The single-BJT branch offset voltage-mode bandgap reference circuit of this invention forms a closed-loop negative feedback system through a PTAT operational amplifier and a single-BJT branch structure with source follower function; additionally, a PSRR high-frequency capacitor C is added to the output node to enhance the voltage. O This improves the power supply rejection ratio (PSRR) at high frequencies.

[0030] Where V BG The output voltage for the bandgap reference is expressed as:

[0031]

[0032] Figure 4 This is a schematic diagram of a PTAT operational amplifier, including a transconductance operational amplifier with a positive feedback load, a common-source amplifier, and a compensation capacitor C between the two stages of the operational amplifier. C The transconductance operational amplifiers with positive feedback loads include NMOS transistors MN5, MN6, MN7, MN8, MN9, MN10, and MN11, and PMOS transistors MP4, MP5, MP6, MP7, MP9, MP10, MP11, MP12, MP13, and MP14. PMOS transistors MP11 and MP12 are cross-coupled loads providing positive feedback. Adding cross-coupled positive feedback loads to the MOS diodes reduces their quiescent current and further improves the gain. The common-source amplifier includes NMOS transistor MN12 and PMOS transistors MP8 and MP15, with compensation capacitor C... C Directly output V from the second stage ctrl The V terminal is connected to a transconductance operational amplifier with a positive feedback load. Q At this point, the positive temperature coefficient offset operational amplifier (i.e., PTAT operational amplifier) ​​and the main BJT branch structure form negative feedback.

[0033] The input pair NMOS (MN6 and MN7) operates in the subthreshold region, and its drain current can be expressed as

[0034]

[0035] where I D0 is the subthreshold quiescent current, which is related to the gain factor, thermal voltage V T , substrate modulation factor, and surface potential, etc. V GS is the gate-source voltage, V DS is the drain-source voltage, and η is the subthreshold slope factor.

[0036] When V DS >V T , the equation is simplified as:

[0037]

[0038] When the currents flowing through the two input transistors MN6 and MN7 operating in the subthreshold region are the same, the difference between ΔV GS can be expressed as:

[0039]

[0040] where V PTAT is the positive temperature coefficient voltage. Generally, the MOS operating in the subthreshold region is greatly affected by the process, and from the equation, it can be seen that it only depends on the width-length ratio of the circuit, and thus it is not affected by the PVT (process, voltage, temperature) variation, which is similar to the PTAT generation based on BJT.

[0041] Figure 5 is a bias current generation circuit schematic diagram, comprising NMOS MN13, NMOS MN14, NMOS MN15, NMOS MN16, NMOS MN17, PMOS MP16, PMOS MP17, PMOS MP18, PMOS MP19, PMOS MP20, PMOS MP21, PMOS MP22, PMOS MP23, PMOS MP24, and resistor R4, for outputting reference current I bias . V BG is an input reference voltage, V IB1 is a bias voltage input.

[0042] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application, and any modification or change made by a person of ordinary skill in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A single BJT branch mismatched voltage mode bandgap reference circuit, characterized by, The DC bias circuit, the PTAT operational amplifier, the single BJT branch structure, the bias current generation circuit, and the PSRR high-frequency improvement capacitor C O ; The direct current bias circuit outputs a reference voltage V IB1 , V IB2 , V IB3 to the PTAT operational amplifier; The PTAT operational amplifier generates a signal V ctrl to control the single BJT branch structure to output a bandgap reference voltage V BG , the PSRR high frequency improvement capacitor C O connected to the bandgap reference voltage V BG ; And the single BJT branch structure also outputs signal V A to the DC bias circuit, output signal V B to the PTAT operational amplifier; The bias current generating circuit receives a bandgap reference voltage V BG and a reference voltage V IB1 , and generates a bandgap reference current I bias .

2. The single BJT leg mismatched voltage mode bandgap reference circuit of Claim 1, wherein, The direct current bias circuit comprises a current generating branch and a bias output branch; The current generating branch comprises NMOS transistor MN1, NMOS transistor MN3 and PMOS transistor MP1; the NMOS transistor MN1 is in MOS diode connection mode, converts current into voltage, and generates reference voltage V IB1 ; The bias output branch comprises a PMOS tube MP2, a PMOS tube MP3 and an NMOS tube MN2; the PMOS tube MP2 and the PMOS tube MP3 are MOS diode connection, generating a bias reference voltage V IB2 , V IB3 ; The input control signal of the direct current bias circuit is the output signal V A , access the gate of the NMOS tube MN3.

3. The single BJT leg mismatched voltage mode bandgap reference circuit of Claim 2, wherein, The single BJT branch structure comprises a bipolar transistor Q1, an NMOS transistor MN4, and resistors R1, R2 and R3; a reference voltage V BG is obtained by linear superposition in the single BJT branch structure ctrl The input control signal of the single BJT branch structure is a V ctrl signal, which is connected to the gate of the NMOS transistor MN4.

4. The single BJT leg mismatched voltage mode bandgap reference circuit of Claim 3, wherein, The PTAT operational amplifier includes a transconductance operational amplifier with a positive feedback load, a common-source amplifier, and a compensation capacitor C between the two-stage operational amplifier C ; wherein, The transconductance operational amplifier with positive feedback load comprises NMOS tubes MN5, MN6, MN7, MN8, MN9, MN10, MN11, PMOS tubes MP4, MP5, MP6, MP7, MP9, MP10, MP11, MP12, MP13 and MP14; the PMOS tubes MP11 and MP12 are cross-coupled load pairs serving as positive feedback load, and cross-coupled positive feedback load is added on the basis of MOS diode, so that the static current of the MOS diode is reduced and the gain is further improved. The common-source amplifier comprises NMOS transistor MN12 and PMOS transistors MP8 and MP15, and compensation capacitor C C The output of the common-source amplifier is directly connected to the output of the transadmission amplifier with positive feedback load.

5. The single BJT leg mismatched voltage mode bandgap reference circuit of Claim 4, wherein, The bias current generation circuit comprises NMOS tube MN13, NMOS tube MN14, NMOS tube MN15, NMOS tube MN16, NMOS tube MN17, PMOS tube MP16, PMOS tube MP17, PMOS tube MP18, PMOS tube MP19, PMOS tube MP20, PMOS tube MP21, PMOS tube MP22, PMOS tube MP23, PMOS tube MP24 and resistance R4, which are used for outputting reference current I bias ; V BG is the input reference voltage of the bias current generation circuit, V IB1 is the bias voltage input of the bias current generation circuit.

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