A statistical delay modeling method for subthreshold combinational logic units

Abstract

The present invention discloses a statistical delay modeling method for a sub-threshold region combinational logic unit, which simulates the delay fluctuation standard deviation of different input conversion times. At the same time, the delay fluctuation standard deviation of different input conversion times is solved by the unit statistical delay model for different fast input and slow input situations, and the normalized error of the two is obtained to delineate the input transition region boundary. The delay fluctuation standard deviation of the two boundaries of the input transition region is obtained by the unit statistical delay model for different fast input and slow input situations, and finally the delay statistical model of the input transition region is obtained. The statistical delay modeling method for a sub-threshold region combinational logic unit provided by the present invention has low simulation overhead and high prediction accuracy, and is of great significance for static timing analysis and timing sign-off of digital integrated circuits.

Description

A statistical delay modeling method for subthreshold combinational logic units Technical Field

[0001] The invention relates to a statistical delay modeling method for a sub-threshold region combinational logic unit, and belongs to the technical field of electronic design automation. Background Art

[0002] In ideal static timing analysis (STA), for example, when the inverter input is 1, the output immediately outputs 0. However, in reality, there is a certain lag between the input and output signals. This lag is the logic cell's delay. Cell delay varies with input transition time. Based on the relationship between input transition time and cell delay, cell input waveforms are classified into two types: fast input and slow input.

[0003] As shown in Figure 1(a) and Figure 1(b), Vin is the waveform of the input signal, taking the inverter input as 1 as an example, Vout is the waveform of the inverter output signal, and Vdd is the voltage of the input signal.

[0004] Figure 1(a) shows a fast input scenario, where the input signal voltage rises sharply from 0 to Vdd before the output signal voltage drops from Vdd to Vdd / 2. The transition time for the input signal voltage to rise sharply from 0 to Vdd is τ. The statistical delay td of the inverter is calculated using the time points corresponding to 50% of the input signal voltage and 50% of the output signal voltage, respectively.

[0005] Figure 1(b) shows a slow input scenario, where the input signal voltage slowly rises from 0 to Vdd after the output signal voltage drops from Vdd to Vdd / 2. The transition time for the input signal voltage to slowly rise from 0 to Vdd is τ. The statistical delay td of the inverter is calculated using the time points corresponding to 50% of the input signal voltage and 50% of the output signal voltage, respectively.

[0006] According to the order in which the input signal waveform reaches Vdd from 0 and the output signal waveform reaches Vdd / 2 from Vdd, the input signal waveform of the unit is divided into two types: fast input and slow input.

[0007] The fast input case corresponds to the case where the input voltage rises sharply from 0 to Vdd at time τ before the output voltage drops from Vdd to Vdd / 2. The slow input case corresponds to the case where the input voltage rises slowly from 0 to Vdd after the output voltage drops from Vdd to Vdd / 2.

[0008] Traditionally, statistical delay models for units with varying input conversion times have only considered slow and fast input scenarios, dividing the input conversion time into two regions: fast and slow. Modeling and analysis are performed based on the input conversion time region. If, under nominal conditions, only the input conversion time is varied without considering process variations, the unit delay has a fixed value for each input conversion time. As the input conversion time gradually increases from 0ps, the unit input signal initially enters the fast input phase. When it increases above the fast-slow boundary, the unit enters the slow input phase. Under nominal conditions, the input signal can accurately switch between fast and slow input at the fast-slow boundary.

[0009] However, it should be noted that when considering process deviations, the unit delay of the same input conversion time will also change, that is, the unit delay is a random variable and not a fixed value. Therefore, in a certain interval near the fast-slow boundary, it is no longer certain whether any input conversion time is a fast input or a slow input. Therefore, for the nominal case, the input category can be determined by the nominal judgment method in a certain interval near the fast-slow boundary, but when considering process parameter fluctuations, the unit delay is a distribution, and the input waveform may be a slow input or a fast input. Especially when the MOS transistor is in the subthreshold region, it will be further aggravated. When counting the category of the input conversion time, it cannot be determined in τ. b The correct switching time is not performed, but the b The surrounding transition area switches and this area is defined as the input transition area. The existence of the input transition area brings challenges to the construction of the unit statistical delay model.

[0010] In summary, those skilled in the art urgently need to solve the technical problem that the traditional construction of unit statistical delay models for different input conversion times ignores the existence of the input transition zone, and still adopts the modeling method of fast input or slow input in this area, which has a great impact on the accuracy of the unit statistical delay model. Summary of the Invention

[0011] Purpose: In order to overcome the deficiencies in the prior art, the present invention provides a method for modeling statistical delay of combinational logic units in the sub-threshold region, so as to solve the technical problem that the traditional unit statistical delay model only considers the fast input and slow input situations, but ignores the situation in the transition region between fast and slow inputs, resulting in large errors in the unit statistical delay model in this region.

[0012] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:

[0013] A statistical delay modeling method for a sub-threshold combinational logic unit comprises the following steps:

[0014] Step 1: For the combinational logic unit, perform transistor-level simulation under subthreshold operating voltage Vdd and load capacitance C0, obtain the nominal delay value td0 of the combinational logic unit step τ = 0, and calculate the input transition time τ at the boundary between fast input and slow input b .

[0015] Step 2: For the combinational logic unit, perform transistor-level simulation at subthreshold operating voltage Vdd and load capacitance C0. When the input transition time τ<τ b When the fast input conversion time is calculated based on the Monte Carlo simulation results The actual simulation delay fluctuation standard deviation of the combinational logic unit under Calculate the fast input conversion time through the fast input unit delay statistical model The delay fluctuation standard deviation of the combinational logic unit under When the input transition time τ>τ b When the slow input conversion time is calculated based on the Monte Carlo simulation results The actual simulation delay fluctuation standard deviation of the combinational logic unit under Calculate the slow input conversion time through the slow input unit delay statistical model The delay fluctuation standard deviation of the combinational logic unit under

[0016] Step 3: Based on the obtained Calculate the normalized error separately According to the normalized error Calculate the left boundary of the input transition region τ b(f) , input transition zone right boundary τ b(s) .

[0017] Step 4: For the combinational logic unit, under the subthreshold operating voltage Vdd and load capacitance C0, use the fast input unit delay statistical model to obtain the input conversion time τ under this load condition b(f) The delay fluctuation standard deviation of the combinational logic unit under The input conversion time τ under this load condition is obtained using the slow input unit delay statistical model b(s) The delay fluctuation standard deviation of the combinational logic unit under Then we can get any load capacitance C L The standard deviation of the delay fluctuation of the combinational logic unit at the left and right boundaries of the input transition region under and

[0018] Step 5: According to the left boundary τ of the input transition area b(f) and the corresponding delay fluctuation standard deviation Input transition region right boundary τb(s) and the corresponding delay fluctuation standard deviation By linear fitting, the combinational logic unit is obtained at the subthreshold working voltage Vdd and load capacitance C L Standard deviation of the delay fluctuation of arbitrary input conversion time in the transition region under the model.

[0019] As a preferred solution, the input conversion time τ b The calculation formula is as follows:

[0020]

[0021] Where: n is the subthreshold slope factor, V T is the thermal voltage.

[0022] As a preferred solution, the combinational logic unit includes a pull-up network and a pull-down network in a stacked structure and a pull-up network and a pull-down network in a parallel structure.

[0023] As a preferred solution, the step 2 specifically includes:

[0024] Step 2.1: For the combinational logic unit, perform transistor-level simulation at the subthreshold operating voltage Vdd and load capacitance C0. When the input transition time τ of the simulated input waveform is 0<τ<τ b When it is called fast input, select n f Quick Input Perform transistor-level simulation to obtain measurement unit delay Statistics of fast input conversion time based on Monte Carlo simulation results The actual simulation delay fluctuation standard deviation of the combinational logic unit under Among them, n f is an integer, n f >1, 1≤i≤n f .

[0025] Step 2.2: Calculate the fast input conversion time based on the fast input statistical model The delay fluctuation standard deviation of the combinational logic unit under Specifically include:

[0026] Step 2.2.1: Convert time based on fast input The actual simulation delay fluctuation standard deviation of the combinational logic unit under make get

[0027] Step 2.2.2: Based on the fast input statistical model Calculate the fast input conversion time The delay fluctuation standard deviation of the combinational logic unit under

[0028] Step 2.3: When the input transition time τ of the simulated input waveform is τ>τ b When it is called slow input, select n s Slow input Perform transistor-level simulation to obtain measurement unit delay Statistical analysis of slow input conversion time based on Monte Carlo simulation results The actual simulation delay fluctuation standard deviation of the combinational logic unit under Among them, n s is an integer, n s >1, 1 <k<2,1≤i≤n s .

[0029] Step 2.3: Calculate the slow input conversion time based on the slow input statistical model The delay fluctuation standard deviation of the combinational logic unit under Specifically include:

[0030] Step 2.3.1: Calculate the standard deviation of the equivalent threshold voltage fluctuation of the pull-up network composed of N PMOS transistors in a stacked structure Calculate the standard deviation of the equivalent threshold voltage fluctuation of a parallel pull-up network composed of N PMOS transistors Where N is an integer, N≥1.

[0031] Step 2.3.2: Calculate the standard deviation of the equivalent threshold voltage fluctuation of the pull-down network composed of N NMOS transistors Calculate the standard deviation of the equivalent threshold voltage fluctuation of a parallel pull-down network composed of N NMOS transistors

[0032] Step 2.3.3: When the pull-down network of the combinational logic unit works and the pull-down network is a stacked structure, according to the slow input statistical model Calculate slow input transition time The delay fluctuation standard deviation of the combinational logic unit under

[0033] Step 2.3.4: When the pull-down network of the combinational logic unit is working and the pull-down network is a parallel structure, according to the slow input statistical model Calculate slow input transition time The delay fluctuation standard deviation of the combinational logic unit under

[0034] Step 2.3.5: When the pull-up network of the combinational logic unit is working and the pull-up network is a stacked structure, according to the slow input statistical model Calculate the slow input transition time The standard deviation of the delay fluctuation of the combinational logic unit under

[0035] Step 2.3.6: When the pull-up network of the combinational logic unit is working and the pull-up network is a parallel structure, according to the slow input statistical model Calculate the slow input transition time The standard deviation of the delay fluctuation of the combinational logic unit under

[0036] As a preferred solution, step 3 specifically includes:

[0037] Step 3.1: When the input transition time 0 < τ < τ b The standard deviation of the delay fluctuation calculated according to the fast input model And the standard deviation of the delay fluctuation obtained from the actual simulation Calculation error

[0038] Step 3.2: When the input transition time τ b < τ < kτ b , 1 < k < 2, the standard deviation of the delay fluctuation calculated according to the slow input model And the standard deviation of the delay fluctuation obtained from the actual simulation Calculation error λ s i ,

[0039] Step 3.3: When the input transition time 0 < τ < τ b The linear fitting interval 1 ≤ i ≤ n f , obtain the normalized error of any input transition time in the interval 0 < τ < τ b When Set the value of ε, and obtain the input transition time τ at this time, which is the left boundary τ of the input transition region b(f) .

[0040] Step 3.4: When the input transition time τ b < τ < kτ b , 1 < k < 2, the linear fitting interval 1 ≤ i ≤ n s , obtain τ b < τ < kτ bNormalized error of any input conversion time in the interval Set the ε value to get the input conversion time τ at this time, which is the right boundary of the input transition area τ b(s) .

[0041] As a preferred solution, the step 4 specifically includes:

[0042] Step 4.1: For the combinational logic unit, use transistor-level simulation tools to simulate the subthreshold operating voltage Vdd and load capacitance C0 to obtain the average step delay of the combinational logic unit. and the standard deviation of step delay fluctuation And calculate the unit step delay sensitivity in this case

[0043] Step 4.2: When the input transition time τ = τ b(s) When , the corresponding input transition zone boundary τ is calculated through the slow input statistical model b(s) The standard deviation of the delayed fluctuation

[0044] The slow input statistical model specifically includes:

[0045] When the pull-down network of the combinational logic unit works and is a stacked structure, the slow input statistical model is

[0046]

[0047] When the pull-down network of the combinational logic unit works and is in parallel structure, the slow input statistical model is

[0048]

[0049] When the pull-up network of the combinational logic unit works and is a stacked structure, the slow input statistical model is

[0050]

[0051] When the pull-up network of the combinational logic unit works and is in a parallel structure, the slow input statistical model is

[0052]

[0053] in, They are the standard deviation of the equivalent threshold voltage fluctuation of the stacked pull-up network composed of N PMOS transistors and the standard deviation of the equivalent threshold voltage fluctuation of the parallel pull-up network. They are the standard deviation of the equivalent threshold voltage fluctuation of the stacked pull-down network composed of N NMOS transistors and the standard deviation of the equivalent threshold voltage fluctuation of the parallel pull-down network.

[0054] Step 4.3: For combinational logic cells, at subthreshold operating voltage Vdd, load C L Under the circumstance of 100 nm, the nominal value of the unit delay is used as the average step delay value by using the transistor simulation tool. By formula Get load C L The standard deviation of step delay fluctuation under the condition By fast input statistical model Calculate the input conversion time τ = τ b(f) Input transition region left boundary τ b(f) The standard deviation of the delayed fluctuation

[0055] Step 4.4: For combinational logic cells, at subthreshold operating voltage Vdd and load C L Next Pass Calculate when input conversion time τ = τ b(s) Input transition region right boundary τ b(s) The standard deviation of the delayed fluctuation

[0056] As a preferred embodiment, the The calculation formula is as follows:

[0057]

[0058] described The calculation formula is as follows:

[0059]

[0060] in, represents the standard deviation of the threshold voltage fluctuation of the simulated NMOS transistor, Respectively represent the channel width, channel length, W of the simulated NMOS transistor n , L n They represent the channel width and channel length of the NMOS transistor in the pull-down network to be determined.

[0061] As a preferred embodiment, the The calculation formula is as follows:

[0062]

[0063] described The calculation formula is as follows:

[0064]

[0065] represents the standard deviation of the threshold voltage fluctuation of the simulated PMOS transistor,

[0066] Where, respectively represent the channel width, channel length, and W of the simulated PMOS transistor. p , L p They represent the channel width and channel length of the PMOS transistor of the pull-up network to be determined.

[0067] As a preferred solution, the combinational logic unit, under the subthreshold working voltage Vdd, the load capacitance C L The calculation formula of the standard deviation model of the delay fluctuation of any input conversion time in the transition zone is as follows:

[0068]

[0069] ,in,

[0070] As a preferred solution, ε=3%.

[0071] Beneficial effect: The present invention provides a statistical delay modeling method for a sub-threshold combinational logic unit, which divides the area near the boundary between traditional fast input and slow input into an input transition zone and performs unit statistical delay modeling. First, the delay fluctuation standard deviation of different input conversion times is simulated, and at the same time, the delay fluctuation standard deviation of different input conversion times is solved by the unit statistical delay model under different conditions of fast input and slow input, and the normalized error of the two is obtained to further define the input transition zone boundary. The range of the input transition zone boundary is independent of the unit drive strength and load. Secondly, the delay fluctuation standard deviation of the two boundaries of the input transition zone is obtained by the unit statistical delay model under different conditions of fast input and slow input, and finally the delay statistical model of the input transition zone is obtained, including: a function of the input conversion time, the two boundaries of the input transition zone and their delay fluctuation standard deviation. The present invention has low simulation overhead and high prediction accuracy, and is of great significance for static timing analysis and timing sign-off of digital integrated circuits. It has the following advantages:

[0072] 1. The present invention fully considers the volatility of unit delay when process parameters fluctuate, and divides the input conversion time into fast input area, input transition area, and slow input area to solve the problem that the input waveform in the input transition area may be slow input or fast input. This situation causes the input conversion time category to be unable to be classified in τ under statistical conditions. b time to switch correctly, but through τb The present invention defines the region as the input transition region and models it separately. However, the traditional unit statistical delay model for different input conversion times ignores the existence of the input transition region and uses τ b The dividing line divides the input conversion time into a fast input area and a slow input area. b The nearby area is also the transition area defined in the present invention. The statistical distribution of delay is partially fast input and partially slow input. Therefore, the traditional model only regards it as pure fast input or pure slow input, which will lead to a large delay error.

[0073] 2. This invention establishes the input transition region based on the statistical delay model of traditional fast and slow input units and the actual simulation normalized error. This established input transition region is applicable to different drive strengths and loads, demonstrating strong generalization capabilities. Because the method requires simulating the standard deviation of the delay fluctuation at both ends of the input transition region, the invention establishes a model that quickly obtains the standard deviation of the delay fluctuation at both ends of the input transition region under different drive strengths and loads, significantly reducing simulation overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] FIG1( a ) is a schematic diagram of input and output signals in a fast input situation; FIG1( b ) is a schematic diagram of input and output signals in a fast input situation.

[0075] FIG2 is a schematic diagram showing the range of the input transition region based on the traditional fast input and slow input unit delay statistical models and the actual simulation normalized error.

[0076] FIG3 is a schematic diagram showing the construction of a unit statistical delay model for different input conversion times in the input transition region when the input transition region range and the standard deviation of delay fluctuations at both ends of the input transition region are known.

[0077] FIG4 is a schematic diagram showing the relationship between the delay standard deviation and the input conversion time. DETAILED DESCRIPTION

[0078] The following is a clear and complete description of the technical solutions in the examples of the present invention, in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0079] The present invention will be further described below with reference to specific embodiments.

[0080] Example 1:

[0081] This embodiment introduces a statistical delay modeling method for a sub-threshold region combinational logic unit, including the following steps:

[0082] Step 1: For a channel width of The channel length is The PMOS transistor operates at a subthreshold voltage V dd Transistor-level simulation is performed to measure the threshold voltage of the PMOS transistor. The channel width is calculated based on the Monte Carlo simulation results. The channel length is The standard deviation of the threshold voltage fluctuation of the PMOS transistor For a channel width of The channel length is NMOS transistor, operating at subthreshold voltage V dd Transistor-level simulation is performed to measure the threshold voltage of NMOS transistors. The channel width is calculated based on the Monte Carlo simulation results. The channel length is The standard deviation of the threshold voltage fluctuation of the NMOS transistor According to the channel width W p , the channel length is L p The PMOS transistor has a channel width of W n , the channel length is L n The pull-up network and pull-down network are constructed by using NMOS transistors, and the standard deviation of the equivalent threshold voltage fluctuation of the pull-up network of the stacked structure and the parallel structure is calculated. The standard deviation of the equivalent threshold voltage fluctuation of the pull-down network of the stacked structure and the parallel structure

[0083] Furthermore, the step 1 specifically includes the following steps:

[0084] Step 1.1: The standard deviation of the equivalent threshold voltage fluctuation of the pull-up network composed of N (N is an integer, N ≥ 1) PMOS transistors in a stacked structure The model can be expressed as

[0085]

[0086] in, represents the standard deviation of the threshold voltage fluctuation of the simulated PMOS transistor, Represent the channel width, channel length, and W of the simulated PMOS transistor respectively. p , L p They represent the channel width and channel length of the PMOS transistor in the network to be determined.

[0087] Step 1.2: The pull-down network of the stacked structure is composed of N (N is an integer, N ≥ 1) NMOS transistors, and the standard deviation of the equivalent threshold voltage fluctuation is The model can be expressed as

[0088]

[0089] in, represents the standard deviation of the threshold voltage fluctuation of the simulated NMOS transistor, Respectively represent the channel width, channel length, W of the simulated NMOS transistor n , L n They represent the channel width and channel length of the NMOS transistor in the network to be determined.

[0090] Step 1.3: The standard deviation of the equivalent threshold voltage fluctuation of the pull-up network composed of N (N is an integer, N ≥ 1) PMOS transistors in parallel The model can be expressed as

[0091]

[0092] Step 1.4: The standard deviation of the equivalent threshold voltage fluctuation of the pull-down network composed of N (N is an integer, N ≥ 1) NMOS transistors in parallel The model can be expressed as

[0093]

[0094] Step 2: Based on the combinational logic unit composed of the pull-up network, pull-down network of the stacked structure and the pull-up network, pull-down network of the parallel structure, transistor-level simulation is performed under the subthreshold operating voltage Vdd and load capacitance C0 to obtain the nominal step (τ=0) delay value td0 of the combinational logic unit and calculate the input conversion time τ at the boundary between the fast input and the slow input. b .

[0095] Furthermore, in step 2, the τ b The calculation formula is as follows:

[0096]

[0097] Where: Vdd is the subthreshold operating voltage, n is the subthreshold slope factor, V T is the thermal voltage.

[0098] Step 3: For the channel with a width of W p , the channel length is L pThe PMOS transistor has a channel width of W n , the channel length is L n The stacked structure and parallel structure of NMOS transistors constitute the combinational logic unit, and the transistor-level simulation is performed under the subthreshold operating voltage Vdd and load capacitance C0 to simulate the input conversion time τ of the input waveform, and τ>0. When the input conversion time τ<τ b When it is called fast input, select n f (n f is an integer, n f >1) Fast input conversion time Perform transistor-level simulation to measure fast input transition times The unit delay of the combinational logic unit under Statistics of fast input conversion time based on Monte Carlo simulation results The delay fluctuation standard deviation of the combinational logic unit under Calculate the fast input conversion time through the fast input unit delay statistical model The delay fluctuation standard deviation of the combinational logic unit under When the input transition time τ>τ b When it is called slow input, select n s (n s is an integer, n s >1) Slow input transition time Perform transistor-level simulation to measure slow input transition times The unit delay of the combinational logic unit under Statistical analysis of slow input conversion time based on Monte Carlo simulation results The delay fluctuation standard deviation of the combinational logic unit under Calculate the slow input conversion time through the slow input unit delay statistical model The delay fluctuation standard deviation of the combinational logic unit under According to the obtained Calculate the normalized error and obtain the input conversion time distribution as shown in Figure 2, and then determine the input conversion time τ b(f) and τ b(s) . The interval (0,τ b(f) ) is called the statistical fast input area, τ b(f) is the right boundary of the statistical fast input area; the interval (τ b(s) ,∞) is called the statistical slow input area, τ b(s) Is the left boundary of the statistical slow input area; the interval (τ b(f) ,τ b(s) ) is called the input transition region, τ b(f) and τ b(s)They are the left and right boundaries of the input transition region, respectively, and are independent of the unit drive strength and load.

[0099] Furthermore, the step 3 specifically includes the following steps:

[0100] Step 3.1: For the channel with a width of W p , the channel length is L p The PMOS transistor has a channel width of W n , the channel length is L n The transistor-level simulation is performed on a combinational logic unit composed of NMOS transistors at a subthreshold operating voltage Vdd and a load capacitance C0. The input conversion time of the simulated input waveform is τ (τ>0). When the input conversion time τ<τ b When it is called fast input, select n f (n f is an integer, n f >1) Quick Input Perform transistor-level simulation to measure cell delay Statistical analysis of actual delay fluctuation standard deviation based on Monte Carlo simulation results Select the step case (τ = 0) to perform transistor-level simulation to measure the unit delay, and calculate the actual delay fluctuation standard deviation σ based on the Monte Carlo simulation results. td (0), by fast input statistical model Corresponding to the input conversion time distribution of segment I in Figure 3, the input conversion time of segment I is less than τ b(f) When the delay fluctuation standard deviation does not change with the input conversion time, but remains unchanged, the corresponding fast input The standard deviation of the delayed fluctuation When the input transition time τ>τ b When it is called slow input, select n s (n s is an integer, n s >1) slow input Perform transistor-level simulation to measure cell delay Statistical analysis of actual delay fluctuation standard deviation based on Monte Carlo simulation results For the combinational logic unit, the slow input is calculated through the slow input statistical model. The standard deviation of the delayed fluctuation The calculation formula of the slow input statistical model is as follows:

[0101]

[0102] in,

[0103] Step 3.2. When the input transition time τ < τ b , the standard deviation of delay fluctuation calculated according to the fast input model and the standard deviation of delay fluctuation f i obtained from actual simulation are used to calculate the error λ . When the input transition time τ b < τ < kτ b , where 1 < k < 2, the standard deviation of delay fluctuation calculated according to the slow input model and the standard deviation of delay fluctuation s i obtained from actual simulation are used to calculate the error λ

[0104] Step 3.3. When the input transition time τ < τ b , perform linear fitting (1 ≤ i ≤ n f ) to obtain the normalized error of any input transition time in this interval . When a value of ε is set, such as ε = 3%, the input transition time τ at this time is obtained, which is the left boundary τ b(f) of the input transition region, corresponding to the abscissa of point a in Figure 2. When the input transition time τ b < τ < kτ b , where 1 < k < 2, perform linear fitting (1 ≤ i ≤ n s ) to obtain the normalized error of any input transition time in this interval . When a value of ε is set, the input transition time τ at this time is obtained, which is the right boundary τ b(s) of the input transition region, corresponding to the abscissa of point b in Figure 3. τ b(f) and τ b(s) are independent of the cell drive strength and load.

[0105] Step 4. For a combinational logic cell composed of a PMOS transistor with a channel width of W p and a channel length of L p and an NMOS transistor with a channel width of W n and a channel length of L n , at the subthreshold operating voltage Vdd and the load capacitance C0, use the fast input cell delay statistical model to obtain the standard deviation of delay fluctuation b(f) of the combinational logic cell at the input transition time τ under this load condition. Use the slow input cell delay statistical model to obtain the input transition time τ b(s)The delay fluctuation standard deviation of the combinational logic unit under Then we can get any load capacitance C L The standard deviation of the delay fluctuation of the combinational logic unit at the left and right boundaries of the input transition region under and

[0106] Furthermore, the step 4 specifically includes the following steps:

[0107] Step 4.1: For the combinational logic unit, use the transistor-level simulation tool to simulate the subthreshold operating voltage Vdd and load capacitance C0 to obtain the step delay mean value under the combinational logic unit. and the standard deviation of step delay fluctuation And calculate the unit step delay sensitivity in this case When the input conversion time τ = τ b(s) When , the corresponding input transition zone boundary τ is calculated through the slow input statistical model b(s) The standard deviation of the delayed fluctuation

[0108] Step 4.2: For the channel with a width of W p , the channel length is L p The PMOS transistor has a channel width of W n , the channel length is L n The combination logic unit is composed of NMOS transistors, the subthreshold working voltage Vdd, the load C L Under the circumstance of 100 nm, the nominal value of the unit delay is used as the average step delay value by using the transistor simulation tool. By formula Get load C L The standard deviation of step delay fluctuation under the condition By fast input statistical model Calculate the input conversion time τ = τ b(f) Input transition region left boundary τ b(f) The standard deviation of the delayed fluctuation The vertical coordinate corresponding to point a in Figure 3 under the current situation.

[0109] Step 4.3: For the channel with a width of W p , the channel length is L p The PMOS transistor has a channel width of W n , the channel length is L n The combination logic unit is composed of NMOS transistors, the subthreshold working voltage Vdd, the load C L Next Pass Calculate when input conversion time τ = τ b(s)Input transition region right boundary τ b(s) The standard deviation of the delayed fluctuation The vertical coordinate corresponding to point b in Figure 3 under the current situation.

[0110] Step 5: For the channel with a width of W p , the channel length is L p The PMOS transistor has a channel width of W n , the channel length is L n The combination logic unit is composed of NMOS transistors, the subthreshold working voltage Vdd, the load C L The left boundary of the input transition region τ is obtained based on b(f) and the corresponding delay fluctuation standard deviation Right boundary τ b(s) and the corresponding delay fluctuation standard deviation The standard deviation of the delay fluctuation of any input conversion time in the transition zone under this combination is obtained by linear fitting

[0111]

[0112] ,in,

[0113] Example 2:

[0114] As shown in Figure 4, the delay standard deviation HSPICE simulation results and the traditional literature model value of the inverter under a 5fF capacitor load vary with the input conversion time. The fast and slow boundaries τ are marked in the figure. b And the upper and lower boundaries of the transition region. In the figure, the standard deviation of the unit delay remains unchanged when the input is fast, that is, in (0, τ b(f) ) The model in this paper is consistent with the traditional literature model, but in (τ b(f) , τ b(s) ) In the transition region, it rises slowly with the input conversion time, and at slow input, the slope is V dd / (nV T ) rises rapidly. In the transition region, due to process variations, the results obtained using the nominal judgment method to determine whether the cell input is fast or slow are not stable. Continuing to use the fast and slow input statistical delay models within this range will result in significant errors. In the input transition region, compared to the traditional fast and slow input delay statistical model, the proposed method achieves smaller errors than the standard HSPICE simulation results. The results of this method are shown as the dotted straight line in the figure.

[0115] In response to load scenario changes, the concept of delay step sensitivity is proposed. This paper proposes a load-adaptive delay model, thereby reducing the simulation overhead caused by load scenario changes. The simulation overhead is measured by the total number of Monte Carlo times consumed. As shown in Table 1 below, the simulation overhead of this model is smaller than that of the model in the literature.

[0116] Table 1 shows the total number of Monte Carlo times consumed by the literature model and the model in this paper

[0117]

[0118]

[0119] Among them, the number of unit types N cell , number of unit sizes N d , number of loads N load , the number of Monte Carlo simulations N MC .

[0120] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A statistical delay modeling method for a sub-threshold combinational logic unit, characterized by: The steps include: Step 1: For the combinational logic unit, perform transistor-level simulation under subthreshold operating voltage Vdd and load capacitance C0, obtain the nominal delay value td0 of the combinational logic unit step τ = 0, and calculate the input transition time τ at the boundary between fast input and slow input b ; Step 2: For the combinational logic unit, perform transistor-level simulation at subthreshold operating voltage Vdd and load capacitance C0. When the input transition time τ<τ b When the fast input conversion time is calculated based on the Monte Carlo simulation results The actual simulation delay fluctuation standard deviation of the combinational logic unit under Calculate the fast input conversion time through the fast input unit delay statistical model The delay fluctuation standard deviation of the combinational logic unit under When the input transition time τ>τ b When the slow input conversion time is calculated based on the Monte Carlo simulation results The actual simulation delay fluctuation standard deviation of the combinational logic unit under Calculate the slow input conversion time through the slow input unit delay statistical model The delay fluctuation standard deviation of the combinational logic unit under Step 3: Based on the obtained Calculate the normalized error λ separately f i ,λ s i , according to the normalized error λ f i ,λ s i Calculate the left boundary of the input transition region τ b(f) , input transition zone right boundary τ b(s) ; Step 4: For the combinational logic unit, under the subthreshold operating voltage Vdd and load capacitance C0, use the fast input unit delay statistical model to obtain the input conversion time τ under this load condition b(f) The delay fluctuation standard deviation of the combinational logic unit under The input conversion time τ under this load condition is obtained using the slow input unit delay statistical model b(s) The delay fluctuation standard deviation of the combinational logic unit under Then we can get any load capacitance C L The standard deviation of the delay fluctuation of the combinational logic unit at the left and right boundaries of the input transition region under and Step 5: According to the left boundary τ of the input transition area b(f) and the corresponding delay fluctuation standard deviation Input transition region right boundary τ b(s) and the corresponding delay fluctuation standard deviation By linear fitting, the combinational logic unit is obtained at the subthreshold working voltage Vdd and load capacitance C L Standard deviation of the delay fluctuation of arbitrary input conversion time in the transition region under the model.

2. The method for statistical delay modeling of a sub-threshold combinational logic unit according to claim 1, wherein: The input conversion time τ b The calculation formula is as follows: Where: n is the subthreshold slope factor, V T is the thermal voltage.

3. The statistical delay modeling method of a sub-threshold combinational logic unit according to claim 1, characterized in that The combination logic unit includes a pull-up network and a pull-down network in a stacked structure and a pull-up network and a pull-down network in a parallel structure.

4. The method for statistical delay modeling of a sub-threshold combinational logic unit according to claim 1, wherein: The step 2 specifically includes: Step 2.1: For the combinational logic unit, perform transistor-level simulation at the subthreshold operating voltage Vdd and load capacitance C0. When the input transition time τ of the simulated input waveform is 0<τ<τ b When it is called fast input, select n f Quick Input Perform transistor-level simulation to obtain measurement unit delay Statistics of fast input conversion time based on Monte Carlo simulation results The actual simulation delay fluctuation standard deviation of the combinational logic unit under Among them, n f is an integer, n f >1, 1≤i≤n f ; Step 2.2: Calculate the fast input conversion time based on the fast input statistical model The delay fluctuation standard deviation of the combinational logic unit under Specifically include: Step 2.2.1: Convert time based on fast input The actual simulation delay fluctuation standard deviation of the combinational logic unit under make get Step 2.2.2: Based on the fast input statistical model Calculate the fast input conversion time The delay fluctuation standard deviation of the combinational logic unit under Step 2.3: When the input transition time τ of the simulated input waveform is τ>τ b When it is called slow input, select n s Slow input Perform transistor-level simulation to obtain measurement unit delay Statistical analysis of slow input conversion time based on Monte Carlo simulation results The actual simulation delay fluctuation standard deviation of the combinational logic unit under Among them, n s is an integer, n s >1, 1 <k<2,1≤i≤n s ; Step 2.3: Calculate the slow input conversion time based on the slow input statistical model The delay fluctuation standard deviation of the combinational logic unit under Specifically include: Step 2.3.1: Calculate the standard deviation of the equivalent threshold voltage fluctuation of the pull-up network composed of N PMOS transistors in a stacked structure Calculate the standard deviation of the equivalent threshold voltage fluctuation of a parallel pull-up network composed of N PMOS transistors Where N is an integer, N≥1; Step 2.3.2: Calculate the standard deviation of the equivalent threshold voltage fluctuation of the pull-down network composed of N NMOS transistors Calculate the standard deviation of the equivalent threshold voltage fluctuation of a parallel pull-down network composed of N NMOS transistors Step 2.3.3: When the pull-down network of the combinational logic unit works and the pull-down network is a stacked structure, according to the slow input statistical model Calculate slow input transition time The delay fluctuation standard deviation of the combinational logic unit under Step 2.3.4: When the pull-down network of the combinational logic unit is working and the pull-down network is a parallel structure, according to the slow input statistical model Calculate the slow input transition time The delay fluctuation standard deviation of the combinational logic unit under Step 2.3.5: When the pull-up network of the combinational logic unit is working and the pull-up network is a stacked structure, according to the slow input statistical model Calculate slow input transition time The delay fluctuation standard deviation of the combinational logic unit under Step 2.3.6: When the pull-up network of the combinational logic unit is working and the pull-up network is in parallel structure, according to the slow input statistical model Calculate the slow input transition time The delay fluctuation standard deviation of the combinational logic unit under 5. The method for statistical delay modeling of a sub-threshold combinational logic unit according to claim 1, wherein: The step 3 specifically includes: Step 3.1: When the input transition time 0 < τ < τ b When the delay fluctuation standard deviation is calculated based on the fast input model Compared with the actual simulation delay fluctuation standard deviation Calculation error λ f i , Step 3.2: When the input conversion time τ b < τ < kτ b , 1 < k < 2, the standard deviation of delay fluctuation calculated according to the slow input model and the standard deviation of delay fluctuation obtained from actual simulation Calculate the error λ s i , Step 3.3: When the input transition time 0 < τ < τ b When the linear fitting interval 1≤i≤n f , we get 0<τ<τ b Normalized error of any input conversion time in the interval when Set the ε value to get the input conversion time τ at this time, which is the left boundary of the input transition area τ b(f) ; Step 3.4: When the input conversion time τ b < τ < kτ b , where 1 < k < 2, the linear fitting interval 1 ≤ i ≤ n s , to obtain τ b < τ < kτ b the normalized error of any input conversion time in the τ interval When set the value of ε, and obtain the input conversion time τ at this time, which is the right boundary τ of the input transition region b(s) .

6. The method for statistical delay modeling of a sub-threshold combinational logic unit according to claim 1, wherein: The step 4 specifically includes: Step 4.1: For the combinational logic unit, use transistor-level simulation tools to simulate the subthreshold operating voltage Vdd and load capacitance C0 to obtain the average step delay of the combinational logic unit. and the standard deviation of step delay fluctuation And calculate the unit step delay sensitivity in this case Step 4.2: When the input transition time τ = τ b(s) When , the corresponding input transition zone boundary τ is calculated through the slow input statistical model b(s) The standard deviation of the delayed fluctuation The slow input statistical model specifically includes: When the pull-down network of the combinational logic unit works and is a stacked structure, the slow input statistical model is When the pull-down network of the combinational logic unit works and is in parallel structure, the slow input statistical model is When the pull-up network of the combinational logic unit works and is a stacked structure, the slow input statistical model is When the pull-up network of the combinational logic unit works and is in a parallel structure, the slow input statistical model is in, are the standard deviation of the equivalent threshold voltage fluctuation of the stacked pull-up network composed of N PMOS transistors and the standard deviation of the equivalent threshold voltage fluctuation of the parallel pull-up network; are the standard deviation of the equivalent threshold voltage fluctuation of the stacked pull-down network composed of N NMOS transistors and the standard deviation of the equivalent threshold voltage fluctuation of the parallel pull-down network; Step 4.3: For combinational logic cells, at subthreshold operating voltage Vdd, load C L In this case, the nominal value of the unit delay is used as the mean step delay value by using the transistor simulation tool. By formula Get load C L The standard deviation of step delay fluctuation under the condition By fast input statistical model Calculate the input conversion time τ = τ b(f) Input transition region left boundary τ b(f) The standard deviation of the delayed fluctuation Step 4.4: For combinational logic cells, at subthreshold operating voltage Vdd and load C L Next Pass Calculate when input conversion time τ = τ b(s) Input transition region right boundary τ b(s) The standard deviation of the delayed fluctuation 7. The method for statistical delay modeling of a sub-threshold combinational logic unit according to claim 4 or 6, characterized in that: described The calculation formula is as follows: described The calculation formula is as follows: in, represents the standard deviation of the threshold voltage fluctuation of the simulated NMOS transistor, Respectively represent the channel width, channel length, W of the simulated NMOS transistor n 、L n They represent the channel width and channel length of the NMOS transistor in the pull-down network to be determined.

8. The method for statistical delay modeling of a sub-threshold combinational logic unit according to claim 4 or 6, characterized in that: described The calculation formula is as follows: described The calculation formula is as follows: in, represents the standard deviation of the threshold voltage fluctuation of the simulated PMOS transistor, Represent the channel width, channel length, and W of the simulated PMOS transistor respectively. p 、L p They represent the channel width and channel length of the PMOS transistor of the pull-up network to be determined.

9. The method for statistical delay modeling of a sub-threshold combinational logic unit according to claim 1, wherein: The combination logic unit, under the subthreshold working voltage Vdd, load capacitance C L The calculation formula of the standard deviation model of the delay fluctuation of any input conversion time in the transition zone is as follows: ， in, 10. The method for statistical delay modeling of a sub-threshold combinational logic unit according to claim 5, wherein: ε=3%.

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