Array substrate row drive circuit

Abstract

The array substrate row driving circuit provided in the application comprises a plurality of cascade gate driving modules, wherein the nth gate driving module comprises a pull-up control unit, a pull-up unit, a pull-down unit, a first pull-down maintaining unit, a second pull-down maintaining unit and a global reset unit, the global reset unit is electrically connected with a first node, a first low-frequency clock signal end, a second low-frequency clock signal end and a first reference signal end, the global reset unit is electrically connected with the first low-frequency clock signal end and the second low-frequency clock signal end instead of being electrically connected with a global reset signal end, so that the number of signal ends electrically connected with the array substrate row driving circuit is reduced, the number of GOA signal lines electrically connected with the signal ends is reduced, and the narrow frame of the display panel is facilitated.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate row driving circuit. Background Technology

[0002] The Gate-driver On Array (GOA) circuit can integrate the shift register function of the chip on film (COF) that provides the gate drive signal onto the display panel, thereby realizing the narrow bezel design of the display panel. Therefore, GOA has become the mainstream driving solution currently used in display panels.

[0003] In order to provide different types of driving signals to the pixel driving circuit of the display panel through the GOA, such as compensation control signals, light emission control signals, data writing control signals, initialization control signals, etc., the GOA needs to be electrically connected to multiple GOA signal lines. Based on the signals provided by the multiple GOA signal lines and the circuit architecture of the GOA, different types of driving signals are provided to the pixel driving circuit.

[0004] However, the number of GOA signal lines electrically connected to the GOA is relatively large, and the GOA and GOA signal lines occupy a large space in the display panel, which is not conducive to the narrow bezel design of the display panel. Summary of the Invention

[0005] This application provides an array substrate row driving circuit, which aims to solve the technical problem that the large number of GOA signal lines connected to the array substrate row driving circuit hinders the narrow bezel of the display panel.

[0006] In a first aspect, this application provides an array substrate row driving circuit, including a cascaded multi-stage gate driving module, wherein the nth stage gate driving module includes:

[0007] A pull-up control unit is electrically connected to the first stage signal output terminal of the np-th stage gate driving module and the first node of the n-th stage gate driving module. The pull-up control unit is used to pull up the potential of the first node under the control of the first stage signal output terminal.

[0008] A pull-up unit is electrically connected to the first clock signal terminal of the array substrate row driving circuit, the second clock signal terminal of the array substrate row driving circuit, the first node, the second-stage transmission signal output terminal of the nth-stage gate driving module, and the drive signal output terminal of the nth-stage gate driving module. The pull-up unit is used to output a second-stage transmission signal to the second-stage transmission signal output terminal and a drive signal to the drive signal output terminal under the control of the potential of the first node, the first clock signal of the first clock signal terminal, and the second clock signal of the second clock signal terminal.

[0009] A pull-down unit is electrically connected to the third-level signal output terminal of the gate driving module of the (n+p)th stage, the first node, and the first reference signal terminal of the array substrate row driving circuit. The pull-down unit is used to pull down the potential of the first node under the control of the third-level signal output terminal and the reference low-level signal of the first reference signal terminal.

[0010] The first pull-down sustaining unit is electrically connected to the first low-frequency clock signal terminal, the first node, and the first reference signal terminal of the array substrate row driving circuit. The first pull-down sustaining unit is used to maintain the potential of the first node at a low potential based on the reference low-level signal under the control of the first low-frequency clock signal of the first low-frequency clock signal terminal.

[0011] The second pull-down sustaining unit is electrically connected to the second low-frequency clock signal terminal, the first node, and the first reference signal terminal of the array substrate row driving circuit. The second pull-down sustaining unit is used to maintain the potential of the first node at a low potential based on the reference low-level signal under the control of the second low-frequency clock signal of the second low-frequency clock signal terminal.

[0012] A global reset unit is electrically connected to the first node, the first low-frequency clock signal terminal, the second low-frequency clock signal terminal, and the first reference signal terminal. The global reset unit is used to provide the reference low-level signal to the first node under the control of the first low-frequency clock signal and the second low-frequency clock signal.

[0013] Wherein, the first node is the node of the line between the pull-up control unit and the pull-up unit, n is an integer greater than or equal to 1, p is an integer greater than or equal to 1, and p is less than n.

[0014] In the array substrate row driving circuit provided in this application, during the effective display phase of any frame display cycle, one of the first low-frequency clock signal and the second low-frequency clock signal is a low-level signal, and the other of the first low-frequency clock signal and the second low-frequency clock signal is a high-level signal.

[0015] Furthermore, within the m-th frame display period and the m+1-th frame display period, at a first preset time point, one of the first low-frequency clock signal and the second low-frequency clock signal switches from the high-level signal to the low-level signal, and at a second preset time point, the other of the first low-frequency clock signal and the second low-frequency clock signal switches from the low-level signal to the high-level signal.

[0016] Wherein, neither the first preset time point nor the second preset time point is earlier than the first end point of the effective display phase of the m-th frame display period, and neither the first preset time point nor the second preset time point is later than the second start point of the effective display phase of the (m+1)-th frame display period, where m is an integer greater than or equal to 1.

[0017] In the array substrate row driving circuit provided in this application, the global reset unit includes a first transistor and a second transistor;

[0018] One of the gates of the first transistor and the second transistor is electrically connected to the first low-frequency clock signal terminal, and the other of the gates of the first transistor and the second transistor is electrically connected to the second low-frequency clock signal terminal. The source of the first transistor is electrically connected to the first reference signal terminal, the drain of the first transistor is electrically connected to the source of the second transistor, and the drain of the second transistor is electrically connected to the first node.

[0019] Between the first preset time point and the second preset time point, one of the first transistor and the second transistor is turned on based on the first low-frequency clock signal, and the other of the first transistor and the second transistor is turned on based on the second low-frequency clock signal.

[0020] In the array substrate row driving circuit provided in this application, the first transistor and the second transistor are both N-type transistors or both P-type transistors. Under the control of the first low-frequency clock signal and the second low-frequency clock signal, which are both first level signals, the first transistor and the second transistor provide the reference low-level signal to the first node.

[0021] In the array substrate row driving circuit provided in this application, at least from the first start time point of the effective display phase of the m-th frame display cycle to the first preset time point, one of the first low-frequency clock signal and the second low-frequency clock signal is the first level signal, and from the first preset time point to at least the second end time point of the effective display phase of the m+1-th frame display cycle, one of the first low-frequency clock signal and the second low-frequency clock signal is the second level signal.

[0022] At least from the first start time point to the second preset time point, the other of the first low-frequency clock signal and the second low-frequency clock signal is the second level signal, and from the second preset time point to at least the second end time point, the other of the first low-frequency clock signal and the second low-frequency clock signal is the first level signal;

[0023] Wherein, the first preset time point is later than the second preset time point, the first level signal is one of the low level signal and the high level signal, and the second level signal is the other of the low level signal and the high level signal.

[0024] In the array substrate row driving circuit provided in this application, the duration difference between the first preset time point and the second preset time point is greater than or equal to the first preset duration.

[0025] In the array substrate row driving circuit provided in this application, from the first preset time point to the third preset time point, one of the first low-frequency clock signal and the second low-frequency clock signal is the second level signal, and the third preset time point is not earlier than the second end time point;

[0026] From the second preset time point to the fourth preset time point, the other of the first low-frequency clock signal and the second low-frequency clock signal is the first level signal. The fourth preset time point is not later than the third start time point of the effective display stage of the m+2 frame display cycle, and the fourth preset time point is later than the third preset time point.

[0027] In the array substrate row driving circuit provided in this application, the time difference between the fourth preset time point and the third preset time point is the same as the time difference between the first preset time point and the second preset time point.

[0028] In the array substrate row driving circuit provided in this application, the pull-up control unit includes a third transistor, the gate and source of the third transistor are electrically connected to the first stage signal output terminal, and the drain of the third transistor is electrically connected to the first node.

[0029] And / or, the pull-up unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the first clock signal terminal, the drain of the fourth transistor is electrically connected to the second stage signal output terminal, the gate of the fifth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the second clock signal terminal, and the drain of the fifth transistor is electrically connected to the drive signal output terminal;

[0030] And / or, the pull-down unit includes a sixth transistor, the gate of the sixth transistor is electrically connected to the signal output terminal of the third stage, the source of the sixth transistor is electrically connected to the first reference signal terminal, and the drain of the sixth transistor is electrically connected to the first node.

[0031] And / or, the first pull-down sustaining unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a seventeenth transistor, and an eighteenth transistor. The gate and source of the seventh transistor are electrically connected to the first low-frequency clock signal terminal. The drain of the seventh transistor is electrically connected to the source of the eighth transistor. The gate of the eighth transistor is electrically connected to the first node. The gate of the ninth transistor is electrically connected to the drain of the seventh transistor. The source of the ninth transistor is electrically connected to the first low-frequency clock signal terminal. The drain of the ninth transistor is electrically connected to the second node of the nth stage gate drive module. The gate of the tenth transistor is electrically connected to the gate of the eighth transistor. The source of the tenth transistor is electrically connected to the first reference signal terminal; the drain of the tenth transistor is electrically connected to the second node; the gate of the eleventh transistor is electrically connected to the second node; the source of the eleventh transistor is electrically connected to the first reference signal terminal; the drain of the eleventh transistor is electrically connected to the first node; the gate of the seventeenth transistor is electrically connected to the second node; the source of the seventeenth transistor is electrically connected to the first reference signal terminal; the drain of the seventeenth transistor is electrically connected to the second node; the gate of the eighteenth transistor is electrically connected to the second node; the source of the eighteenth transistor is electrically connected to the first reference signal terminal; and the drain of the eighteenth transistor is electrically connected to the drive signal output terminal.

[0032] And / or, the second pull-down sustaining unit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a nineteenth transistor, and a twentieth transistor. The gate and source of the twelfth transistor are electrically connected to the second low-frequency clock signal terminal. The drain of the twelfth transistor is electrically connected to the source of the thirteenth transistor. The gate of the thirteenth transistor is electrically connected to the first node. The gate of the fourteenth transistor is electrically connected to the drain of the twelfth transistor. The source of the fourteenth transistor is electrically connected to the second low-frequency clock signal terminal. The drain of the fourteenth transistor is electrically connected to the third node of the nth stage gate drive module. The gate of the fifteenth transistor is electrically connected to the gate of the thirteenth transistor. The fifteenth transistor is electrically connected to the first reference signal terminal, and its drain is electrically connected to the third node. The sixteenth transistor is electrically connected to the gate of the third node, and its source is electrically connected to the first reference signal terminal. The nineteenth transistor is electrically connected to the gate of the third node, and its source is electrically connected to the first reference signal terminal. The drain of the nineteenth transistor is electrically connected to the third node. The twentieth transistor is electrically connected to the gate of the third node, and its source is electrically connected to the first reference signal terminal. The drain of the twentieth transistor is electrically connected to the drive signal output terminal.

[0033] In the array substrate row driving circuit provided in this application, the nth stage gate driving module further includes a leakage protection unit. The leakage protection unit is electrically connected to the first node, the second reference signal terminal of the array substrate row driving circuit, the first pull-down sustaining unit, the second pull-down sustaining unit, the pull-down unit, and the global reset unit. The leakage protection unit is used to prevent leakage of the first pull-down sustaining unit, the second pull-down sustaining unit, the pull-down unit, and the global reset unit under the control of the potential of the first node and the reference high-level signal of the second reference signal terminal.

[0034] The array substrate row driving circuit provided in this application electrically connects the global reset unit in the gate driving module to the first low-frequency clock signal terminal and the second low-frequency clock signal terminal of the array substrate row driving circuit, instead of electrically connecting the global reset unit to the global reset signal terminal of the array substrate row driving circuit. This reduces the number of signal terminals electrically connected to the array substrate row driving circuit, and consequently reduces the number of GOA signal lines connected to the corresponding signal terminals, which is beneficial for narrowing the bezel of the display panel. Attached Figure Description

[0035] Figure 1 A block diagram of an array substrate row driving circuit provided for an embodiment of this application;

[0036] Figure 2 for Figure 1 A block diagram of the nth-stage gate drive module of the array substrate row drive circuit shown;

[0037] Figure 3 for Figure 2 The diagram shows a schematic of the first type of circuit for the nth-stage gate drive module.

[0038] Figure 4 for Figure 3 The circuit diagram shown illustrates the first timing sequence of the first low-frequency clock signal and the second low-frequency clock signal.

[0039] Figure 5 for Figure 3 The circuit diagram shown illustrates a second timing sequence for the first low-frequency clock signal and the second low-frequency clock signal.

[0040] Figure 6 for Figure 2 The diagram shows a second type of circuit for the nth-stage gate drive module. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. The described embodiments are only used to explain the ideas of the present invention and should not be regarded as limiting the scope of protection of this application.

[0042] The transistors used in the embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Since the source and drain of the transistors are interchangeable, in this application embodiment, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source and the other the drain. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, when the transistors used in the embodiments of this application are P-type transistors, they conduct when the gate is low and are cut off when the gate is high. When the transistors used in the embodiments of this application are N-type transistors, they conduct when the gate is high and are cut off when the gate is low.

[0043] In related technologies, each gate drive module of GOA needs to be electrically connected to the global reset signal terminal. Then, through the global reset signal terminal which is electrically connected to the corresponding GOA signal line, the global reset signal output by the global reset signal will pull down the potential of the first node (also known as the pull-up node) of each gate drive module under the drive of the global reset signal after the effective display phase of the current frame display cycle ends and before the effective display phase of the next frame display cycle begins. This releases the residual charge at the first node of each gate drive module and completes the global reset.

[0044] In order to provide different types of driving signals to the pixel driving circuit via the array substrate row driving circuit, the array substrate row driving circuit needs to be electrically connected to multiple GOA signal lines. This allows the array substrate row driving circuit to provide different types of driving signals to the pixel driving circuit based on the signals provided by the multiple GOA signal lines and the circuit architecture of the array substrate row driving circuit. However, as the number of GOA signal lines electrically connected to the GOA increases, the space occupied by the GOA and GOA signal lines in the display panel also increases accordingly, which is detrimental to achieving narrow bezels in the display panel.

[0045] Based on this, embodiments of this application propose an array substrate row driving circuit in which a global reset unit is electrically connected to a first low-frequency clock signal terminal and a second low-frequency clock signal terminal. Instead of electrically connecting the global reset unit to the global reset signal terminal, the global reset unit shares the first low-frequency clock signal terminal with the first pull-down sustaining unit and shares the second low-frequency clock signal terminal with the second pull-down sustaining unit. This reduces the number of signal terminals electrically connected to the array substrate row driving circuit and the number of GOA signal lines connected to the corresponding signal terminals.

[0046] like Figure 1 as well as Figure 2 As shown, the array substrate row driving circuit 1000 includes cascaded multi-stage gate driving modules 100. The nth stage gate driving module 100 includes a pull-up control unit 10, a pull-up unit 20, a pull-down unit 30, a first pull-down sustaining unit 40, a second pull-down sustaining unit 50, and a global reset unit 60. Here, n is an integer greater than or equal to 1.

[0047] The pull-up control unit 10 is electrically connected to the first-stage signal output terminal Cout(np) of the np-th stage gate drive module 100 and the first node Q(n) of the n-th stage gate drive module 100. Here, p is an integer greater than or equal to 1, and p is less than n. The first node Q(n) is the node of the line between the pull-up control unit 10 and the pull-up unit 20.

[0048] The pull-up control unit 10 is used to pull up the potential of the first node Q(n) under the control of the first-stage transmission signal provided by the first-stage transmission signal output terminal Cout(np). The first-stage transmission signal is the stage transmission signal output by the np-th stage gate drive module 100.

[0049] In the array substrate row driving circuit 1000, for the first-stage gate driving module 100 to the p-th stage gate driving module 100 (i.e., the first p-stage gate driving modules 100), the stage transmission signal of the pn-th stage gate driving module 100 does not exist. Therefore, in the first-stage gate driving module 100 to the p-th stage gate driving module 100, a start signal can be set to replace the stage transmission signal of the pn-th stage. Similarly, for the last-stage gate driving module 100 to the p-th-last stage gate driving module 100 (i.e., the last p-stage gate driving module 100), the stage transmission signal of the (n+p)-th stage gate driving module 100 does not exist. Therefore, in the last-stage gate driving module 100 to the p-th-last stage gate driving module 100, a start signal or another signal can be set to drive the stage transmission signal of the (n+p)-th stage gate driving module 100. Apart from the differences mentioned above, the circuit structure and signal connections of the front p-stage gate drive module 100 and the rear p-stage gate drive module 100 are the same as those of the other stage gate drive modules 100.

[0050] The pull-up unit 20 is electrically connected to the first clock signal terminal CKa of the array substrate row driving circuit 1000, the second clock signal terminal CKb of the array substrate row driving circuit 1000, the first node Q(n), the second-stage transmission signal output terminal Cout(n) of the nth-stage gate driving module 100, and the drive signal output terminal WR(n) of the nth-stage gate driving module 100.

[0051] The pull-up unit 20 is used to output a second-stage transmission signal to the second-stage transmission signal output terminal Cout(n) under the control of the potential of the first node Q(n) and the first clock signal provided by the first clock signal terminal CKa. The second-stage transmission signal is the transmission signal output by the nth-stage gate drive module 100. The pull-up unit 20 is also used to output a drive signal to the drive signal output terminal WR(n) under the control of the potential of the first node Q(n) and the second clock signal provided by the second clock signal terminal CKb.

[0052] The pull-down unit 30 is electrically connected to the third-level signal output terminal of the n+p-th level gate drive module 100, the first node Q(n), and the first reference signal terminal VGL of the array substrate row drive circuit 1000.

[0053] The pull-down unit 30 is used to pull down the potential of the first node Q(n) under the control of the third-level transmission signal output from the third-level transmission signal output terminal and the reference low-level signal provided by the first reference signal terminal VGL.

[0054] The first pull-down sustaining unit 40 is electrically connected to the first low-frequency clock signal terminal LC1, the first node Q(n), and the first reference signal terminal VGL of the array substrate row driving circuit 1000.

[0055] The first pull-down sustaining unit 40 is used to maintain the potential of the first node Q(n) at a low potential based on a reference low-level signal under the control of the first low-frequency clock signal provided by the first low-frequency clock signal terminal LC1.

[0056] The second pull-down sustaining unit 50 is electrically connected to the second low-frequency clock signal terminal LC2, the first node Q(n), and the first reference signal terminal VGL of the array substrate row drive circuit 1000.

[0057] The second pull-down sustaining unit 50 is used to maintain the potential of the first node Q(n) at a low potential based on the reference low-level signal under the control of the second low-frequency clock signal provided by the second low-frequency clock signal terminal LC2.

[0058] The global reset unit 60 is electrically connected to the first node Q(n), the first low-frequency clock signal terminal LC1, the second low-frequency clock signal terminal LC2, and the first reference signal terminal VGL.

[0059] The global reset unit 60 is used to provide the reference low level signal of the first reference signal terminal VGL to the first node Q(n) under the control of the first low frequency clock signal and the second low frequency clock signal.

[0060] The array substrate row driving circuit 1000 provided in this embodiment electrically connects the global reset unit 60 in the gate driving module 100 to the first low-frequency clock signal terminal LC1 and the second low-frequency clock terminal of the array substrate row driving circuit 1000. Under the control of the first low-frequency clock signal and the second low-frequency clock signal, the global reset unit 60 provides the reference low-level signal of the first reference signal terminal VGL to the first node Q(n) to release the residual charge of the first node Q(n) and ensure that the pull-up unit 20 is turned off more thoroughly.

[0061] In other words, in the array substrate row driving circuit 1000 provided in this embodiment, by replacing the global reset unit 60 of the related technology with the global reset signal terminal independent of the first low-frequency clock signal terminal LC1 and the second low-frequency clock signal terminal LC2, the number of signal terminals electrically connected to the array substrate row driving circuit 1000 is reduced, thereby reducing the number of GOA signal lines connected to the corresponding signal terminals, which is beneficial for the narrow bezel of the display panel.

[0062] Within one frame display cycle, the multi-stage gate drive module 100 in the array substrate row drive circuit 1000 needs to output the corresponding stage transmission signal and drive signal step by step.

[0063] The second-level transmission signal output by the current-level gate driving module 100 (such as the nth-level gate driving module 100) serves as the start signal for controlling the pull-up unit 20 of the next-level gate driving module 100 to operate. Here, the next-level gate driving module 100 refers to another gate driving module 100 that is electrically connected to the current-level gate driving module 100. For example, if the current-level gate driving module 100 is the nth-level gate driving module 100, then the next-level gate driving module 100 is the (n+p)th-level gate driving module 100.

[0064] The driving signal output by the current stage gate driving module 100 (such as the nth stage gate driving module 100) serves as an electrical signal that drives the corresponding transistors in the pixel driving circuit of at least the nth pixel row to turn on or off.

[0065] Each frame display cycle includes an effective display phase and a vertical blanking phase (V-Blanking time). During the effective display phase, the array substrate row driving circuit 1000 outputs the corresponding driving signal to each row of pixel units from the first row to the last row, causing multiple rows of pixel units to emit light sequentially. During the vertical blanking phase, the array substrate row driving circuit 1000 stops providing the corresponding driving signal to the corresponding row of pixel units, and the pixel units do not emit light.

[0066] In some embodiments provided in this application, during the effective display phase of any frame display cycle, one of the first low-frequency clock signal and the second low-frequency clock signal is a low-level signal, and the other of the first low-frequency clock signal and the second low-frequency clock signal is a high-level signal.

[0067] It should be understood that since both the first pull-down sustaining unit 40 and the second pull-down sustaining unit 50 are in the same state of being in operation and being off based on a high-level signal, for example, the first pull-down sustaining unit 40 is in operation based on a first low-frequency clock signal that is high, and the second pull-down sustaining unit 50 is also in operation based on a second low-frequency clock signal that is high, therefore, during the effective display phase of any frame display cycle, based on the fact that one of the first low-frequency clock signal and the second low-frequency clock signal is a low-level signal and the other of the first low-frequency clock signal and the second low-frequency clock signal is a high-level signal, one of the first pull-down sustaining unit 40 and the second pull-down sustaining unit 50 is in the on state, and the other of the first pull-down sustaining unit 40 and the second pull-down sustaining unit 50 is in the off state.

[0068] Furthermore, within two consecutive display periods, namely the m-th frame display period F(m) and the (m+1)-th frame display period F(m+1), at a first preset time point t1, one of the first low-frequency clock signal and the second low-frequency clock signal switches from a high-level signal to a low-level signal. Within the m-th frame display period F(m) and the (m+1)-th frame display period F(m+1), at a second preset time point t2, the other of the first low-frequency clock signal switches from a low-level signal to a high-level signal.

[0069] Wherein, the first preset time point t1 and the second preset time point t2 are both no earlier than the first end point t(m)_2 of the effective display phase of the m-th frame display period F(m), and the first preset time point t1 and the second preset time point t2 are both no later than the second start point t(m+1)_1 of the effective display phase of the (m+1)-th frame display period F(m+1), where m is an integer greater than or equal to 1. That is to say, the first preset time point t1 and the second preset time point t2 are both located during the vertical blanking period between two consecutive frame display periods.

[0070] Based on the fact that one of the first low-frequency clock signal and the second low-frequency clock signal switches from a high-level signal to a low-level signal at a first preset time point t1, one of the first low-frequency clock signal and the second low-frequency clock signal is in the working state during the effective display phase of the m-frame display period F(m), and in the off state during the effective display phase of the m+1-frame display period F(m+1).

[0071] Based on the fact that one of the first low-frequency clock signal and the second low-frequency clock signal switches from a low-level signal to a high-level signal at a second preset time point t2, one of the first low-frequency clock signal and the second low-frequency clock signal is in the working state during the effective display phase of the m-th frame display period F(m), and in the effective display phase of the m+1-th frame display period F(m+1).

[0072] In this way, during a series of consecutive display cycles, the first pull-down sustaining unit 40 and the second pull-down sustaining unit 50 work alternately in the effective display phase to maintain the potential of the first node Q(n) at a low potential in each effective display phase.

[0073] The global reset unit 60, under the control of a first low-frequency clock signal that switches from a high-level signal to a low-level signal at a first preset time t1 and a second low-frequency clock signal that switches from a low-level signal to a high-level signal at a second preset time t2, provides a reference low-level signal to the first node Q(n). The vertical blanking phase of two adjacent display cycles completes the release of residual charge at the first node Q(n) in each gate drive module 100, thereby resetting the first node Q(n) in each gate drive module 100.

[0074] Specifically, in some embodiments provided in this application, such as Figure 3 As shown, Figure 3 and Figure 2 The difference is that, Figure 3 The global reset unit 60 shown includes a first transistor T1 and a second transistor T2.

[0075] One of the gates of the first transistor T1 and the second transistor T2 is electrically connected to the first low-frequency clock signal terminal LC1, and the other of the gates of the first transistor T1 and the second transistor T2 is electrically connected to the second low-frequency clock signal terminal LC2. The source of the first transistor T1 is electrically connected to the first reference signal terminal VGL, the drain of the first transistor T1 is electrically connected to the source of the second transistor T2, and the drain of the second transistor T2 is electrically connected to the first node Q(n).

[0076] Furthermore, in this embodiment, between the first preset time point t1 and the second preset time point t2, one of the first transistor T1 and the second transistor T2 is turned on based on the first low-frequency clock signal, and the other of the first transistor T1 and the second transistor T2 is turned on based on the second low-frequency clock signal. In this way, the global reset unit 60 provided in this embodiment, based on the electrical connection between the first transistor T1 and the second transistor T2 and the first node Q(n), the first reference signal terminal VGL, the first low-frequency clock signal terminal LC1, and the second low-frequency clock signal terminal LC2, continuously outputs a reference low-level signal to the first node Q(n) between the first preset time point t1 and the second preset time point t2, releasing the residual charge at the first node Q(n).

[0077] Furthermore, in some embodiments provided in this application, both the first transistor T1 and the second transistor T2 are N-type transistors. Under the control of both the first low-frequency clock signal and the second low-frequency clock signal being a first level signal, the first transistor T1 and the second transistor T2 provide a reference low-level signal to the first node Q(n). In this embodiment, the first level signal refers to a high-level signal, thus the first transistor T1 and the second transistor T2 are in a conducting state between a first preset time point t1 and a second preset time point t2, based on the fact that both the first low-frequency clock signal and the second low-frequency clock signal are high-level signals.

[0078] Furthermore, in some embodiments provided in this application, both the first transistor T1 and the second transistor T2 are P-type transistors. Under the control of both the first low-frequency clock signal and the second low-frequency clock signal being a first level signal, the first transistor T1 and the second transistor T2 provide a reference low-level signal to the first node Q(n). In this embodiment, the first level signal refers to a low-level signal, thus the first transistor T1 and the second transistor T2 are in a conducting state between a first preset time point t1 and a second preset time point t2, based on the fact that both the first low-frequency clock signal and the second low-frequency clock signal are low-level signals.

[0079] Please see Figure 4 as well as Figure 3 In one embodiment provided in this application, such as Figure 4 As shown, from at least the first start time t(m)_1 of the effective display phase T(m) of the m-th frame display period F(m) to the first preset time t1, one of the first low-frequency clock signal and the second low-frequency clock signal is a first level signal. And from at least the first preset time t1 to the second end time t(m+1)_2 of the effective display phase T(m+1) of the (m+1)-th frame display period F(m+1), one of the first low-frequency clock signal and the second low-frequency clock signal is a second level signal.

[0080] At least from the first starting point t(m)_1 to the second preset point t2, the other of the first low-frequency clock signal and the second low-frequency clock signal is a second level signal, and from the second preset point t2 to at least the second ending point t(m+1)_2, the other of the first low-frequency clock signal and the second low-frequency clock signal is a first level signal.

[0081] Wherein, the first preset time point t1 is not later than the second starting time point t(m+1)_1, the second preset time point t2 is not earlier than the first ending time point t(m)_2, and the first preset time point t1 is later than the second preset time point t2.

[0082] The first level signal is one of a low level signal and a high level signal, and the second level signal is the other of a low level signal and a high level signal.

[0083] In this way, between the first preset time point t1 and the second preset time point t2, both the first transistor T1 and the second transistor T2 are turned on based on the first level signal. The first transistor T1 and the second transistor T2 continuously output the reference low level signal to the first node Q(n) to release the residual charge at the first node Q(n).

[0084] Furthermore, in some embodiments provided in this application, the duration difference between the first preset time point t1 and the second preset time point t2 is greater than or equal to the first preset duration.

[0085] Specifically, the first preset duration is determined based on the refresh rate of the display panel and the number of pixel rows in the display panel. Taking a refresh rate of 60 Hz and a number of pixel rows of 1920 as an example, the pixel row scanning time of the display panel is 1 / (60*1920) seconds, then the first preset duration is greater than or equal to 1 / (60*1920) seconds.

[0086] Furthermore, in some embodiments provided in this application, such as Figure 5 as well as Figure 3 As shown, from the first preset time point t1 to the third preset time point t3, one of the first low-frequency clock signal and the second low-frequency clock signal is a second level signal. The third preset time point t3 is not earlier than the second end point T(m+1)_2 of the effective display phase T(m+1) of the (m+1)th frame display period F(m+1). From the second preset time point t2 to the fourth preset time point t4, the other of the first low-frequency clock signal and the second low-frequency clock signal is a first level signal. The fourth preset time point t4 is not later than the third start point T(m+2)_1 of the effective display phase T(m+2) of the (m+2)th frame display period F(m+2), and the fourth preset time point t4 is later than the third preset time point t3.

[0087] In this way, between the second end point t(m+1)_2 of the effective display phase T(m+1) of the m+1 frame display period F(m+1) and the third start point T(m+2)_1 of the effective display phase T(m+2) of the m+2 frame display period F(m+2), and specifically between the third preset point t3 and the fourth preset point t4, the first transistor T1 and the second transistor T2 are both turned on based on the first low-frequency clock signal and the second low-frequency clock signal, which are both first level signals. The first transistor T1 and the second transistor T2 continuously output the reference low-level signal to the first node Q(n) to release the residual charge at the first node Q(n).

[0088] Furthermore, in some embodiments provided in this application, the duration difference between the fourth preset time point t4 and the third preset time point t3 is the same as the duration difference between the first preset time point t1 and the second preset time point t2. That is, during the vertical blanking phase TB_(m+1,m+2) between the effective display phase T(m+1) of the (m+1)th frame display period F(m+1) and the effective display phase T(m+2) of the (m+2)th frame display period F(m+2), and during the vertical blanking phase TB_(m,m+1) between the effective display phase T(m) of the (m)th frame display period F(m) and the effective display phase T(m+1) of the (m+1)th frame display period F(m) and the (m+1)th frame display period F(m+1), the duration for which the first transistor T1 and the second transistor T2 are simultaneously turned on is the same.

[0089] Specifically, in some embodiments provided in this application, the time difference between the first preset time point t1 and the first end point t(m)_2 is the same as the time difference between the fourth preset time point t4 and the second end point t(m+1)_2, and the time difference between the second preset time point t2 and the first end point t(m)_2 is the same as the time difference between the third preset time point t3 and the second end point t(m+1)_2.

[0090] In this way, within two consecutive display frames, the duration for which one of the first and second low-frequency clock signals remains at a low level is the same as the duration for which the other of the first and second low-frequency clock signals remains at a low level. Similarly, within two consecutive display frames, the duration for which one of the first and second low-frequency clock signals remains at a high level is the same as the duration for which the other of the first and second low-frequency clock signals remains at a high level.

[0091] like Figure 3 As shown, in some embodiments provided in this application, the pull-up control unit 10 includes a third transistor T3, the gate and source of the third transistor T3 are electrically connected to the first stage signal output terminal Cout(np), and the drain of the third transistor T3 is electrically connected to the first node Q(n).

[0092] like Figure 3 As shown, in some embodiments provided in this application, the pull-up unit 20 includes a fourth transistor T4 and a fifth transistor T5. The gate of the fourth transistor T4 is electrically connected to the first node Q(n), the source of the fourth transistor T4 is electrically connected to the first clock signal terminal CKa, and the drain of the fourth transistor T4 is electrically connected to the second-stage transmission signal output terminal Cout(n). The gate of the fifth transistor T5 is electrically connected to the first node Q(n), the source of the fifth transistor T5 is electrically connected to the second clock signal terminal CKb, and the drain of the fifth transistor T5 is electrically connected to the drive signal output terminal WR(n).

[0093] like Figure 3 As shown, in some embodiments provided in this application, the pull-down unit 30 includes a sixth transistor T6. The gate of the sixth transistor T6 is electrically connected to the third-stage signal output terminal, the source of the sixth transistor T6 is electrically connected to the first reference signal terminal VGL, and the drain of the sixth transistor T6 is electrically connected to the first node Q(n).

[0094] like Figure 3As shown, in some embodiments provided in this application, the first pull-down sustaining unit 40 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The gate and source of the seventh transistor T7 are electrically connected to the first low-frequency clock signal terminal LC1, the drain of the seventh transistor T7 is electrically connected to the source of the eighth transistor T8, the gate of the eighth transistor T8 is electrically connected to the first node Q(n), the gate of the ninth transistor T9 is electrically connected to the drain of the seventh transistor T7, the source of the ninth transistor T9 is electrically connected to the first low-frequency clock signal terminal LC1, and the drain of the ninth transistor T9 is connected to the second node Q(n) of the nth-stage gate drive module 100. B1(n) is electrically connected. The gate of the tenth transistor T10 is electrically connected to the gate of the eighth transistor T8. The source of the tenth transistor T10 is electrically connected to the first reference signal terminal VGL. The drain of the tenth transistor T10 is electrically connected to the second node QB1(n). The gate of the eleventh transistor T11 is electrically connected to the second node QB1(n). The source of the eleventh transistor T11 is electrically connected to the first reference signal terminal VGL. The drain of the eleventh transistor T11 is electrically connected to the first node Q(n).

[0095] The seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 form an inverter, which, under the control of the first low-frequency clock signal, keeps the potential of the second node QB1(n) out of phase with the potential of the first node Q(n).

[0096] When the pull-up control unit 10 pulls up the potential of the first node Q(n), the first pull-down sustaining unit 40 pulls down the potential of the second node QB1(n) to the potential of the reference low-level signal. After the potential of the first node Q(n) is pulled down, the potential of the second node QB1(n) is periodically raised using the first low-frequency clock signal, so that the eleventh transistor T11 is in the conducting state under the control of the periodically raised potential of the second node QB1(n), maintaining the potential of the first node Q(n) at the potential of the reference low-level signal.

[0097] like Figure 3As shown, in some embodiments provided in this application, the second pull-down sustaining unit 50 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16. The gate and source of the twelfth transistor T12 are electrically connected to the second low-frequency clock signal terminal LC2. The drain of the twelfth transistor T12 is electrically connected to the source of the thirteenth transistor T13. The gate of the thirteenth transistor T13 is electrically connected to the first node Q(n). The gate of the fourteenth transistor T14 is electrically connected to the drain of the twelfth transistor T12. The source of the fourteenth transistor T14 is electrically connected to the second low-frequency clock signal terminal LC2. The drain of the fourteenth transistor T14 is connected to the nth stage gate drive module 100. The third node QB2(n) is electrically connected, the gate of the fifteenth transistor T15 is electrically connected to the gate of the thirteenth transistor T13, the source of the fifteenth transistor T15 is electrically connected to the first reference signal terminal VGL, the drain of the fifteenth transistor T15 is electrically connected to the third node QB2(n), the gate of the sixteenth transistor T16 is electrically connected to the third node QB2(n), the source of the sixteenth transistor T16 is electrically connected to the first reference signal terminal VGL, and the drain of the sixteenth transistor T16 is electrically connected to the first node Q(n).

[0098] When the pull-up control unit 10 pulls up the potential of the first node Q(n), the second pull-down sustaining unit 50 pulls down the potential of the third node QB2(n) to the potential of the reference low-level signal. After the potential of the first node Q(n) is pulled down, the potential of the third node QB2(n) is periodically raised using the second low-frequency clock signal, so that the eleventh transistor T11 is in the conducting state under the control of the periodically raised potential of the second node QB1(n), maintaining the potential of the first node Q(n) at the potential of the reference low-level signal.

[0099] In some embodiments provided in this application, such as Figure 6 As shown, the first pull-down sustaining unit 40 also includes a seventeenth transistor T17 and an eighteenth transistor T18.

[0100] The gate of the seventeenth transistor T17 is electrically connected to the second node QB1(n), the drain of the seventeenth transistor T17 is electrically connected to the second stage signal output terminal Cout(n), and the source of the seventeenth transistor T17 is electrically connected to the first reference signal terminal VGL.

[0101] When the seventeenth transistor T17 is in the conducting state according to the potential of the second node QB1(n), it outputs a reference low-level signal to the second stage signal output terminal Cout(n), pulls down the potential of the second stage signal output terminal Cout(n) and maintains the potential of the second stage signal output terminal Cout(n) at a low potential.

[0102] The gate of the eighteenth transistor T18 is electrically connected to the second node QB1(n), the source of the eighteenth transistor T18 is electrically connected to the first reference signal terminal VGL, and the drain of the eighteenth transistor T18 is electrically connected to the drive signal output terminal WR(n).

[0103] The second pull-down sustaining unit 50 also includes a nineteenth transistor T19 and a twentieth transistor T20. The gate of the nineteenth transistor T19 is electrically connected to the third node QB2(n), the source of the nineteenth transistor T19 is electrically connected to the first reference signal terminal VGL, and the drain of the nineteenth transistor T19 is electrically connected to the third node QB2(n). The gate of the twentieth transistor T20 is electrically connected to the third node QB2(n), the source of the twentieth transistor T20 is electrically connected to the first reference signal terminal VGL, and the drain of the twentieth transistor T20 is electrically connected to the drive signal output terminal WR(n).

[0104] like Figure 6 As shown, to improve the stability of the first-stage transmission signal in the pull-up control unit 10, the pull-up control unit 10 includes a first third transistor T3_1 and a second third transistor T3_2. The gate of the first third transistor T3_1, the gate of the second third transistor T3_2, and the source of the first third transistor T3_1 are all electrically connected to the first-stage transmission signal output terminal Cout(np). The drain of the first third transistor T3_1 is electrically connected to the source of the second third transistor T3_2, and the drain of the second third transistor T3_2 is electrically connected to the first node Q(n).

[0105] like Figure 6 As shown, in order to improve the conduction of the fourth transistor T4 and the fifth transistor T5 of the pull-up unit 20, the pull-up unit 20 also includes a first capacitor C1 and a second capacitor C2.

[0106] The first plate of the first capacitor C1 is electrically connected to the gate of the fourth transistor T4, and the second plate of the first capacitor C1 is electrically connected to the drain of the fourth transistor T4. The first plate of the second capacitor C2 is electrically connected to the gate of the fifth transistor T5, and the second plate of the second capacitor C2 is electrically connected to the drain of the fifth transistor T5.

[0107] When the fourth transistor T4 is turned on, the first capacitor C1 raises the potential at the gate of the fourth transistor T4 to a higher level, making the fourth transistor T4 more conductive. Similarly, when the fifth transistor T5 is turned on, the second capacitor C2 raises the potential at the gate of the fifth transistor T5 to a higher level, making the fifth transistor T5 more conductive.

[0108] like Figure 6As shown, to improve the stability of the pull-down unit 30 in transmitting the reference low-level signal, the pull-down unit 30 includes a first sixth transistor T6_1 and a second sixth transistor T6_2. The gates of the first sixth transistor T6_1 and the second sixth transistor T6_2 are both electrically connected to the first stage signal output terminal Cout(np). The source of the first sixth transistor T6_1 is electrically connected to the second reference signal terminal VGH. The drain of the first sixth transistor T6_1 is electrically connected to the source of the second sixth transistor T6_2. The drain of the second sixth transistor T6_2 is electrically connected to the first node Q(n).

[0109] like Figure 6 As shown, in some embodiments provided in this application, to ensure stability when the potential of the first node Q(n) is high, similarly, the first pull-down sustaining unit 40 includes two seventh transistors T7 (i.e., Figure 6 T7_1 and T7_2 in the middle) and two eleventh transistors T11 (i.e. Figure 6 Similarly, the second pull-down sustaining unit 50 includes two twelfth transistors T12 (i.e., T11_1 and T11_2 in the original text). Figure 6 T12_1 and T12_2 in the middle) and two sixteenth transistors T16 (i.e. Figure 6 (T16_1 and T16_2 in the text).

[0110] Furthermore, in some embodiments provided in this application, the first pull-down sustaining unit 40 further includes a twenty-second transistor T22. The gate of the twenty-second transistor T22 is electrically connected to the first stage signal output terminal Cout(np), the source of the twenty-second transistor T22 is electrically connected to the first reference signal terminal VGL, and the drain of the twenty-second transistor T22 is electrically connected to the second node QB1(n).

[0111] Furthermore, in some embodiments provided in this application, the second pull-down sustaining unit 50 further includes a twenty-third transistor T23. The gate of the twenty-third transistor T23 is electrically connected to the first stage signal output terminal Cout(np), the source of the twenty-third transistor T23 is electrically connected to the first reference signal terminal VGL, and the drain of the twenty-third transistor T23 is electrically connected to the third node QB2(n).

[0112] like Figure 6As shown, the nth-stage gate drive module 100 also includes a leakage protection unit 70. The leakage protection unit 70 is electrically connected to the first node Q(n), the second reference signal terminal VGH of the array substrate row drive circuit 1000, the first pull-down sustaining unit 40, the second pull-down sustaining unit 50, the pull-down unit 30, and the global reset unit 60. The leakage protection unit 70 is used to prevent leakage from the first pull-down sustaining unit 40, the second pull-down sustaining unit 50, the pull-down unit 30, and the global reset unit 60 under the control of the potential of the first node Q(n) and the reference high-level signal of the second reference signal terminal VGH.

[0113] The leakage protection unit 70 includes at least one twenty-first transistor T21. The gate of the twenty-first transistor T21 is electrically connected to the first node Q(n), the source of the twenty-first transistor T21 is electrically connected to the second reference signal terminal VGH, and the drain of the twenty-first transistor T21 is electrically connected to the nth holding signal terminal N(n).

[0114] Furthermore, the nth stage hold signal terminal N(n) is electrically connected to the drain of the first sixth transistor T6_1 and the source of the second sixth transistor T6_2. When the potential of the first node Q(n) is high, the leakage protection transistor T91 is in the on state, and the nth stage hold signal terminal N(n) outputs a reference high-level signal. At this time, the drain of the first sixth transistor T6_1 is electrically connected to the nth stage hold signal terminal N(n), thereby completely turning off the first sixth transistor T6_1, preventing leakage from the first node Q(n) through the pull-down unit 30, and thus reducing the leakage path of the first node Q(n).

[0115] Furthermore, the nth stage hold signal terminal N(n) is electrically connected to the drain of the first sixth transistor T6_1 and the source of the second sixth transistor T6_2. When the potential of the first node Q(n) is high, the twenty-first transistor T21 is in the on state, and the nth stage hold signal terminal N(n) outputs a reference high-level signal. At this time, the drain of the first sixth transistor T6_1 is electrically connected to the nth stage hold signal terminal N(n), thereby completely turning off the first sixth transistor T6_1, preventing leakage of the first node Q(n) through the pull-down unit 30, and thus reducing the leakage path of the first node Q(n).

[0116] In some embodiments provided in this application, to ensure the stability of the leakage protection unit 70, the leakage protection unit 70 includes two twenty-first transistors T21, namely a first twenty-first transistor T21_1 and a second twenty-first transistor T21_2. The gates of the first twenty-first transistor T21_1 and the second twenty-first transistor T21_2 are both electrically connected to the first node Q(n). The source of the second twenty-first transistor T21_2 is electrically connected to the second reference signal terminal VGH. The drain of the second twenty-first transistor T21_2 is electrically connected to the source of the first twenty-first transistor T21_1. The drain of the first twenty-first transistor T21_1 is electrically connected to the nth stage hold signal terminal N(n).

[0117] Furthermore, the nth stage hold signal terminal N(n) is electrically connected to the drain of the first eleventh transistor T11_1 and the source of the second eleventh transistor T11_2. When the potential of the first node Q(n) is high, the twenty-first transistor T21 is in the on state, and the nth stage hold signal terminal N(n) outputs a reference high-level signal. At this time, the drain of the first eleventh transistor T11_1 is electrically connected to the nth stage hold signal terminal N(n), thereby completely turning off the first eleventh transistor T11_1, preventing leakage of the first node Q(n) through the first pull-down holding unit 40, thus reducing the leakage path of the first node Q(n).

[0118] Similarly, the holding signal terminal N(n) of the nth stage is also electrically connected to the drain of the first sixteenth transistor T16_1 and the source of the second sixteenth transistor T16_2, so that the first sixteenth transistor T16_1 is completely turned off, avoiding leakage of the first node Q(n) through the second pull-down holding unit 50 and reducing the leakage path of the first node Q(n).

[0119] Furthermore, the nth stage hold signal terminal N(n) is electrically connected to the drain of the first transistor T1 and the source of the second transistor T2. When the potential of the first node Q(n) is high, the twenty-first transistor T21 is in the on state, and the nth stage hold signal terminal N(n) outputs a reference high-level signal. At this time, the drain of the first transistor T1 is electrically connected to the nth stage hold signal terminal N(n), thereby completely turning off the first transistor T1, preventing leakage of the first node Q(n) through the global reset unit 60, and thus reducing the leakage path of the first node Q(n).

[0120] Based on the fact that the leakage protection unit 70 is electrically connected to the first pull-down sustaining unit 40, the second pull-down sustaining unit 50, the pull-down unit 30 and the global reset unit 60 respectively, the leakage path of the first node Q(n) is reduced, which helps to ensure the waveform stability of the stage transmission signal of the nth stage gate drive module 100 and the waveform stability of the drive signal of the nth stage gate drive module 100.

[0121] It should be noted that in some embodiments provided in this application, such as Figure 6 As shown, the first reference signal terminal VGL includes a first reference low-level signal terminal VGL1, a second reference low-level signal terminal VGL2, and a third reference low-level signal terminal VGL3. The potential of the second reference low-level signal provided by the second reference low-level signal terminal VGL2 is higher than the potential of the first reference low-level signal provided by the first reference low-level signal terminal VGL1, thereby completely turning off the fifth transistor T5 to prevent leakage or erroneous output of scan signals. Similarly, the potential of the third reference low-level signal provided by the third reference low-level signal terminal VGL3 is higher than the potential of the first reference low-level signal provided by the first reference low-level signal terminal VGL1, thereby completely turning off the ninth transistor T9 and the fourteenth transistor T14. This prevents the ninth transistor T9 from erroneously outputting a first low-frequency clock signal and raising the potential of the second node QB1(n), and prevents the fourteenth transistor T14 from erroneously outputting a second low-frequency clock signal and raising the potential of the third node QB2(n).

[0122] Of course, this application may have other various embodiments. Without departing from the spirit and essential points of this application, those skilled in the art can make various corresponding changes and modifications based on this application, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A row driving circuit for an array substrate, characterized in that, The nth stage gate drive module includes cascaded multi-stage gate drive modules. A pull-up control unit is electrically connected to the first stage signal output terminal of the np-th stage gate driving module and the first node of the n-th stage gate driving module. The pull-up control unit is used to pull up the potential of the first node under the control of the first stage signal output terminal. A pull-up unit is electrically connected to the first clock signal terminal of the array substrate row driving circuit, the second clock signal terminal of the array substrate row driving circuit, the first node, the second-stage transmission signal output terminal of the nth-stage gate driving module, and the drive signal output terminal of the nth-stage gate driving module. The pull-up unit is used to output a second-stage transmission signal to the second-stage transmission signal output terminal and a drive signal to the drive signal output terminal under the control of the potential of the first node, the first clock signal of the first clock signal terminal, and the second clock signal of the second clock signal terminal. A pull-down unit is electrically connected to the third-level signal output terminal of the gate driving module of the (n+p)th stage, the first node, and the first reference signal terminal of the array substrate row driving circuit. The pull-down unit is used to pull down the potential of the first node under the control of the third-level signal output terminal and the reference low-level signal of the first reference signal terminal. The first pull-down sustaining unit is electrically connected to the first low-frequency clock signal terminal, the first node, and the first reference signal terminal of the array substrate row driving circuit. The first pull-down sustaining unit is used to maintain the potential of the first node at a low potential based on the reference low-level signal under the control of the first low-frequency clock signal of the first low-frequency clock signal terminal. The second pull-down sustaining unit is electrically connected to the second low-frequency clock signal terminal, the first node, and the first reference signal terminal of the array substrate row driving circuit. The second pull-down sustaining unit is used to maintain the potential of the first node at a low potential based on the reference low-level signal under the control of the second low-frequency clock signal of the second low-frequency clock signal terminal. A global reset unit is electrically connected to the first node, the first low-frequency clock signal terminal, the second low-frequency clock signal terminal, and the first reference signal terminal. The global reset unit is used to provide the reference low-level signal to the first node under the control of the first low-frequency clock signal and the second low-frequency clock signal. Wherein, the first node is the node of the line between the pull-up control unit and the pull-up unit, n is an integer greater than or equal to 1, p is an integer greater than or equal to 1, and p is less than n.

2. The array substrate row driving circuit according to claim 1, characterized in that, During the effective display phase of any frame display cycle, one of the first low-frequency clock signal and the second low-frequency clock signal is a low-level signal, and the other of the first low-frequency clock signal and the second low-frequency clock signal is a high-level signal. Furthermore, within the m-th frame display period and the m+1-th frame display period, at a first preset time point, one of the first low-frequency clock signal and the second low-frequency clock signal switches from the high-level signal to the low-level signal, and at a second preset time point, the other of the first low-frequency clock signal and the second low-frequency clock signal switches from the low-level signal to the high-level signal. Wherein, neither the first preset time point nor the second preset time point is earlier than the first end point of the effective display phase of the m-th frame display period, and neither the first preset time point nor the second preset time point is later than the second start point of the effective display phase of the (m+1)-th frame display period, where m is an integer greater than or equal to 1.

3. The array substrate row driving circuit according to claim 2, characterized in that, The global reset unit includes a first transistor and a second transistor; One of the gates of the first transistor and the second transistor is electrically connected to the first low-frequency clock signal terminal, and the other of the gates of the first transistor and the second transistor is electrically connected to the second low-frequency clock signal terminal. The source of the first transistor is electrically connected to the first reference signal terminal, the drain of the first transistor is electrically connected to the source of the second transistor, and the drain of the second transistor is electrically connected to the first node. Between the first preset time point and the second preset time point, one of the first transistor and the second transistor is turned on based on the first low-frequency clock signal, and the other of the first transistor and the second transistor is turned on based on the second low-frequency clock signal.

4. The array substrate row driving circuit according to claim 3, characterized in that, Both the first transistor and the second transistor are either N-type transistors or both are P-type transistors. Under the control of both the first low-frequency clock signal and the second low-frequency clock signal being first level signals, the first transistor and the second transistor provide the reference low-level signal to the first node.

5. The array substrate row driving circuit according to claim 4, characterized in that, At least from the first start time of the effective display phase of the m-th frame display cycle to the first preset time, one of the first low-frequency clock signal and the second low-frequency clock signal is the first level signal, and from the first preset time to at least the second end time of the effective display phase of the m+1-th frame display cycle, one of the first low-frequency clock signal and the second low-frequency clock signal is the second level signal. At least from the first start time point to the second preset time point, the other of the first low-frequency clock signal and the second low-frequency clock signal is the second level signal, and from the second preset time point to at least the second end time point, the other of the first low-frequency clock signal and the second low-frequency clock signal is the first level signal; Wherein, the first preset time point is later than the second preset time point, the first level signal is one of the low level signal and the high level signal, and the second level signal is the other of the low level signal and the high level signal.

6. The array substrate row driving circuit according to claim 5, characterized in that, The time difference between the first preset time point and the second preset time point is greater than or equal to the first preset time.

7. The array substrate row driving circuit according to claim 5 or 6, characterized in that, From the first preset time point to the third preset time point, one of the first low-frequency clock signal and the second low-frequency clock signal is the second level signal, and the third preset time point is not earlier than the second end point; From the second preset time point to the fourth preset time point, the other of the first low-frequency clock signal and the second low-frequency clock signal is the first level signal. The fourth preset time point is not later than the third start time point of the effective display stage of the m+2 frame display cycle, and the fourth preset time point is later than the third preset time point.

8. The array substrate row driving circuit according to claim 7, characterized in that, The time difference between the fourth preset time point and the third preset time point is the same as the time difference between the first preset time point and the second preset time point.

9. The array substrate row driving circuit according to claim 1, characterized in that, The pull-up control unit includes a third transistor, the gate and source of the third transistor are electrically connected to the first stage signal output terminal, and the drain of the third transistor is electrically connected to the first node. And / or, the pull-up unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is electrically connected to the first node, the source of the fourth transistor is electrically connected to the first clock signal terminal, the drain of the fourth transistor is electrically connected to the second stage signal output terminal, the gate of the fifth transistor is electrically connected to the first node, the source of the fifth transistor is electrically connected to the second clock signal terminal, and the drain of the fifth transistor is electrically connected to the drive signal output terminal; And / or, the pull-down unit includes a sixth transistor, the gate of the sixth transistor is electrically connected to the signal output terminal of the third stage, the source of the sixth transistor is electrically connected to the first reference signal terminal, and the drain of the sixth transistor is electrically connected to the first node. And / or, the first pull-down sustaining unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a seventeenth transistor, and an eighteenth transistor. The gate and source of the seventh transistor are electrically connected to the first low-frequency clock signal terminal. The drain of the seventh transistor is electrically connected to the source of the eighth transistor. The gate of the eighth transistor is electrically connected to the first node. The gate of the ninth transistor is electrically connected to the drain of the seventh transistor. The source of the ninth transistor is electrically connected to the first low-frequency clock signal terminal. The drain of the ninth transistor is electrically connected to the second node of the nth stage gate drive module. The gate of the tenth transistor is electrically connected to the gate of the eighth transistor. The source of the tenth transistor is electrically connected to the first reference signal terminal; the drain of the tenth transistor is electrically connected to the second node; the gate of the eleventh transistor is electrically connected to the second node; the source of the eleventh transistor is electrically connected to the first reference signal terminal; the drain of the eleventh transistor is electrically connected to the first node; the gate of the seventeenth transistor is electrically connected to the second node; the source of the seventeenth transistor is electrically connected to the first reference signal terminal; the drain of the seventeenth transistor is electrically connected to the second node; the gate of the eighteenth transistor is electrically connected to the second node; the source of the eighteenth transistor is electrically connected to the first reference signal terminal; and the drain of the eighteenth transistor is electrically connected to the drive signal output terminal. And / or, the second pull-down sustaining unit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a nineteenth transistor, and a twentieth transistor. The gate and source of the twelfth transistor are electrically connected to the second low-frequency clock signal terminal. The drain of the twelfth transistor is electrically connected to the source of the thirteenth transistor. The gate of the thirteenth transistor is electrically connected to the first node. The gate of the fourteenth transistor is electrically connected to the drain of the twelfth transistor. The source of the fourteenth transistor is electrically connected to the second low-frequency clock signal terminal. The drain of the fourteenth transistor is electrically connected to the third node of the nth stage gate drive module. The gate of the fifteenth transistor is electrically connected to the gate of the thirteenth transistor. The fifteenth transistor is electrically connected to the first reference signal terminal, and its drain is electrically connected to the third node. The sixteenth transistor is electrically connected to the gate of the third node, and its source is electrically connected to the first reference signal terminal. The nineteenth transistor is electrically connected to the gate of the third node, and its source is electrically connected to the first reference signal terminal. The drain of the nineteenth transistor is electrically connected to the third node. The twentieth transistor is electrically connected to the gate of the third node, and its source is electrically connected to the first reference signal terminal. The drain of the twentieth transistor is electrically connected to the drive signal output terminal.

10. The array substrate row driving circuit according to claim 1 or 9, characterized in that, The gate drive module of the nth stage further includes a leakage protection unit. The leakage protection unit is electrically connected to the first node, the second reference signal terminal of the array substrate row drive circuit, the first pull-down sustaining unit, the second pull-down sustaining unit, the pull-down unit, and the global reset unit. The leakage protection unit is used to prevent leakage of the first pull-down sustaining unit, the second pull-down sustaining unit, the pull-down unit, and the global reset unit under the control of the potential of the first node and the reference high-level signal of the second reference signal terminal.

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