Systems and methods for defect weighting with co-located modeled blemishes

Abstract

Systems and methods are disclosed for generating a defect criticality. Such systems and methods can include identifying a defect result including a defect and a defect location. Such systems and methods can include receiving a flaw test recipe configured to test potential flaws at a plurality of test locations. Such systems and methods can include identifying a plurality of N detection parameters based on a countable number of times the flaw test recipe is configured to test potential flaws. Such systems and methods can include determining a plurality of weighting parameters based on the plurality of N detection parameters. Such systems and methods can include generating the defect criticality of the defect based on a proximity between the plurality of test locations and the defect location and the plurality of weightings.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63 / 315,098, entitled “System for Statistical Detection of Semiconductor Reliability Failures Using the N-Detect Parameter from ATPG Test Patterns to Weight Co-Located Defectivity,” filed March 1, 2022, which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to die screening systems, and more particularly to weighting defects for the purpose of screening dies. BACKGROUND

[0004] Risk-averse users of semiconductor devices, such as automotive, military, aerospace, and medical applications, require failure rates in the parts-per-billion (PPB) range, which is far below typical failure rates. Identifying and screening out faulty devices is key to meeting these industry requirements.

[0005] During the process of manufacturing semiconductor devices, wafers go through hundreds of processing steps to pattern the devices. During these steps, inspection and metrology steps are performed to ensure that the process is within control limits and that the product of manufacture will be produced at the end of the manufacturing cycle. Inspection systems can find unexpected defects in the patterned structures of the devices, while metrology systems can measure physical parameters of the features of the devices (e.g., film thickness, pattern, overlay, etc.) relative to expected physical parameters. Systems based on electrical testing (e.g., electrical probes) can also be used to test for defects by testing the proper electrical functionality of the devices.

[0006] Test-based die screening techniques are typically based on flaw models. For example, when there is a defect, a flaw model can test the expected response of the circuit. Automatic test pattern generation (ATPG) software utilizes various flaw models to generate electrical test recipes (e.g., test patterns, inputs, and the like) that can test for the presence of potential flaws.

[0007] A "stuck-at" fault model is a particular fault model used by fault simulators and ATPG subsystems to model manufacturing defects within integrated circuits. Individual signals and pins are assumed to be stuck at logic "1", "0", and "X". For example, an input is tied to a logic 1 state during test generation to ensure that a particular test pattern can be applied to find manufacturing defects with that type of behavior. Likewise, an input can be tied to a logic 0 to model the behavior of a defective circuit that cannot toggle its output pin. However, not all faults must be analyzed using stuck-at fault models. Therefore, other fault models are typically used in addition to stuck-at fault models. A fault model can test a particular potential fault multiple times using various test patterns. However, testing each possible potential fault is typically costly because while some test patterns can test many faults at once, as the test coverage (i.e., the number of possible faults being tested) approaches 100%, the number of tests required increases exponentially. Furthermore, due to the logic layout, some faults can not be (e.g., determined to be) testable. ATPG software and operators typically find a balance that limits the number of tests to be performed to a reasonable number, where some potential faults are tested multiple times (e.g., 5, 10, 100 times) and other potential faults can be tested only once or not at all.

[0008] A challenge to increasing reliability is that a relatively large percentage of reliability failures of samples entering the supply chain are due to test escape defects. For example, one definition of a test escape defect is a defect that is detected (e.g., optically imaged) but the sample still passes all tests somehow (e.g., due to test coverage gaps) and the defect is incorrectly identified as harmless. As mentioned above, screening out these failures by increasing test coverage can become too expensive and impractical. It is therefore desirable to more accurately screen samples and address the above defects. SUMMARY

[0009] A screening system for generating a defect criticality of a defect according to one or more embodiments of the present disclosure is disclosed. In one illustrative embodiment, the screening system includes a controller communicatively coupled to one or more sample analysis subsystems. In another illustrative embodiment, the controller includes one or more processors and can include a memory. In another illustrative embodiment, the one or more processors are configured to execute a set of program instructions stored on the memory. In another illustrative embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to identify a defect result including a defect and a defect location of the defect. In another illustrative embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to receive flaw test recipes, where each flaw test recipe is configured to test one or more of a plurality of potential flaws at a plurality of test locations. In another illustrative embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to identify a plurality of N-detection parameters, where each N-detection parameter of the plurality of N-detection parameters is associated with a test location of a potential flaw of the plurality of potential flaws and is configured to test a countable number of times the potential flaw based on the flaw test recipe. In another illustrative embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to determine a plurality of weighting parameters based on the plurality of N-detection parameters, where the plurality of weighting parameters are associated with the plurality of test locations. In another illustrative embodiment, the one or more processors are configured to execute program instructions that cause the one or more processors to generate a defect criticality of the defect based on at least: a proximity between the plurality of test locations of the plurality of potential flaws and the defect location of the defect; and the plurality of weighting parameters associated with the plurality of test locations.

[0010] A method according to one or more embodiments of the present disclosure is disclosed. In one illustrative embodiment, the method can include, but is not limited to, identifying a defect result including a defect and a defect location of the defect. In another illustrative embodiment, the method can include receiving flaw test recipes, where each flaw test recipe is configured to test one or more of a plurality of potential flaws at a plurality of test locations. In another illustrative embodiment, the method can include identifying a plurality of N detection parameters, where each N detection parameter of the plurality of N detection parameters is associated with a test location of a potential flaw of the plurality of potential flaws and is configured to test a countable number of times the potential flaw based on the flaw test recipe. In another illustrative embodiment, the method can include determining a plurality of weighting parameters based on the plurality of N detection parameters, where the plurality of weighting parameters are associated with the plurality of test locations. In another illustrative embodiment, the method can include generating a defect criticality of the defect based on at least a proximity between the plurality of test locations of the plurality of potential flaws and the defect location of the defect and the plurality of weighting parameters associated with the plurality of test locations.

[0011] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the application as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the general description, serve to explain the principles of the application. BRIEF DESCRIPTION OF DRAWINGS

[0012] Many of the advantages of the present disclosure can be better understood by referring to the accompanying drawings.

[0013] Figure 1 A block diagram illustrating a screening system according to one or more embodiments of the present disclosure is described.

[0014] Figure 2A A conceptual diagram illustrating a layout including features and potential flaws according to one or more embodiments of the present disclosure is described.

[0015] Figure 2B A conceptual diagram illustrating a layout including features and potential flaws according to one or more embodiments of the present disclosure is described.

[0016] Figure 2C A conceptual diagram illustrating a layout including features and potential flaws according to one or more embodiments of the present disclosure is described.

[0017] Figure 3 A flow diagram depicting a method for generating a defect criticality of a defect according to one or more embodiments of the present disclosure is described.

[0018] Figure 4A diagram depicts a flowchart of a method for generating defect criticality of a defect via a screening system according to one or more embodiments of the present disclosure.

[0019] Figure 5 A diagram depicts a flowchart of a screening system according to one or more embodiments of the present disclosure.

[0020] Figure 6A A diagram depicts a graphical representation of a number of potential flaws for each N detection parameter value of a baseline ATPG fixed pattern test for a circuit according to one or more embodiments of the present disclosure.

[0021] Figure 6B A diagram depicts a graphical representation of a number of potential flaws for each N detection parameter value of a baseline ATPG fixed pattern test for different circuits according to one or more embodiments of the present disclosure.

[0022] Figure 7 A diagram depicts a graphical representation of a number of potential flaws for each N detection parameter value of a baseline ATPG fixed pattern test for different circuits according to one or more embodiments of the present disclosure.

[0023] Figure 8 A diagram depicts an exemplary FinFET transistor cell for cell-aware testing (CAT) flaw modeling according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings. The present disclosure has been particularly shown and described with respect to particular embodiments and specific features thereof. The embodiments set forth herein are considered to be illustrative and not restrictive. It will be readily apparent to one of ordinary skill in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the disclosure.

[0025] Embodiments of the present disclosure relate to generating defect criticality of a defect using N detection parameters. For example, embodiments of the present disclosure relate to determining a likelihood that a defect becomes a test escape defect (e.g., a fatal defect that passes some or all electrical testing in some manner) based on 1) a proximity of the defect to a test location of electrical testing and 2) a number of times the test location is tested.

[0026] It is contemplated herein that there can be a correlation between the N detection parameter (i.e., the countable number of tests performed for a particular flaw / location) and the defect criticality of nearby defects. It can be difficult to determine whether a defect will lead to a flaw using only non-test based inspection methods (e.g., imaging). If a defect does lead to a flaw, it tends to occur near the defect. For example, a defect between two features can lead to a shorting flaw between those features. The more times a flaw is tested and passes the test, the less likely it is that the particular flaw exists. Similarly, if many flaws are tested in a region many times, it is less likely that any flaws exist in the region at all. If no flaws exist in a region, and defects tend to lead to flaws near the defect, then it follows that defects in this region are less likely to be defect-causing (i.e., fatal) defects, given the same other conditions. Rather, defects near a region of relatively high testing are more likely to be nuisance defects. Conversely, defects near a region that is tested less and thus has a lower N detection parameter value are more difficult to judge as to whether they can be fatal defects. Therefore, defects in (or near) such lower testing regions are expected to be given closer attention and / or weighted more heavily by increasing the defect criticality associated with such defects.

[0027] This correlation between the N detection parameter and proximity of defects can be used to reduce overkill and underkill in the screening process, thereby improving customer satisfaction and reducing costs. Some embodiments can enhance existing defect weighting / screening techniques by further adding the N detection parameter as a consideration when weighting defects for die screening purposes. In one example, if there are many defects with high defect criticality on a die, this die can be screened out of the supply chain.

[0028] The N detection parameter weighting method applies to both fixed pattern and transition delay testing. These are efficient testing methods and are almost universally applied as the basis for any test plan. When extremely high coverage is required, advanced flaw models are sometimes placed on top of these methods. For the purposes of this disclosure, by noting that for these cases, the N detection parameter can equal 1, the N detection parameter method can be extended to advanced flaw models such as deterministic bridging and cell-aware, as they are inherently based on the concept of physically-aware flaw modeling.

[0029] There are many defect weighting methods. However, unlike embodiments of the present disclosure, other defect weighting methods do not seek to weight defectivity based on flaw level test parameters. Some defect weighting methods rely on weighting defects specifically according to defect attributes. For example, inspection subsystems can be used to image defects and generate parameters such as defect size, shape, background information, polarity, and many other attributes to be used to weight defects. Other defect weighting methods track X and Y direction coordinates of defects. Such defect locations can be accompanied, for example, by manually drawing relatively large bounding boxes around functional blocks of a device to help weight defects. One example is macro bounding boxes to exclude or reduce consideration of defects occurring in open areas of a device that do not contain critical circuitry. In such methods, defects occurring in these areas can be given low or zero weight values. In another example, macro bounding boxes are utilized to preferentially weight critical blocks of a circuit. Defects occurring in these areas can be given high weight values. In another example, macro bounding boxes are utilized to preferentially weight large functional blocks of a circuit that are exceptionally difficult to test. For example, defects occurring in analog sections of a circuit can be given higher weight values. Other defect weighting methods include contextual information related to defect locations (e.g., coordinates) based on design layout information associated with design rule edge proximity. These precise (e.g., sub-micron precision) areas of interest are typically used by advanced defect inspection systems (e.g., nanometers, pinpoints, and pixels). However, according to one or more embodiments of the present disclosure, these other defect weighting methods do not seek to weight defectivity based on flaw level test parameters.

[0030] For purposes of the present disclosure, the term "flaw" and the like generally encompasses modeled "potential" flaws that can or can not be present. Various flaws can be tested including, but not limited to, shorted flaws (e.g., shorts), open flaws, and stuck-type flaws. In some cases, flaws can be tested deterministically. However, due to various constraints (e.g., complexity of a circuit, test time / cost constraints, and the like), some flaws are only tested probabilistically such that a result of a test indicates a probability that a flaw is present. To increase a chance of detecting a flaw, many test patterns of various flaw models can each simultaneously probabilistically test many flaws such that at least some flaws are probabilistically tested multiple times.

[0031] For example, a shorted flaw at a particular location between two features of a sample can be tested any number of times (e.g., 1 time, 2 times, 3 times, 4 times, 5 times, 8 times, 15 times, 30 times, 50 times, 100 times, 300 times, or more) according to a set of flaw test recipes that includes many test patterns. For purposes of the present disclosure, unless otherwise noted, the countable number of times a potential flaw (and / or a test location associated with such flaw) is tested (or configured to be tested) using a set of flaw test recipes is an "N detection" parameter.

[0032] Defects that occur during the manufacturing process can have a wide range of impact on the performance of the field device. A killer defect is a defect that causes a flaw in the electrical functionality of the sample such that the sample is not suitable for entering the supply chain, while nuisance defects have little impact (i.e., suitable for entering the supply chain). For example, a "killer" defect that occurs in a known or unknown location within the design can result in immediate device failure. Killer defects in unknown locations can be particularly problematic, for example, because of their susceptibility to reliability escape in the test gap, where a semiconductor device can fail functionally after processing, but due to limitations in testing, the device manufacturer cannot make this determination. By way of another example, a class of defects known as latent reliability defects (LRDs) can not cause failure during manufacturing / testing or can not cause immediate device failure during operation, but can cause early failure of the device during operation when used in a working environment. It is noted herein that for the purposes of this disclosure, the terms "manufacturing process" and "manufacturing process" are considered equivalent along with corresponding variants of the term (e.g., "manufacturing line" and "fabrication line" and the like).

[0033] The correlation between N detection parameters and LRDs does not necessarily exist because, according to at least one definition, LRDs do not cause any test failures. Rather, LRDs cause flaws in the future. In this regard, increasing the number of area passes will not necessarily reduce the likelihood that nearby defects are not LRDs. Defect characterization techniques using characteristics such as defect size, shape, and the like can be more suitable for identifying LRDs without considering the N detection parameters of the level of flaw.

[0034] If a defect is misclassified as a nuisance defect, then the test-escaped die can enter the supply chain in a false negative case. Conversely, if a nuisance defect is misclassified as a killer defect and removed from the supply chain, then the manufacturing process causes unnecessary yield loss in a false positive case.

[0035] Generally, one or more of various techniques of screening systems can be used to screen samples with defects from the supply chain.

[0036] Because reliability is generally a statistical phenomenon and not deterministic, it is difficult to reliably characterize defects as "killer" or "non-killer" / nuisance. Rather, engineers can employ a statistical weighting system— the higher the weighting (e.g., defect criticality) assigned to a particular defect, the higher the probability that the defect causes a reliability failure.

[0037] Various reliability screening methods can be utilized, such as inline characterization methods (e.g., inline defect inspection methods) or test methods (e.g., electrical test methods). In general terms, inline characterization methods that produce defect results can be image-based, but test methods that produce test results are generally not image-based and can be test-based.

[0038] Inline defect screening techniques can be particularly useful for improving the reliability of samples. For example, inline parts average test (I-PAT) defect classifiers can be used to detect / characterize defects and determine bin attributes, as disclosed in U.S. Patent No. 10,761,128, entitled “Methods and Systems for Inline Parts Average Testing and Latent Reliability Defect Detection,” filed April 5, 2017, the entirety of which is hereby incorporated by reference.

[0039] In addition to imaging defects to screen out unreliable samples, there are various test-based methods, such as (but not limited to) testing devices (e.g., circuits, logic gates, etc.) for proper electrical functionality using electrical test probes, automated test equipment, and the like. In embodiments, testing can include (but is not limited to) post- package testing (e.g., unit probe testing, class probe testing), burn-in testing, testing performed after the manufacturing process (e.g., electrical wafer sort), and / or other quality checks (e.g., final testing).

[0040] Figure 1A block diagram of a screening system 100 in accordance with one or more embodiments of the present disclosure is illustrated. In embodiments, the screening system 100 includes one or more sample analysis subsystems 106. In embodiments, the one or more sample analysis subsystems 106 include one or more characterization subsystems 112 and one or more test subsystems 114. The characterization subsystems 112 can include, but are not limited to, an inspection subsystem 128 and / or a metrology subsystem 130. The test subsystems 114 can include, but are not limited to, an electrical test subsystem 132 and / or a stress test subsystem 134. In embodiments, the screening system 100 includes a controller 122 including one or more processors 124, memory 126 and a user interface 102. In embodiments, a defect test recipe 108 is received by the controller 122 and stored on the memory 126. The test subsystems 114 can be configured to generate test results based on the defect test recipe 108. In embodiments, one or more characterization subsystems 112 are used to generate defect results 110, which are stored on the memory 126 and include defects and defect locations. The one or more sample analysis subsystems 106 can further include a layout extraction subsystem 136 and / or an ATPG software module 138. For example, the defect test recipe 108 can be generated using the ATPG software module 138 and a layout map of the features of the sample 104 can be generated using the layout extraction subsystem 136.

[0041] The screening system 100 can be configured to screen a population of samples 104. In embodiments, the samples 104 can be a single die in a sample, several dies in a sample, several dies in a plurality of samples in a batch, or several dies in a plurality of samples in a plurality of batches.

[0042] For the purposes of the present disclosure, the term "defect" can refer to a physical defect, a metrology outlier, or other physical characteristic of a semiconductor device that is deemed abnormal, as discovered by an inline inspection subsystem. A defect can be considered any deviation of a manufactured layer or manufactured pattern in a layer from a design characteristic, including but not limited to physical, mechanical, chemical, or optical properties. Additionally, a defect can be considered any deviation in the alignment or bonding of components in a manufactured semiconductor die package. Furthermore, a defect can be of any size relative to a semiconductor die or feature thereon. In this way, a defect can be smaller than a semiconductor die (e.g., on the scale of one or more patterned features) or can be larger than a semiconductor die (e.g., as part of a wafer-scale scratch or pattern). For example, a defect can include a deviation in the thickness or composition of a sample layer before or after patterning. By way of another example, a defect can include a deviation in the size, shape, orientation, or location of a patterned feature. By way of another example, a defect can include a defect associated with a photolithography and / or etching step, such as but not limited to a bridge (or lack thereof) between adjacent structures, a pit, or a hole. By way of another example, a defect can include a damaged portion of the sample 104, such as but not limited to a scratch or a chip. For example, the severity of a defect (e.g., the length of a scratch, the depth of a pit, the measured magnitude or polarity of a defect, or the like) can be important and considered to weight the defect. By way of another example, a defect can include a foreign particle introduced to the sample 104. By way of another example, a defect can be a misaligned and / or misbonded packaged component on the sample 104. Thus, it should be appreciated that examples of defects in the present disclosure are provided for illustrative purposes only and should not be construed as limiting.

[0043] The inspection subsystem 128 of the screening system 100 can include any inspection subsystem known in the art. For example, the inspection subsystem 128 can include an optical inspection subsystem configured to detect defects based on interrogating the sample 104 with light from any source, such as but not limited to a laser source, a lamp source, an x-ray source, or a broadband plasma source. By way of another example, the inspection subsystem 128 can include a particle beam inspection subsystem configured to detect defects based on interrogating the sample with one or more particle beams, such as but not limited to an electron beam, an ion beam, or a neutral particle beam. For example, the inspection subsystem 128 can include a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For the purposes of the present disclosure, the inspection subsystem 128 can be a single inspection subsystem or can represent a group of inspection subsystems.

[0044] Metrology sub-system 130 can include any metrology sub-system known in the art. In embodiments, metrology sub-system 130 is configured to characterize properties such as, but not limited to, layer thickness, layer composition, critical dimension (CD), overlay, or lithography process parameters (e.g., intensity or dose of illumination during a lithography step). In this regard, metrology sub-system 130 can provide information about sample 104, one or more layers of sample 104, or manufacturing of one or more semiconductor dies of sample 104 that can be related to a probability of manufacturing defects that can lead to reliability issues of the resulting manufactured devices. For purposes of the present disclosure, metrology sub-system 130 can be a single metrology sub-system 130 or can represent a group of metrology sub-systems 130.

[0045] Figure 2A A conceptual diagram of layout map 206 of sample 104 including defects 208, potential flaws 210, and features 224a, 224b according to one or more embodiments of the present disclosure is illustrated. In embodiments, test locations 202 can be associated with each potential flaw 210. In embodiments, test locations 202 include test location regions 212 and boundaries 214. Figure 2B and 2C An additional conceptual diagram of layout map 206 of sample 104 including defects 208, potential flaws 210, and features 224a, 224b according to one or more embodiments of the present disclosure is illustrated.

[0046] Although Figures 2A to 2C depicting a particular set of attributes, number, type, location, shape, configuration, arrangement, and the like, of defects 208, test locations 202, and flaws 210 of layout map 206, it should be noted that, Figures 2A to 2C are provided for illustrative purposes only and should not be construed as limiting the scope of the present disclosure. For example, in embodiments, test locations 202 do not necessarily include regions or boundaries 214 and can be point-based locations of flaws 210, such as 2-dimensional coordinates of a single point (e.g., a center point of potential flaw 210). In another example, boundaries 214 can be any shape such as circular, irregular, or the like. In another example, layout map 206 can be 3-dimensional across multiple layers of sample 104 and, for example, boundaries 214 and defects 208 can be 3-dimensional.

[0047] A challenge in screening sample 104 is identifying which defects 208 are fatal defects that lead to flaws 210. In embodiments, defects 208 are weighted with a defect criticality-based proximity test parameter rather than, for example, an associated defect criticality metric of a total number of tests performed for an entire die. For example, defect criticality can be based on a test parameter such as N detection parameter associated with a proximity test location 202. For example, proximity 220 between defect 208 and test location 202 can be based on a distance between defect 208 and test location 202 (asFigure 2C The defect criticality of the defect 208 is generated based on the defect result 110 and the N detection parameters associated with the test site 202 (as shown in FIG. 1).

[0048] Figure 3 A flowchart depicting a method 300 for generating a defect criticality of a defect 208 in accordance with one or more embodiments of the present disclosure is illustrated.

[0049] In step 302, a defect result 110 is identified (e.g., determined, received, acquired, generated, and the like). The defect can be identified using any characterization system known in the art. For example, the controller 122 can identify a defect result 110 for a population of dies 104 based on online characterization subsystem data received from an online characterization subsystem 112 of one or more sample analysis subsystems 106 of the screening system 100. For example, the defect result 110 can include a defect 208 and a defect location.

[0050] In step 304, a flaw test recipe 108 is received. For example, the flaw test recipe 108 can be received from an external source and stored on the memory 126, generated on an ATPG software module 138 of a subsystem and stored on the memory 126, and the like. For example, the flaw test recipe 108 can be generated based on various flaw models from Figure 1 The flaw test recipe 108 is generated and received from the ATPG software module 138 of the screening system 100.

[0051] In embodiments, each flaw test recipe 108 is a test pattern configured to test one or more of a plurality of potential flaws 210 at a plurality of test sites 202. For example, the flaw test recipe 108 can be a set (i.e., a plurality) of flaw test recipes 108 of a single test program specifically generated for a particular type of sample 104.

[0052] In embodiments, the flaw test recipe 108 is based on at least one of the following types of flaw models: a stuck-at flaw model, a transition delay flaw model, a cell-aware flaw model, a deterministic bridge flaw model, and / or any other flaw model for which N detection parameter values can be applied.

[0053] In step 306, a plurality of N detection parameters are identified. The N detection parameters can be identified (e.g., generated, received, and the like) using any method disclosed herein or known in the art.

[0054] For example, the ATPG software module 138 can certainly be configured to output N detection parameters that generate the flaw test recipe 108. In this regard, the identification can simply receive the flaw test recipe 108 that includes such N detection parameters. However, the identification of N detection parameters is not limited to such examples and in some examples, some N detection parameters can need to be determined / calculated / generated. In embodiments, the N detection parameters can be determined in embodiments based on the design data of the sample 104 and the received flaw test recipe 108. For example, the flaw test recipe 108 can indicate which features or which types of flaws are tested by which flaw test recipe 108. In this regard, the processor 124 can be used to count the number of times each flaw 210, test location 202, feature, or the like is tested and store this data in a table on the memory 126. For example, the final count of the number of times a particular flaw 210 is tested can be "identified" as a particular N detection parameter of the plurality of N detection parameters.

[0055] In embodiments, the description of a particular term or element is non-limiting and can generally apply to other terms and elements associated with the described term or element. In this regard, elements and terms can be associated with each other such that a reference to one element and term can also represent a reference to another element and term. For example, a flaw 210 can be associated with two features 224a, 224b, N detection parameters, weighting parameters, test locations 202, test location areas 212, boundaries 214, and the like. Furthermore, each associated element can be cross-associated with every other associated element. For the purposes of this disclosure, the terms "associated" and the like mean related, based on, paired, and / or the like. For example, each flaw 210 can be "paired" with a respective test location 202. For all embodiments and concepts of this disclosure, multiple associations and cross-associations of these terms and elements can be difficult to describe concisely. Therefore, although the language of this disclosure can describe methods, steps, concepts, systems, and the like in relation to a limited subset of such associated terms, such descriptions are for illustrative purposes and should not be construed as limiting to this disclosure. For example, a description relating to a flaw 210 such as "based on," "adjacent to," and the like can additionally apply to a test location 202, a boundary 214, or another element associated with this flaw 210. In this regard, elements and terms can be associated with each other such that a reference to one element and term can represent a reference to another element and term, generally and specifically. In another example, the phrase "flaw's N detection parameter" can represent "test location's N detection parameter."

[0056] In embodiments, multiple flaws 210 can be associated with the same test location 202. For example, an open circuit flaw and a closed circuit flaw can be so close as to be considered in the same area and this area can be determined to be a single "test location" and assigned an N detection parameter. This N detection parameter can be the sum of the N detection parameters of all flaws 210 associated with this test location 202.

[0057] In step 308, a plurality of weightings are determined based on the plurality of N detection parameters. In embodiments, a weighting parameter can be associated with a test location 202 and used to generate a defect criticality of nearby defects 208. In embodiments, the controller 122 of the screening system 100 uses the processor 124 to determine the weighting parameters and store the weighting parameters on the memory 126.

[0058] Various methods can be utilized to determine the weighting parameters, such as, but not limited to, methodologies utilizing a binning approach, algorithmic equations, machine learning models, and any other methodologies known in the art suitable for using N detection parameters.

[0059] For example, determining and assigning such weighting parameters can include binning the flaws 210 by their respective N detection parameters and then assigning a weighting parameter (e.g., a weight value) to each flaw 210 in the bin. For example, one schema is assigning test locations 202 and / or flaws 210 with an N detection parameter of 1 or less to a first bin, assigning test locations 202 and / or flaws 210 with an N detection parameter of 2 to 5 to a second bin, assigning test locations 202 and / or flaws 210 with an N detection parameter of 6 to 10 to a third bin, and assigning test locations 202 and / or flaws 210 with an N detection parameter of 11 or more to a fourth bin. Then, for example, each test location 202 in the first bin can be assigned a first weighting parameter, each test location 202 in the second bin can be assigned a second weighting parameter, etc. In this regard, the weighting parameters can be efficiently co-assigned to each bin and associated with their respective bin.

[0060] In another instance, an algorithmic equation approach can be used to determine the weighting parameters. Non-limiting examples of weighting parameter equations include weighting parameters equal to 1 / (N detection parameter), 1-(N detection parameter), and / or similar. For at least these instances, a lower N detection parameter results in a higher weighting parameter. In this regard, the determination of multiple weighting parameters in step 308 can be based on an inverse relational pattern, such that a weighting parameter associated with a relatively lower N detection parameter is determined to be relatively high. In an embodiment, due to the configuration of the screening system 100 (e.g., the stored algorithm), a higher weighting parameter results in a higher defect criticality for nearby defects, which can indicate the greater importance and / or greater probability of becoming a test escape defect. In this regard, a low N detection parameter (e.g., 1, corresponding to being tested only once) can (for example) result in nearby defects being weighted more heavily.

[0061] In another instance, weighting parameters can be determined via a machine learning model module (not shown). For example, in a method using one or more cells of test location 202, the machine learning model can be configured to determine the cells. In another instance, the machine learning model can be configured to optimize the weighting parameters associated with the cells. For example, this step can be performed during the device conformity verification phase when a larger number of tests are typically performed in conjunction with aging tests and other activities that produce accelerated failure test results 118. In some cases, a dedicated test device sample can be used to determine which weighting parameter values ​​should be associated with which cells of a particular type of sample and then fine-tuned for product samples. For example, the test device sample could be a sample rigorously tested for defects, allowing for a better understanding and statistical modeling of the correlation between the N-detection parameter of defect 210 and nearby defects 208. Such a statistical model can be used to determine the appropriate weighting parameters associated with the N-detection parameter. As an illustrative example that is not necessarily an accurate description of the correlation, it can be shown that all N-detection parameter values ​​exceeding 100 have decreasing returns in predicting the criticality of defects and therefore should be equally segmented and weighted.

[0062] In step 310, the defect criticality of defect 208 is generated based on at least each of the following: proximity 220 between a plurality of test locations 202 and the defect location of defect 208; and a plurality of weighted parameters. In embodiments, any system can generate the defect criticality. For example, the controller 122 of screening system 100 may use processor 124 to generate defect criticality 232 and store the defect criticality in memory 126.

[0063] In this embodiment, any method can be used to determine proximity 220. (Return to Reference) Figure 2C In an embodiment, proximity 220 is typically a measure of the distance between two elements, but is not necessarily equal to that distance.

[0064] For example, proximity 220 can be, but is not limited to, a binary determination of whether defect 208 is close enough to flaw 210. For example, if this binary determination is negative (i.e., defect 208 is far from flaw 210), then controller 122 can be configured to ignore the N detection parameters. In another example, proximity 220 is a value indicative of a distance (e.g., 10 microns). In another example, generating a defect criticality can be based on intersection 216 of proximity boundary 222 and boundary 214.

[0065] In other examples, proximity 220 can be based on a threshold, such that in determining weighting parameters 230, boundaries 214 that result in an intersection 216 with proximity boundary 222 of defect 208 can be considered, and boundaries 214 associated with N detection parameters outside of this proximity boundary 222 are not considered in this determination. For example, as shown in Figure 2C In an embodiment, proximity boundary 222 can be determined by radius 218 (e.g., which can be referred to as an "overlay radius") or any other geometric rule. For example, proximity boundary 222 can be determined by a user. For example, proximity boundary 222 can be selected by a user as appropriate for point-based defect 208. In an embodiment, a case study can be performed or analyzed to determine how far defect 208 can be and still result in flaw 210, and this distance can be used to determine proximity boundary 222. In an embodiment, proximity boundary 222 and / or radius 218 is large enough to allow for error margin considerations of inaccuracies in a measurement subsystem (e.g., inspection subsystem), but small enough that the statistical probability of false positives (e.g., defect 208 being falsely weighted based on a distant, unrelated flaw 210) is low.

[0066] In an embodiment, boundaries 214 of test location 202 can be determined via various methodologies. In an embodiment, as shown in Figure 2A In an embodiment, test location region 212 and boundaries 214 for an electrical short flaw 210 are based on, for example, net pair combinations of features 224a, 224b. For example, test location region 212 can be defined by a geometric proximity rule for structure testing based on fixed and / or transit delay flaw models that features 224a, 224b are each potential neighboring net pair combination. For example, a short is a proximity rule can be configured to define test location region 212 as the region between two nearest edges of two nearby features 224a, 224b, with additional margin to expand this region. In this regard, such flaw models can model a short between features 224a, 224b.

[0067] In embodiments, the test location area 212 and the boundary 214 of a defect 210 that is an electrical open-circuit flaw (not shown) is based on a single feature, contact, via, or interconnect. For example, the open-circuit flaw can be defined using geometric rules for electrical open-circuit flaws of fixed and transit delay flaw models based on the perimeter of a single feature, contact, via, or interconnect (e.g., the perimeter with or without additional margin).

[0068] Figure 4 A flowchart depicting a method 400 for generating defect criticality of defects 208 according to one or more embodiments of the present disclosure is illustrated.

[0069] In a defect detection step 402, defects can be detected according to one or more embodiments. For example, referring back to Figure 3 , the defect detection step 402 can include the step 302, or vice versa. In embodiments, data from the step 402 is summarized before and / or after the defect-based classification step 410. In embodiments, 100% of the dies are screened in the defect detection step 402.

[0070] In embodiments, the data 110a from the defect detection step 402 can be raw sensor data and / or at least partially processed / summarized data indicative of the number of defects detected, classified, characterized, and / or the like. This raw and / or processed data 110a can be used in an optional defect-based classification step 410 to generate defect results 110b. For example, the defect-based classification step 410 can be used to generate defect results 110b via a defect classifier such as an I-PAT defect classifier. Such defect results 110b can be defect results 110.

[0071] In embodiments, the defect detection step 402 occurs during, before, or after a plurality of layer operations 404 (e.g., lithography, etching, alignment, bonding, or the like) of a critical manufacturing step of the sample 104. In this regard, the defect detection step 402 at various stages of the manufacturing process can be referred to as in-line defect detection.

[0072] The defect detection step 402 can be performed using any system known in the art such as the characterization sub-system 112. For example, the sample 104 can be screened using the in-line defect inspection sub-system 128 and the metrology sub-system 130. Note that the metrology sub-system 130 can not necessarily be used to directly image the defects, but data from it (e.g., film thickness, etc.) can be used in the defect detection step 402 to improve the accuracy of defect detection and characterization.

[0073] In embodiments, the defect results 110 can be passed to a layout library 412, as by Figure 4the layout library 412. In embodiments, the layout library 412 receives, stores, and / or aggregates the defect results 110b and can include other data. For example, the layout library 412 can store layout maps (e.g., the layout map 206 of Figure 2A In some examples, the layout map 206 is a table of values stored on the memory 126. In embodiments, the layout library 412 can be referred to as a "die layout N detection map library."

[0074] In embodiments, the layout library data 416 (e.g., the layout map 206 with the defect results 110b) can be received by the layout analyzer 414. In embodiments, the layout analyzer 414 is a module. In embodiments, the layout analyzer 414 can perform one or more analyses and / or operations related to the layout map 206 or any other data received. For example, the layout analyzer 414 can bin the blemishes 210 and / or associated test locations 202 into one or more bins based on respective N detection parameter values and then apply respective weighting parameters to each bin.

[0075] In embodiments, the layout analyzer 414 can analyze the layout library data 416 to determine Figure 2A various elements of the layout map 206. For example, the layout analyzer 414 can be configured to determine the boundaries 214, the proximity boundaries 222, and the like. In some examples, the layout analyzer 414 can be configured to determine the proximity 220 of the defect 208 based on the layout map 206.

[0076] In embodiments, the defect results 110b modified by the layout analyzer 414 can be passed back from the layout library 412 to the defect-based classification step 410. For example, for purposes of determining the weighting parameters, the layout library 412 and the layout analyzer 414 can be used to determine the proximity 220 between the defect 208 and the blemish 210 using the layout map 206. For example, returning reference to Figure 3 The proximity used in the determination step 310 and / or the plurality of weighting parameters of the determination step 308 can be performed using the layout analyzer 414. The defect results 110b passed back to the defect-based classification step 410 can be modified to include such weighting parameters and / or proximity 220.

[0077] In embodiments, the defect-based classification step 410 can include generating a defect criticality. For example, returning reference to Figure 3 The defect criticality of the generation step 310 can be performed at the defect-based classification step 410. For example, the defect results 110b can be modified at the defect-based classification step 410 to generate modified defect results 110c. For example, the modified defect results 110c can include at least one defect criticality and can be passed to the statistical outlier detection subsystem 418.

[0078] In an embodiment, defect results 110 (e.g., defect results 110a, 110b, and / or 110c) can be based on a statistical outlier analysis, such as G-PAT, P-PAT, Z-PAT, or the like.

[0079] In test and test-based classification step 408, testing and classification can be performed according to one or more embodiments. Step 408 can be performed by any test-based tool known in the art. For example, test and test-based classification step 408 can include binning dies based on electrical test results using electrical test subsystem 132, resulting in test results 118.

[0080] In an embodiment, screening system 100 includes a statistical outlier detection subsystem 418. In an embodiment, test subsystem 114 can output test results 118 to statistical outlier detection subsystem 418 and, for example, defect classifier can output defect results 116c to statistical outlier detection subsystem 418.

[0081] Statistical outlier detection subsystem 418 can perform any analysis on any portion of received results. For example, statistical outlier detection subsystem 418 can determine or generate output data 420 based on defect results 110c and test results 118. Output data 420 can be configured to be transmitted to any location, such as to a system for handling and discarding dies or to a user interface 102 for process monitoring. In one example, this output data 420 can be a sample weighting (e.g., die weighting or die defect rate) that indicates the reliability of one or more samples 104 based at least on the criticality of defects of the samples 104. For example, output data 420 can be outlier data. For example, statistical outlier detection subsystem 418 can include and / or be configured to perform a Z-PAT methodology. By way of another example, statistical outlier detection subsystem 418 can include and / or be configured to perform other PAT methodologies or other known statistical outlier determination techniques.

[0082] Figure 5 A flowchart illustrating screening system 100 according to one or more embodiments of the present disclosure is described. Referring back to Figures 1 to 4 For one or more embodiments of the present disclosure, Figure 5 may be used to conceptually illustrate how some terms can be related to or based on other terms.

[0083] For example, as Figure 5 illustrated in FIG. 3 and referring back to Figure 3 criticality of defects of step 310, defect criticality 232 can be based on proximity 220 and weighting parameter 230. Additionally, weighting parameter 230 can be based on N detection parameter 204.

[0084] Note that embodiments herein can be used to enhance existing defect criticality generation techniques, such as defect classification techniques and / or defect screening techniques. For example, defect criticality 232 can be generated based on other factors besides weighting parameters 230 and proximity 220. For example, as shown in FIG. 2, defect criticality 232 can be further based on defect characteristics 228, such as (but not limited to) defect size, shape, location, critical dimension, and the like. For example, an I-PAT defect classifier system can use weighting parameters 230 as well as defect characteristics 228 to generate defect criticality 232 for one or more defects 208. Figure 5

[0085] In embodiments, a defect classifier can be an element of characterization subsystem 112 or separate from characterization subsystem 112. For example, a defect classifier can be located on the same or different controller as characterization subsystem 112. A defect classifier can generally (but not limited to) be configured to provide various “defect-based” results 110 based on characterization subsystem data. For example, results corresponding to (but not limited to) methods of detection, re-detection, characterization, and / or classification of defects can be determined using inspection subsystem 128. Further, results of such methods can themselves be further used (e.g., in defect-based classification step 410; using a defect classifier; and the like) to perform additional analysis. For example, such results can be used to further analyze one or more die / wafer reliability. For example, such results can be used to bin dies as acceptable or discardable, and such binning results themselves can be included as part of defect results 110. For example, an I-PAT defect classifier can be used to detect / characterize defects and determine binning attributes, as disclosed in U.S. Patent No. 10,761,128, filed April 5, 2017, entitled “Methods and Systems for Inline Parts Average Testing and Latent Reliability Defect Detection,” the entirety of which is hereby incorporated by reference. Note that the above examples are for illustrative purposes only, and any defect detection method and system can be used to achieve any defect-based results 110.

[0086] In embodiments, layout map 206 can (but need not) be based on sample design data 234. For example, layout extraction subsystem 136 of FIG. 1 can use sample design data 234 to generate layout map 206. Figure 1

[0087] ​​Sample design data 234 can generally be any data indicative of the design, layout, or location of features, devices, layers, and the like of sample 104. For example, sample design data 234 can assist in locating other unknown test locations 202 to, for example, generate layout map 206. For example, a defect test recipe 108 can reference a component (e.g., transistor, other device, feature, and the like) associated with a defect 210, but not necessarily the test location 202 of the defect 210. Sample design data 234 can list the same components and their physical locations on the sample in a cross-referable manner. For example, in an embodiment, screening system 100 interfaces with layout extraction subsystem 136 (e.g., but not limited to, Calibre xRC) and ATPG software module 138 to cross-reference each respective defect (and associated N detection parameters 204) with a test location 202. In this regard, a test location 202 (e.g., X and Y coordinates of test location 202) can be determined and associated with its respective defect 210 and N detection parameters 204.

[0088] In an embodiment, sample design data 234 is used to generate defect test recipe 108. For example, ATPG software module 138 can be used to generate defect test recipe 108 based on sample design data 234 and one or more defect models (e.g., fixed pattern defect models or any other defect models used by ATPG software in the industry).

[0089] In an embodiment, a die defect rate (e.g., output data 420 of Figure 4 is determined based at least in part on a plurality of defect criticalities including defect criticality 232, where the plurality of defect criticalities are associated with a plurality of layers of the die. For example, a plurality of weighted parameters 230 of a plurality of defects 208 at a plurality of defect locations 226 can be combined to determine an overall die defect rate of the die. The die defect rate can be used to determine whether the die should be removed from the supply chain and discarded.

[0090] In an embodiment, one or more statistical outliers of a plurality of wafers are identified based at least in part on a weighted defect rate (i.e., die defect rate) of a die, where the plurality of wafers include the die. In an embodiment, a portion of the one or more statistical outliers of the plurality of wafers are selectively de-qualified from entering the supply chain of downstream manufacturing processes based on a selected risk tolerance level.

[0091] For the purposes of this disclosure, a "module" can represent, without limitation, program instructions or a subset of program instructions configured to cause one or more processors or other specialized hardware / circuitry to execute a software application.

[0092] In embodiments, the samples 104 can be screened by any technique, in any order (sequentially and / or in parallel), individually, in batches, one or more times, and the like. For example, initially, a plurality of key manufacturing steps at a plurality of layers of a population of samples 104 can be screened online by the characterization subsystem 112, such as by Figure 4 Material flow 406a shows. Then, for example, at or near the end of the manufacturing process, a population of samples 104 can be screened by the test subsystem 114 to perform one or more electrical tests, such as by Figure 4 Material flow 406b shows.

[0093] In a selection step, specified regions (e.g., "regions of interest") can be identified based on the N detection parameter 204. For example, the specified regions can be regions of the integrated circuit having low N detection parameter 204 values. In embodiments, such specified regions can be configured to receive defect inspection (e.g., high sensitivity inspection, such as SEM subsystem inspection). In other examples, defects outside of these specified regions can be ignored or weighted less.

[0094] Figure 6A and 6B illustrates the variation in the N detection parameter distribution for two circuits using a given flaw model. In some circuit design and flaw modeling methodologies, the number of flaws with an N detection parameter value of 1 ranges from 1% to 15% of the total population.

[0095] Figure 6A illustrates a graphical representation 602 of the number of potential flaws for each N detection parameter value of a baseline ATPG fixed pattern for circuit A according to one or more embodiments of the disclosure. For example, the N detection parameter value of each flaw can be determined and then, for each N detection parameter value, the number of flaws having this value can be plotted to produce the graphical representation 602. For example, based on the graphical representation 602, there are approximately 10 or so flaws with an N detection parameter value of 122. For example, a flaw test recipe for circuit A can include over 130 or so flaw test recipes, where each flaw test recipe tests one or more flaws. In this regard, in embodiments, the same flaw test recipe can be common to more than one flaw, such that a single flaw test recipe can increase the N parameter value of more than one flaw.

[0096] Figure 6B illustrates a graphical representation 606 of the number of potential flaws for each N detection parameter value of a baseline ATPG fixed pattern for a different circuit B according to one or more embodiments of the disclosure.

[0097] Figure 7Illustrated top views illustrating various analog test escape defects 700a, 700b, 700c, and 700d. For example, a test escape defect 700 can be an open defect that passed all testing in some manner, but is a fatal defect.

[0098] Figure 8 An exemplary FinFET transistor cell 802 is illustrated for cell-aware flaw modeling (e.g., cell-aware test (CAT) flaw modeling). In embodiments, a cell-aware boundary can be based on a cell associated with a cell-aware flaw. In generating a flaw test recipe 108 for a cell-aware flaw model of a transistor, the ATPG software module 138 can typically do so based on a defined "cell." For example, a boundary 214 of a flaw 210 can be defined as the boundary of the cell associated with this flaw 210. For example, in Figure 8 In embodiments, the boundary can be a footprint / area occupied by the FinFET transistor cell 802. Further, exemplary defects (not shown) can include "scrap" beyond one of the features of the transistor or lack of the feature. Cell-aware flaw models typically target leakage defects in the FinFET that force the transistor to be partially or fully on and drive strength defects that force the transistor to be partially or fully off.

[0099] Referring again to Figure 1 In embodiments, the one or more processors 124 of the controller 122 can be communicatively coupled to the memory 126, where the one or more processors 124 can be configured to execute a set of program instructions maintained in the memory 126, and the set of program instructions can be configured to cause the one or more processors 124 to perform various functions and steps of the present disclosure.

[0100] In embodiments, the display of the user interface 102 can be configured to display data of the screening system 100 to a user.

[0101] It is noted herein that one or more components of the screening system 100 can be communicatively coupled to various other components of the screening system 100 in any manner known in the art. For example, the one or more processors 124 can be communicatively coupled to each other and to other components via wired (e.g., copper wires, fiber optic cables, and the like) or wireless connections (e.g., RF coupling, IR coupling, WiMax, Bluetooth, 3G, 4G, 4G LTE, 5G, and the like). By way of another example, the controller 122 can be communicatively coupled to one or more components of the screening system 100 via any wired or wireless connection known in the art.

[0102] In one embodiment, the one or more processors 124 can include any one or more processing elements known in the art. In this sense, the one or more processors 124 can include any microprocessor-type device configured to execute software algorithms and / or instructions. In one embodiment, the one or more processors 124 can be comprised of each of a desktop computer, a mainframe computer system, a workstation, a video computer, a parallel processor, or other computer system (e.g., network computer) configured to execute a program configured to operate the screening system 100 as described throughout the present disclosure. It should be recognized that the steps described throughout the present disclosure can be carried out by a single computer system or, alternatively, multiple computer systems. Further, it should be recognized that the steps described throughout the present disclosure can be carried out on any one or more of the one or more processors 124. Generally, the term "processor" can be broadly defined to encompass any device having one or more processing elements that execute program instructions from memory 126. Further, different subsystems of the screening system 100 (e.g., the characterization subsystem 112, the testing subsystem 114, the controller 122, the user interface 102, and the like) can include processors or logic elements suitable for carrying out at least a portion of the steps described throughout the present disclosure. Thus, the above description should not be interpreted as a limitation on the present disclosure but merely an illustration.

[0103] The memory 126 can include any storage media suitable for storing program instructions executable by the associated one or more processors 124 and data received from the screening system 100. For example, the memory 126 can include non-transitory memory media. For example, the memory 126 can include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical memory devices (e.g., magnetic disk), magnetic tape, solid state drives, and the like. It should be further noted that the memory 126 can be housed in a common controller housing with the one or more processors 124. In alternative embodiments, the memory 126 can be remotely located relative to the physical location of the processors 124, the controller 122, and the like. In another embodiment, the memory 126 maintains program instructions for causing the one or more processors 124 to carry out the various steps described by the present disclosure.

[0104] In one embodiment, the user interface 102 is communicatively coupled to the controller 122. The user interface 102 can include, but is not limited to, one or more desktop computers, tablet computers, smart phones, smart watches, or the like. In another embodiment, the user interface 102 includes a display for displaying data of the screening system 100 to a user. The display of the user interface 102 can include any display known in the art. For example, the display can include, but is not limited to, a liquid crystal display (LCD), an organic light emitting diode (OLED) based display, or a CRT display. Those skilled in the art will recognize that any display device capable of integration with the user interface 102 is suitable for implementation in the present disclosure. In another embodiment, a user can input selections and / or instructions in response to data displayed to the user via a user input device of the user interface 102. For example, a user can view (or the controller can be configured to display) the weighting parameters or layout map. In at least one embodiment, the screening system is configured to display a graphical user interface on the user interface 102, where the graphical user interface includes the weighting parameters and / or quantitative representation of defect criticality.

[0105] All of the methods described herein can include storing results of one or more steps of the method embodiments in a memory. The results can include any of the results described herein and can be stored in any manner known in the art. The memory can include any memory described herein or any other suitable storage medium known in the art. After the results have been stored, the results can be accessed in the memory and used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, and the like. Further, the results can be stored "permanently," "semi-permanently," "temporarily," or for some period of time. For example, the memory can be random access memory (RAM) and the results can not necessarily be saved in the memory indefinitely.

[0106] It is further contemplated that each of the embodiments of the methods described above can include any other steps of any other methods described herein. Additionally, each of the embodiments of the methods described above can be performed by any of the systems and / or components described herein.

[0107] Those skilled in the art will recognize that the component operations, devices, objects, and the discussion accompanying them as described herein are used as examples for the sake of conceptual clarity and that various configuration modifications are contemplated. Consequently, as used herein, the specific exemplars set forth and the accompanying discussion are intended to be representative of their more general classes. In general, use of any specific exemplar is intended to be representative of its class, and the non-inclusion of specific components, operations, devices, and objects should not be taken as limiting.

[0108] As used herein, directional terms such as "top," "bottom," "upper," "lower," "above," "below," "up," "down," and "downward" are intended to provide relative positions for purposes of description and are not intended to designate absolute reference frames. One skilled in the art will appreciate the various modifications to the described embodiments, and the general principles defined herein can be applied to other embodiments as well.

[0109] With respect to the use of substantially any plural and / or singular term herein, those having skill in the art can translate the contexts and / or applications from the plural to the singular and / or from the singular to the plural as is appropriate to the disclosures herein. For clarity, various singular / plural permutations are not explicitly delineated herein.

[0110] The subject matter described herein is sometimes illustrated using different components contained within other components or connected thereto. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermediate components. Likewise, any two components so associated can also be viewed as being "connected" or "coupled" to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "couplable" to each other to achieve the desired functionality. Specific examples of couplable include but are not limited to physically mateable and / or physically interacting components and / or wirelessly interactable and / or wirelessly interacting components and / or logically interacting and / or logically interactable components.

[0111] Further, it is to be understood that the invention is defined by the appended claims. Those skilled in the art will appreciate that, in general, the terms used in this specification and appended claims (e.g., in the body of the appended claims) are intended to be interpreted broadly. For example, the terms "including" and "having" should be interpreted as "including but not limited to," the term "has" should be interpreted as "has at least," the term "includes" should be interpreted as "includes but is not limited to," and the like. Those skilled in the art will further appreciate that if a specific number of a claim recitation is intended, the intent will be recited explicitly, for example, as "at least one of A and B or C" and that no inference will be drawn as to a specific number of recitations. For example, as a draftman has no intention to limit the claim to one of A or B or C, even if an explicit recitation of a specific number, such as one, is merely suggested, unless specifically recited, the draftman will appreciate that the claim will be read to be as broad as it would be under common draftsmanship understanding.For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0112] It is believed that, through the foregoing description, the present disclosure and many of its attendant advantages will be understood by those of ordinary skill in the art. It will be apparent, however, that various changes can be made thereto without departing from the scope of the disclosed subject matter or sacrificing all of its material advantages. The form herein described is merely an example embodiment and the appended claims are intended to cover all such changes and modifications that fall within the scope of the present disclosure. Furthermore, it is to be understood that the application is defined by the appended claims.

Claims

1. A screening system for determining the criticality of defects, comprising: A controller communicatively coupled to one or more sample analysis subsystems, wherein the one or more sample analysis subsystems include at least one testing subsystem and at least one online characterization subsystem, the controller comprising one or more processors configured to execute program instructions that cause the one or more processors to: Defect results that identify the defects and their locations; Receive defect test formulations, wherein each defect test formulation is configured to test one or more of a plurality of potential defects at a plurality of test locations; and Identify a plurality of N detection parameters, wherein each of the plurality of N detection parameters is a countable number of tests performed for a defect or location, which is associated with the test location of the potential defect of the plurality of potential defects and configured based on the defect test recipe to test the potential defect a countable number of times. Multiple weighting parameters are determined based on the multiple N detection parameters, wherein the multiple weighting parameters are associated with the multiple test locations; The severity of the defect is determined at least based on the following: The proximity between the plurality of test locations of the plurality of potential defects and the defect location of the defect; and The plurality of weighting parameters are associated with the plurality of test locations.

2. The screening system of claim 1, wherein receiving the defect test formula includes generating a layout diagram of the plurality of test locations, wherein the severity of the defect that generates the defect is further based on the layout diagram.

3. The screening system of claim 1, wherein the one or more processors are further configured to execute the program instructions, the program instructions causing the one or more processors to: Based on the plurality of N detection parameters, the plurality of test locations are divided into a plurality of grids, wherein the plurality of weighting parameters are further based on and associated with the plurality of grids.

4. The screening system of claim 1, wherein the identification of the defect results is performed via an online characterization subsystem of the one or more sample analysis subsystems.

5. The screening system of claim 1, wherein each of the plurality of test locations comprises a test location region of a plurality of test location areas, wherein receiving the plurality of test locations includes: Determine the boundaries of the multiple test location regions.

6. The screening system of claim 5, wherein the one or more processors are further configured to execute the program instructions, the program instructions causing the one or more processors to: Determine the proximity boundaries associated with the defect.

7. The screening system of claim 6, wherein the criticality of generating the defect is further based on the intersection of the proximity boundary and the boundary.

8. The screening system of claim 5, wherein determining the boundary of the plurality of test location regions comprises determining the short-circuit boundary based on a pair of neighboring features associated with a potential short-circuit defect of the plurality of potential defects.

9. The screening system of claim 5, wherein determining the boundaries of the plurality of test location regions comprises determining open-circuit boundaries based on features associated with potential open-circuit defects of the plurality of potential defects.

10. The screening system of claim 5, wherein determining the boundaries of the plurality of test location regions comprises determining unit-aware boundaries based on units associated with unit-aware potential defects of the plurality of potential defects.

11. The screening system of claim 1, wherein the determination of the plurality of weighted parameters is performed via a machine learning model.

12. The screening system of claim 1, wherein the determination of the plurality of weighting parameters is based on an inverse relational pattern, such that a weighting parameter associated with a relatively low N detection parameter is determined to be relatively high.

13. The screening system of claim 1, wherein the one or more processors are further configured to execute the program instructions, the program instructions causing the one or more processors to: The weighted defect rate of the die is determined at least in part based on a plurality of defect severity levels, including the defect severity level, wherein the plurality of defect severity levels are associated with a plurality of layers of the die.

14. The screening system of claim 13, wherein the one or more processors are further configured to execute the program instructions, the program instructions causing the one or more processors to: Identifying one or more statistical outliers among a plurality of wafers, wherein the plurality of wafers comprises the bare die, based at least in part on the weighted defect rate of the bare die; and Based on a selected risk tolerance level, a subset of the statistical outliers of the plurality of wafers may be selectively disqualified from entering the supply chain of the downstream manufacturing process.

15. The screening system of claim 1, wherein the one or more processors are further configured to execute the program instructions, the program instructions causing the one or more processors to: The specified region is identified based on the multiple N detection parameters.

16. The screening system of claim 15, wherein the one or more processors are further configured to execute the program instructions, the program instructions causing the one or more processors to: Perform defect inspection on the specified area.

17. A method for generating the criticality of a defect, comprising: Defect results that identify the defects and their locations; Receive defect test formulations, wherein each defect test formulation is configured to test one or more of a plurality of potential defects at a plurality of test locations; and Identify a plurality of N detection parameters, wherein each of the plurality of N detection parameters is a countable number of tests performed for a defect or location, which is associated with the test location of the potential defect of the plurality of potential defects and configured based on the defect test recipe to test the potential defect a countable number of times. Multiple weighting parameters are determined based on the multiple N detection parameters, wherein the multiple weighting parameters are associated with the multiple test locations; The severity of the defect is determined at least based on the following: The proximity between the plurality of test locations of the plurality of potential defects and the defect location of the defect; and The plurality of weighting parameters are associated with the plurality of test locations.

18. The method of claim 17, wherein receiving the defect test formula includes generating a layout diagram of the plurality of test locations, wherein the severity of the defect that generates the defect is further based on the layout diagram.

19. The method of claim 17, further comprising: Based on the plurality of N detection parameters, the plurality of test locations are divided into a plurality of grids, wherein the plurality of weighting parameters are further based on and associated with the plurality of grids.

20. The method of claim 17, wherein the identification of the defect results is performed via an online characterization subsystem of the one or more sample analysis subsystems.

21. The method of claim 17, wherein each of the plurality of test locations comprises a test location region of a plurality of test location areas, wherein receiving the plurality of test locations includes: Determine the boundaries of the multiple test location regions.

22. The method of claim 21, further comprising: Determine the proximity boundaries associated with the defect.

23. The method of claim 22, wherein the criticality of generating the defect is further based on the intersection of the proximity boundary and the boundary.

24. The method of claim 21, wherein determining the boundary of the plurality of test location regions comprises determining the short-circuit boundary based on a pair of neighboring features associated with a potential short-circuit defect of the plurality of potential defects.

25. The method of claim 21, wherein determining the boundaries of the plurality of test location regions comprises determining open-circuit boundaries based on features associated with potential open-circuit defects of the plurality of potential defects.

26. The method of claim 21, wherein determining the boundary of the plurality of test location regions comprises determining a cell-aware boundary based on cells associated with cell-aware potential defects of the plurality of potential defects.

27. The method of claim 17, wherein the determination of the plurality of weighted parameters is performed via a machine learning model.

28. The method of claim 17, wherein the determination of the plurality of weighting parameters is based on an inverse relational pattern, such that a weighting parameter associated with a relatively low N detection parameter is determined to be relatively high.

29. The method of claim 17, further comprising: The weighted defect rate of the die is determined at least in part based on a plurality of defect severity levels, including the defect severity level, wherein the plurality of defect severity levels are associated with a plurality of layers of the die.

30. The method of claim 29, further comprising: The statistical outliers in a plurality of wafers, comprising the bare die, are identified at least in part based on the weighted defect rate of the bare die. and Based on a selected risk tolerance level, a subset of the statistical outliers of the plurality of wafers may be selectively disqualified from entering the supply chain of the downstream manufacturing process.

31. The method of claim 17, further comprising: The specified region is identified based on the multiple N detection parameters.

32. The method of claim 31, further comprising: Perform defect inspection on the specified area.

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