Display panel and display device

Abstract

This invention provides a display panel and a display device. The display panel includes R rows of pixel circuits, M rows of compensation circuits, multiple data lines, N scan lines, and a driving circuit. Some of the compensation circuits and some of the pixel circuits are located in the same column, and the pixel circuits and compensation circuits in the same column are connected to the same data line. The driving circuit includes N cascaded driving units. The first to Rth level driving units are each connected to a row of pixel circuits via a scan line and provide driving signals to the corresponding row of pixel circuits. The (R+1)th to (R+M)th level driving units are each connected to a row of compensation circuits via a scan line and provide driving signals to the corresponding row of compensation circuits. During the non-light-emitting phase of a display frame, the driving signal applied to the corresponding scan line by each driving unit includes at least two conduction pulses to improve the problem of dim brightness in the scanning end area during display, thereby improving the display effect.

Description

Technical Field

[0001] This invention relates to a display panel and a display device, belonging to the field of display technology. Background Art

[0002] OLED (Organic Light-Emitting Diode) boasts a range of advantages, including self-illumination, wide viewing angles, lightweight, thinness, high brightness, low power consumption, and fast response. Therefore, OLED displays have become extremely popular both domestically and internationally, with broad application prospects. However, current display devices still require improvement. Summary of the Invention

[0003] The present invention provides a display panel and a display device to solve the problem of dim brightness in the scanning end area of ​​the display device in multiple initialization schemes.

[0004] In a first aspect, embodiments of the present invention provide a display panel, comprising:

[0005] R-row pixel circuit, where R is a positive integer, is used to drive R-row light-emitting elements to emit light;

[0006] Multiple compensation circuits, including M rows of compensation circuits, where M is a positive integer; some of the compensation circuits and some of the pixel circuits are located in the same column in the M rows of compensation circuits;

[0007] Multiple data lines, the pixel circuit and the compensation circuit located in the same column are connected to the same data line, and the data line provides data signals;

[0008] N scan lines, where N = R + M, and the data lines connected to the pixel circuit and the compensation circuit in the same column are arranged to intersect with the N scan lines;

[0009] The driving circuit includes N cascaded driving units. The first to Rth level driving units are each connected to a row of pixel circuits via a scan line and provide driving signals to the corresponding row of pixel circuits. The pixel circuits respond to the driving signals to receive the data signals. The (R+1)th to (R+M)th level driving units are each connected to a row of compensation circuits via a scan line and provide driving signals to the corresponding row of compensation circuits. During the non-light-emitting phase of a display frame, the driving signals applied by each driving unit to the corresponding scan line include at least two conduction pulses.

[0010] Based on the above display panel, optionally, the compensation circuit includes a switching element and a compensation capacitor, the scan line is connected to the control terminal of the switching element, and the drive signal is used to control the switching element to close so that the data signal is written into the compensation capacitor.

[0011] Based on the above display panel, optionally, the pixel circuit includes a data writing transistor and a storage capacitor. The input terminal of the data writing transistor is connected to the data line, the output terminal of the data writing transistor is connected to one end of the storage capacitor, the control terminal of the data writing transistor is connected to the scan line, and the data writing transistor is used to write data signals to the storage capacitor.

[0012] The capacitance of the compensation capacitor is equal to the capacitance of the storage capacitor.

[0013] Based on the above display panel, optionally, the display panel includes a display area and a non-display area located on at least one side of the display area, the pixel circuit is located in the display area, and the compensation circuit is located in the non-display area.

[0014] Based on the above display panel, optionally, the dimension of the electrode plate of the compensation capacitor along the column direction is smaller than the dimension of the electrode plate of the storage capacitor along the column direction.

[0015] Based on the above display panel, optionally, the compensation capacitor includes an upper electrode plate and a lower electrode plate disposed opposite to each other, and the storage capacitor includes an upper electrode plate and a lower electrode plate disposed opposite to each other.

[0016] The upper electrode of the compensation capacitor is disposed in the same layer as the upper electrode of the storage capacitor; and / or, the lower electrode of the compensation capacitor is disposed in the same layer as the lower electrode of the storage capacitor.

[0017] Based on the above display panel, optionally, the non-display area includes a bonding area, and the compensation circuit is located between the bonding area and the display area.

[0018] Based on the above display panel, optionally, during the non-light-emitting phase of a display frame, the driving signal applied by the driving unit to the corresponding scan line includes P conduction pulses, where M≥(P-1).

[0019] Based on the above display panel, optionally, P equals 3 and M equals 2.

[0020] Based on the above display panel, optionally, the widths of the P conduction pulses are the same, and the widths between any two adjacent conduction pulses are the same.

[0021] Based on the above display panel, optionally, M equals 2(P-1).

[0022] Based on the above display panel, optionally, the R-row pixel circuit includes a first circuit group and a second circuit group. In the row direction, the second circuit group is located on one side of the first circuit group. The number of rows of the pixel circuit in the first circuit group is equal to R, and the number of rows of the pixel circuit in the second circuit group is less than the number of rows of the pixel circuit in the first circuit group. From the top edge to the bottom edge of the display panel, a portion of the multiple rows of pixel circuits in the second circuit group corresponds one-to-one with a portion of the multiple rows of pixel circuits in the first circuit group and is located in the same row.

[0023] The M-row compensation circuit forms a multi-column compensation circuit, and the multi-column compensation circuit is located in the same column as the multi-column pixel circuit of the first circuit group.

[0024] Based on the above display panel, optionally, the R-row pixel circuit includes two second circuit groups, with the first circuit group located between the two second circuit groups.

[0025] Based on the above display panel, optionally, the plurality of compensation circuits may further include compensation circuits located in the same column corresponding one-to-one with the multiple columns of pixel circuits in the second circuit group.

[0026] Based on the above display panel, optionally, for the multi-column pixel circuit of the second circuit group, the number of rows of the compensation circuit corresponding to different column pixel circuits is the same.

[0027] Based on the above display panel, optionally, for the multi-column pixel circuit of the second circuit group, the number of rows of the compensation circuit corresponding to each column of pixel circuit is greater than or equal to (P-2).

[0028] Based on the above display panel, optionally, the switching element includes a switching transistor, which has the same structure as the data writing transistor.

[0029] In a second aspect, embodiments of the present invention also provide a display device, which includes a display panel as described in any one of the first aspects.

[0030] The display panel and display device provided by the present invention include an R-row pixel circuit, an M-row compensation circuit, multiple data lines, N scan lines, and a driving circuit. The R-row pixel circuit drives the R-row light-emitting elements to emit light. In the M-row compensation circuit, some compensation circuits and some pixel circuits are located in the same column. The pixel circuits and compensation circuits in the same column are connected to the same data line, which provides data signals. The data line connected to the pixel circuits and compensation circuits in the same column is intersected with the N scan lines. The driving circuit includes N cascaded driving units. The first to R-level driving units are each connected to a row of pixel circuits via a scan line and provide driving signals to the corresponding row of pixel circuits. The pixel circuits respond to the driving signals to receive data signals. The R-level to M-level driving units are each connected to a row of compensation circuits via a scan line and provide driving signals to the corresponding row of compensation circuits. During the non-light-emitting phase of a display frame, the driving signals applied by each driving unit to the corresponding scan line include at least two conduction pulses. With this configuration, by adding an M-row compensation circuit to the display panel, the data voltage written to the subsequent rows of pixel circuits can be compensated, thereby improving the problem of the dim brightness in the scanning end area when the display panel is displayed and enhancing the display effect. Attached Figure Description

[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. Furthermore, these drawings and textual descriptions are not intended to limit the scope of the inventive concept in any way, but rather to illustrate the concept of the invention to those skilled in the art by reference to specific embodiments.

[0032] Figure 1 This is a schematic diagram showing that the brightness of the scanning end area of ​​a display panel is too low.

[0033] Figure 2 A schematic diagram illustrating the principle of the data writing stage;

[0034] Figure 3 This is a timing diagram of the display panel's operation.

[0035] Figure 4 This is a schematic diagram of the structure of a display panel provided in one embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the structure of a compensation circuit provided in one embodiment of the present invention;

[0037] Figure 6 This is another structural schematic diagram of a display panel provided in one embodiment of the present invention;

[0038] Figure 7This is a schematic diagram of the area where the compensation circuit is located in a display panel according to an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of the area where the compensation circuit is located in a display panel according to another embodiment of the present invention;

[0040] Figure 9 This is a schematic diagram of the signal transmitted by the scan lines of a display panel.

[0041] Figure 10 This is a schematic diagram of the signal transmission of the scan lines of a display panel according to an embodiment of the present invention.

[0042] Explanation of reference numerals in the attached figures: 1-Pixel circuit; 10-First circuit group; 11-Second circuit group; 110-Sub-circuit group; 2-Compensation circuit; 21-Switching element; 22-Compensation capacitor; 3-Data line; 4-Scan line; 5-Drive circuit; 6-Control chip. DETAILED DESCRIPTION

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0044] OLED displays typically emit light through pixel circuits. However, due to stress issues in the thin-film transistors within these pixel circuits, insufficient brightness in the first frame occurs during the transition from low to high grayscale levels. To address this, the data writing transistors in the pixel circuits can be turned on multiple times during the non-emitting phases of a display frame, with data signals transmitted only during the final on-time interval (referred to as the N-Scan scheme). However, this scheme results in a darker brightness in the end area of ​​the scanned display panel, affecting the display effect. After investigating this phenomenon, the inventors discovered the following reasons for it:

[0045] Reference Figures 1 to 3 , Figure 1 This is a schematic diagram showing that the brightness of the scanning end area of ​​a display panel is relatively low. Figure 2 This is a schematic diagram illustrating the principle of the data writing stage. Figure 3 This is a timing diagram. Figure 1Taking a display panel with 9 rows of pixel circuits as an example, each row of pixel circuits is connected to scan lines Scan_1 to Scan_9 in a one-to-one correspondence. Rows 1 to 5 are located in area A, and rows 6 to 9 are located in area B. Taking the above N Scan as 3 Scan as an example, in the non-light-emitting stage of a display frame, Figure 3 The driving signal in the timing diagram includes three turn-on pulses, each with a width of 1H, and the width between any two adjacent turn-on pulses is also 1H. For each row of pixel circuits, the data signal can be transmitted to the pixel circuit within the interval of the third turn-on pulse of the driving signal. Specifically, in... Figure 1 and Figure 2 In this configuration, the drive units connected to the scan lines are cascaded, such as... Figure 9As shown, when the drive signals transmitted on scan lines Scan_1, Scan_3, and Scan_5 are valid (all three scan lines are in the conduction pulse interval), the thin-film transistors T2 of the pixel circuits in rows 1, 3, and 5 are turned on; then, when the drive signals transmitted on scan lines Scan_2, Scan_4, and Scan_6 are valid, the thin-film transistors T2 of the pixel circuits in rows 2, 4, and 6 are turned on; then, when the drive signals transmitted on scan lines Scan_3, Scan_5, and Scan_7 are valid, the thin-film transistors T2 of the pixel circuits in rows 3, 5, and 7 are turned on; then, when the drive signals transmitted on scan lines Scan_4, Scan_5, and Scan_6 ...5, Scan_6, Scan_7, and Scan_8 are valid, the thin-film transistors T2 of the pixel circuits in rows 3, 5, and 7 are valid, the thin-film transistors T2 of the pixel circuits in rows 3, 5, and 7 are valid, the thin-film transistors T2 of the pixel circuits in rows 3, 5, and 7 are valid, the thin-film transistors T2 of the pixel circuits in rows 3, 4, and 5 are valid, the thin-film transistors T2 of the pixel circuits in rows 3, 5, and 5 are valid, the thin-film transistors T2 of the pixel circuits in rows 3, 5, and 5 are valid, the thin-film transistors T2 of the pixel circuits in rows 3, 5, and 5 are valid, the thin-film transistors T2 of the pixel circuits in rows The drive signals transmitted on Scan_6 and Scan_8 are valid signals, and the thin-film transistors T2 of the pixel circuits in rows 4, 6, and 8 are turned on; then the drive signals transmitted on scan lines Scan_5, Scan_7, and Scan_9 are valid signals, and the thin-film transistors T2 of the pixel circuits in rows 5, 7, and 9 are turned on; then the drive signals transmitted on scan lines Scan_6 and Scan_8 are valid signals; then the drive signals transmitted on scan lines Scan_7 and Scan_9 are valid signals; then the drive signals transmitted on scan line Scan_8 are valid signals; then the drive signals transmitted on scan line Scan_9 are valid signals. When transmitting data signals to the first row of pixel circuits in area A of the display panel, scan lines Scan_1, Scan_3, and Scan_5 all transmit valid signals, controlling the thin-film transistors T2 of the three rows of pixel circuits to turn on. The data signals are pulled low due to the presence of three coupling capacitors Cscan_data between the scan lines and the data lines (scan lines Scan_1, Scan_3, and Scan_5 overlap with the data lines, generating coupling capacitance). Similarly, when transmitting data signals to the second to fifth rows of pixel circuits in area A of the display panel, the data lines also generate coupling capacitance with the three scan lines. For the sixth and seventh rows of pixel circuits in area B (i.e., the end of the scan), the number of scan lines transmitting valid signals is 2. Figure 2 (the middle part); for the 8th and 9th row pixel circuits in area B, the number of scan lines transmitting valid signals is 1 ( Figure 2 (The rightmost part); it can be seen that the number of coupling capacitors between the scan lines and data lines in area B is less than 3, which causes the data signal to be pulled down by the coupling capacitor Cscan_data by less than that in area A. The voltage Vdata of the data signal actually written to the pixel is higher than that in area A, which ultimately leads to the brightness of area B being darker (darker than area A).

[0046] Additionally, due to the scanning end region (i.e. Figure 1The number of rows of pixel circuit 1 that simultaneously writes data signals to area B is less than that of the normal area (i.e., Figure 1 The number of rows of pixel circuit 1 in area A of the display panel is affected by the fact that the voltage of the data signal written to pixel circuit 1 in the end area of ​​the scan is greater than that in the normal area, resulting in a darker brightness in the end area of ​​the scan. Therefore, for the 3Scan solution, the last four rows of pixel circuits on the display panel have defects.

[0047] To address the above problems, some embodiments of the present invention provide a display panel, see reference. Figure 4 , Figure 4 This is a schematic diagram of the structure of a display panel provided in one embodiment of the present invention. Figure 4 As shown, the display panel in this embodiment includes:

[0048] R-row pixel circuit 1, where R is a positive integer, is used to drive the R-row light-emitting elements to emit light;

[0049] Multiple compensation circuits 2, including M rows of compensation circuits 2, where M is a positive integer ( Figure 3 In the middle, M=2); in row M compensation circuit 2, part of compensation circuit 2 and part of pixel circuit 1 are located in the same column;

[0050] Multiple data lines 3, each data line 3 is used to write data signals to the pixel circuit 1 and compensation circuit 2 in the same column; that is, the pixel circuit 1 and compensation circuit 2 located in the same column are connected to the same data line 3, and the data line 3 provides data signals.

[0051] N scan lines 4, where N = R + M; data lines 3 connected to pixel circuit 1 and compensation circuit 2 in the same column are arranged to intersect with N scan lines 4;

[0052] The driving circuit 5 includes N cascaded driving units (not shown in the figure). The first to Rth level driving units are each connected to a row of pixel circuits 1 via a scan line 4 and provide driving signals to the corresponding row of pixel circuits 1. The pixel circuits 1 respond to the driving signals to receive data signals. The (R+1)th to (R+M)th level driving units are each connected to a row of compensation circuits 2 via a scan line 4 and provide driving signals to the corresponding row of compensation circuits 2. During the non-light-emitting phase of a display frame, the driving signals applied by each driving unit to the corresponding scan line 4 include at least two conduction pulses (see...). Figure 3 ).

[0053] The pixel circuit 1 includes at least one data writing transistor, one storage capacitor, one driving transistor, and one light-emitting element. The data writing transistor includes a control terminal, an input terminal, and an output terminal. The control terminal is connected to the scan line 4, the input terminal is connected to the data line 3, and the output terminal is connected to one end of the storage capacitor. The data writing transistor is used to write data signals to the storage capacitor, and the storage capacitor is used to store the written data signals.

[0054] The data signal on data line 3 is written into the storage capacitor for storage, and the driving transistor is used to drive the light-emitting element to emit light based on the data signal stored in the storage capacitor.

[0055] Furthermore, in some embodiments, the pixel circuit 1 can be a 7T1C circuit. Here, T represents a transistor and C represents a capacitor; that is, the pixel circuit 1 can be composed of seven transistors (including a data writing transistor and a driving transistor) and one capacitor (i.e., a storage capacitor). Of course, this invention is not limited to this. In other embodiments, the pixel circuit 1 can also be based on the 7T1C circuit, with the addition, reduction, or adjustment of some components to optimize or adjust the performance or function of the pixel circuit 1.

[0056] Scan line 4 extends roughly along the row direction of pixel circuit 1. When the driving unit outputs a driving signal, the driving signal is transmitted through scan line 4 to the control terminal of the data writing transistor, which controls the data writing transistor to turn on. Thus, the data signal on data line 3 can be written to the storage capacitor through the data writing transistor, which in turn charges the storage capacitor.

[0057] Furthermore, to address the issue of insufficient brightness in the first frame, this embodiment employs the aforementioned N-Scan scheme. This involves multiple turns on the data writing transistors of the pixel circuit during the non-light-emitting phases within a display frame, and transmitting the data signal during the final turn-on phase. For example, it could be... Figure 2 and Figure 3 The 3Scan scheme is shown.

[0058] In this embodiment, an M-row compensation circuit 2 is also provided, and an M-level driving unit is added to the driving circuit 5 after the R-level driving unit. Taking the 3Scan scheme as an example, during the transmission of data signals to the last four rows of the R-row pixel circuit, the M-level driving unit can control the partial or complete opening of the M-row compensation circuit 2. With this setting, during the transmission of data signals to each row of pixel circuit 1 through the data line 3, the number of scan lines 4 that generate coupling capacitance with the data line 3 remains consistent, so that the voltage of the data signal obtained by the pixel circuit 1 in the scanning end area and the normal area is consistent or nearly consistent. At the same time, the compensation circuit 2 can also share part of the data signal written to the last four rows of pixel circuit 1, thereby compensating for the voltage of the data written to the last four rows of pixel circuit 1, so that the voltage of the data signal obtained by the pixel circuit 1 in the scanning end area and the normal area is consistent or nearly consistent.

[0059] It should be noted that since the human eye can no longer accurately distinguish the difference in brightness when the difference is less than a certain value, in practice, it is not required that the brightness of the scanned end area and the normal area be completely consistent. As long as the difference in brightness is small enough that it does not give the user a noticeable visual difference.

[0060] Reference Figure 5 , Figure 5 This is a schematic diagram of a compensation circuit provided in one embodiment of the present invention. Figure 5 As shown, in some embodiments, the compensation circuit 2 may include a switching element 21 and a compensation capacitor 22. The scan line 4 is connected to the control terminal of the switching element 21, and a drive signal is used to control the switching element 21 to close, so that the data signal is written into the compensation capacitor 22. That is, when no drive signal is received, the switching element 21 of the compensation circuit 2 remains open; when a drive signal is received, the switching element 21 of the compensation circuit 2 switches to a closed state, so that the data signal on the data line 3 can charge the compensation capacitor 22 through the switching element 21, and the compensation capacitor 22 shares a portion of the data signal of the pixel circuit 1 in the scanning end region.

[0061] Furthermore, in some embodiments, the switching element 21 may include a switching transistor, and the film layer in which its structure is located may be completely identical to the film layer in which the data writing transistor of the pixel circuit 1 is located, and / or, the film layer in which the compensation capacitor 22 is located may be completely identical to the film layer in which the storage capacitor of the pixel circuit 1 is located. In some embodiments, the switching transistor and the data writing transistor have the same structure, for example, the same type, the same aspect ratio of the channel, etc. In this way, the fabrication of the switching element 21 and the compensation capacitor 22 of the compensation circuit 2 can be completed simultaneously when the data writing transistor and the storage capacitor of the pixel circuit 1 are actually fabricated, reducing the complexity of the process.

[0062] Furthermore, in some embodiments, the load of the compensation circuit 2 is the same as the load of the pixel circuit 1. This ensures that the consumption of the input data signal by the compensation circuit 2 and the pixel circuit 1 is equal, thereby better guaranteeing consistent display brightness across the entire area of ​​the compensated display panel. Additionally, in some embodiments, the capacitance of the compensation capacitor 22 can be equal to the capacitance of the storage capacitor. Thus, when charging the compensation capacitor 22 and the data capacitor using the data signal, the amount of electricity charged to both is the same, further ensuring consistent display brightness across the entire area of ​​the compensated display panel.

[0063] Furthermore, in some embodiments, considering that the area corresponding to the compensation circuit 2 does not need to emit light, the compensation circuit 2 can include all the structures in the pixel circuit 1 except for the light-emitting element. That is, when fabricating the pixel circuit 1, the compensation circuit 2 can be fabricated simultaneously using the same process; only the step of fabricating the light-emitting element needs to be omitted when fabricating the compensation circuit 2. In this way, the modification to the process can be minimized, which is beneficial to the implementation of the actual process.

[0064] Continue to refer to Figure 4 In some embodiments, the display panel includes a display area AA and a non-display area NA located on at least one side of the display area AA. Pixel circuit 1 is located in the display area AA, and compensation circuit 2 is located in the non-display area NA. Specifically, the non-display area NA includes a bonding area, and compensation circuit 2 is located between the bonding area and the display area AA. Preferably, the dimension of the electrode plate of compensation capacitor 22 along the column direction is smaller than the dimension of the electrode plate of storage capacitor along the column direction. The column direction is... Figure 3 The scanning direction or the opposite direction of the scanning direction is perpendicular to the row direction of pixel circuit 1.

[0065] Specifically, since the compensation circuit 2 is located in the non-display area NA, and the non-display area NA forms a bezel in the display panel, the inclusion of the compensation circuit 2 inevitably widens the bezel of the display panel. Therefore, to reduce the bezel size, in this embodiment, the dimension of the plates of the compensation capacitor 22 along the column direction is smaller than the dimension of the plates of the storage capacitor along the column direction. That is, as shown... Figure 4 As shown, in the column direction, the width of the plates of the compensation capacitor 22 is smaller than the width of the plates of the storage capacitor. This, to some extent, avoids excessive increase in the frame size when the compensation circuit 2 is installed.

[0066] In some embodiments, the compensation capacitor 22 can be a stacked structure. Specifically, in a stacked structure, the dielectric layers between the plates of multiple compensation capacitors 22 can share boundaries, thereby reducing the overall area of ​​the multiple compensation capacitors 22 while keeping the capacitance value unchanged.

[0067] In some embodiments, the compensation capacitor 22 includes an upper electrode plate and a lower electrode plate disposed opposite to each other, the storage capacitor includes an upper electrode plate and a lower electrode plate disposed opposite to each other, the upper electrode plate of the compensation capacitor 22 is disposed in the same layer as the upper electrode plate of the storage capacitor, and / or, the lower electrode plate of the compensation capacitor 22 is disposed in the same layer as the lower electrode plate of the storage capacitor.

[0068] Furthermore, in some embodiments, the thickness of the dielectric layer of the compensation capacitor 22 is less than the thickness of the dielectric layer of the storage capacitor. Specifically, since the capacitance value is inversely proportional to the plate spacing, when the capacitance value of the compensation capacitor 22 is equal to the capacitance value of the storage capacitor, and the thickness of the dielectric layer of the compensation capacitor 22 is less than the thickness of the dielectric layer of the storage capacitor, the plate area of ​​the compensation capacitor 22 can be smaller, thereby reducing the frame space occupied by the compensation capacitor 22.

[0069] It is understandable that the compensation capacitor 22 can simultaneously adopt a multilayer structure and a dielectric layer that is thinner than that of the storage capacitor, and the present invention does not limit this.

[0070] Furthermore, as mentioned earlier, since the human eye has limited ability to distinguish brightness differences, in practice, compensation can be made only for a portion of the theoretically darker area, thereby reducing the brightness difference between the scanned end area and the normal area, as long as the human eye cannot perceive the brightness difference.

[0071] In summary, during the non-light-emitting phase of a display frame, the driving signals applied to the corresponding scan line 4 by each driving unit include P conduction pulses. Generally, the number of rows M of the compensation circuit 2 can be greater than or equal to P-1, and a larger M results in better compensation, but also a more complex structure and a greater increase in border width. Preferably, P equals 3 and M equals 2. In some embodiments, the width of the P conduction pulses is the same, which can be 1H, and the width between any two adjacent conduction pulses is the same, or the width between any two adjacent conduction pulses can also be 1H. Here, the width between two adjacent conduction pulses refers to the width between the cutoff time of the previous conduction pulse and the start time of the next conduction pulse.

[0072] In related technologies, taking the 3Scan scheme as an example, during the transmission of data signals to the fourth-to-last row pixel circuit 1 and the third-to-last row pixel circuit 1, the number of scan lines 4 that generate coupling capacitance with the data lines 3 is 2, resulting in a smaller degree of defects. However, during the transmission of data signals to the second-to-last row pixel circuit 1 and the first-to-last row pixel circuit 1, the number of scan lines 4 that generate coupling capacitance with the data lines 3 is 1, resulting in a larger degree of defects. Taking P = 3 and M = 2 as an example, during the transmission of data signals to the second-to-last row pixel circuit 1, the first row compensation circuit 2 can be simultaneously controlled to receive data signals; similarly, during the transmission of data signals to the first-to-last row pixel circuit 1, the second row compensation circuit 2 can be simultaneously controlled to receive data signals. This configuration reduces the degree of defects in the last two rows while preventing excessive increases in border width.

[0073] In another implementation, M equals 2(P-1); taking the 3Scan scheme as an example, M equals 4. During the transmission of data signals to the fourth-to-last row pixel circuit 1, the second-to-last row pixel circuit 1 and the first row compensation circuit 2 can be simultaneously controlled to receive data signals; during the transmission of data signals to the third-to-last row pixel circuit 1, the first-to-last row pixel circuit 1 and the second row compensation circuit 2 can be simultaneously controlled to receive data signals; during the transmission of data signals to the second-to-last row pixel circuit 1, the first row compensation circuit 2 and the third row compensation circuit 2 can be simultaneously controlled to receive data signals; during the transmission of data signals to the first-to-last row pixel circuit 1, the second row compensation circuit 2 and the fourth row compensation circuit 2 can be simultaneously controlled to receive data signals. Specifically, as... Figure 10 As shown, taking a display panel including 9 rows of pixel circuits 1 and 4 rows of compensation circuits 2 as an example, the 9 rows of pixel circuits 1 correspond to scan lines Scan_1 to Scan_9, and the 4 rows of compensation circuits correspond to scan lines Scan_10 to Scan_13. In the third conduction pulse interval of scan line Scan_6, scan lines Scan_8 and Scan_10 are also controlled to be in the conduction pulse interval; in the third conduction pulse interval of scan line Scan_7, scan lines Scan_9 and Scan_11 are also controlled to be in the conduction pulse interval; in the third conduction pulse interval of scan line Scan_8, scan lines Scan_10 and Scan_12 are also controlled to be in the conduction pulse interval; in the third conduction pulse interval of scan line Scan_9, scan lines Scan_11 and Scan_13 are also controlled to be in the conduction pulse interval.

[0074] In another implementation, taking the 3Scan scheme as an example, M equals 2. During the transmission of data signals to the fourth-to-last row pixel circuit 1, the second-to-last row pixel circuit 1 and the first row compensation circuit 2 can be simultaneously controlled to receive data signals; during the transmission of data signals to the third-to-last row pixel circuit 1, the first-to-last row pixel circuit 1 and the second row compensation circuit 2 can be simultaneously controlled to receive data signals; during the transmission of data signals to the second-to-last row pixel circuit 1, the first row compensation circuit 2 and the second row compensation circuit 2 can be simultaneously controlled to receive data signals; during the transmission of data signals to the first-to-last row pixel circuit 1, the first row compensation circuit 2 and the second row compensation circuit 2 can be simultaneously controlled to receive data signals.

[0075] Furthermore, in some embodiments, the display panel may also include a Demux circuit (also known as a multiplexer or demultiplexer). The Demux circuit includes one input terminal, at least two selection switches, and at least two output terminals. The input terminal is used to input data signals provided by the data terminal (e.g., control chip 6), and the output terminals are connected to the input terminal of the data line 3 of the display panel. Based on this, by reasonably controlling the opening and closing of each selection switch, the data signal input from the input terminal can be selectively output from one of the output terminals to the corresponding data line 3. This configuration reduces the number of data channels at the data terminal, thus simplifying the structure of the data terminal.

[0076] Based on this, since the Demux circuit is set up, there is an interval between the scanned multi-row pixel circuits 1 each time they are scanned simultaneously. Therefore, the number of darker pixel rows will increase exponentially in practice, and the multiplier is equal to the number of output terminals of the Demux circuit. Accordingly, the number of rows in the compensation circuit 2 also needs to be increased.

[0077] In one implementation, such as Figure 6As shown, the R-row pixel circuit 1 includes a first circuit group 10 and a second circuit group 11. In the row direction, the second circuit group 11 is located on one side of the first circuit group 10. The R-row pixel circuit 1 may include two second circuit groups 11, with the first circuit group 10 located between the two second circuit groups 11. The number of rows of pixel circuits 1 in the first circuit group 10 is equal to R, and the number of rows of pixel circuits 1 in the second circuit group 11 is less than the number of rows of pixel circuits 1 in the first circuit group 10. From the top edge to the bottom edge of the display panel, multiple rows of pixel circuits 1 in the second circuit group 11 correspond one-to-one with portions of multiple rows of pixel circuits 1 in the first circuit group 10, thus forming an arc corner at the bottom edge of the display panel. The aforementioned M-row compensation circuit 2 forms a multi-column compensation circuit 2, which corresponds one-to-one with the multi-column pixel circuits 1 of the first circuit group 10 and is located in the same column. The aforementioned multiple compensation circuits 2 also include compensation circuits 2 that correspond one-to-one with the multi-column pixel circuits 1 of the second circuit group 11 and are located in the same column. For the multi-column pixel circuit 1 of the second circuit group 11, the number of rows of the compensation circuit 2 corresponding to each column of pixel circuit 1 is the same. For the multi-column pixel circuit 1 of the second circuit group 11, the number of rows of the compensation circuit 2 corresponding to each column of pixel circuit 1 is greater than or equal to (P-2).

[0078] like Figure 6 As shown, each of the second circuit groups 11 described above may include multiple sub-circuit groups 110 distributed along the row direction, such as two or three sub-circuit groups 110. In two adjacent sub-circuit groups 110, the number of rows of pixel circuit 1 in the sub-circuit group 110 closer to the first circuit group 10 is greater than the number of rows of pixel circuit 1 in the sub-circuit group 110 farther from the first circuit group 10.

[0079] In addition, if Figure 1 As shown, in some solutions, the display panel includes a straight edge area and an arc-shaped corner area located on at least one side of the straight edge area. For example, in common devices such as smartphones and smartwatches, the four corners of the display panel all include arc-shaped corners. Based on this, in some embodiments, the arc-shaped corner area may be provided with at least one row of compensation circuit 2.

[0080] Specifically, refer to Figure 6 , Figure 6 This is a schematic diagram of the arc corner area of ​​a display panel provided in one embodiment of the present invention. Figure 6 As shown, since the corner area is not equipped with pixel circuit 1, the scanning end area of ​​the corner area and the scanning end area of ​​the straight edge area are misaligned in the row direction of pixel circuit 1. Therefore, in order to improve the dark phenomenon in the corner area, compensation circuit 2 can also be set in the corner area.

[0081] Reference Figure 7 and Figure 8 , Figure 7 and Figure 8These are schematic diagrams showing the areas where the compensation circuit is located in the display panel according to two embodiments of the present invention. Figure 7 The scanning direction is shown to be from the direction away from the control chip 6 to the direction closer to the control chip 6. This scanning scheme can be simply referred to as forward scanning. In this forward scanning scheme, the compensation circuit 2 is located at the end of the display panel closer to the control chip 6. Figure 8 The scanning direction is shown to be from the direction closest to the control chip 6 to the direction furthest from the control chip 6; this scanning scheme can be simply referred to as reverse scanning. In this reverse scanning scheme, the compensation circuit 2 is located at the end of the display panel furthest from the control chip 6. The control chip 6 is located in the bonding area.

[0082] Furthermore, it should be noted that, in addition to the structures mentioned in the above embodiments, the display panel may also include other structures necessary for realizing its function. However, the present invention does not modify these structures, and therefore they will not be described one by one.

[0083] Furthermore, embodiments of the present invention also provide a display device, which may include the display module panel of the above embodiments. This display device may be a mobile phone, tablet computer, or laptop computer, etc.

[0084] Unless otherwise defined, the technical or scientific terms used in the embodiments of this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to avoid confusion of the constituent elements.

[0085] Unless the context otherwise requires, throughout this specification, the term "comprising" is interpreted as open and encompassing, meaning "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

Claims

1. A display panel, characterized in that, include: R-row pixel circuit, where R is a positive integer, is used to drive R-row light-emitting elements to emit light; Multiple compensation circuits, including M rows of compensation circuits, where M is a positive integer; In the M-row compensation circuit, some of the compensation circuits and some of the pixel circuits are located in the same column; Multiple data lines, the pixel circuit and the compensation circuit located in the same column are connected to the same data line, and the data line provides data signals; N scan lines, where N=R+M, and the data lines connected to the pixel circuit and the compensation circuit in the same column are arranged to intersect with the N scan lines; The driving circuit includes N cascaded driving units. The first to Rth level driving units are each connected to a row of pixel circuits via a scan line and provide driving signals to the corresponding row of pixel circuits. The pixel circuits respond to the driving signals to receive the data signals. The (R+1)th to (R+M)th level driving units are each connected to a row of compensation circuits via a scan line and provide driving signals to the corresponding row of compensation circuits. During the non-light-emitting phase of a display frame, the driving signals applied by each driving unit to the corresponding scan line include at least two conduction pulses.

2. The display panel according to claim 1, characterized in that, The compensation circuit includes a switching element and a compensation capacitor. The scan line is connected to the control terminal of the switching element, and the drive signal is used to control the switching element to close so that the data signal is written into the compensation capacitor.

3. The display panel according to claim 2, characterized in that, The pixel circuit includes a data writing transistor and a storage capacitor. The input terminal of the data writing transistor is connected to the data line, the output terminal of the data writing transistor is connected to one end of the storage capacitor, and the control terminal of the data writing transistor is connected to the scan line. The data writing transistor is used to write data signals to the storage capacitor. The capacitance of the compensation capacitor is equal to the capacitance of the storage capacitor.

4. The display panel according to claim 3, characterized in that, The display panel includes a display area and a non-display area located on at least one side of the display area, the pixel circuit is located in the display area, and the compensation circuit is located in the non-display area.

5. The display panel according to claim 3, characterized in that, The dimensions of the plates of the compensation capacitor along the column direction are smaller than those of the plates of the storage capacitor along the column direction.

6. The display panel according to claim 3, characterized in that, The compensation capacitor includes an upper electrode plate and a lower electrode plate arranged opposite to each other, and the storage capacitor includes an upper electrode plate and a lower electrode plate arranged opposite to each other. The upper electrode of the compensation capacitor is disposed in the same layer as the upper electrode of the storage capacitor; and / or, the lower electrode of the compensation capacitor is disposed in the same layer as the lower electrode of the storage capacitor.

7. The display panel according to claim 4, characterized in that, The non-display area includes a bonding area, and the compensation circuit is located between the bonding area and the display area.

8. The display panel according to claim 1, characterized in that, During the non-light-emitting phase of a display frame, the driving signal applied by the driving unit to the corresponding scan line includes P conduction pulses, where M ≥ (P-1).

9. The display panel according to claim 8, characterized in that, P equals 3, M equals 2.

10. The display panel according to claim 8, characterized in that, The widths of the P conduction pulses are the same, and the widths between any two adjacent conduction pulses are the same.

11. The display panel according to claim 8, characterized in that, M equals 2(P-1).

12. The display panel according to claim 1 or 8, characterized in that, The R-row pixel circuit includes a first circuit group and a second circuit group. In the row direction, the second circuit group is located on one side of the first circuit group. The number of rows of the pixel circuit in the first circuit group is equal to R, and the number of rows of the pixel circuit in the second circuit group is less than the number of rows of the pixel circuit in the first circuit group. From the top edge to the bottom edge of the display panel, the multi-row pixel circuits in the second circuit group correspond one-to-one with the multi-row pixel circuits in the first circuit group and are located in the same row. The M-row compensation circuit forms a multi-column compensation circuit, and the multi-column compensation circuit is located in the same column as the multi-column pixel circuit of the first circuit group.

13. The display panel according to claim 12, characterized in that, The R-row pixel circuit includes two second circuit groups, with the first circuit group located between the two second circuit groups.

14. The display panel according to claim 12, characterized in that, The plurality of compensation circuits also include compensation circuits located in the same column that correspond one-to-one with the multiple columns of pixel circuits in the second circuit group.

15. The display panel according to claim 12, characterized in that, For the multi-column pixel circuit of the second circuit group, the number of rows is the same as that of the compensation circuit corresponding to different column pixel circuits.

16. The display panel according to claim 12, characterized in that, For the multi-column pixel circuit of the second circuit group, the number of rows of the compensation circuit corresponding to each column of pixel circuit is greater than or equal to (P-2).

17. The display panel according to claim 3, characterized in that, The switching element includes a switching transistor, which has the same structure as the data writing transistor.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 17.

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