Method for manufacturing stacked transistors, stacked transistors, devices, and apparatuses

Abstract

The present application provides a method for manufacturing a stacked transistor, a stacked transistor, a device, and an apparatus. The above method includes: sequentially stacking a first active structure, an isolation active structure, and a second active structure on a substrate; forming a first transistor based on the first active structure; depositing a first insulating material on a first surface of the first transistor facing the second active structure to form a first semiconductor material layer; depositing a second insulating material on the second active structure and the first semiconductor material layer to form a second semiconductor material layer; removing a part of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer; removing the first semiconductor material layer to expose the isolation active structure; performing an oxidation treatment on the isolation active structure to form an isolation dielectric structure; removing a part of the second semiconductor material layer covering the second active structure to expose the second active structure; and forming a second transistor based on the second active structure.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and in particular, to a method for manufacturing a stacked transistor, a stacked transistor, a device, and an apparatus. Background Art

[0002] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size has become a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, stacked transistors can further improve the transistor integration density, and have become one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] When using the traditional monolithic solution to manufacture a stacked transistor, electrical isolation is required between the active regions of the upper transistor and the lower transistor. The current electrical isolation methods have the following technical difficulties: for the ion implantation method, process control is difficult, and the diffusion effect of the implanted ions will have a greater impact on the thermal budget of subsequent processes, and at the same time, it will cause damage to the device structure. Summary of the Invention

[0004] This application provides a method for manufacturing a stacked transistor, a stacked transistor, a device, and an apparatus, so as to achieve isolation between the active regions of the first transistor and the second transistor without damaging the device structure.

[0005] In a first aspect, an embodiment of this application provides a method for manufacturing a stacked transistor. The method includes: sequentially stacking a first active structure, an isolation active structure, and a second active structure on a substrate; forming a first transistor based on the first active structure; depositing a first insulating material on a first surface of the first transistor facing the second active structure to form a first semiconductor material layer; the first semiconductor material layer surrounds the isolation active structure; depositing a second insulating material on the second active structure and the first semiconductor material layer to form a second semiconductor material layer; the second semiconductor material layer wraps the second active structure; removing a part of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer; removing the first semiconductor material layer to expose the isolation active structure; performing an oxidation treatment on the isolation active structure to form an isolation dielectric structure; removing a part of the second semiconductor material layer covering the second active structure to expose the second active structure; forming a second transistor based on the second active structure.

[0006] In some possible embodiments, before forming the first transistor based on the first active structure, the method further includes: depositing a dielectric material on the first active structure, the isolation active structure, and the second active structure to form a shallow trench isolation structure; the shallow trench isolation structure encapsulates the first active structure, the isolation active structure, and the second active structure; removing a first portion of the shallow trench isolation structure to expose the first active structure; before forming the second transistor based on the second active structure, the method further includes: flipping the wafer and removing the substrate.

[0007] In some possible embodiments, after flipping the wafer and removing the substrate, and before forming the first semiconductor material layer, the above method further includes: removing a portion of the second active structure that is far from the first active structure to form a first groove; depositing a second insulating material in the first groove to form a first filling structure; removing a second portion of the shallow trench isolation structure to expose the second active structure and the isolation active structure.

[0008] In some possible embodiments, removing a portion of the second semiconductor material layer that covers the first semiconductor material layer to expose the first semiconductor material layer includes: removing a portion of the second semiconductor material layer that covers the first semiconductor material layer, and a portion of the second semiconductor material layer that covers the first filling structure, to expose the first semiconductor material layer and the first filling structure.

[0009] In some possible embodiments, after oxidizing the isolation active structure to form an isolation dielectric structure, the above method further includes: removing the first filling structure and the second semiconductor material layer to expose the second active structure; forming the second transistor based on the second active structure.

[0010] In some possible embodiments, removing a portion of the second semiconductor material layer that covers the first semiconductor material layer to expose the first semiconductor material layer includes: removing a portion of the second semiconductor material layer that covers the first semiconductor material layer, and a portion of the second semiconductor material layer that covers the second surface of the second active structure, to expose the first semiconductor material layer and the second surface; the second surface is the surface of the second active structure that is far from the first active structure.

[0011] In some possible embodiments, after removing the first semiconductor material layer to expose the isolation active structure, the above method further includes: depositing a second insulating material on the second surface and a first region of the first surface, to form a third semiconductor material layer; the first region does not contact the second active structure.

[0012] In some possible embodiments, after oxidizing the isolation active structure to form an isolation dielectric structure, the above method further includes: removing the second semiconductor material layer and the third semiconductor material layer to expose the second active structure; forming a second transistor based on the second active structure.

[0013] In some possible embodiments, forming a first transistor based on the first active structure includes: sequentially forming a first dummy gate structure, a first spacer, a first source / drain structure, and a first interlayer dielectric layer of the first transistor based on the first active structure; removing the first dummy gate structure, and forming a first gate structure and a first gate dielectric layer; performing back-end process on the first interlayer dielectric layer to form a first metal interconnect layer.

[0014] In some possible embodiments, forming a second transistor based on the second active structure includes: sequentially forming a second dummy gate structure, a second spacer, a second source / drain structure, and a second interlayer dielectric layer of the second transistor based on the second active structure; removing the second dummy gate structure, and forming a second gate structure and a second gate dielectric layer; performing back-end process on the second interlayer dielectric layer to form a second metal interconnect layer.

[0015] In a second aspect, an embodiment of the present application provides a stacked transistor, which includes: a first transistor; a second transistor; the first active structure of the first transistor and the second active structure of the second transistor are formed by the same process, and the first transistor and the second transistor are self-aligned; an isolation dielectric structure, which is used to isolate the first active structure and the second active structure, and the isolation dielectric structure is located between the first active structure and the second active structure.

[0016] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: the stacked transistor as described in the above embodiment.

[0017] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and the semiconductor device as described in the above embodiment, and the semiconductor device is disposed on the circuit board.

[0018] In the present application, by oxidizing the isolation active structure located between the first active structure and the second active structure to form an isolation dielectric structure, the isolation between the active regions of the first transistor and the second transistor can be achieved without damaging the device structure.

[0019] Furthermore, compared with the traditional ion implantation and the isolation method using silicon-on-insulator (SOI), the process of preparing the isolation dielectric structure in the present application is simpler, and at the same time, the self-alignment problem of the first transistor and the second transistor is taken into account, ensuring the consistency of the active regions of the first transistor and the second transistor.

[0020] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0022] Figure 1 Schematic diagram of the first implementation process of the method for manufacturing a stacked transistor in an embodiment of this application;

[0023] Figure 2 Schematic diagram of the first structure of the stacked transistor in an embodiment of this application;

[0024] Figures 3A to 3F Schematic diagram of the first manufacturing process of the stacked transistor in an embodiment of this application;

[0025] Figures 4A to 4D Schematic diagram of the second manufacturing process of the stacked transistor in an embodiment of this application;

[0026] The above figures:

[0027] 10. Stacked transistor; 11. First transistor; 111. First active structure; 112. First spacer; 113. First source / drain structure; 114. First interlayer dielectric layer; 115. First gate dielectric layer; 116. First gate structure; 117. First metal interconnect layer; 12. Second transistor; 121. Second active structure; 122. Second spacer; 123. Second source / drain structure; 124. Second interlayer dielectric layer; 125. Second gate dielectric layer; 126. Second gate structure; 127. Second metal interconnect layer; 128. Second dummy gate structure; 13. Isolation dielectric structure; 14. First insulating layer; 15. Carrier wafer; 21. Substrate; 22. Fin structure; 221. First fin structure; 222. Second fin structure; 223. Isolation active structure; 23. Shallow trench isolation structure; 231. First part of the shallow trench isolation structure; 232. Second part of the shallow trench isolation structure; 233. Shallow trench isolation layer; 24. First groove; 25. First filling structure; 31. First semiconductor material layer; 32. Second semiconductor material layer; 33. Third semiconductor material layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0029] In the current context where Moore's Law is continuously deepening, after the technology node of gate-all-around FET (GAA), continuously advancing the miniaturization of transistor size is a hot issue in the current industry research and development. By stacking transistors in three dimensions, two or more layers of transistors can be integrated in the vertical space, which helps to further improve the transistor integration density and circuit performance, and is considered one of the important technologies to continue the miniaturization of integrated circuit size.

[0030] In one embodiment, there are two schemes for the manufacturing process of stacked transistors. The first is the monolithic scheme, and the second is the sequential scheme.

[0031] For the first scheme, N field effect transistors (NFETs) and P field effect transistors (PFETs) are fabricated on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, that is, NFETs or PFETs. Moreover, the upper and lower layer transistors must be strictly in the same planar space without alignment deviation. The advantage of this scheme is better integration density. The disadvantages of this scheme include the following two points: (1) The process is complex and requires a large amount of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and a basic complementary metal-oxide-semiconductor (CMOS) circuit must rely on two layers of transistors, resulting in poor design flexibility.

[0032] For the second scheme, it is based on wafer bonding and processed layer by layer. Specifically, the upper layer transistor is fabricated by bonding a wafer on top of the already fabricated lower layer transistor, stacking two transistors vertically. However, the temperature needs to be strictly controlled during the thermal process of fabricating the upper layer transistor to avoid affecting the lower layer transistor and the interconnecting wires. The advantage of this scheme is that due to wafer bonding, the device structures, channel crystal orientations, and even channel materials used for the upper and lower layer transistors can be optimized accordingly to obtain better and more matching device performance. The current technical challenges of this scheme include: (1) The fabrication of a high-quality upper layer transistor active layer; (2) The thinning and defect control of the upper layer bonded wafer; (3) There is an alignment error between the upper and lower layer transistors, and the lithography accuracy requirement is extremely high.

[0033] Among them, in the above-mentioned first solution (i.e., the single-chip solution), electrical isolation is required between the active regions of the upper transistor and the lower transistor. The current isolation methods include: (1) using an SOI substrate and forming a natural electrical isolation layer by using the buried oxide layer (BOX) in the SOI substrate; (2) forming an electrical isolation layer by ion implantation of P-type ions, N-type ions or oxygen ions. However, the cost of the SOI substrate is very high, and it is difficult to obtain an SOI substrate with a suitable thickness of the BOX layer and the device layer; for the ion implantation method, process control is difficult, and the diffusion effect of the implanted ions will have a greater impact on the thermal budget of the subsequent process, and at the same time, it will cause damage to the device structure.

[0034] To solve the above technical problems, an embodiment of the present application provides a method for manufacturing a stacked transistor to achieve isolation between the active regions of the first transistor and the second transistor without damaging the device structure.

[0035] In the embodiment of the present application, the above-mentioned stacked transistor can be applied to semiconductor devices such as memories and processors.

[0036] In one embodiment, the stacked transistor may include at least two transistors. For example, taking the first transistor and the second transistor as an example. The first transistor and the second transistor are arranged back to back. Among them, the first active structure in the first transistor and the second active structure in the second transistor are formed by the same process, and it can be understood that the first active structure and the second active structure are self-aligned.

[0037] In the embodiment of the present application, the first transistor and the second transistor in the stacked transistor may be the same type of transistor, such as any one of the following: fin field-effect transistor, gate-all-around transistor, planar transistor, and vertical transistor.

[0038] Figure 2 For a stacked transistor composed of fin field-effect transistors, the following combines Figure 2 The stacked transistor shown is used to illustrate the method for manufacturing the stacked transistor provided by the embodiment of the present application.

[0039] Figure 1 This is a schematic diagram of the first implementation process of the method for manufacturing a stacked transistor in the embodiment of the present application. Among them, the stacked transistor includes a first active structure for manufacturing a first transistor, a second active structure for manufacturing a second transistor, and an isolation active structure located between the first active structure and the second active structure. Refer to Figure 1 As shown, the method for manufacturing the above-mentioned stacked transistor may include:

[0040] S101, sequentially stack and arrange a first active structure, an isolation active structure, and a second active structure on a substrate.

[0041] It can be understood that in the process of fabricating a stacked transistor, a substrate is first provided, and an active structure is etched based on the substrate; then, a first transistor is fabricated based on the first active structure; next, the first transistor is flipped so that the second active structure faces upward; then, a second transistor is fabricated based on the second active structure; thus, the first transistor and the second transistor are formed to be disposed back-to-back.

[0042] In some embodiments, when the stacked transistor is a fin field-effect transistor, the above-mentioned sequentially stacking the first active structure, the isolation active structure, and the second active structure on the substrate may include: etching the substrate to form a plurality of fin structures; the fin structures are divided into three parts from top to bottom, the first part is the first active structure, the second part is the isolation active structure, and the third part is the second active structure.

[0043] In other embodiments, when the stacked transistor is a gate-all-around transistor, the above-mentioned sequentially stacking the first active structure, the isolation active structure, and the second active structure on the substrate may include: etching the substrate to form a columnar structure, wherein the substrate is formed by alternately depositing silicon (Si) layers and silicon germanium (SiGe) layers; the columnar structure is divided into three parts from top to bottom, the first part is the first active structure, the second part is the isolation active structure, and the third part is the second active structure.

[0044] In still other embodiments, when the stacked transistor is a planar transistor, the above-mentioned sequentially stacking the first active structure, the isolation active structure, and the second active structure on the substrate may include: etching the substrate to form a block structure; the block structure is divided into three parts from top to bottom, the first part is the first active structure, the second part is the isolation active structure, and the third part is the second active structure.

[0045] In the embodiments of the present application, since the stacked transistor includes two transistors (i.e., the first transistor and the second transistor), and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, therefore, when etching the substrate, a relatively large etching depth can be adopted. For example, the height of the etched fin structure (which can also be a columnar structure or a block structure) can be greater than 100 nm. It should be noted that the height of the fin structure can be set according to actual situations, and the embodiments of the present application do not make specific limitations thereto.

[0046] S102, form a first transistor based on the first active structure.

[0047] In some possible embodiments, the above S102 may include: based on the first active structure, successively forming a first dummy gate structure, a first spacer, a first source / drain structure, and a first interlayer dielectric layer of the first transistor; removing the first dummy gate structure, and forming a first gate structure and a first gate dielectric layer; performing back-end process treatment on the first interlayer dielectric layer to form a first metal interconnect layer.

[0048] In some embodiments, the above based on the first active structure, successively forming a first dummy gate structure, a first spacer, a first source / drain structure, and a first interlayer dielectric layer of the first transistor may include: lithographically opening the gate region of the first transistor, and depositing a semiconductor material (such as polysilicon) in the gate region to form a first dummy gate structure of the first transistor; forming first spacers on both sides of the first dummy gate structure; removing a part of the first active structure by etching to provide a source / drain trench of the first transistor, using the first spacers as a mask, selectively epitaxially growing a strained material such as silicon germanium or silicon carbide in the source / drain trench of the first transistor to fill the source / drain trench of the first transistor, and then through a heavy doping process, forming a first source / drain structure on the above strained material; depositing an insulating material (such as silicon dioxide (SiO 2 )) above the first active structure and the first source / drain structure to form a first interlayer dielectric layer; the first interlayer dielectric layer may cover the first active structure and the first source / drain structure; then, removing the first dummy gate structure, depositing an insulating material on the surface of the first active structure to form a first gate dielectric layer of the first transistor; depositing a metal material in the gate region to form a first gate structure; finally, performing back-end process treatment on the first interlayer dielectric layer to form a first metal interconnect layer.

[0049] It should be noted that for ease of description, the first source / drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the second source / drain structure, the first source / drain metal, the second source / drain metal, the source / drain trench, etc. are all similar to the first source / drain structure, where "source / drain" is an abbreviation for "source and / or drain".

[0050] In some possible embodiments, after forming the first transistor based on the first active structure and before the above-mentioned wafer flipping and substrate removal, the above method may further include: depositing an insulating material (such as silicon oxide) on the first metal interconnect layer to form a first insulating layer, and bonding the first insulating layer to a carrier wafer.

[0051] In the embodiments of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after wafer flipping, effectively preventing the first transistor from being broken by external forces during the process of manufacturing the second transistor.

[0052] S103. Deposit a first insulating material on the first surface of the first transistor facing the second active structure to form a first semiconductor material layer.

[0053] Among them, the first semiconductor material layer covers the first surface and surrounds the isolation active structure.

[0054] It can be understood that the first transistor and the second transistor are arranged back to back. During the manufacturing process, the first transistor is manufactured first. After the first transistor is manufactured, the first transistor is flipped, and a first insulating material is deposited above the first transistor (that is, the first surface of the first transistor close to the second transistor) to form a first semiconductor material layer.

[0055] In the embodiments of the present application, the first insulating material may include, but is not limited to, amorphous carbon and amorphous silicon, etc., and may also be other insulating materials. The embodiments of the present application do not make specific limitations on this.

[0056] S104. Deposit a second insulating material on the second active structure and the first semiconductor material layer to form a second semiconductor material layer.

[0057] Among them, the second semiconductor material layer wraps the second active structure and covers the first semiconductor material layer.

[0058] It can be understood that by using the atomic layer deposition method, depositing the second insulating material on the second active structure and the first semiconductor material layer, the formed second semiconductor material layer can wrap the second active structure and cover the first semiconductor material layer at the same time.

[0059] In the embodiments of the present application, the second insulating material is a different insulating material from the first insulating material. For the convenience of description, the following takes the second insulating material as silicon nitride (SiN) as an example for illustration. It should be noted that the second insulating material may also be other insulating materials. The embodiments of the present application do not make specific limitations on this.

[0060] S105. Remove a part of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer.

[0061] It can be understood that in the subsequent manufacturing process, it is necessary to expose the isolation active structure. Therefore, in the order of stacking of each material layer, first remove that part of the second semiconductor material layer covering the first semiconductor material layer (that is, the part of the second semiconductor material layer covering the first semiconductor material layer) to expose the first semiconductor layer, so as to facilitate the subsequent removal of the first semiconductor material layer.

[0062] S106. Remove the first semiconductor material layer to expose the isolation active structure.

[0063] Understandably, after exposing the first semiconductor material, the first semiconductor material layer is removed to expose the isolation active structure, facilitating the subsequent oxidation process.

[0064] S107, perform an oxidation process on the isolation active structure to form an isolation dielectric structure.

[0065] Understandably, through the oxidation process, the material of the isolation active structure is oxidized into another material different from the first active structure and the second active structure, and the isolation active structure is transformed into an isolation dielectric structure. Due to the difference in materials, the isolation dielectric structure can be used to isolate the first active structure and the second active structure.

[0066] In the embodiments of the present application, since the isolation dielectric structure is located between the first active structure and the second active structure, and the material of the isolation dielectric structure formed by the oxidation process is different from the materials of the first active structure and the second active structure, the isolation dielectric structure can achieve isolation between the active regions of the first transistor and the second transistor.

[0067] In the embodiments of the present application, the active region is a collective term for the source region, the drain region, and the channel region.

[0068] S108, remove a part of the second semiconductor material layer covering the second active structure to expose the second active structure.

[0069] Understandably, in the above S105, the entire second semiconductor material layer is not removed, and a part of the second semiconductor material layer still surrounds the surface of the second active structure. After removing this part of the second semiconductor material layer, the second active structure can be exposed, facilitating the subsequent preparation of the second transistor.

[0070] S109, form a second transistor based on the second active structure.

[0071] In some possible implementation manners, the above S109 may include: based on the second active structure, sequentially forming a second dummy gate structure, second spacer walls, second source / drain structures, and a second interlayer dielectric layer of the second transistor; removing the second dummy gate structure, and forming a second gate structure and a second gate dielectric layer; performing back-end process treatment on the second interlayer dielectric layer to form a second metal interconnect layer.

[0072] It should be noted that the process of preparing the second transistor is the same as the process of preparing the first transistor described above, and the embodiments of the present application will not elaborate herein.

[0073] In some possible embodiments, before the above-mentioned S102, the above method may further include: depositing a dielectric material on the first active structure, the isolation active structure, and the second active structure to form a shallow trench isolation structure; the shallow trench isolation structure encapsulates the first active structure, the isolation active structure, and the second active structure; removing a first portion of the shallow trench isolation structure to expose the first active structure; before forming the second transistor based on the second active structure, the above method may further include: flipping the wafer and removing the substrate.

[0074] In the embodiments of the present application, the dielectric material (i.e., insulating material) for forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si 3 N 4 ), silicon dioxide (SiO 2 ), or silicon carbon oxide (SiCO), etc., or may be other insulating materials, and the embodiments of the present application do not make specific limitations thereto.

[0075] In some embodiments, after forming the shallow trench isolation structure, the above method may further include: performing chemical-mechanical planarization (CMP) processing on the shallow trench isolation structure.

[0076] In the embodiments of the present application, performing chemical-mechanical planarization processing on the shallow trench isolation structure can make the corrosion depths corresponding to the shallow trench isolation structures in different regions the same when etching the shallow trench isolation structure subsequently, so that the top heights of the exposed active structures are the same.

[0077] It should be noted that the etching process mentioned in the embodiments of the present application may include any one of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal process, and the embodiments of the present application do not make limitations thereto.

[0078] In the embodiments of the present application, the solvent used for etching the shallow trench isolation structure may be: DHF solution or BOE solution. The solvent adopted in the etching process in the embodiments of the present application can be selected according to actual situations and is not limited to the above DHF solution or BOE solution.

[0079] In some possible embodiments, after the above-mentioned flipping the wafer and removing the substrate, and before forming the first semiconductor material layer, the above method may further include: removing a portion of the second active structure away from the first active structure to form a first groove; depositing a second insulating material in the first groove to form a first filling structure; removing a second portion of the shallow trench isolation structure to expose the second active structure and the isolation active structure.

[0080] It can be understood that after removing the substrate, the shallow trench isolation structure is exposed. At this time, the shallow trench isolation structure and the second active structure have the same horizontal height in the direction perpendicular to the substrate. Then, a part of the second active structure can be etched by selective etching to form a first groove.

[0081] Among them, the etching height (i.e., the height of the first groove) can be set according to the actual situation, and the embodiments of the present application do not make specific limitations on this.

[0082] In some embodiments, a second insulating material is deposited together in the first groove and above the shallow trench isolation structure. After deposition, the second insulating material fills the first groove and covers the surface of the shallow trench isolation structure; then, the deposited second insulating material is subjected to CMP treatment, and the CMP stops at the surface of the shallow trench isolation structure, and the second insulating material in the first groove is not removed, forming a first filling structure.

[0083] In some embodiments, the shallow trench isolation structure is composed of a first part and a second part. The first part wraps the first active structure, and the second part wraps the second active structure and the isolation active structure.

[0084] In some possible implementation manners, in the case of forming the above first filling structure, S105 may include: removing a part of the second semiconductor material layer covering the first semiconductor material layer and a part of the second semiconductor material layer covering the first filling structure to expose the first semiconductor material layer and the first filling structure.

[0085] It can be understood that the second semiconductor material layer covers the surfaces of the first filling structure, the first semiconductor material layer, and the first active structure. Since both the second semiconductor material layer and the first filling structure use the second insulating material (taking SiN as an example), the thickness of the SiN material on the second surface of the second active structure (i.e., the side of the second active structure away from the first active structure) is greater than the thickness of the SiN material on the first semiconductor material layer. At this time, the SiN material covering the first semiconductor material layer and a part of the SiN material on the second surface of the second active structure can be removed by anisotropic etching, and the remaining SiN material wraps the surface of the second active structure.

[0086] In some possible implementation manners, in the case of forming the above first filling structure, after S107, the method may further include: removing the first filling structure and the second semiconductor material layer to expose the second active structure; forming a second transistor based on the second active structure.

[0087] It can be understood that taking the second insulating material as SiN material as an example, after forming the isolation dielectric structure, the SiN material covering the surface of the second active structure is removed to expose the second active structure, so as to facilitate the subsequent preparation of the second transistor.

[0088] In some possible implementation manners, without forming the above-mentioned first filling structure, S105 may include: removing a part of the second semiconductor material layer covering the first semiconductor material layer and a part of the second semiconductor material layer covering the second surface of the second active structure to expose the first semiconductor material layer and the second surface. Wherein, the second surface is the surface of the second active structure away from the first active structure.

[0089] It can be understood that taking the second insulating material as SiN material as an example, after depositing (such as atomic layer deposition) a layer of SiN material on the surface of the second active structure and the first semiconductor material layer, the deposited SiN material is the second semiconductor material layer, and the second semiconductor material layer wraps the second active structure and covers the first semiconductor material layer. Then, the SiN material on the second surface of the second active structure and the first semiconductor material layer can be removed by anisotropic etching. After the etching is completed, the remaining SiN material is located on the side surface of the second active structure (that is, the surface of the second active structure except for the second surface and the surface in contact with the isolation active structure).

[0090] In some possible implementation manners, without forming the above-mentioned first filling structure, after S106, the method may further include: depositing a second insulating material on the second surface and the first region of the first surface to form a third semiconductor material layer. Wherein, the first region is not in contact with the second active structure.

[0091] It can be understood that taking the second insulating material as SiN material as an example, after removing the first semiconductor material layer, a layer of SiN material (such as physical vapor deposition) is deposited on the second surface of the second active structure and the region (i.e., the first region) on the first surface that is not in contact with the isolation active structure to form a third semiconductor material layer. The third semiconductor material layer is not in contact with the isolation active structure. While exposing the isolation active structure, the third semiconductor material layer and the second semiconductor material layer jointly wrap the second active structure. In this way, the second active structure can be protected from oxidation during the subsequent oxidation process.

[0092] In some possible implementation manners, without forming the above-mentioned first filling structure, after S107, the method may further include: removing the second semiconductor material layer and the third semiconductor material layer to expose the second active structure; forming a second transistor based on the second active structure.

[0093] Understandably, taking the second insulating material as SiN material as an example, after forming the isolation dielectric structure, the SiN material wrapped on the surface of the second active structure and the first surface of the first transistor is removed, and the second active structure is exposed, facilitating the subsequent preparation of the second transistor.

[0094] Next, taking the first transistor and the second transistor as fin field-effect transistors as an example, the stacked transistor provided by the embodiment of the present application will be described. Figure 2 It is a schematic diagram of the first structure of the stacked transistor in the embodiment of the present application. Among them, Figure 2 in (a) is the design layout of the stacked transistor. It should be noted that for the convenience of understanding, only the fin structure, gate structure, and source-drain structure are shown in the design layout; (b) is the cross-sectional view of the stacked transistor taken along the cross-sectional direction of the gate structure (i.e., the A-A' direction); (c) is the cross-sectional view of the stacked transistor taken along the cross-sectional direction of the source-drain structure (i.e., the B-B' direction); (d) is the cross-sectional view of the stacked transistor taken along the cross-sectional direction of the fin structure (i.e., the C-C' direction).

[0095] Refer to Figure 2 As shown, the stacked transistor 10 includes a first transistor 11, a second transistor 12, and an isolation dielectric structure 13; among them, the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed by the same process, and the first transistor 11 and the second transistor 12 are self-aligned; the isolation dielectric structure 13 is used to isolate the first active structure 111 and the second active structure 121, and the isolation dielectric structure 13 is located between the first active structure 111 and the second active structure 121.

[0096] In the embodiment of the present application, since the first active structure 111 of the first transistor 11 and the second active structure 121 of the second transistor 12 are formed by the same etching process, the self-alignment of the first transistor 11 and the second transistor 12 can be achieved.

[0097] Next, in combination with the above preparation method, the Figure 2 preparation process of the stacked transistor shown will be described. Figure 2 The stacked transistor shown can be prepared through the Figures 3A to 3F process shown, Figures 3A to 3F It is a schematic diagram of the first preparation process of the stacked transistor in the embodiment of the present application.

[0098] In an example, taking the first transistor 11 and the second transistor 12 as fin field-effect transistors as an example, the first preparation process of the stacked transistor 10 may include the following steps:

[0099] The first step: Provide a substrate 21 (such as a Si substrate) (refer to Figure 3A(a) in

[0100] Step 2: Etch the substrate 21 to form a plurality of fin structures 22, and deposit a dielectric material on the plurality of fin structures 22 to form a shallow trench isolation structure 23 (see Figure 3A (b) in

[0101] Among them, as shown in Figure 3A (b), the fin structure 22 is composed of a first fin structure 221, a second fin structure 222, and an isolation active structure 223; the shallow trench isolation structure 23 is composed of a first part 231 of the shallow trench isolation structure, a second part 232 of the shallow trench isolation structure, and a shallow trench isolation layer 233.

[0102] Step 3: Remove the first part 231 of the shallow trench isolation structure to expose the first fin structure 221; then, sequentially form the first dummy gate structure, the first spacer 112, the first source / drain structure 113, and the first interlayer dielectric layer 114 in the first transistor 11 according to standard steps; after removing the first dummy gate structure, form a first gate dielectric layer 115, a first gate structure 116, and a first metal interconnect layer 117 (see Figure 3A (c) in

[0103] Step 4: Deposit an oxide above the first metal interconnect layer 117 to form a first insulating layer 14, and bond the first insulating layer 14 to the carrier wafer 15. Then, flip the first transistor 11 after bonding the carrier wafer 15 so that the substrate 21 faces upward (see Figure 3B (a) in

[0104] Step 5: Perform wafer thinning on the substrate 21 until the substrate 21 is removed, exposing the surface of the second fin structure 222 away from the first fin structure 221 (see Figure 3B (b) in

[0105] Step 6: Remove a part of the second fin structure 222 by selective etching to form a first groove 24 (see Figure 3B (c) in

[0106] Step 7: Deposit SiN material (not shown in the figure) in the first groove 24 and on the second part 232 of the shallow trench isolation structure, and perform CMP processing on the deposited SiN material until the CMP stops at the surface of the second part 232 of the shallow trench isolation structure; after the CMP processing, form a first filling structure 25 (see Figure 3C (a) in

[0107] Step 8: Remove the second part 232 of the shallow trench isolation structure by etching to expose the second fin structure 222 and the shallow trench isolation layer 233 (see Figure 3C (b) in

[0108] In the embodiment of the present application, the shallow trench isolation layer 233 is used to isolate the first transistor 11 and the second transistor 12.

[0109] Ninth step: Deposit amorphous carbon on the shallow trench isolation layer 233 to form the first semiconductor material layer 31 (see (c) in Figure 3C .

[0110] Tenth step: Atomic layer deposit a layer of SiN material on the first semiconductor material layer 31 and the surface of the second fin structure 222 to form the second semiconductor material layer 32. Among them, due to the first filling structure 25, the thickness of the SiN material on the surface of the second fin structure 222 far from the first fin structure 221 is greater than the thickness of the SiN material on the remaining surfaces (see (a) in Figure 3D .

[0111] Eleventh step: Remove the SiN material on the surface of the second fin structure 222 far from the first fin structure 221 and on the first semiconductor material layer 31 by anisotropic etching (see (b) in Figure 3D .

[0112] Twelfth step: Remove the first semiconductor material layer 31 by isotropic etching to expose the isolation active structure 223 (see (c) in Figure 3D .

[0113] Thirteenth step: Oxidize the isolation active structure 223 to form the isolation dielectric structure 13 (see (a) in Figure 3E .

[0114] Fourteenth step: Remove the SiN material on the surface of the second fin structure 222 by isotropic etching (see (b) in Figure 3E .

[0115] Fifteenth step: Adopt standard steps to form the second dummy gate structure 128 of the second transistor 12 (see (c) in Figure 3E .

[0116] Sixteenth step: Adopt standard steps to sequentially prepare the second spacer 122, the second source / drain structure 123, and the second interlayer dielectric layer 124 in the second transistor 12 (see (a) in Figure 3F .

[0117] Seventeenth step: Remove the second dummy gate structure 128 to expose the gate region of the second transistor 12, deposit an insulating material at the connection between the gate region and the second fin structure 222 to form the second gate dielectric layer 125; deposit a metal material in the gate region to form the second gate structure 126 (see (b) in Figure 3F .

[0118] The eighteenth step: Perform post-process treatment on the second interlayer dielectric layer 124 to form the second metal interconnect layer 127 (see (c) in Figure 3F ).

[0119] Thus, the first transistor 11 and the second transistor 12 are fin field-effect transistors prepared by the above first preparation method, and the stacked transistor 10 in which the first active structure 111 and the second active structure 121 are isolated by the isolation dielectric structure 13 is completed.

[0120] The above Figures 3A to 3F shown preparation process is only one example of the stacked transistor in the embodiments of the present application. The stacked transistor in the embodiments of the present application can also be prepared by the process shown in Figures 4A to 4D , Figures 4A to 4D which is a schematic diagram of the second preparation process of the stacked transistor in the embodiments of the present application.

[0121] In one example, taking the first transistor 11 and the second transistor 12 as fin field-effect transistors as an example, the first preparation process of the stacked transistor 10 may include the following steps:

[0122] The first step: Provide a substrate 21 (such as an Si substrate); form a plurality of fin structures 22 and a shallow trench isolation structure 23; form the first transistor 11; flip the first transistor 11 after bonding the carrier wafer 15 so that the substrate 21 is placed upward; remove the substrate 21 to expose the surface of the second fin structure 222 away from the first fin structure 221 (the specific process can refer to the first to fifth steps in the first preparation process of the above stacked transistor) (see (a) in Figure 4A ).

[0123] The second step: Remove the second part 232 of the shallow trench isolation structure to expose the second fin structure 222, the isolation active structure 223 and the shallow trench isolation layer 233 (see (b) in Figure 4A ).

[0124] The third step: Deposit amorphous carbon on the shallow trench isolation layer 233 to form the first semiconductor material layer 31 (see (c) in Figure 4A ).

[0125] The fourth step: Atomic layer deposit a layer of SiN material on the first semiconductor material layer 31 and the surface of the second fin structure 222 to form the second semiconductor material layer 32 (see (a) in Figure 4B ).

[0126] Step 5: By anisotropic etching, remove the SiN material on the surface of the second fin structure 222 away from the first fin structure 221 and the SiN material on the first semiconductor material layer 31 (see (b) in Figure 4B ).

[0127] Step 6: By anisotropic etching, remove the first semiconductor material layer 31 (see (c) in Figure 4B ).

[0128] Step 7: Deposit SiN material on the surface of the second fin structure 222 away from the first fin structure 221 and on a part of the shallow trench isolation layer 233 (the area not in contact with the isolation active structure 223) to form the third semiconductor material layer 33 (see (a) in Figure 4C ).

[0129] Step 8: Oxidize the exposed isolation active structure 223 to form the isolation dielectric structure 13 (see (b) in Figure 4C ).

[0130] Step 9: Remove the second semiconductor material layer 32 and the third semiconductor material layer 33 to expose the second fin structure 222 (see (c) in Figure 4C ).

[0131] Step 10: Form the second transistor 12 (for the specific process, refer to Steps 15 to 17 in the first preparation process of the above stacked transistors) (see Figure 4D ).

[0132] So far, the stacked transistor 10 in which the first transistor 11 and the second transistor 12 are fin field-effect transistors and the first active structure 111 and the second active structure 121 are isolated by the isolation dielectric structure 13 has been prepared by the above second preparation method.

[0133] It should be noted that when the stacked transistor is a fully surrounding gate transistor, a planar transistor, or a vertical transistor, the preparation method of the stacked transistor is the same as that of the stacked transistor being a fin field-effect transistor in the above embodiments, and the embodiments of the present application will not elaborate on this.

[0134] In the embodiments of the present application, by oxidizing the isolation active structure located between the first active structure and the second active structure to form the isolation dielectric structure, the isolation between the active regions of the first transistor and the second transistor can be achieved without damaging the device structure.

[0135] Furthermore, compared with traditional ion implantation and isolation methods using silicon-on-insulator (SOI), the process for fabricating the isolation dielectric structure in the embodiments of the present application is simpler, and at the same time takes into account the self-alignment problems of the first transistor and the second transistor, ensuring the consistency of the active regions of the first transistor and the second transistor.

[0136] Furthermore, the stacked transistor provided in the embodiments of the present application can be detected using detection and analysis instruments, such as: scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the stacked transistor provided in the embodiments of the present application can be sliced by TEM to detect the isolation dielectric structure located between the first active structure and the second active structure.

[0137] In the embodiments of the present application, the isolation dielectric structure may not be rectangular, but elliptical or other shapes, and the embodiments of the present application do not make specific limitations in this regard. And through TEM slicing, it can be observed that the growth quality of the material of the isolation dielectric structure (i.e., SiO x ) may be non-uniform.

[0138] The embodiments of the present application provide a semiconductor device, including: a stacked transistor as described in the above embodiments. For the specific limitations of the stacked transistor, reference can be made to the Figure 2 stacked transistor shown above, which will not be elaborated here.

[0139] The embodiments of the present application provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above-mentioned stacked transistor. For the specific limitations of the stacked transistor, reference can be made to the Figure 2 stacked transistor shown above, which will not be elaborated here.

[0140] In the description of the present application, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expression of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine the different embodiments or examples described in the present application and the features of different embodiments or examples.

[0141] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: A first active structure, an isolation active structure and a second active structure are sequentially stacked on a substrate; Based on the first active structure, forming a first transistor; Depositing a first insulating material on a first surface of the first transistor facing the second active structure to form a first semiconductor material layer; the first semiconductor material layer surrounds the isolation active structure; Depositing a second insulating material on the second active structure and the first semiconductor material layer to form a second semiconductor material layer; the second semiconductor material layer wraps the second active structure; removing a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer; removing the first semiconductor material layer to expose the isolation active structure; performing oxidation treatment on the isolation active structure to form an isolation dielectric structure; removing a portion of the second semiconductor material layer covering the second active structure to expose the second active structure; Based on the second active structure, a second transistor is formed.

2. The method according to claim 1, characterized in that Before forming the first transistor based on the first active structure, the method further includes: depositing a dielectric material on the first active structure, the isolation active structure and the second active structure to form a shallow trench isolation structure; the shallow trench isolation structure wraps the first active structure, the isolation active structure and the second active structure; removing a first portion of the shallow trench isolation structure to expose the first active structure; Before forming the second transistor based on the second active structure, the method further includes: flipping the wafer and removing the substrate.

3. The method according to claim 2, characterized in that After flipping the wafer and removing the substrate, and before forming the first semiconductor material layer, the method further includes: removing a portion of the second active structure away from the first active structure to form a first groove; depositing the second insulating material in the first groove to form a first filling structure; A second portion of the shallow trench isolation structure is removed to expose the second active structure and the isolation active structure.

4. The method according to claim 3, characterized in that The removing a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer comprises: A portion of the second semiconductor material layer covering the first semiconductor material layer and a portion of the second semiconductor material layer covering the first filling structure are removed to expose the first semiconductor material layer and the first filling structure.

5. The method according to claim 4, characterized in that After the isolation active structure is oxidized to form an isolation dielectric structure, the method further includes: removing the first filling structure and the second semiconductor material layer to expose the second active structure; Based on the second active structure, the second transistor is formed.

6. The method according to claim 2, characterized in that The removing a portion of the second semiconductor material layer covering the first semiconductor material layer to expose the first semiconductor material layer comprises: A portion of the second semiconductor material layer covering the first semiconductor material layer and a portion of the second semiconductor material layer covering the second surface of the second active structure are removed to expose the first semiconductor material layer and the second surface; the second surface is a surface of the second active structure away from the first active structure.

7. The method according to claim 6, characterized in that After removing the first semiconductor material layer to expose the isolation active structure, the method further includes: A second insulating material is deposited on the second surface and a first region of the first surface to form a third semiconductor material layer; the first region is not in contact with the second active structure.

8. The method according to claim 7, characterized in that After the isolation active structure is oxidized to form an isolation dielectric structure, the method further includes: removing the second semiconductor material layer and the third semiconductor material layer to expose the second active structure; Based on the second active structure, the second transistor is formed.

9. The method according to claim 1, characterized in that: The forming of the first transistor based on the first active structure includes: Based on the first active structure, a first dummy gate structure, a first spacer, a first source-drain structure and a first interlayer dielectric layer of a first transistor are sequentially formed; removing the first dummy gate structure, and forming a first gate structure and a first gate dielectric layer; A back-end process is performed on the first interlayer dielectric layer to form a first metal interconnection layer.

10. The method according to claim 1, characterized in that The forming of the second transistor based on the second active structure comprises: Based on the second active structure, a second dummy gate structure, a second spacer, a second source-drain structure and a second interlayer dielectric layer of the second transistor are sequentially formed; removing the second dummy gate structure, and forming a second gate structure and a second gate dielectric layer; A back-end process is performed on the second interlayer dielectric layer to form a second metal interconnection layer.

11. A stacked transistor, characterized in that: The stacked transistor is prepared by the method for preparing the stacked transistor according to any one of claims 1 to 10, wherein the stacked transistor comprises: a first transistor; a second transistor; a first active structure of the first transistor and a second active structure of the second transistor are formed by a same process, and the first transistor and the second transistor are self-aligned; An isolation dielectric structure, the isolation dielectric structure is used to isolate the first active structure from the second active structure, and the isolation dielectric structure is located between the first active structure and the second active structure; the isolation dielectric structure is obtained by oxidizing the isolation active structure located between the first active structure and the second active structure.

12. A semiconductor device, characterized in that: include: The stacked transistor of claim 11.

13. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 12, wherein the semiconductor device is arranged on the circuit board.

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