Shallow trench preparation method, shallow trench isolation structure preparation method, semiconductor device

Abstract

The present invention provides a method for preparing a shallow trench, a method for preparing a shallow trench isolation structure, and a semiconductor device; the method includes: providing a silicon substrate; sequentially forming a pad silicon dioxide layer and a silicon nitride layer on the silicon substrate in a direction away from the silicon substrate; forming a patterned first mask layer on the silicon nitride layer and the pad silicon dioxide; wherein, the first mask layer includes a first window region and a blocking region; using the first mask layer as a mask to etch the silicon nitride layer and the pad silicon dioxide layer located in the first window region in sequence, and stopping the etching end point on the surface of the silicon substrate; performing an etch-back on the silicon nitride layer by wet etching to expose the pad silicon dioxide layer below the silicon nitride, so as to form a second hard mask layer including a second window region; using the second hard mask layer as a mask to etch the pad silicon dioxide layer and the silicon substrate within the second window, rounding at least the top corners of the edges of the shallow trench covered under part of the pad silicon dioxide layer, and forming a shallow trench with a preset depth.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a method for preparing a shallow trench, a method for preparing a shallow trench isolation structure, and a semiconductor device. Background Art

[0002] In order to meet the continuously increasing integration requirements in integrated circuits, semiconductor isolation technology has evolved from the earliest pn junction isolation technology to shallow trench isolation technology (STI technology - Shallow Trench Isolation technology).

[0003] Among them, the STI technology requires first forming a shallow trench structure; then depositing field oxide silicon dioxide in the shallow trench structure through a high-density plasma chemical vapor deposition process (HDP CVD process - High Density Plasma Chemical Vapor Deposition process) to form a field oxide to isolate devices; and finally removing the excess silicon dioxide and silicon nitride.

[0004] As the semiconductor process size continues to break through, the aspect ratio of the shallow trench is also continuously increasing.

[0005] For shallow trenches with an aspect ratio greater than 6:1, the silicon dioxide filled by the HDP CVD process has relatively serious voids and cannot meet the process requirements. Therefore, after entering the 65nm process node, the high aspect ratio process (HARP - High Aspect Ratio Process) is adopted in the art to replace the HDP CVD process to improve the filling quality of silicon dioxide in the shallow trench.

[0006] In addition, during the process of forming the shallow trench structure, increasing the curvature radius of the active region apex is also very important for the performance and yield of the device. If the curvature radius is too small and the apex is too sharp, a high edge electric field will be generated at the sidewall of the shallow trench isolation, resulting in a high leakage current, which shows a "double hump" when testing the Id-Vg curve, that is, there is a phenomenon of instantaneous current increase before the gate voltage reaches the threshold voltage.

[0007] Therefore, before filling the shallow trench by the HARP process, the prior art in the art usually performs silicon nitride back-etching after the shallow trench etching is completed, and then performs sidewall oxidation of the trench. On the one hand, the sidewall oxidation of the trench is to increase the curvature radius of the active region apex, and on the other hand, the silicon nitride back-etching is beneficial to increasing the window for filling the subsequent insulating medium and improving the filling efficiency. However, the problems of this solution are as follows:

[0008] (1) The amplitude of increasing the curvature radius of the active region apex by the sidewall oxidation of the trench is limited and cannot effectively improve the "double hump" problem.

[0009] (2) When performing silicon nitride etch-back, the acidic solution used for etch-back will come into extensive contact with the sidewalls of the shallow trench, which may cause unknown defects in the silicon substrate.

[0010] Therefore, providing a method for preparing a trench that can achieve significant rounding and reduce the risk of substrate defects has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0011] To solve the above problems, the present invention provides a method for preparing a trench, a trench structure, and a semiconductor device.

[0012] According to the first aspect of the present invention, a method for preparing a shallow trench is provided, including:

[0013] Providing a silicon substrate;

[0014] Forming a pad silicon dioxide layer and a silicon nitride layer on the silicon substrate in sequence in a direction away from the silicon substrate;

[0015] Forming a patterned first mask layer on the silicon nitride layer and the pad silicon dioxide; wherein, the first mask layer includes a first window region and a blocking region;

[0016] Using the first mask layer as a mask to perform dry etching on the silicon nitride layer and the pad silicon dioxide layer located in the first window region in sequence, and stopping the etching end point on the surface of the silicon substrate;

[0017] Performing etch-back on the silicon nitride layer by wet etching to expose the pad silicon dioxide layer below the silicon nitride, so as to form a second hard mask layer including a second window region;

[0018] Using the second hard mask layer as a mask to perform dry etching on the pad silicon dioxide layer and the silicon substrate within the second window, rounding at least the top corners of the edges of the shallow trench covered by the pad silicon dioxide layer, and forming a shallow trench with a preset depth.

[0019] Optionally, forming the pad silicon dioxide layer on the silicon substrate specifically includes:

[0020] Placing the silicon substrate in a furnace tube, introducing oxygen at a first temperature to form the pad silicon dioxide layer on the silicon substrate.

[0021] Optionally, forming the silicon nitride layer on the pad silicon dioxide layer specifically includes:

[0022] Introducing SiH4 and NH3 gases into the furnace tube, reacting to generate Si3N4, and depositing on the surface of the pad silicon dioxide layer to form a silicon nitride layer.

[0023] Optionally, forming the first mask layer on the silicon nitride layer and the pad silicon dioxide layer specifically includes:

[0024] Spin-coating a photoresist layer on the silicon nitride layer;

[0025] Exposing and developing the photoresist layer to form a patterned photoresist of the first mask layer;

[0026] Dry-etching the silicon nitride layer and the pad silicon dioxide layer to form the silicon nitride and the pad silicon dioxide of the first mask layer pattern.

[0027] Optionally, the etching selectivity of the silicon substrate compared to the pad silicon dioxide layer satisfies that when the shallow trench etching depth reaches 75% - 99% of the final depth, at least part / fully of the exposed part of the pad silicon dioxide layer is consumed.

[0028] Optionally, after forming the shallow trench, it further includes: forming a sidewall oxide layer on the sidewalls of the shallow trench by using a high-temperature furnace tube process.

[0029] According to the second aspect of the present invention, there is provided a method for preparing a shallow trench isolation structure, including:

[0030] Preparing a shallow trench by the shallow trench preparation method provided by the first aspect and optional solutions of the present invention;

[0031] Filling an insulating medium in the shallow trench to form a shallow trench isolation structure.

[0032] Optionally, filling an insulating medium in the shallow trench to form a shallow trench isolation structure specifically includes:

[0033] Filling an insulating medium in the shallow trench until the insulating medium covers the silicon nitride layer to form an insulating medium layer;

[0034] Performing a high-temperature annealing on the insulating medium layer;

[0035] Grinding the insulating medium layer to completely expose the silicon nitride layer;

[0036] Removing the silicon nitride layer by a wet etching process.

[0037] Optionally, grinding the insulating medium layer specifically includes: grinding the surface of the insulating medium layer to be lower than the silicon nitride layer by a CMP process to completely expose the silicon nitride layer.

[0038] Optionally, the process of filling the insulating medium specifically includes: a high aspect ratio process.

[0039] According to a third aspect of the present invention, there is provided a semiconductor device including a shallow trench isolation structure prepared by the method for preparing a shallow trench isolation structure provided in the second aspect and optional solutions of the present invention.

[0040] In the method for preparing a trench provided by the present invention, after dry etching the silicon nitride layer and the pad silicon dioxide layer in sequence, the silicon nitride layer is first etched back to expose the pad silicon dioxide layer below the silicon nitride; then, using the silicon nitride layer and the exposed part of the pad silicon dioxide layer as a mask, the pad silicon dioxide layer and the silicon substrate are dry etched to round at least the top corners of the edges of the shallow trench covered under the pad silicon dioxide layer and form a shallow trench with a preset depth. By first etching back the silicon nitride and then etching the shallow trench, when etching the silicon substrate using the silicon nitride layer and the exposed pad silicon dioxide layer as a hard mask, the pad silicon dioxide serving as the hard mask is also slowly consumed and is completely etched away or partially etched away before the shallow trench etching is completed, so that the edges of the shallow trench are completely exposed or partially exposed. Since the etching rate of the edge top corners is faster than that of the inside of the shallow trench, the exposed part of the shallow trench edge is consumed, making the top corners of the trench edge have a larger radius of curvature, realizing the rounding of the top corners of the active region, which is beneficial to the subsequent deposition of trench oxide and is not likely to have a hanging effect. In addition, since this method first etches back the silicon nitride and then etches the shallow trench, it avoids the defects inside the silicon substrate caused by the etching liquid coming into contact with the inside of the silicon substrate during the etching back of the silicon nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0042] Figure 1 is a flowchart of a prior art method for preparing a shallow trench;

[0043] Figure 2 is the process of the method for preparing a shallow trench provided by the first embodiment of the present invention Figure 1 ;

[0044] Figure 3 is the process of the method for preparing a shallow trench provided by the first embodiment of the present invention Figure 2 ;

[0045] Figure 4 is the process of the method for preparing a shallow trench isolation structure provided by the second embodiment of the present invention Figure 1 ;

[0046] Figures 5 - 11 is Figure 2 a schematic diagram of the device structure corresponding to the method for preparing a shallow trench provided at different process stages;

[0047] Figure 12 The Figure 3 device structure schematic diagram corresponding to the shallow trench preparation method provided in step S27;

[0048] Figures 13 - 15 The Figure 1 device structure schematic diagrams corresponding to the shallow trench preparation method provided by the prior art at different process stages;

[0049] Figures 16 - 18 The Figure 4 device structure schematic diagrams corresponding to the shallow trench isolation structure preparation method provided at different process stages.

[0050] Reference numerals:

[0051] 101 - silicon substrate;

[0052] 102 - pad silicon dioxide layer;

[0053] 103 - silicon nitride layer;

[0054] 103a - second window area;

[0055] 104 - first mask layer;

[0056] 104a - first window area;

[0057] 105 - sidewall oxide layer;

[0058] 301 - insulating dielectric layer. Detailed implementation manners

[0059] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0060] Please refer to Figure 1 , and in combination with Figures 13 - 15 , the specific steps of the shallow trench etching process in the prior art are as follows:

[0061] S11: Provide a silicon substrate.

[0062] S12: Sequentially form a pad silicon dioxide layer and a silicon nitride layer on the silicon substrate in a direction away from the silicon substrate.

[0063] S13: Form a patterned photoresist layer on the silicon nitride layer and the pad silicon dioxide layer; wherein, the photoresist layer includes a window area and a blocking area.

[0064] S14: Use the photoresist layer as a mask to sequentially perform dry etching on the silicon nitride layer and the pad silicon dioxide layer located in the window area, and stop the etching endpoint on the surface of the silicon substrate.

[0065] Among them, since steps S11 to S14 are similar to the following steps S21 to S24, the schematic diagrams of the device structures corresponding to each step of steps S11 to S14 can be referred to Figures 5 to 8 , and will not be elaborated here.

[0066] S15: Use the silicon nitride layer and the pad silicon dioxide layer as a hard mask to etch the silicon substrate to form a shallow trench with a preset depth, as Figure 13 shown.

[0067] S16: Use phosphoric acid to etch back the silicon nitride layer to expose the pad silicon dioxide layer below the silicon nitride, as Figure 14 shown.

[0068] S17: Oxidize the sidewalls of the shallow trench to generate a sidewall oxide layer, as Figure 15 shown.

[0069] Among them, Figures 13 to 15 The marks 201, 201a, 202, 203, 205 that appear in respectively correspond to the silicon substrate, shallow trench, pad silicon dioxide layer, silicon nitride layer, and sidewall oxide in the above steps.

[0070] In the above-mentioned existing shallow trench etching process, the silicon nitride layer has always remained on the surface of the shallow trench edge, resulting in the inability to expose the top corners of the shallow trench edge, that is, the top corners of the active region edge cannot be exposed. For the convenience of description, the names of the top corners of the following shallow trench edges are all replaced by the top corners of the active region edge. Therefore, after the shallow trench is formed, the top corners of the active region edge are still sharp top corners. Although the formation of sidewall oxide will partially oxidize the top corners of the shallow trench edge, it is still impossible to significantly increase the curvature radius of the top corners of the active region edge. At the same time, in the prior art, the silicon nitride layer is etched back after the shallow trench etching of the silicon substrate, which will cause a large amount of phosphoric acid to contact the sidewalls of the shallow trenches of the silicon substrate, thereby possibly causing defects inside the silicon substrate. Although the etching back of the silicon nitride layer usually uses phosphoric acid with a high etching selectivity for silicon nitride, it is still impossible to completely avoid the possibility of generating defects inside the silicon substrate.

[0071] In view of this, through repeated experiments and demonstrations, the inventors of the present invention have proposed a new method for preparing trenches, which is specifically as follows: After sequentially dry-etching the silicon nitride layer and the pad silicon dioxide layer located in the first window region using a photoresist layer as a mask, the present invention first uses wet etching to etch back the silicon nitride layer to expose the pad silicon dioxide layer below the silicon nitride; then, using the silicon nitride layer and the exposed part of the pad silicon dioxide layer as a mask, dry-etch the pad silicon dioxide layer and the silicon substrate to round at least part of the top corners of the active region edge covered under the pad silicon dioxide layer and form a shallow trench with a preset depth.

[0072] It can be seen that for the technical solution provided by the present invention, on the one hand, by first etching back the silicon nitride and then etching the shallow trench, when using the exposed pad silicon dioxide layer as a hard mask to etch the silicon substrate, the pad silicon dioxide as the hard mask is also slowly consumed and is completely etched off or partially etched off before the completion of the shallow trench etching, so that the shallow trench edge is completely exposed or partially exposed. Since the etching rate of the edge top corner is faster than that of the inside of the shallow trench, the exposed part of the shallow trench edge is consumed, making the top corners of the trench edge have a larger curvature radius, that is, realizing the rounding of the active region top corners, which is conducive to the subsequent manufacturing process. On the other hand, since this method first etches back the silicon nitride and then etches the shallow trench, it avoids the defects inside the silicon substrate caused by the contact between the etching liquid used in the process of etching back the silicon nitride and the inside of the silicon substrate.

[0073] The technical solution of the present invention will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0074] Please refer to Figure 2 and in combination with Figures 5 - 11, the first embodiment of the present invention provides a method for preparing a trench, including:

[0075] S21: Provide a silicon substrate 101, as Figure 5 shown.

[0076] S22: Sequentially form a pad silicon dioxide layer 102 and a silicon nitride layer 103 on the silicon substrate 101 in a direction away from the silicon substrate 101, as Figure 6 shown.

[0077] Among them, as a specific implementation manner, S22 specifically includes:

[0078] S221: Grow the pad silicon dioxide layer 102 on the silicon substrate 101 by thermal oxidation. Specifically: Place the silicon substrate 101 in a furnace tube, and introduce high-purity oxygen at a high temperature of 600 - 1100 °C to grow a silicon dioxide thin film on the surface of the silicon substrate 101. Among them, the temperature and the purity of oxygen can be set accordingly according to the required thickness of the silicon dioxide thin film, and are not limited here.

[0079] S222: Deposit the silicon nitride layer 103 on the surface of the pad silicon dioxide layer 102. Specifically: At a high temperature of 600 °C, introduce silane gas and ammonia gas. These two gases will undergo a chemical reaction at high temperature to generate silicon nitride, and finally deposit on the pad silicon dioxide layer 102 to form a silicon nitride thin film. Of course, in addition to the above method for preparing the silicon nitride layer 103, other methods such as low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition are also included, and are not limited here.

[0080] S23: Form a patterned first mask layer 104 on the silicon nitride layer 103 and the pad silicon dioxide layer 102; among them, the first mask layer 104 includes a first window region 104a and a blocking region, as Figure 7 shown.

[0081] Among them, as a specific implementation manner, the patterned first mask layer 104 is a patterned photoresist layer. Based on this, S23 specifically includes: Spin-coat photoresist on the surface of the silicon nitride layer 103, and expose and develop the photoresist according to a photomask to form a first window region 104a and a blocking region, so as to form a patterned photoresist layer. Of course, the present invention is not limited thereto, and the first mask layer can also use other materials.

[0082] S24: Use the patterned first mask layer 104 as a mask to sequentially perform dry etching on the silicon nitride layer 103 and the pad silicon dioxide layer 102 located in the first window region 104a, and stop the etching end point on the surface of the silicon substrate 101, as Figure 8 shown.

[0083] Among them, as a specific implementation manner, S24 specifically includes: First, using the patterned first mask layer 104 as a mask, dry-etch the silicon nitride layer 103 exposed in the first window area 104a; after the exposed silicon nitride layer 103 is etched away, then dry-etch the exposed pad silicon dioxide layer 102 until the exposed pad silicon dioxide layer 102 is etched away, and the etching end point stops on the surface of the silicon substrate 101. Among them, the etching gas can be chlorine gas, or hydrogen bromide, or a mixed gas of the two. The specific gas can be selected according to requirements and is not limited herein. The specific methods of dry etching include: reactive ion etching, ion beam etching, plasma etching, etc. The specific method can be selected according to requirements and is not limited herein. Among them, after the etching of the exposed pad silicon dioxide layer 102 is completed, it further includes: removing the remaining first mask layer.

[0084] S25: Use wet etching to etch back the silicon nitride layer 103 to expose the pad silicon dioxide layer 102 below the silicon nitride, so as to form a second hard mask layer including a second window area 103a, as Figure 9 shown.

[0085] Among them, as a specific implementation manner, S25 specifically includes: Etch back the silicon nitride layer 103 through phosphoric acid to form a second window area 103a, so as to reduce the line width of the pattern of the silicon nitride layer 103 on the active region, and further expose the pad silicon dioxide layer 102 below the silicon nitride layer 103 to form a second hard mask layer. Among them, the etching-back degree of the silicon nitride layer 103 can be 5% of the shallow trench depth of the silicon substrate 101. Of course, the etching-back degree of the silicon nitride layer 103 can also be adaptively adjusted according to the depth of the shallow trench. For example, when the etching depth of the shallow trench is relatively deep, the etching-back degree of the silicon nitride layer 103 can be set to 6% of the shallow trench depth; vice versa. The specific setting can be adjusted according to requirements and is not limited herein.

[0086] S26: Using the second hard mask layer as a mask, dry-etch the pad silicon dioxide layer 102 and the silicon substrate 101 in the second window, round the top corners of at least part of the active region edge covered by the pad silicon dioxide layer 102, and form a shallow trench with a preset depth.

[0087] Among them, as a specific implementation manner, S26 specifically includes: etching the pad silicon dioxide serving as the second hard mask layer and the exposed silicon substrate 101 with a mixed gas of argon and halogen elements. Of course, the specific etching gas can also be adaptively modified and adjusted according to the specific process conditions, which is not limited here. Due to the selection of the corresponding etching gas, the etching selectivity of silicon to silicon dioxide is relatively large. Therefore, during the etching process, the etching rate of the silicon substrate 101 is relatively fast, while the etching rate of the pad silicon dioxide layer 102 is relatively slow. Please refer to as Figure 10 shown. At the initial stage of etching, the exposed silicon substrate 101 will be etched relatively fast, while the silicon substrate 101 under the second hard mask layer will be protected by the pad silicon dioxide and not be etched. As the etching continues, the pad silicon dioxide serving as the second hard mask layer will also be gradually etched. Please refer to as Figure 11 shown. Before forming a shallow trench with a preset depth, by controlling the etching selectivity of silicon to silicon dioxide, the pad silicon dioxide layer 102 serving as the second hard mask layer is completely etched or partially etched, so that the silicon substrate 101 under the second hard mask layer is completely exposed or partially exposed. At this time, there is a top corner structure on the silicon substrate 101 exposed on both sides of the trench; in the remaining etching process, obviously, the protruding top corner structure has a faster etching rate than the bottom of the shallow trench, so that the sharp corner of the top corner structure is etched off, thus completing the top corner rounding of the active region edge. Among them, the degree of top corner rounding of the active region edge can be controlled by controlling the etching selectivity of silicon to silicon dioxide, so that the pad silicon dioxide serving as the second hard mask layer is completely consumed or partially consumed when the etching depth of the shallow trench reaches 75% - 99% of the final depth. Of course, when the pad silicon dioxide serving as the second hard mask layer is completely consumed or partially consumed, the specific ratio at which the etching depth of the shallow trench reaches the final depth can be controlled according to the degree of rounding of the top corner of the active region, which is not limited here.

[0088] To ensure that the top corners of the active region can be significantly rounded at different etching depths, when the etching depth of the trench is relatively shallow, the etching selectivity of silicon to silicon dioxide can be reduced to shorten the protection time of the pad silicon dioxide serving as the second mask layer for the silicon substrate 101; when the etching depth of the trench is relatively deep, the etching selectivity of silicon to silicon dioxide can be increased to increase the protection time of the pad silicon dioxide serving as the second mask layer for the silicon substrate 101. Among them, the etching selectivity of silicon to silicon dioxide can be controlled by changing the composition or proportion of the etching gas. The specific control method is common knowledge in the art and will not be elaborated here.

[0089] As an example, in a 55nm semiconductor process, when etching a shallow trench with a depth of 400nm, a silicon dioxide layer with a thickness of 5nm is used as the second hard mask layer. At this time, by controlling the gas composition and ratio, the etching selectivity of silicon to silicon dioxide is controlled at about 60-78:1, so that when the shallow trench is etched to 300-390nm, the silicon dioxide as the second hard mask layer will be completely consumed or partially consumed. Then the top corners of the edge of the active area will be exposed to varying degrees. At this time, the top corner structure is more likely to receive the etching gas, so it is etched faster. When the shallow trench is etched to the target depth of 400nm, the top corners of the edge of the active area will be etched with a morphology with a larger radius of curvature.

[0090] As another example, when etching a groove with a depth of 1000nm, 5nm thick silicon dioxide is also selected as the second hard mask layer. At this time, by controlling the gas composition and ratio, the etching selectivity of silicon to silicon dioxide is controlled to about 160-198:1. In this way, when the shallow groove is etched to 800-990nm, the silicon dioxide as the second hard mask layer is completely consumed or partially consumed. Similarly, when the groove is etched to the target depth of 1000nm, the top corner of the edge of the active area will also be etched with a morphology with a larger radius of curvature. Of course, the above implementation is only a specific description of two situations, and the specific settings can be adaptively adjusted according to actual conditions, and are not limited here.

[0091] Please refer to Figure 3 , such as steps S21-S26, the shallow trench rounding is completed, and the shallow trench oxide deposition process is required to be performed later, such as step S27. Figures 5 - 12 As another embodiment of the present invention, a method for preparing a groove is provided in Figure 2 Based on the process shown in FIG. 1 , S27 is added: a high temperature furnace tube process is used to form a sidewall oxide layer 105 on the sidewall of the shallow trench to repair the damage caused by the trench etching to the silicon substrate 101; at the same time, the top angle of the active area can be made smoother. The corresponding device structure diagram after step S27 is completed is shown in FIG. Figure 12 In addition, the other steps of this embodiment and the device structure diagram corresponding to each step are the same as those described above. Figure 2 The corresponding embodiments are the same and will not be described again here.

[0092] A second embodiment of the present invention provides a method for preparing a shallow trench isolation structure, comprising:

[0093] S31: preparing a shallow trench by the shallow trench preparation method provided by the first embodiment of the present invention.

[0094] The specific steps in S31 and the device structure diagram corresponding to each step are the same as those described above. Figure 3It is the same as the corresponding embodiment and will not be elaborated here.

[0095] S32: Fill the shallow trench with an insulating medium until the insulating medium covers the silicon nitride layer to form an insulating dielectric layer 301. Please refer to Figure 16 .

[0096] Among them, the process of filling the insulating medium usually selects a high aspect ratio process; the insulating medium filled is usually silicon dioxide. Of course, other materials with insulating properties and meeting the filling requirements can also be used as the insulating medium of the present invention, which is not limited here.

[0097] S33: Perform high-temperature annealing on the insulating dielectric layer 301. Please refer to Figure 16 .

[0098] S34: Grind the insulating dielectric layer 301 to completely expose the silicon nitride layer. Please refer to Figure 17 .

[0099] Among them, grinding the insulating dielectric layer 301 specifically includes: grinding the surface of the insulating dielectric layer to be lower than the silicon nitride layer by CMP process to completely expose the silicon nitride layer.

[0100] S35: Remove the silicon nitride layer by wet etching process. Please refer to Figure 18 .

[0101] In addition, the third embodiment of the present invention also provides a semiconductor device, including a shallow trench isolation structure prepared by the method for preparing a shallow trench isolation structure.

[0102] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a shallow trench, characterized in that, Comprising: Providing a silicon substrate; Forming a pad silicon dioxide layer and a silicon nitride layer in sequence on the silicon substrate in a direction away from the silicon substrate; Forming a patterned first mask layer on the silicon nitride layer and the pad silicon dioxide layer; wherein, the first mask layer includes a first window region and a blocking region; Using the first mask layer as a mask to perform dry etching on the silicon nitride layer and the pad silicon dioxide layer located in the first window region in sequence, and stopping the etching endpoint at the surface of the silicon substrate; Performing a back-etch on the silicon nitride layer by wet etching to expose the pad silicon dioxide layer below the silicon nitride layer to form a second hard mask layer including a second window region; Using the second hard mask layer as a mask to perform dry etching on the pad silicon dioxide layer and the silicon substrate in the second window region, rounding at least part of the top corners of the sidewalls of the shallow trench covered by the pad silicon dioxide layer, and forming a shallow trench with a preset depth; Wherein, the etching selectivity of the silicon substrate compared to the pad silicon dioxide layer satisfies: when the etching depth of the shallow trench reaches 75% - 99% of the final depth, the exposed pad silicon dioxide layer is partially consumed or completely consumed.

2. The shallow trench preparation method according to claim 1, characterized in that, Forming the pad silicon dioxide layer on the silicon substrate specifically includes: Placing the silicon substrate in a furnace tube and introducing oxygen at a first temperature to form the pad silicon dioxide layer on the silicon substrate; Forming the silicon nitride layer on the pad silicon dioxide layer specifically includes: Introducing SiH4 and NH3 gases into the furnace tube, reacting to generate Si3N4, and depositing it on the surface of the pad silicon dioxide layer.

3. The method for preparing a shallow trench according to claim 1, characterized in that, Forming the first mask layer on the silicon nitride layer and the pad silicon dioxide layer specifically includes: Spin-coating a photoresist layer on the silicon nitride layer; Exposing and developing the photoresist layer to form a patterned photoresist of the first mask layer; Dry etching the silicon nitride layer and the pad silicon dioxide layer to form the silicon nitride layer and the pad silicon dioxide layer of the first mask layer pattern.

4. The shallow trench preparation method according to claim 1, wherein After forming the shallow trench, it further includes: forming a sidewall oxide layer on the sidewalls of the shallow trench by a high-temperature furnace tube process.

5. A method for preparing a shallow trench isolation structure, characterized in that, Comprising: Preparing a shallow trench by the shallow trench preparation method according to any one of claims 1 - 4; Filling an insulating medium in the shallow trench to form a shallow trench isolation structure.

6. The method for preparing a shallow trench isolation structure according to claim 5, wherein Filling an insulating medium in the shallow trench to form a shallow trench isolation structure specifically includes: Filling an insulating medium in the shallow trench until the insulating medium covers the silicon nitride layer to form an insulating medium layer; Performing a high-temperature annealing on the insulating medium layer; Grinding the insulating medium layer to completely expose the silicon nitride layer; Removing the silicon nitride layer by a wet etching process.

7. The method for manufacturing a shallow trench isolation structure according to claim 6, wherein Grinding the insulating medium layer specifically includes: grinding the surface of the insulating medium layer to be lower than the silicon nitride layer by a CMP process to completely expose the silicon nitride layer.

8. The method for preparing a shallow trench isolation structure according to claim 6, wherein The process of filling the insulating medium specifically includes: a high aspect ratio process.

9. A semiconductor device, characterized in that, Including a shallow trench isolation structure prepared by the shallow trench isolation structure preparation method according to claim 8.

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