A semiconductor device

Abstract

The present invention discloses a semiconductor device. The semiconductor device includes a silicon carbide substrate; a silicon carbide epitaxial layer arranged on one side of the silicon carbide substrate along a first direction; a first body region and a source region are both located on the side of the epitaxial layer away from the silicon carbide substrate along the first direction; the source region is located on the side of the first body region away from the silicon carbide substrate; a gate insulating layer arranged on the side of the epitaxial layer away from the silicon carbide substrate; a gate arranged on the side of the gate insulating layer away from the silicon carbide substrate; a drain region arranged on the side of the silicon carbide substrate away from the silicon carbide epitaxial layer and electrically connected to the silicon carbide substrate; an emitter region arranged on the source region away from the gate along a second direction; the emitter region is electrically connected to the source region; a base region arranged between the epitaxial layer and the silicon carbide substrate along the first direction; a collector region arranged on the side of the base region close to the drain region, and the collector region is electrically connected to the drain region. The technical solution provided in this embodiment integrates a silicon carbide field effect transistor and a bipolar transistor on the same chip to improve the switching efficiency of the semiconductor device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] With the development of semiconductor technology, people have higher and higher requirements for semiconductor devices. Although silicon is the most widely used semiconductor in electronic products, recent studies have shown that it has certain limitations, especially in high-power applications. Bandgap is a relevant factor for semiconductor-based circuits because high bandgap has advantages in operation at high temperature, voltage and frequency. The bandgap of silicon is 1.12eV, while the bandgap value of silicon carbide is 3.2eV, which is about 3 times higher than that of silicon, so silicon carbide power devices have higher performance and efficiency, higher switching frequency and smaller total footprint. SiC MOSFETs have excellent characteristics and unipolar conduction mechanisms, which leads to their reduced size and improved switching performance, which means that when having the same current and voltage ratings, the size of SiC MOSFETs can be much smaller than Si counterparts. Due to the smaller size, the overall parasitic capacitance is smaller, which enables SiC metal-oxide-semiconductor field-effect transistors to achieve high switching speeds and low on-resistance. Therefore, SiC-based converters have great application potential in hybrid / electric vehicles, solar inverters and uninterruptible power supplies.

[0003] In many applications, field effect transistors need to be used in conjunction with bipolar transistors. Existing independently packaged silicon carbide field effect transistors and independently packaged bipolar transistors need to be electrically connected through wire bonding, which will result in large parasitic capacitance and parasitic inductance in the circuit, affecting the switching efficiency of the device, and has become a technical problem that needs to be urgently solved in the industry. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor device to solve the problem that a circuit formed by connecting existing independently packaged silicon carbide field effect transistors and independently packaged bipolar transistors by wire bonding has large parasitic capacitance and parasitic inductance, which affects the switching efficiency of the device.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] An embodiment of the present invention provides a semiconductor device, including:

[0007] Silicon carbide substrate;

[0008] A silicon carbide extension layer disposed on one side of the silicon carbide substrate along a first direction, wherein the first direction is a thickness direction of the silicon carbide substrate;

[0009] A first body region and a source region are arranged on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate along a first direction; the source region is located on a side of the first body region away from the silicon carbide substrate;

[0010] A gate insulating layer disposed along a first direction on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate;

[0011] A gate disposed along a first direction on a side of the gate insulating layer away from the silicon carbide substrate;

[0012] A drain region disposed along a first direction on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer and electrically connected to the silicon carbide substrate;

[0013] An emitter region is arranged in a second direction away from the source region and away from the gate, and the second direction is a direction parallel to the plane where the silicon carbide substrate is located; the emitter region is electrically connected to the source region;

[0014] A base region disposed between the silicon carbide epitaxial layer and the silicon carbide substrate along a first direction;

[0015] The collector region is arranged on the side of the base region close to the drain region, and the collector region is electrically connected to the drain region.

[0016] Optionally, an orthographic projection of the collector region on the silicon carbide substrate at least partially overlaps with an orthographic projection of the emitter region on the silicon carbide substrate and an orthographic projection of the base region on the silicon carbide substrate.

[0017] Optionally, the silicon carbide substrate has a first semiconductor type;

[0018] The semiconductor type of the silicon carbide epitaxial layer is the same as the semiconductor type of the silicon carbide substrate;

[0019] The semiconductor type of the base region is the same as that of the silicon carbide substrate;

[0020] The collector region and the emitter region have a second semiconductor type;

[0021] The body region has a second semiconductor type, and the source region and the drain region have a first semiconductor type;

[0022] The first semiconductor type and the second semiconductor type are different.

[0023] Optionally, the emission region and the source region are arranged adjacent to each other; or,

[0024] A gap is provided between the emitter region and the source region.

[0025] Optionally, the semiconductor device further comprises:

[0026] a second body region, the second body region at least partially surrounding the emitting region;

[0027] The second body region has a second semiconductor type;

[0028] Preferably, the second body region is arranged between the emitter region and the first body region and between the emitter region and the silicon carbide epitaxial layer;

[0029] Preferably, the first body region at least partially surrounds the source region.

[0030] Optionally, the semiconductor device further comprises:

[0031] an isolation region, disposed between the emission region and the first body region;

[0032] Preferably, the material of the isolation region comprises silicon dioxide.

[0033] Optionally, the base region covers the silicon carbide substrate and the collector region.

[0034] Optionally, the collector region and the silicon carbide substrate are arranged in the same layer.

[0035] Optionally, the first body region and the source region at least partially surround the gate;

[0036] The collector region at least partially surrounds the silicon carbide substrate;

[0037] The emitter region at least partially surrounds the silicon carbide substrate.

[0038] Optionally, the drain region, the source region, the first body region and the gate form a silicon carbide field effect transistor;

[0039] The emitter region, the base region and the collector region form a silicon carbide bipolar transistor; the field effect transistor and the silicon carbide bipolar transistor are packaged as the semiconductor device.

[0040] This arrangement allows the silicon carbide field effect transistor and the silicon carbide bipolar transistor to be in the same cell and share terminals, and can be packaged together to form a semiconductor device of a silicon carbide field effect transistor with an integrated bipolar transistor.

[0041] The semiconductor device provided by the embodiment of the present invention is provided by arranging the emitter region on the side of the source region away from the gate, and electrically connecting the emitter region to the source region. Along the first direction, the base region is arranged between the silicon carbide epitaxial layer and the silicon carbide substrate. And by arranging the collector region on the side of the base region close to the drain region, the collector region is electrically connected to the drain region. In this way, the emitter region, the base region and the collector region of the semiconductor device provided by this embodiment form a silicon carbide bipolar transistor structure. Since the emitter region is electrically connected to the source region, and the collector region is electrically connected to the drain region, the semiconductor device provided by this embodiment integrates the silicon carbide field effect transistor and the silicon carbide bipolar transistor on the same silicon carbide epitaxial layer, the same cell, and a common terminal, so that the semiconductor device has a very small gate drive voltage, and at the same time achieves the effect of current amplification, reduces the chip area, reduces the parasitic capacitance and parasitic inductance caused by independent packaging and electrical wiring connection, reduces the packaging cost, and improves the switching efficiency of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.

[0043] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0044] Figure 2 is a schematic diagram of a circuit principle of a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0046] Figure 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0047] Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0048] Figure 6 It is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0050] Based on the above technical problems, this embodiment proposes the following solutions:

[0051] Figure 1 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention. Figure 2 Schematic diagram of a circuit principle of a semiconductor device provided by an embodiment of the present invention. Figure 1 and Figure 2The semiconductor device provided by the embodiment of the present invention comprises: a silicon carbide substrate 101; a silicon carbide epitaxial layer 102 disposed on one side of the silicon carbide substrate 101 along a first direction Y, wherein the first direction Y is the thickness direction of the silicon carbide substrate 101; a first body region 103 and a source region 104 located on a side of the silicon carbide epitaxial layer 102 away from the silicon carbide substrate 101 along the first direction Y; the source region 104 is located on a side of the first body region 103 away from the silicon carbide substrate 101; a gate insulating layer 105 disposed on a side of the silicon carbide epitaxial layer 102 away from the silicon carbide substrate 101 along the first direction Y; and a gate insulating layer 106 disposed on the gate insulating layer 107 along the first direction Y. 5 is a gate G away from the side of the silicon carbide substrate 101; a drain region D is arranged on the side of the silicon carbide substrate 101 away from the silicon carbide epitaxial layer 102 along the first direction Y and is electrically connected to the silicon carbide substrate 101; an emitter region 201 is arranged in the source region 104 away from the gate G along the second direction X, and the second direction X is a direction parallel to the plane where the silicon carbide substrate 101 is located; the emitter region 201 is electrically connected to the source region; a base region 202 is arranged between the silicon carbide epitaxial layer 102 and the silicon carbide substrate 101 along the first direction Y; and a collector region 203 is arranged on the side of the base region 202 close to the drain region D, and the collector region 203 is electrically connected to the drain region D.

[0052] Specifically, the first direction Y is the thickness direction of the silicon carbide substrate 101. The second direction X is a direction parallel to the silicon carbide substrate 101. The silicon carbide substrate 101 may be a heavily doped first conductivity type semiconductor silicon carbide silicon carbide substrate 101. The silicon carbide epitaxial layer 102 may be a lightly doped first conductivity type silicon carbide semiconductor drift layer. The first body region 103 may be a lightly doped second conductivity type silicon carbide semiconductor well region. The source region 104 may be a heavily doped first conductivity type silicon carbide semiconductor.

[0053] Optionally, based on the above technical solution, the first conductive type silicon carbide substrate can also be a semi-insulating silicon carbide substrate. The first conductive type silicon carbide epitaxial layer 102 as a drift region can also be a first conductive type gallium nitride material. That is, a gallium nitride epitaxial layer is epitaxially grown on a semi-insulating silicon carbide substrate, and then a gallium nitride device is prepared on the gallium nitride epitaxial layer. Since gallium nitride materials have good heat dissipation performance, high breakdown electric field, high saturation velocity and higher electron mobility, gallium nitride power devices have broad application prospects in high-power high-frequency energy conversion and high-frequency microwave communications. Compared with its equivalent silicon field-effect transistor, the gallium nitride field-effect transistor has the advantages of lower gate capacitance, lower gate drive voltage and higher rated voltage capability.

[0054] The gate insulating layer 105 at least partially covers the silicon carbide epitaxial layer 102, and at least part of the gate insulating layer 105 is disposed adjacent to the body region and the source region 104. The gate G is disposed on a side of the gate insulating layer 105 away from the silicon carbide substrate 101. The source region 104 and the body region form a channel. The gate insulating layer 105 is used to separate the gate G from the body region.

[0055] When the bias voltage on the gate G is greater than the threshold voltage, a channel region is formed in the first body region 103. Under the action of the high voltage in the drain region D, electrons flow out from the source region 104, pass through the channel region and the silicon carbide epitaxial layer 102 in sequence, and then enter the silicon carbide substrate 101 and flow out from the drain region D, forming a complete current path, and the field effect transistor is in the on state. When the bias voltage on the gate G is less than the threshold voltage, the field effect transistor is in the off state.

[0056] Along the second direction X, an emitter region 201 is arranged at the source region 104 away from the gate G, and the emitter region 201 is electrically connected to the source region 104 through the source electrode S. Along the first direction Y, the base region 202 is arranged between the silicon carbide epitaxial layer 102 and the silicon carbide substrate 101. The collector region 203 is arranged on the side of the base region 202 close to the drain region D, and the collector region 203 is electrically connected to the drain region D. This arrangement allows the emitter region 201 and the base region 202 to form a PN junction, and the base region 202 and the collector region 203 to form a PN junction. Thus, the emitter region 201, the base region 202 and the collector region 203 form a silicon carbide bipolar transistor structure. Since the emitter region 201 is electrically connected to the source region 104, and the collector region 203 is electrically connected to the drain region D, the silicon carbide field effect transistor and the silicon carbide bipolar transistor included in the semiconductor device are integrated on the same silicon carbide epitaxial layer 102, achieving a very small gate drive voltage and a current amplification effect.

[0057] The specific working principle of the semiconductor device of the silicon carbide field effect transistor integrated with the bipolar transistor is as follows: when the semiconductor device of the silicon carbide field effect transistor integrated with the bipolar transistor is turned on, a forward voltage VG is applied to the gate G, and VG>VTH, where VTH is the threshold voltage of the field effect transistor. A forward voltage VD is applied to the drain region D, and the current flows from the drain region D to the source region 104. The current I B That is the source-drain current I of the field effect transistor DS , that is, see Figure 2 , I B＝ I DS The collector voltage of the SiC bipolar transistor is the drain voltage of the field effect transistor. This setting makes the gate drive voltage of the field effect transistor smaller, and finally the emitter current I of the SiC bipolar transistor is obtained. EThe amplification effect. When the semiconductor device is turned off, a negative voltage VG’ is applied to the gate G, or VG’ < VTH, and the field effect transistor is turned off, without current, realizing the switching function of the entire semiconductor device.

[0058] The semiconductor device provided in this embodiment is a silicon carbide field effect transistor device integrated with a bipolar transistor. By disposing the emitter region 201 on the side of the source region 104 away from the gate G and electrically connecting the emitter region 201 to the source region. Along the first direction Y, the base region 202 is disposed between the silicon carbide epitaxial layer 102 and the silicon carbide substrate 101. And by disposing the collector region 203 on the side of the base region 202 close to the drain region D and electrically connecting the collector region 203 to the drain region D. With such a setting, the emitter region 201, the base region 202, and the collector region 203 of the semiconductor device of the silicon carbide field effect transistor integrated with a bipolar transistor provided in this embodiment form a silicon carbide bipolar transistor structure. Since the emitter region 201 is electrically connected to the source region 104 and the collector region 203 is electrically connected to the drain region D, the semiconductor device provided in this embodiment integrates a silicon carbide field effect transistor and a silicon carbide bipolar transistor on the same silicon carbide epitaxial layer 102, enabling the semiconductor device to have a very small gate drive voltage, while realizing the current amplification effect, reducing the parasitic capacitance and parasitic inductance, and improving the switching efficiency of the semiconductor device. In addition, the independently packaged silicon carbide field effect transistor and the independently packaged bipolar transistor occupy a relatively large area in the application design, while the semiconductor device provided in this embodiment integrates the silicon carbide field effect transistor and the silicon carbide bipolar transistor in the same cell, sharing terminals, and can be packaged together as a semiconductor device of a silicon carbide field effect transistor integrated with a bipolar transistor, reducing the area of the semiconductor device.

[0059] It should be noted that this design scheme is applicable not only to planar MOSFETs but also to trench MOSFETs. When the field effect transistor is of a trench structure, it can include both a double trench type and a single trench type MOSFET.

[0060] Optionally, based on the above embodiments, continue to refer to Figure 1 , the orthographic projection of the collector region 203 on the silicon carbide substrate 101 overlaps at least partially with the orthographic projection of the emitter region 201 on the silicon carbide substrate 101 and the orthographic projection of the base region 202 on the silicon carbide substrate 101.

[0061] Specifically, such a setting makes the amplification factor of the silicon carbide bipolar transistor relatively large, further improving the amplification effect of the silicon carbide bipolar transistor.

[0062] Optionally, based on the above embodiments, continue to combine Figure 1 and Figure 2, the silicon carbide substrate 101 has a first semiconductor type; the semiconductor type of the silicon carbide epitaxial layer 102 is the same as the semiconductor type of the silicon carbide substrate 101; the semiconductor type of the base region 202 is the same as the semiconductor type of the silicon carbide substrate 101; the collector region 203 and the emitter region 201 have a second semiconductor type; the body region has the second semiconductor type, and the source region 104 has the first semiconductor type; the first semiconductor type and the second semiconductor type are different.

[0063] It should be noted that Figure 1 The SiC PNP BJT+enhancement SiC NMOSFET is taken as an example only, but the design scheme is also applicable to SiC NPN BJT+enhancement SiC PMOS, SiC PNP BJT+enhancement SiC PMOS and SiC NPN BJT+enhancement SiC NMOS, without any limitation here.

[0064] It should be noted that Figure 2 The case of a PNP type semiconductor device is shown as an example, and no limitation is made here.

[0065] Optional, Figure 3 FIG. 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. Figure 1 , the emitter region 201 and the source region 104 are arranged adjacent to each other; or, see Figure 3 , a gap is set between the emitter region 201 and the source region 104.

[0066] Specifically, such a configuration separates the emitter region 201 and the source region 104, which can better avoid the emitter region 201 and the source region 104 being close together, thereby avoiding the formation of a lateral parasitic PNP, thereby reducing parasitic energy consumption, and further avoiding the generation of parasitic capacitance, thereby greatly reducing the risk of latch-up.

[0067] Optional, Figure 4 FIG. 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. Figure 4 The semiconductor device of the silicon carbide field effect transistor with integrated bipolar transistor may also include: a second body region 204, the second body region 204 at least partially surrounds the emitter region 201; the second body region 204 has a second semiconductor type; preferably, the second body region 204 is arranged between the emitter region 201 and the first body region 103 and between the emitter region 201 and the silicon carbide epitaxial layer 102; preferably, the first body region 103 at least partially surrounds the source region 104.

[0068] Specifically, by providing the second body region 204, the function of the emitter region 201 is further enhanced. On the other hand, the emitter region 201 and the source region 104 are separated by the second body region 204, thereby avoiding the formation of a lateral parasitic PNP, and further reducing parasitic energy consumption. The first body region 103 is provided to at least partially surround the source region 104, so that the function of the source region 104 is further enhanced. The second body region 204 and the first body region 103 can have the same semiconductor type. The material of the drain D can include a conductive metal and a conductive metal alloy.

[0069] It should be noted that Figure 4 The first body region 103 and the second body region 204 are shown as examples. The first body region 103 and the second body region 204 may be formed by the same process, which is not limited herein.

[0070] An optional implementation manner, based on the above embodiments, the types of doping ions in the silicon carbide substrate 101, the silicon carbide epitaxial layer 102, the source region 104, the gate G and the base region 202 are all N-type; the types of doping ions in the first body region 103, the emitter region 201 and the collector region 203 are all P-type.

[0071] In another optional implementation, based on the above embodiments, the doping ions of the silicon carbide substrate 101, the silicon carbide epitaxial layer 102, the source region 104, the gate G and the base region 202 are all of P type; the doping ions of the first body region 103, the emitter region 201 and the collector region 203 are all of N type.

[0072] Optional, Figure 5 FIG. 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. Figure 5 The semiconductor device further includes: an isolation region 301 disposed between the emitter region 201 and the first body region 103; preferably, the material of the isolation region 301 may include silicon dioxide.

[0073] Specifically, an isolation region 301 is added between the emitter region 201 and the first body region 103. Figure 3 The case where the emitter region 201 is P++ and the first body region 103 is P-Well is exemplarily shown, and no limitation is made here. An isolation region 301 is added between the emitter region 201 and the first body region 103, which can effectively reduce the parasitic PNP transistor effect along the second direction X. The isolation region 301 can also be added between the collector region 203 and the silicon carbide substrate 101. The isolation region 301 can be set to reduce the parasitic PNP transistor effect along the second direction X. The material of the isolation region 301 may include an inorganic material, such as a silicon dioxide material. The isolation region 301 is provided with silicon dioxide, which can further reduce the parasitic PNP transistor effect along the second direction X and improve the conduction efficiency of the semiconductor device.

[0074] Optional, Figure 6 FIG. 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. Figure 6 , the base region 202 covers the silicon carbide substrate 101 and the collector region 203 .

[0075] Specifically, such a configuration allows the base region 202 to be manufactured using one process without the need for two masking steps, thereby reducing process costs. On the other hand, since the conductivity type of the base region 202 can be set to be the same conductivity type as the heavily doped silicon carbide epitaxial layer 102, the source-drain current of the field effect transistor can be further increased.

[0076] Optionally, based on the above embodiments, continue to refer to Figure 6 The collector region 203 and the silicon carbide substrate 101 are arranged in the same layer.

[0077] Specifically, such a configuration is conducive to further reducing the thickness of the semiconductor device, is conducive to the lightweight and thin design of the semiconductor device, reduces the volume of the semiconductor device, and improves the integration of the semiconductor device.

[0078] Optionally, based on the above embodiments, continue to refer to Figure 6 , the first body region 103 and the source region 104 at least partially surround the gate G; the collector region 203 at least partially surrounds the silicon carbide substrate 101; the emitter region 201 at least partially surrounds the silicon carbide substrate 101. Optionally, the drain region D, the source region 104, the first body region 103 and the gate G form a field effect transistor; the emitter region 201, the base region 202 and the collector region 203 form a silicon carbide bipolar transistor; the silicon carbide field effect transistor and the silicon carbide bipolar transistor are packaged as a semiconductor device.

[0079] Specifically, such a configuration can make the semiconductor device of the silicon carbide field effect transistor integrated with the bipolar transistor smaller in area, the packaging cost of the semiconductor device lower, and further reduce the parasitic capacitance and inductance. By integrating the silicon carbide MOSFET and the silicon carbide BJT into the same chip, it can not only reduce the packaging cost of the device and the module area, but also avoid additional parasitic effects, further improving the switching efficiency.

[0080] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: Silicon carbide substrate; A silicon carbide epitaxial layer disposed on one side of the silicon carbide substrate along a first direction, wherein the first direction is a thickness direction of the silicon carbide substrate; A first body region and a source region are arranged on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate along the first direction; the source region is located on a side of the first body region away from the silicon carbide substrate; A gate insulating layer disposed on a side of the silicon carbide epitaxial layer away from the silicon carbide substrate along the first direction; A gate disposed along the first direction on a side of the gate insulating layer away from the silicon carbide substrate; A drain region disposed along the first direction on a side of the silicon carbide substrate away from the silicon carbide epitaxial layer and electrically connected to the silicon carbide substrate; An emitter region is arranged in the source region away from the gate along a second direction, wherein the second direction is a direction parallel to the plane where the silicon carbide substrate is located; the emitter region is electrically connected to the source region; A base region disposed between the silicon carbide epitaxial layer and the silicon carbide substrate along the first direction; A collector region disposed on a side of the base region close to the drain region, the collector region being electrically connected to the drain region; A gap is provided between the emitter region and the source region; The drain region, the source region, the first body region and the gate form a field effect transistor; The emitter region, the base region and the collector region form a silicon carbide bipolar transistor; The field effect transistor and the silicon carbide bipolar transistor are packaged as the semiconductor device.

2. The semiconductor device according to claim 1, wherein: An orthographic projection of the collector region on the silicon carbide substrate at least partially overlaps with an orthographic projection of the emitter region on the silicon carbide substrate and an orthographic projection of the base region on the silicon carbide substrate.

3. The semiconductor device according to claim 1, wherein: The silicon carbide substrate has a first semiconductor type; The semiconductor type of the silicon carbide epitaxial layer is the same as the semiconductor type of the silicon carbide substrate; The semiconductor type of the base region is the same as the semiconductor type of the silicon carbide substrate; The collector region and the emitter region have a second semiconductor type; The body region has a second semiconductor type, and the source region and the drain region have a first semiconductor type; The first semiconductor type and the second semiconductor type are different.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a second body region, the second body region at least partially surrounding the emitting region; The second body region has a second semiconductor type; The second body region is disposed between the emitter region and the first body region and between the emitter region and the silicon carbide epitaxial layer; The first body region at least partially surrounds the source region.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: an isolation region, disposed between the emitter region and the first body region; The material of the isolation region includes silicon dioxide.

6. The semiconductor device according to claim 1, wherein: The base region covers the silicon carbide substrate and the collector region.

7. The semiconductor device according to claim 1, wherein: The collector region and the silicon carbide substrate are arranged in the same layer.

8. The semiconductor device according to claim 1, wherein: The first body region and the source region each at least partially surround the gate; The collector region at least partially surrounds the silicon carbide substrate; The emitter region at least partially surrounds the silicon carbide substrate.

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