Q value detection circuit, method, wireless charging transmission circuit, chip and device

Abstract

The present application provides a Q value detection circuit, method, wireless charging transmitting circuit, chip and electronic device. The voltage sampling circuit transmits the resonant voltage to the sampling and holding circuit and the comparison circuit respectively, so that the comparison circuit obtains the first square wave pulse signal and the second square wave pulse signal, and the logic control circuit obtains the control signal. In this way, the sampling and holding circuit can obtain the first peak voltage and the second peak voltage of the resonant voltage that just appear at the peak position according to the control signal. Furthermore, the analog-to-digital conversion circuit can obtain the converted first peak voltage and the converted second peak voltage, so that the microprocessor can obtain the Q value detection result according to the converted first peak voltage and the converted second peak voltage. Since the first peak voltage and the second peak voltage appear exactly at the peak position, the converted first peak voltage and the converted second peak voltage also appear exactly at the peak position. Thereby, the detection accuracy of the Q value detection circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of wireless charging technology, and in particular to a Q value detection circuit, method, wireless charging transmitting circuit, chip and electronic device. Background Art

[0002] The principle of wireless charging technology is to achieve wireless transmission of electric energy through electromagnetic field coupling between the transmitting coil in the transmitter end (TX) circuit and the receiving coil in the receiver end (RX) circuit. The RLC resonant circuit of the TX circuit itself has a fixed Q value. Since the introduction of the RX circuit causes the Q value of the RLC resonant circuit to change, it is determined whether the RX circuit is introduced by detecting whether the Q value changes. For example, for a mobile phone's wireless charger, the mobile phone is the RX circuit, the wireless charger is the TX circuit, the transmitting coil is located in the wireless charger, and the receiving coil is located inside the mobile phone. When the mobile phone is placed on the wireless charger, the Q value of the wireless charger will change.

[0003] In the related art, the electrical signal of the transmitting coil is compared with a preset threshold to obtain a peak signal corresponding to the electrical signal, and then the Q value is calculated based on the peak signal.

[0004] However, in the related art, the preset threshold is set in advance, and it is impossible to ensure that the peak signal appears exactly at the peak of the self-oscillation generated by the RLC resonant circuit, resulting in low detection accuracy of the Q value. Summary of the invention

[0005] The present application provides a Q value detection circuit, method, wireless charging transmission circuit, chip and electronic device, which can improve the Q value detection accuracy.

[0006] In a first aspect, the present application provides a Q value detection circuit, which is applied to a wireless charging transmitting circuit, wherein the wireless charging transmitting circuit includes a resonant circuit. The Q value detection circuit includes: a voltage sampling circuit, a sample-and-hold circuit, a comparison circuit, a logic control circuit, an analog-to-digital conversion circuit, and a microprocessor.

[0007] The input end of the voltage sampling circuit is electrically connected between the capacitor and the transmitting coil in the resonant circuit, the output end of the voltage sampling circuit is electrically connected to the input end of the sampling and holding circuit and the first input end of the comparison circuit, the output end of the comparison circuit is electrically connected to the input end of the logic control circuit, the output end of the logic control circuit is electrically connected to the control end of the sampling and holding circuit, the output end of the sampling and holding circuit is electrically connected to the input end of the analog-to-digital conversion circuit, the output end of the analog-to-digital conversion circuit is electrically connected to the input end of the microprocessor, and the second input end of the comparison circuit is used to access the reference voltage.

[0008] The voltage sampling circuit is used to collect the resonant voltage of the resonant circuit and transmit the resonant voltage to the sampling and holding circuit and the comparison circuit respectively.

[0009] A comparison circuit is used to compare the resonant voltage and the reference voltage to obtain a first square wave pulse signal and a second square wave pulse signal respectively, and transmit the first square wave pulse signal and the second square wave pulse signal to the logic control circuit. The reference voltage includes: a first reference voltage and a second reference voltage. The first reference voltage is used to determine the peak voltage of the resonant voltage, and the second reference voltage is used to determine the period in which the peak voltage of the resonant voltage is located.

[0010] The logic control circuit is used to perform logic processing on the first square wave pulse signal and the second square wave pulse signal to obtain a control signal, and transmit the control signal to the sampling and holding circuit. The control signal is used to instruct the sampling and holding circuit to perform sampling and holding.

[0011] The sampling and holding circuit is used to sample and hold the maximum forward peak voltage of the resonant voltage under the action of the control signal for two adjacent cycles, obtain the first peak voltage corresponding to the resonant voltage in the previous cycle and the second peak voltage corresponding to the resonant voltage in the next cycle, and transmit the first peak voltage and the second peak voltage to the analog-to-digital conversion circuit.

[0012] The analog-to-digital conversion circuit is used to perform analog-to-digital conversion on the first peak voltage and the second peak voltage respectively to obtain the converted first peak voltage and the converted second peak voltage, and transmit the converted first peak voltage and the converted second peak voltage to the microprocessor.

[0013] The microprocessor is used to obtain a Q value detection result according to the converted first peak voltage and the converted second peak voltage.

[0014] Through the Q value detection circuit provided by the first aspect, the voltage sampling circuit can collect the resonant voltage of the resonant circuit, so that the voltage sampling circuit can monitor the change trend of the resonant voltage. In addition, the voltage sampling circuit transmits the resonant voltage to the sampling and holding circuit and the comparison circuit respectively, so that the comparison circuit can compare the resonant voltage and the reference voltage to obtain the first square wave pulse signal and the second square wave pulse signal, and the logic control circuit can perform logic processing on the first square wave pulse signal and the second square wave pulse signal to obtain the control signal. In this way, when the voltage sampling circuit monitors that the change trend of the resonant voltage is the maximum positive peak voltage, the sampling and holding circuit can sample and hold the maximum positive peak voltage of the resonant voltage according to the control signal, so that the sampling and holding circuit can obtain the first peak voltage and the second peak voltage at the peak position of the resonant voltage that just appears in two adjacent cycles. Furthermore, the analog-to-digital conversion circuit can perform analog-to-digital conversion on the first peak voltage to obtain the converted first peak voltage, and can perform analog-to-digital conversion on the second peak voltage to obtain the converted second peak voltage, so that the microprocessor can obtain the Q value detection result according to the converted first peak voltage and the converted second peak voltage. Since the first peak voltage appears exactly at the peak position in the previous cycle, and the second peak voltage appears exactly at the peak position in the next cycle, the first peak voltage after conversion also appears exactly at the peak position in the previous cycle, and the second peak voltage after conversion also appears exactly at the peak position in the next cycle, thereby improving the detection accuracy of the Q value detection circuit.

[0015] In a possible design, the control signal includes a first control signal, a second control signal and a third control signal, and the sampling and holding circuit includes: an operational amplifier, a resetter, a first holder and a second holder. The operational amplifier is a unit gain operational amplifier with no load current at the output end of the operational amplifier.

[0016] The first input terminal of the operational amplifier is electrically connected to the output terminal of the voltage sampling circuit, the output terminal of the operational amplifier is electrically connected to the input terminal of the first holder and the input terminal of the second holder respectively, the output terminal of the first holder and the output terminal of the second holder are both electrically connected to the input terminal of the analog-to-digital conversion circuit, the output terminal of the first holder, the output terminal of the second holder and the control terminal of the resetter are all electrically connected to the output terminal of the logic control circuit, the second input terminal of the operational amplifier and the first terminal of the resetter are both electrically connected between the output terminal of the operational amplifier and the input terminal of the first holder, and the second terminal of the resetter is grounded.

[0017] The operational amplifier is used to follow the change of the resonant voltage in the previous cycle, and obtain the first peak voltage when the output voltage of the operational amplifier gradually increases from 0 to the maximum forward peak voltage.

[0018] The first holder is used to sample and hold the first peak voltage under the action of the first control signal in the previous cycle.

[0019] The resetter is used to reset the output voltage of the operational amplifier under the action of the second control signal in the next cycle, so that the output voltage of the operational amplifier changes from the first peak voltage to 0.

[0020] The operational amplifier is also used to obtain a second peak voltage in a subsequent cycle following the change of the resonant voltage when the output voltage of the operational amplifier gradually increases from 0 to the maximum forward peak voltage.

[0021] The second holder is used to sample and hold the second peak voltage under the action of the third control signal in the next cycle.

[0022] In a possible design, the retainer includes: a control switch and a retaining component.

[0023] The first end of the control switch is electrically connected to the output end of the operational amplifier, the second end of the control switch is electrically connected to the input end of the holding component, the output end of the holding component is electrically connected to the input end of the analog-to-digital conversion circuit, and the control end of the control switch and the control end of the holding component are both electrically connected to the output end of the logic control circuit.

[0024] In one possible design, the maintaining component includes a capacitor and a switch tube, the first end of the switch tube is electrically connected to the second end of the control switch, the control end of the switch tube is electrically connected to the output end of the logic control circuit, the second end of the switch tube is grounded, and the capacitor is connected in parallel with the switch tube.

[0025] In a possible design, the microprocessor is specifically used to obtain a target peak voltage based on the converted first peak voltage and the converted second peak voltage, and obtain a Q value detection result based on the target peak voltage.

[0026] In one possible design, the comparison circuit includes a first comparator and a second comparator, the first input terminal of the first comparator and the first input terminal of the second comparator are both electrically connected to the output terminal of the voltage sampling circuit, the second input terminal of the first comparator is used to access the first reference voltage, the second input terminal of the second comparator is used to access the second reference voltage, and the output terminal of the first comparator and the output terminal of the second comparator are both electrically connected to the input terminal of the logic control circuit.

[0027] The first comparator is used for comparing the resonant voltage with the first reference voltage to generate a first square wave pulse signal.

[0028] The second comparator is used for comparing the resonant voltage with the second reference voltage to generate a second square wave pulse signal.

[0029] In a second aspect, the present application provides a Q value detection method, which is applied to the Q value detection circuit in the above-mentioned first aspect and any possible design of the first aspect, and the method includes:

[0030] The voltage sampling circuit collects the resonant voltage of the resonant circuit and transmits the resonant voltage to the sampling and holding circuit and the comparison circuit respectively.

[0031] The comparison circuit compares the resonant voltage of the resonant circuit with the reference voltage to obtain a first square wave pulse signal and a second square wave pulse signal respectively, and transmits the first square wave pulse signal and the second square wave pulse signal to the logic control circuit. The reference voltage includes: a first reference voltage and a second reference voltage. The first reference voltage is used to determine the peak voltage of the resonant voltage, and the second reference voltage is used to determine the period in which the peak voltage of the resonant voltage is located.

[0032] The logic control circuit performs logic processing on the first square wave pulse signal and the second square wave pulse signal to obtain a control signal, and transmits the control signal to the sampling and holding circuit. The control signal is used to instruct the sampling and holding circuit to perform sampling and holding.

[0033] For two adjacent cycles, the sampling and holding circuit samples and holds the maximum forward peak voltage of the resonant voltage under the action of the control signal, obtains the first peak voltage corresponding to the resonant voltage in the previous cycle and the second peak voltage corresponding to the resonant voltage in the next cycle, and transmits the first peak voltage and the second peak voltage to the analog-to-digital conversion circuit.

[0034] The analog-to-digital conversion circuit performs analog-to-digital conversion on the first peak voltage and the second peak voltage respectively to obtain a converted first peak voltage and a converted second peak voltage.

[0035] The microprocessor obtains a Q value detection result according to the converted first peak voltage and the converted second peak voltage.

[0036] The beneficial effects of the methods provided in the above-mentioned second aspect and each possible design of the above-mentioned second aspect can be referred to the beneficial effects brought about by the above-mentioned first aspect and each possible implementation method of the first aspect, and will not be repeated here.

[0037] In a third aspect, the present application provides a foreign body detection method, which is applied to the Q value detection circuit in the first aspect and any possible design of the first aspect, and the method includes:

[0038] According to the Q value detection result, it is determined whether there is a foreign object in the working range of the wireless charging transmitting circuit.

[0039] In a fourth aspect, the present application provides a wireless charging transmitting circuit, comprising: an inverter circuit, a resonant circuit, and a Q value detection circuit in the above-mentioned first aspect and any possible design of the first aspect.

[0040] The inverter circuit and the Q value detection circuit are both electrically connected to the resonance circuit.

[0041] In a fifth aspect, the present application provides a chip, comprising: the Q value detection circuit in the above-mentioned first aspect and any possible design of the first aspect, or the wireless charging transmission circuit in the above-mentioned fourth aspect.

[0042] In a sixth aspect, the present application provides an electronic device, comprising: the chip in the fifth aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the structure of a Q value detection circuit provided for related technology;

[0044] Figure 2 It is a schematic diagram of the working waveform of the Q value detection circuit in the related art;

[0045] Figure 3 A structural schematic diagram of another Q value detection circuit provided for related technology;

[0046] Figure 4 It is a schematic diagram of the working waveform of the Q value detection circuit in the related art;

[0047] Figure 5 A schematic diagram of the structure of a wireless charging system provided in one embodiment of the present application;

[0048] Figure 6 A schematic diagram of a wireless charging transmission circuit structure provided in one embodiment of the present application;

[0049] Figure 7 A schematic diagram of the structure of a Q value detection circuit provided in one embodiment of the present application;

[0050] Figure 8 A schematic diagram of a Q value detection method provided in one embodiment of the present application;

[0051] Fig. 9 A schematic diagram of the structure of another Q value detection circuit provided in one embodiment of the present application;

[0052] Fig.10 A schematic diagram of operating waveforms of a Q-value detection circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0053] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0054] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0055] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0056] Reference Figure 1 , Figure 1 A schematic diagram of a Q value detection circuit provided for related technology, Figure 2 Shows Figure 1 The working waveform diagram of the Q value detection circuit is shown in Figure 2. Figure 1 As shown in FIG. 1 , in the related art, when the RLC resonant circuit generates self-excited oscillation, the capacitor voltage VQD in the RLC resonant circuit is collected by a sampling circuit composed of resistors R1 and R2. In this way, the comparator CMP1 compares the reference voltage vth1 with the capacitor voltage VQD, and obtains Figure 2The square wave cmp1 shown in FIG. 1 is shown in FIG. 1 . Then, the microprocessor circuit can obtain the time t1 corresponding to the last peak value in the square wave cmp1. Similarly, the comparator CMP2 compares the reference voltage vth2 and the capacitor voltage VQD to obtain the following: Figure 2 The square wave cmp2 shown in FIG. 1 is a square wave of FIG. 1 . Furthermore, the microprocessor circuit can obtain the time t2 corresponding to the last peak value in the square wave cmp2. Thus, the Q value is calculated according to the reference voltage vth1, the time t1, the reference voltage vth2 and the time t1.

[0057] Reference Figure 3 , Figure 3 A schematic diagram of a Q value detection circuit provided for related technology, Figure 4 Shows Figure 3 The working waveform diagram of the Q value detection circuit is shown in Figure 2. Figure 3 As shown, in the related art, when the RLC resonant circuit generates self-excited oscillation, the on-current IQ of the power switch device Q2 or the power switch device Q4 is detected. In this way, the comparator CMP3 compares the reference current ith1 with the on-current IQ to obtain Figure 4 The square wave cmp3 shown in FIG. 1 is a square wave. Then, the microprocessor circuit can obtain the time t3 corresponding to the last peak value in the square wave cmp3. Similarly, the comparator CMP4 compares the reference current ith2 with the conduction current IQ and obtains Figure 4 The square wave cmp4 shown in FIG. 1 is a square wave of FIG. 1 . Furthermore, the microprocessor circuit can obtain the time t4 corresponding to the last peak value in the square wave cmp4. Thus, the Q value is calculated according to the reference current ith1, the time t3, the reference current ith2 and the time t4.

[0058] Among them, when the switch S1 is closed, Q4 is in the on state, Q1, Q2 and Q3 are in the off state, and the power supply voltage VDC1 charges the RLC resonant circuit. After the voltage across the capacitor in the RLC resonant circuit reaches the power supply voltage VDC1, when the switch S1 is turned off, Q2 and Q4 are in the on state, and Q1 and Q3 are still in the off state, the electric energy stored in the RLC resonant circuit will be discharged, causing the RLC resonant circuit to generate self-excited oscillation.

[0059] However, in the above-mentioned related technologies, the reference voltage vth1, the reference voltage vth2, the reference current ith1 and the reference current ith2 are all set in advance, and it cannot be guaranteed that the peak signal appears exactly at the peak of the self-oscillation generated by the RLC resonant circuit, resulting in low detection accuracy of the Q value.

[0060] In order to solve the above technical problems, the present application provides a Q value detection circuit, method, wireless charging transmission circuit, chip and electronic device.

[0061] Among them, the Q value detection circuit and the wireless charging transmission circuit can be chips or circuit modules.

[0062] Reference Figure 5 , Figure 5 This is a schematic diagram of the structure of a wireless charging system provided in one embodiment of the present application. Figure 5 As shown, the wireless charging system may include: a wireless charging receiving circuit 2000 and a wireless charging transmitting circuit 1000 .

[0063] The wireless charging receiving circuit 2000 may include but is not limited to: a rectifying circuit and a receiving circuit. The wireless charging transmitting circuit 1000 may at least include: an inverter circuit 300 and a resonant circuit 200 .

[0064] The electronic device may include: a chip. In some examples, the electronic device may be a wireless charger or a wireless charging adapter, which is not specifically limited in the embodiments of the present application.

[0065] The Q value detection result is used to determine whether the wireless charging transmitting circuit 1000 transmits power to the wireless charging receiving circuit 2000. If the Q value detection result is other values, it means that there is no wireless charging receiving circuit 2000, and it may be just a piece of metal or something else. In this way, the wireless charging transmitting circuit 1000 does not need to transmit power to the wireless charging receiving circuit 2000. If the Q value detection result is a specific value, it means that there may be a wireless charging receiving circuit 2000. In this way, the wireless charging transmitting circuit 1000 needs to transmit power to the wireless charging receiving circuit 2000.

[0066] When the Q value detection result obtained by the wireless charging transmitting circuit 1000 indicates that the wireless charging transmitting circuit 1000 can transmit power to the wireless charging receiving circuit 2000, the wireless charging transmitting circuit 1000 transmits power to the wireless charging receiving circuit 2000, so that the wireless charging receiving circuit 2000 can provide power to the load. In this way, the load can be charged through the wireless charging technology, ensuring that the load can work normally.

[0067] The loads may include but are not limited to: smart phones, smart watches and electric vehicles.

[0068] Reference Figure 6 , Figure 6 Shows Figure 5 The schematic diagram of the wireless charging transmitter circuit in FIG. Figure 6 As shown, the wireless charging transmitting circuit 1000 may include: an inverter circuit 300 , a resonant circuit 200 and a Q value detection circuit 100 .

[0069] The inverter circuit 300 and the Q-value detection circuit 100 are both electrically connected to the resonance circuit 200 .

[0070] The inductor coil in the resonant circuit 200 is used as a transmitting coil.

[0071] The present application provides a foreign body detection method, the method comprising:

[0072] According to the Q value detection result, it is determined whether there is a foreign object in the working range of the wireless charging transmitting circuit.

[0073] Since the wireless charging / powering device itself is composed of an RLC resonant circuit, the RLC circuit of the device itself has a fixed Q value. The introduction of foreign matter (here the foreign matter is a metal conductor) causes the Q value of the RLC circuit to change. Therefore, people have invented a method to determine whether there is a foreign matter by detecting the change in the Q value.

[0074] Reference Figure 7 , Figure 7 Shows Figure 6 A schematic diagram of the structure of a Q value detection circuit. Figure 7 As shown, the Q value detection circuit 100 may include: a voltage sampling circuit 110 , a sample-and-hold circuit 120 , a comparison circuit 130 , a logic control circuit 140 , an analog-to-digital conversion circuit 150 and a microprocessor 160 .

[0075] The input end of the voltage sampling circuit 110 is electrically connected between the capacitor and the transmitting coil in the resonant circuit 200, the output end of the voltage sampling circuit 110 is electrically connected to the input end of the sampling and holding circuit 120 and the first input end of the comparison circuit 130, the output end of the comparison circuit 130 is electrically connected to the input end of the logic control circuit 140, the output end of the logic control circuit 140 is electrically connected to the control end of the sampling and holding circuit 120, the output end of the sampling and holding circuit 120 is electrically connected to the input end of the analog-to-digital conversion circuit 150, the output end of the analog-to-digital conversion circuit 150 is electrically connected to the input end of the microprocessor 160, and the second input end of the comparison circuit 130 is used to access the reference voltage.

[0076] The voltage sampling circuit 110 , the sample-and-hold circuit 120 , the comparison circuit 130 , the logic control circuit 140 , the analog-to-digital conversion circuit 150 and the microprocessor 160 may be arranged separately or integrated.

[0077] Below, refer to Figure 8 , Figure 8 A schematic diagram of a Q value detection method provided in an embodiment of the present application. Figure 8 As shown, the method includes:

[0078] S101 . A voltage sampling circuit collects a resonance voltage of a resonance circuit, and transmits the resonance voltage to a sampling and holding circuit and a comparison circuit respectively.

[0079] S102: The comparison circuit compares the resonant voltage of the resonant circuit with the reference voltage to obtain a first square wave pulse signal and a second square wave pulse signal respectively, and transmits the first square wave pulse signal and the second square wave pulse signal to the logic control circuit.

[0080] The reference voltage includes: a first reference voltage vth1 and a second reference voltage vth2. The first reference voltage vth1 is used to determine the peak voltage of the resonance voltage VQD, and the second reference voltage vth2 is used to determine the period in which the peak voltage of the resonance voltage VQD is located.

[0081] S103 , the logic control circuit performs logic processing on the first square wave pulse signal and the second square wave pulse signal to obtain a control signal, and transmits the control signal to the sampling and holding circuit.

[0082] S104, the sampling and holding circuit samples and holds the maximum positive peak voltage of the resonant voltage for two adjacent cycles under the action of the control signal, obtains the first peak voltage corresponding to the resonant voltage in the previous cycle and the second peak voltage corresponding to the resonant voltage in the next cycle, and transmits the first peak voltage and the second peak voltage to the analog-to-digital conversion circuit.

[0083] S105 , the analog-to-digital conversion circuit performs analog-to-digital conversion on the first peak voltage and the second peak voltage respectively to obtain a converted first peak voltage and a converted second peak voltage.

[0084] S106. The microprocessor obtains a Q value detection result according to the converted first peak voltage and the converted second peak voltage.

[0085] Among them, one cycle refers to the process in which the resonant voltage VQD of the resonant circuit 200 gradually increases from 0 to the maximum positive peak voltage, then gradually decreases from the maximum positive peak voltage to the maximum negative peak voltage, and finally gradually increases from the maximum negative peak voltage to 0.

[0086] The voltage sampling circuit 110 can collect the resonance voltage VQD of the resonance circuit 200. Thus, the voltage sampling circuit 110 can monitor the change trend of the resonance voltage VQD of the resonance circuit 200. The change trend is that the resonance voltage VQD of the resonance circuit 200 gradually increases from 0 to the maximum positive peak voltage, then gradually decreases from the maximum positive peak voltage to the maximum negative peak voltage, and finally gradually increases from the maximum negative peak voltage to 0. In addition, the voltage sampling circuit 110 can transmit the resonance voltage VQD to the sampling and holding circuit 120 and the comparison circuit 130 respectively.

[0087] In this way, the comparison circuit 130 can compare the resonance voltage VQD with the reference voltage to obtain the first square wave pulse signal p1 and the second square wave pulse signal p2 respectively. Furthermore, the comparison circuit 130 can transmit the first square wave pulse signal p1 and the second square wave pulse signal p2 to the logic control circuit 140 .

[0088] The first square wave pulse signal p1 is obtained by comparing the voltage value of the resonance voltage VQD with the first reference voltage vth1. The second square wave pulse signal p2 is obtained by comparing the voltage value of the resonance voltage VQD with the second reference voltage vth2.

[0089] In this way, the logic control circuit 140 can perform logic processing on the first square wave pulse signal p1 and the second square wave pulse signal p2 to obtain a control signal. Furthermore, the logic control circuit 140 can transmit the control signal to the sample and hold circuit 120 .

[0090] The control signal is used to instruct the sample and hold circuit 120 to enter a working state.

[0091] The logic processing may be a logic AND operation, a logic OR operation, or a combination of a logic AND operation and a logic OR operation, which is not specifically limited in the embodiments of the present application.

[0092] In addition, if the first square wave pulse signal p1 is absent, the logic control circuit 140 will not output the control signal. In this way, the sample and hold circuit 120 will no longer continue to sample and hold the maximum forward peak voltage of the resonant voltage.

[0093] Similarly, the logic control circuit 140 can perform logic processing on the first square wave pulse signal p1' and the second square wave pulse signal p2 to obtain a control signal. If the first square wave pulse signal p1' does not exist, the logic control circuit 140 will not output a control signal. In this way, the sampling and holding circuit 120 will no longer continue to sample and hold the maximum forward peak voltage of the resonant voltage.

[0094] For two adjacent periods, the following describes how the sample-and-hold circuit 120 obtains the first peak voltage VC1_1 and the second peak voltage VC1_2.

[0095] In the previous cycle, when the voltage sampling circuit 110 monitors that the change trend of the resonance voltage VQD is gradually rising from 0 to the maximum forward peak voltage, the sampling and holding circuit 120 can sample and hold the maximum forward peak voltage of the resonance voltage VQD according to the control signal, so that the sampling and holding circuit 120 can obtain the peak voltage of the resonance voltage VQD that just appears at the peak position, that is, the first peak voltage VC1_1 corresponding to the resonance voltage VQD in the previous cycle. In addition, the sampling and holding circuit 120 can transmit the first peak voltage VC1_1 to the analog-to-digital conversion circuit 150.

[0096] In the next cycle, when the voltage sampling circuit 110 detects that the resonance voltage VQD gradually rises from 0 to the maximum forward peak voltage again, the sampling and holding circuit 120 can sample and hold the maximum forward peak voltage of the resonance voltage VQD according to the control signal, so that the sampling and holding circuit 120 can obtain the peak voltage of the resonance voltage VQD that just appears at the peak position, that is, the second peak voltage VC1_2 corresponding to the resonance voltage VQD in the next cycle. In addition, the sampling and holding circuit 120 can transmit the second peak voltage VC1_2 to the analog-to-digital conversion circuit 150.

[0097] Based on this, the analog-to-digital conversion circuit 150 can perform analog-to-digital conversion on the first peak voltage VC1_1 to obtain the converted first peak voltage VC1_1. The analog-to-digital conversion circuit 150 can perform analog-to-digital conversion on the second peak voltage VC1_2 to obtain the converted second peak voltage VC1_2. Furthermore, the analog-to-digital conversion circuit 150 can transmit the converted first peak voltage VC1_1 and the converted second peak voltage VC1_2 to the microprocessor 160.

[0098] Furthermore, the microprocessor 160 may obtain a Q value detection result according to the converted first peak voltage VC1_1 and the converted second peak voltage VC1_2.

[0099] The Q value detection circuit, chip, method, transmitting circuit, system and electronic device provided by the present application. The voltage sampling circuit can collect the resonant voltage of the resonant circuit, so that the voltage sampling circuit can monitor the change trend of the resonant voltage. In addition, the voltage sampling circuit transmits the resonant voltage to the sampling and holding circuit and the comparison circuit respectively, so that the comparison circuit can compare the resonant voltage and the reference voltage to obtain the first square wave pulse signal and the second square wave pulse signal, and the logic control circuit can perform logic processing on the first square wave pulse signal and the second square wave pulse signal to obtain the control signal. In this way, when the voltage sampling circuit monitors that the change trend of the resonant voltage is the maximum positive peak voltage, the sampling and holding circuit can sample and hold the maximum positive peak voltage of the resonant voltage according to the control signal, so that the sampling and holding circuit can obtain the first peak voltage and the second peak voltage at the peak position of the resonant voltage that just appears in two adjacent cycles. Furthermore, the analog-to-digital conversion circuit can perform analog-to-digital conversion on the first peak voltage to obtain the converted first peak voltage, and can perform analog-to-digital conversion on the second peak voltage to obtain the converted second peak voltage, so that the microprocessor can obtain the Q value detection result according to the converted first peak voltage and the converted second peak voltage. Since the first peak voltage appears exactly at the peak position in the previous cycle, and the second peak voltage appears exactly at the peak position in the next cycle, the first peak voltage after conversion also appears exactly at the peak position in the previous cycle, and the second peak voltage after conversion appears exactly at the peak position in the next cycle. Thus, the detection accuracy of the Q value detection circuit is improved.

[0100] Based on the description of the above embodiment, a possible implementation of the comparison circuit 130 is exemplified. Fig. 9 , Fig. 9 Shows Figure 7 The schematic diagram of the Q value detection circuit in Figure 2 is shown in Figure 2. Fig. 9 As shown, the comparison circuit 130 may include a first comparator CMP1 and a second comparator CMP2 .

[0101] The first input terminal of the first comparator CMP1 and the first input terminal of the second comparator CMP2 are both electrically connected to the output terminal of the voltage sampling circuit 110, the second input terminal of the first comparator CMP1 is used to access the first reference voltage vth1, the second input terminal of the second comparator CMP2 is used to access the second reference voltage vth2, and the output terminal of the first comparator CMP1 and the output terminal of the second comparator CMP2 are both electrically connected to the input terminal of the logic control circuit 140.

[0102] The first input terminal of the first comparator CMP1 and the first input terminal of the second comparator CMP2 are both positive phase input terminals, and the second input terminal of the first comparator CMP1 and the second input terminal of the second comparator CMP2 are both negative phase input terminals.

[0103] The reference voltage may include: a first reference voltage vth1 and a second reference voltage vth2. The voltage value of the first reference voltage vth1 is different from the voltage value of the second reference voltage vth2, and the second reference voltage vth2 is zero voltage.

[0104] The first comparator CMP1 may compare the resonance voltage VQD with the first reference voltage vth1 and generate a first square wave pulse signal p1.

[0105] The second comparator CMP2 can compare the resonance voltage VQD and the second reference voltage vth2 to generate a second square wave pulse signal p2.

[0106] In addition, the second square wave pulse signal p2 is an enable signal of the operational amplifier AMP, which makes the output voltage VTH1_BUF of the operational amplifier AMP gradually increase from 0 to the maximum forward peak voltage. Similarly, the second square wave pulse signal p2 is an enable signal of the operational amplifier AMP', which makes the output voltage VTH1_BUF' of the operational amplifier AMP' gradually increase from 0 to the maximum forward peak voltage.

[0107] The number of the first comparators CMP1 may be two. For the convenience of distinction, one of them is the first comparator CMP1 and the other is the first comparator CMP1'. The difference between the first comparator CMP1 and the first comparator CMP1' is that the voltage value of the first reference voltage vth1 connected to the second input terminal of the first comparator CMP1 is greater than the voltage value of the first reference voltage vth1' connected to the second input terminal of the first comparator CMP1'.

[0108] Based on the above description, the first comparator CMP1 ′ can compare the resonance voltage VQD and the first reference voltage vth1 ′ to generate a first square wave pulse signal p1 ′.

[0109] In summary, the first comparator generates a first square wave pulse signal by comparing the resonant voltage of the resonant circuit with the first reference voltage. The second comparator generates a second square wave pulse signal by comparing the resonant voltage of the resonant circuit with the second reference voltage. Thus, the comparison circuit can obtain the first square wave pulse signal and the second square wave pulse signal.

[0110] Based on the description of the above embodiment, a possible implementation of the sample and hold circuit 120 is exemplified. Fig. 9 As shown, the sample-and-hold circuit 120 may include: an operational amplifier AMP, a resetter 122 , a first holder 121 and a second holder 123 .

[0111] Since the operational amplifier AMP is a unit gain operational amplifier AMP with no load current at the output terminal of the operational amplifier AMP, after the resonance voltage VQD gradually rises from 0 to the maximum positive peak voltage, the operational amplifier AMP only follows the resonance voltage VQD to rise to the maximum positive peak voltage, but does not follow the resonance voltage VQD to gradually decrease from the maximum positive peak voltage to the maximum negative peak voltage, and does not follow the resonance voltage VQD to gradually rise from the maximum negative peak voltage to 0.

[0112] The first input terminal of the operational amplifier AMP is electrically connected to the output terminal of the voltage sampling circuit 110, the output terminal of the operational amplifier AMP is electrically connected to the input terminal of the first holder 121 and the input terminal of the second holder 123 respectively, the output terminal of the first holder 121 and the output terminal of the second holder 123 are both electrically connected to the input terminal of the analog-to-digital conversion circuit 150, the output terminal of the first holder 121, the output terminal of the second holder 123 and the control terminal of the resetter 122 are all electrically connected to the output terminal of the logic control circuit 140, the second input terminal of the operational amplifier AMP and the first terminal of the resetter 122 are both electrically connected between the output terminal of the operational amplifier AMP and the input terminal of the first holder 121, and the second terminal of the resetter 122 is grounded.

[0113] The control signal may include a first control signal VS1, a second control signal VRST1, and a third control signal VS2. The second control signal VRST1 may include a first sub-control signal VRST1_1 and a second sub-control signal VRST1_2. The first sub-control signal VRST1_1 is used to reset the previously held first peak voltage VC1_1 when the first holder 121 samples and holds the first peak voltage VC1_1. The second sub-control signal VRST1_2 is used to reset the previously held second peak voltage VC1_2 when the second holder 123 samples and holds the second peak voltage VC1_2.

[0114] In the previous cycle, since the operational amplifier AMP can follow the resonance voltage VQD to rise to the maximum forward peak voltage, when the output voltage VTH1_BUF of the operational amplifier AMP gradually rises from 0 to the maximum forward peak voltage, the operational amplifier AMP can obtain the first peak voltage VC1_1.

[0115] Thus, in the previous cycle, the first holder 121 can sample and hold the first peak voltage VC1_1 according to the first control signal VS1, so that the sample and hold circuit 120 can obtain the first peak voltage VC1_1.

[0116] In the next cycle, the resetter 122 may reset the output voltage VTH1_BUF of the operational amplifier AMP according to the second control signal VRST1 , so that the output voltage VTH1_BUF of the operational amplifier AMP changes from the first peak voltage VC1_1 to 0.

[0117] Thus, in the next cycle, since the operational amplifier AMP can again follow the resonance voltage VQD to rise to the maximum forward peak voltage, when the output voltage VTH1_BUF of the operational amplifier AMP gradually rises from 0 to the maximum forward peak voltage, the operational amplifier AMP can obtain the second peak voltage VC1_2.

[0118] Furthermore, in the next cycle, the second holder 123 can sample and hold the second peak voltage VC1_2 according to the third control signal VS2, so that the sample and hold circuit 120 can obtain the second peak voltage VC1_2.

[0119] The number of operational amplifiers AMP, the number of resetters 122, the number of first retainers 121, and the number of second retainers 123 can all be two. For easy distinction, one is the operational amplifier AMP, the other is the operational amplifier AMP', one is the resetter 122, the other is the resetter 122', one is the first retainer 121, the other is the first retainer 121', one is the second retainer 123, and the other is the second retainer 123'.

[0120] Similarly, the control signal may include a first control signal VS1', a second control signal VRST1' and a third control signal VS2'. The second control signal VRST1' may include a first sub-control signal VRST1_1' and a second sub-control signal VRST1_2'. The first sub-control signal VRST1_1' is used to reset the previously held first peak voltage VC1_1' when the first holder 121' samples and holds the first peak voltage VC1_1'. The second sub-control signal VRST1_2' is used to reset the previously held second peak voltage VC1_2' when the second holder 123' samples and holds the second peak voltage VC1_2'.

[0121] Thus, in the previous cycle, the operational amplifier AMP' can obtain the first peak voltage VC1_1', so that the first holder 121' can sample and hold the first peak voltage VC1_1' according to the first control signal VS1', so that the sample-hold circuit 120 can obtain the first peak voltage VC1_1'. In the next cycle, the operational amplifier AMP' can obtain the second peak voltage VC1_2', so that the second holder 123' can sample and hold the second peak voltage VC1_2' according to the third control signal VS2', so that the sample-hold circuit 120 can obtain the second peak voltage VC1_2'.

[0122] In some examples, the microprocessor 160 may specifically obtain the target peak voltage Vth1 according to the converted first peak voltage VC1_1 and the converted second peak voltage VC1_2. Furthermore, the microprocessor 160 may obtain the Q value detection result according to the target peak voltage Vth1.

[0123] If the voltage value of the converted first peak voltage VC1_1 is greater than the voltage value of the converted second peak voltage VC1_2, the microprocessor 160 determines the converted first peak voltage VC1_1 as the target peak voltage. If the voltage value of the converted first peak voltage VC1_1 is less than the voltage value of the converted second peak voltage VC1_2, the microprocessor 160 determines the converted second peak voltage VC1_2 as the target peak voltage.

[0124] Similarly, the microprocessor 160 can obtain the target peak voltage Vth2 according to the converted first peak voltage VC1_1 ′ and the converted second peak voltage VC1_2 ′.

[0125] The microprocessor 160 specifically calculates the Q value detection result according to formula (1).

[0126]

[0127] Wherein, π is pi, N is the period difference between the target peak voltage Vth1 and the target peak voltage Vth2, Vth1 is the target peak voltage obtained by the microprocessor 160 according to the converted first peak voltage VC1_1 and the converted second peak voltage VC1_2, and Vth2 is the target peak voltage obtained by the microprocessor 160 according to the converted first peak voltage VC1_1' and the converted second peak voltage VC1_2'.

[0128] In summary, in the previous cycle, the operational amplifier can obtain the first peak voltage, so that the first holder samples and holds the first peak voltage. In the next cycle, the resetter resets the output voltage of the operational amplifier, so that the operational amplifier once again follows the change of the resonant voltage. In this way, in the next cycle, the operational amplifier can obtain the second peak voltage, so that the second holder samples and holds the second peak voltage. Thus, the sample-and-hold circuit can obtain the first peak voltage and the second peak voltage.

[0129] Based on the description of the above embodiment, a possible implementation of the retainer is exemplified. Fig. 9 As shown, the retainer may include: a control switch and a retaining assembly.

[0130] The first end of the control switch is electrically connected to the output end of the operational amplifier AMP, the second end of the control switch is electrically connected to the input end of the holding component, the output end of the holding component is electrically connected to the input end of the analog-to-digital conversion circuit 150, and the control end of the control switch and the control end of the holding component are both electrically connected to the output end of the logic control circuit 140.

[0131] The first retainer 121 and the second retainer 123 are both retainers. The working principles of the first retainer 121 and the second retainer 123 are similar. For ease of understanding, the following embodiments are described by taking the retainer as the first retainer 121 as an example.

[0132] In the previous cycle, under the action of the first control signal VS1, the control switch is turned on to connect the operational amplifier AMP and the holding component. In this way, after the operational amplifier AMP and the holding component are connected, the holding component can sample and hold the first peak voltage VC1_1, so that the first holder 121 can sample and hold the first peak voltage VC1_1.

[0133] In some examples, the holding component may include a capacitor and a switch.

[0134] The first end of the switch tube is electrically connected to the second end of the control switch, the control end of the switch tube is electrically connected to the output end of the logic control circuit 140, the second end of the switch tube is grounded, and the capacitor is connected in parallel with the switch tube.

[0135] In summary, by controlling the switch, the holding component can sample and hold the peak voltage. Thus, the first holder can sample and hold the first peak voltage, and the second holder can sample and hold the second peak voltage.

[0136] Next, combine Fig.10 , Fig.10 Shows Figure 7 and Fig. 9The working waveform diagram of the Q value detection circuit in FIG. The working principle of the Q value detection circuit 100 is introduced in detail. For two adjacent cycles, T0-T1 is the previous cycle, and T1-T2 is the next cycle.

[0137] At time T0, the resetter 122 can reset the output voltage VTH1_BUF of the operational amplifier AMP according to the second control signal VRST1, so that the output voltage VTH1_BUF of the operational amplifier AMP rises to the maximum forward peak voltage following the resonant voltage VQD. At this time, under the action of the first sub-control signal VRST1_1, the holding component resets the previous first peak voltage VC1_1. In this way, under the action of the first control signal VS1, the control switch S1 is turned on, so that the holding component can sample and hold the first peak voltage VC1_1. Thus, the first holder 121 can sample and hold the first peak voltage VC1_1.

[0138] Similarly, the resetter 122' can reset the output voltage VTH1_BUF' of the operational amplifier AMP' according to the second control signal VRST1', so that the output voltage VTH1_BUF' of the operational amplifier AMP' rises to the maximum forward peak voltage following the resonant voltage VQD. At this time, under the action of the first sub-control signal VRST1_1', the holding component resets the previous first peak voltage VC1_1'. In this way, under the action of the first control signal VS1', the control switch S1' is turned on, so that the holding component can sample and hold the first peak voltage VC1_1'. Thus, the first holder 121' can sample and hold the first peak voltage VC1_1'.

[0139] At time T1, the resetter 122 can reset the output voltage VTH1_BUF of the operational amplifier AMP according to the second control signal VRST1, so that the output voltage VTH1_BUF of the operational amplifier AMP rises to the maximum forward peak voltage following the resonant voltage VQD. At this time, under the action of the second sub-control signal VRST1_2, the holding component resets the previous second peak voltage VC1_2. In this way, under the action of the third control signal VS2, the control switch S2 is turned on, so that the holding component can sample and hold the second peak voltage VC1_2. Thus, the second holder 122 can sample and hold the second peak voltage VC1_2.

[0140] Similarly, the resetter 122' can reset the output voltage VTH1_BUF' of the operational amplifier AMP' according to the second control signal VRST1', so that the output voltage VTH1_BUF' of the operational amplifier AMP' rises to the maximum forward peak voltage following the resonant voltage VQD. At this time, under the action of the second sub-control signal VRST1_2', the holding component resets the previous second peak voltage VC1_2'. In this way, under the action of the third control signal VS2', the control switch S2' is turned on, so that the holding component can sample and hold the second peak voltage VC1_2'. Thus, the second holder 122' can sample and hold the second peak voltage VC1_2'.

[0141] At time T2, the resetter 122 can reset the output voltage VTH1_BUF of the operational amplifier AMP according to the second control signal VRST1, so that the output voltage VTH1_BUF of the operational amplifier AMP rises to the maximum forward peak voltage following the resonant voltage VQD. At this time, under the action of the first sub-control signal VRST1_1, the holding component resets the previous first peak voltage VC1_1. In this way, under the action of the first control signal VS1, the control switch S1 is turned on, so that the holding component can sample and hold the first peak voltage VC1_1. Thus, the first holder 121 can sample and hold the first peak voltage VC1_1.

[0142] Similarly, the resetter 122' can reset the output voltage VTH1_BUF' of the operational amplifier AMP' according to the second control signal VRST1', so that the output voltage VTH1_BUF' of the operational amplifier AMP' rises to the maximum forward peak voltage following the resonant voltage VQD. At this time, under the action of the first sub-control signal VRST1_1', the holding component resets the previous first peak voltage VC1_1'. In this way, under the action of the first control signal VS1', the control switch S1' is turned on, so that the holding component can sample and hold the first peak voltage VC1_1'. Thus, the first holder 121' can sample and hold the first peak voltage VC1_1'.

[0143] At time T3, the resetter 122' can reset the output voltage VTH1_BUF' of the operational amplifier AMP' according to the second control signal VRST1', so that the output voltage VTH1_BUF' of the operational amplifier AMP' rises to the maximum forward peak voltage following the resonant voltage VQD. At this time, under the action of the first sub-control signal VRST1_1', the holding component resets the previous first peak voltage VC1_1'. In this way, under the action of the first control signal VS1', the control switch S1' is turned on, so that the holding component can sample and hold the first peak voltage VC1_1'. Thus, the first holder 121' can sample and hold the first peak voltage VC1_1'.

[0144] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A Q value detection circuit, characterized in that: Applied to a wireless charging transmitting circuit, the wireless charging transmitting circuit includes a resonant circuit; the Q value detection circuit includes: a voltage sampling circuit, a sample-and-hold circuit, a comparison circuit, a logic control circuit, an analog-to-digital conversion circuit and a microprocessor; The input end of the voltage sampling circuit is electrically connected between the capacitor and the transmitting coil in the resonant circuit, the output end of the voltage sampling circuit is electrically connected to the input end of the sampling and holding circuit and the first input end of the comparison circuit, the output end of the comparison circuit is electrically connected to the input end of the logic control circuit, the output end of the logic control circuit is electrically connected to the control end of the sampling and holding circuit, the output end of the sampling and holding circuit is electrically connected to the input end of the analog-to-digital conversion circuit, the output end of the analog-to-digital conversion circuit is electrically connected to the input end of the microprocessor, and the second input end of the comparison circuit is used to access the reference voltage; The voltage sampling circuit is used to collect the resonant voltage of the resonant circuit to monitor the change trend of the resonant voltage, and transmit the resonant voltage to the sampling and holding circuit and the comparison circuit respectively; The comparison circuit is used to compare the resonant voltage and the reference voltage to obtain a first square wave pulse signal and a second square wave pulse signal respectively, and transmit the first square wave pulse signal and the second square wave pulse signal to the logic control circuit, the reference voltage includes: a first reference voltage and a second reference voltage, the first reference voltage is used to determine the peak voltage of the resonant voltage, and the second reference voltage is used to determine the period where the peak voltage of the resonant voltage is located; The logic control circuit is used to perform logic processing on the first square wave pulse signal and the second square wave pulse signal to obtain a control signal, and transmit the control signal to the sampling and holding circuit; The sampling and holding circuit is used for sampling and holding the maximum forward peak voltage of the resonant voltage under the action of the control signal for two adjacent cycles, when the voltage sampling circuit monitors that the change trend of the resonant voltage is gradually rising from 0 to the maximum forward peak voltage, to obtain a first peak voltage corresponding to the resonant voltage in the previous cycle and a second peak voltage corresponding to the resonant voltage in the next cycle, and transmit the first peak voltage and the second peak voltage to the analog-to-digital conversion circuit; The analog-to-digital conversion circuit is used to perform analog-to-digital conversion on the first peak voltage and the second peak voltage respectively to obtain a converted first peak voltage and a converted second peak voltage, and transmit the converted first peak voltage and the converted second peak voltage to the microprocessor; The microprocessor is used to obtain a Q value detection result according to the converted first peak voltage and the converted second peak voltage.

2. The Q value detection circuit according to claim 1, characterized in that: The control signal includes a first control signal, a second control signal and a third control signal, and the sampling and holding circuit includes: an operational amplifier, a resetter, a first holder and a second holder; wherein the operational amplifier is a unit gain operational amplifier with no load current at the output end of the operational amplifier; The first input terminal of the operational amplifier is electrically connected to the output terminal of the voltage sampling circuit, the output terminal of the operational amplifier is electrically connected to the input terminal of the first holder and the input terminal of the second holder respectively, the output terminal of the first holder and the output terminal of the second holder are both electrically connected to the input terminal of the analog-to-digital conversion circuit, the output terminal of the first holder, the output terminal of the second holder and the control terminal of the resetter are all electrically connected to the output terminal of the logic control circuit, the second input terminal of the operational amplifier and the first terminal of the resetter are both electrically connected between the output terminal of the operational amplifier and the input terminal of the first holder, and the second terminal of the resetter is grounded; The operational amplifier is used to follow the change of the resonant voltage in the previous cycle, and obtain the first peak voltage when the output voltage of the operational amplifier gradually increases from 0 to the maximum forward peak voltage; The first holder is used to sample and hold the first peak voltage under the action of the first control signal in the previous cycle; The resetter is used for resetting the output voltage of the operational amplifier under the action of the second control signal in the next cycle, so that the output voltage of the operational amplifier changes from the first peak voltage to 0; The operational amplifier is further configured to obtain the second peak voltage in the latter period, following the change of the resonant voltage, when the output voltage of the operational amplifier gradually increases from 0 to the maximum forward peak voltage; The second holder is used for sampling and holding the second peak voltage under the action of the third control signal in the next cycle.

3. The Q value detection circuit according to claim 2, characterized in that the retainer include: Control switches and holding components; The first end of the control switch is electrically connected to the output end of the operational amplifier, the second end of the control switch is electrically connected to the input end of the holding component, the output end of the holding component is electrically connected to the input end of the analog-to-digital conversion circuit, and the control end of the control switch and the control end of the holding component are both electrically connected to the output end of the logic control circuit.

4. The Q value detection circuit according to claim 3, characterized in that: The holding component includes a capacitor and a switch tube, the first end of the switch tube is electrically connected to the second end of the control switch, the control end of the switch tube is electrically connected to the output end of the logic control circuit, the second end of the switch tube is grounded, and the capacitor is connected in parallel with the switch tube.

5. The Q value detection circuit according to any one of claims 1 to 4, characterized in that: The microprocessor is specifically used to obtain a target peak voltage according to the converted first peak voltage and the converted second peak voltage, and to obtain the Q value detection result according to the target peak voltage.

6. The Q value detection circuit according to any one of claims 1 to 4, characterized in that: The comparison circuit includes a first comparator and a second comparator, wherein the first input terminal of the first comparator and the first input terminal of the second comparator are both electrically connected to the output terminal of the voltage sampling circuit, the second input terminal of the first comparator is used to access the first reference voltage, the second input terminal of the second comparator is used to access the second reference voltage, and the output terminal of the first comparator and the output terminal of the second comparator are both electrically connected to the input terminal of the logic control circuit; The first comparator is used to compare the resonant voltage and the first reference voltage to generate the first square wave pulse signal; The second comparator is used to compare the resonant voltage and the second reference voltage to generate the second square wave pulse signal.

7. A Q value detection method, characterized in that: The method is applied to the Q value detection circuit according to any one of claims 1 to 6, and the method comprises: The voltage sampling circuit collects the resonant voltage of the resonant circuit to monitor the change trend of the resonant voltage, and transmits the resonant voltage to the sampling and holding circuit and the comparison circuit respectively; The comparison circuit compares the resonant voltage of the resonant circuit with the reference voltage to obtain a first square wave pulse signal and a second square wave pulse signal respectively, and transmits the first square wave pulse signal and the second square wave pulse signal to the logic control circuit, wherein the reference voltage includes: a first reference voltage and a second reference voltage, wherein the first reference voltage is used to determine the peak voltage of the resonant voltage, and the second reference voltage is used to determine the period where the peak voltage of the resonant voltage is located; The logic control circuit performs logic processing on the first square wave pulse signal and the second square wave pulse signal to obtain a control signal, and transmits the control signal to the sampling and holding circuit; For two adjacent cycles, when the voltage sampling circuit detects that the change trend of the resonant voltage is gradually rising from 0 to the maximum forward peak voltage, the sampling and holding circuit samples and holds the maximum forward peak voltage of the resonant voltage under the action of the control signal, obtains a first peak voltage corresponding to the resonant voltage in the previous cycle and a second peak voltage corresponding to the resonant voltage in the next cycle, and transmits the first peak voltage and the second peak voltage to the analog-to-digital conversion circuit; The analog-to-digital conversion circuit performs analog-to-digital conversion on the first peak voltage and the second peak voltage to obtain a converted first peak voltage and a converted second peak voltage; The microprocessor obtains a Q value detection result according to the converted first peak voltage and the converted second peak voltage.

8. A foreign body detection method, characterized in that: The method is applied to the Q value detection circuit according to any one of claims 1 to 6, and the method comprises: According to the Q value detection result, it is determined whether there is a foreign object within the working range of the wireless charging transmitting circuit.

9. A wireless charging transmitting circuit, characterized in that: include: An inverter circuit, a resonant circuit, and a Q value detection circuit as claimed in any one of claims 1 to 6; The inverter circuit and the Q value detection circuit are both electrically connected to the resonance circuit.

10. A chip, characterized in that: include: The Q value detection circuit according to any one of claims 1 to 6, or the wireless charging transmission circuit according to claim 9.

11. An electronic device, characterized in that: include: The chip as claimed in claim 10.

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