A repairable reference voltage generating circuit and method with internal feedback

Abstract

The application relates to a repairable adjustable reference voltage generating circuit and method with internal feedback. The circuit structure of the application comprises a first-stage internal loop and a second-stage reference voltage adjustment loop. The first-stage internal loop comprises a reference voltage circuit, a differential output sampling circuit, an error amplifier circuit and an output driving circuit. The output VREF of the reference voltage circuit is connected with the error amplifier circuit. The output VOD of the differential output sampling circuit is connected with the error amplifier circuit. The output VFB of the error amplifier circuit is connected with the output driving circuit. The differential output VA and VB of the output driving circuit are connected with the differential output sampling circuit. The second-stage reference voltage adjustment loop comprises a reference voltage circuit, an error amplifier circuit and a reference adjustment circuit. The output VREF of the reference voltage circuit is connected with the error amplifier circuit. The output VFB of the error amplifier circuit is connected with the reference adjustment circuit. The output of the reference adjustment circuit is connected with the output VREF of the reference voltage circuit. The application adjusts the output swing and swing reference voltage through the structure of the two-stage loop, and guarantees the swing stability and consistency of the differential output voltage in the MLVDS driving circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and particularly relates to an adjustable reference voltage generation circuit and method with internal feedback. Background Technology

[0002] LVDS is a low-voltage differential signaling interface technology. With its inherent low voltage, low power consumption, and low noise characteristics, it has become the preferred interface standard for broadband high-speed system design. In addition to point-to-point transmission, multi-point LVDS (MLVDS) bus transceivers support multi-node interconnection, providing multiple high data rates and enabling reliable data transmission systems across multiple nodes. The differential voltage swing output by the MLVDS driver ranges from 480mV to 650mV. To ensure the stability and consistency of the signal swing across multiple channels, a stable reference voltage generation circuit is required. Summary of the Invention

[0003] To address the aforementioned technical problems in the background art, this invention provides an adjustable reference voltage generation circuit and method with internal feedback. By adjusting the output swing and swing reference voltage through a two-stage loop structure, the differential output voltage swing in the MLVDS drive circuit is kept stable and consistent.

[0004] The technical solution of this invention is: an adjustable reference voltage generation circuit with internal feedback, characterized in that: the adjustable reference voltage generation circuit with internal feedback includes a first-stage internal loop and a second-stage reference voltage adjustment loop. The first-stage internal loop includes a reference voltage circuit, a differential output sampling circuit, an error amplifier circuit, and an output driving circuit. The output VREF of the reference voltage circuit is connected to the error amplifier circuit. The output VOD of the differential output sampling circuit is connected to the error amplifier circuit. The output VFB of the error amplifier circuit is connected to the output driving circuit. The differential outputs VA and VB of the output driving circuit are connected to the differential output sampling circuit. The second-stage reference voltage adjustment loop includes a reference voltage circuit, an error amplifier circuit, and a reference adjustment circuit. The output VREF of the reference voltage circuit is connected to the error amplifier circuit. The output VFB of the error amplifier circuit is connected to the reference adjustment circuit. The output of the reference adjustment circuit is connected to the output VREF of the reference voltage circuit.

[0005] Furthermore, the reference voltage circuit is composed of a current IEF, a positive temperature coefficient resistor RP, and a negative temperature coefficient resistor RN connected in series. The reference voltage VREF of the differential mode swing of the reference voltage circuit is generated by the voltage drop across the resistor caused by the current IEF.

[0006] Furthermore, the differential output sampling circuit includes a high-level sampling circuit, a low-level sampling circuit, and a differential sampling circuit. The input of the high-level sampling circuit is connected to the differential outputs VA and VB of the output driving circuit, and the output is the high-level voltage VOH of the input differential signal. The input of the low-level sampling circuit is connected to the differential outputs VA and VB of the output driving circuit, and the output voltage is the low-level voltage VOL of the differential signal. The input of the differential sampling circuit is connected to the outputs VOH and VOL of the high-level sampling circuit and the low-level sampling circuit. The differential output voltage VOD is obtained by subtracting the high and low levels.

[0007] Furthermore, the output drive circuit includes a bias current IBN, a bias current transistor PM0, a PMOS driver transistor PM1, a PMOS driver transistor PM2, an NMOS driver transistor NM1, an NMOS driver transistor NM2, and a load resistor ROUT. The bias current IBN is a fixed current bias. The gate input of the bias current transistor PM0 is connected to the output voltage VFB of the error amplifier, and the output is connected to the PMOS driver transistors PM1 and PM2. The drive current in the output drive circuit can be adjusted. The gates of the PMOS driver transistors PM1 and NMOS driver transistor NM1, as well as the gates of the PMOS driver transistors PM2 and NMOS driver transistor NM2, respectively receive the differential signals INN and INP from the previous stage differential output sampling circuit. The load resistor ROUT is connected to the PMOS driver transistors PM1, PM2, NMOS driver transistor NM1, and NM2 respectively. The drive current flowing through the load resistor ROUT generates output differential signals VA and VB with opposite phases.

[0008] Furthermore, the reference adjustment circuit includes a PMOS current transistor PM3, a resistor R0, and an NMOS switch NM3. The gate of the PMOS current transistor PM3 is connected to the output VFB of the error amplifier circuit, the source is connected to the power supply, the drain is connected to the positive terminal VG of the resistor R0, and the other end of the resistor R0 is grounded. The gate of the NMOS switch NM3 is connected to the positive terminal VG of the resistor R0, the source is grounded, and the drain is connected to the output VREF of the reference voltage circuit.

[0009] A method for implementing the above-described adjustable reference voltage generation circuit with internal feedback, characterized in that the method includes the following steps:

[0010] 1) In the first-stage internal loop, when the output VOD of the differential output sampling circuit is greater than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit becomes higher, which reduces the drive current of the PMO transistor in the output drive circuit, thereby reducing the differential swing of the output VA and VB in the output drive circuit, and thus reducing the VOD in the output drive circuit, and the internal loop tends to be stable; when the output VOD of the differential output sampling circuit is less than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit becomes lower, which increases the drive current of the PMO transistor in the output drive circuit, thereby increasing the differential swing of the output VA and VB in the output drive circuit, and thus increasing the VOD in the output drive circuit, and the first-stage internal loop tends to be stable.

[0011] 2) In the second-stage reference voltage adjustment loop, when the output VOD of the differential output sampling circuit is less than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit decreases, causing the drive current of the PMO transistor in the output drive circuit to increase. This increases the differential swing of the outputs VA and VB in the output drive circuit, and consequently increases the VOD in the output drive circuit. When VOD is still less than VREF, the first-stage internal loop is unstable and cannot meet the swing requirements, so the second-stage reference voltage adjustment loop is activated. When VFB decreases, the current transistor PM3 is turned on, and the current flows through the resistor RO to generate a voltage VG. When VG is greater than the threshold voltage of the switching transistor NM3, the switching transistor NM3 is turned on. The on-resistance of the switching transistor NM3 is then connected in parallel with the positive temperature coefficient resistor RP and the negative temperature coefficient resistor RN connected in series in the reference voltage circuit, and the reference voltage VREF decreases until the output VREF of the reference voltage circuit is equal to the output VOD of the differential output sampling circuit. Both loops tend to stabilize.

[0012] This invention provides an adjustable reference voltage generation circuit and method with internal feedback. The circuit utilizes a dual-loop differential-mode feedback mechanism to achieve a stable output swing. A control signal is generated by comparing the differential-mode voltage with a reference voltage to adjust the output signal current, thereby achieving the required stable output swing. Simultaneously, a reverse switch controls the reference voltage value. If the internal loop cannot meet the swing requirements, a second-stage loop is activated to adjust the reference voltage. Therefore, the beneficial effect of this invention is that it adjusts the output swing and swing reference voltage through a two-stage loop structure, ensuring the stability and consistency of the differential output voltage swing in the MLVDS drive circuit. Attached Figure Description

[0013] Figure 1 This is an overall circuit block diagram of the present invention;

[0014] Figure 2 This is a circuit diagram of the reference voltage circuit of the present invention;

[0015] Figure 3 This is a circuit diagram of the differential output sampling circuit of the present invention;

[0016] Figure 4 This is a circuit diagram of the error amplifier circuit of the present invention;

[0017] Figure 5 This is a circuit diagram of the output drive circuit of the present invention;

[0018] Figure 6 This is a circuit diagram of the reference adjustment circuit of the present invention. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0020] See Figure 1 The specific embodiment of the internal feedback adjustable reference voltage generation circuit of the present invention includes a first-stage internal loop and a second-stage reference voltage adjustment loop.

[0021] The first-stage internal loop includes a reference voltage circuit, a differential output sampling circuit, an error amplifier circuit, and an output driver circuit. The output VREF of the reference voltage circuit is connected to the error amplifier circuit, the output VOD of the differential output sampling circuit is connected to the error amplifier circuit, the output VFB of the error amplifier circuit is connected to the output driver circuit, and the differential outputs VA and VB of the output driver circuit are connected to the differential output sampling circuit.

[0022] The second-stage reference voltage adjustment loop includes a reference voltage circuit, an error amplifier circuit, and a reference adjustment circuit. The output VREF of the reference voltage circuit is connected to the error amplifier circuit, the output VFB of the error amplifier circuit is connected to the reference adjustment circuit, and the output of the reference adjustment circuit is connected to the output VREF of the reference voltage circuit.

[0023] In the first-stage internal loop, when the output VOD of the differential output sampling circuit is greater than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit increases, causing the drive current of the PMO transistor in the output driver circuit to decrease. This reduces the differential swing of the outputs VA and VB in the output driver circuit, consequently decreasing VOD in the output driver circuit, and the internal loop tends to stabilize. When the output VOD of the differential output sampling circuit is less than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit decreases, causing the drive current of the PMO transistor in the output driver circuit to increase. This increases the differential swing of the outputs VA and VB in the output driver circuit, consequently increasing VOD in the output driver circuit, and the first-stage internal loop tends to stabilize.

[0024] In the second-stage reference voltage adjustment loop, when the output VOD of the differential output sampling circuit is less than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit decreases, causing the drive current of the PMO transistor in the output drive circuit to increase. This increases the differential swing of the outputs VA and VB in the output drive circuit, and consequently, increases VOD in the output drive circuit. When VOD is still less than VREF, the first-stage internal loop is unstable and cannot meet the swing requirements, thus activating the second-stage reference voltage adjustment loop. When VFB decreases, the current transistor PM3 conducts, and the current flows through the resistor RO to generate a voltage VG. When VG is greater than the threshold voltage of the switching transistor NM3, the switching transistor NM3 conducts. The on-resistance of the switching transistor NM3 is then connected in parallel with the positive temperature coefficient resistor RP and the negative temperature coefficient resistor RN, which are connected in series in the reference voltage circuit. This reduces the reference voltage VREF until the output VREF of the reference voltage circuit equals the output VOD of the differential output sampling circuit, at which point both loops tend to stabilize.

[0025] refer to Figure 2 The specific embodiment of the reference voltage circuit of the present invention includes a current IREF, a positive temperature coefficient resistor RP, and a negative temperature coefficient resistor RN. The differential mode swing reference voltage VREF is generated by the voltage drop across the resistor caused by the current IREF. Since the resistance changes significantly with temperature, it is necessary to select a current that changes in the opposite direction to the resistance to counteract the effect of temperature on the reference voltage. In this circuit, the negative temperature coefficient current IREF and the positive temperature coefficient resistor are selected to generate the differential mode swing reference voltage VREF. Since the slopes of the current and resistance changes with temperature are not consistent, the positive temperature coefficient resistor RP and the negative temperature coefficient resistor RN are connected in series, and the ratio of the two resistors is adjusted so that the final differential mode swing reference voltage changes less with temperature.

[0026] The input of the differential sampling circuit is connected to the differential outputs VA and VB of the output drive circuit. The circuit calculates the difference between the high and low levels to obtain the differential output voltage VOD.

[0027] The error amplifier circuit compares the differential output voltage swing VOD with the swing reference voltage VREF. The positive input is connected to the output VOD of the differential output sampling circuit, and the negative input is connected to the output VREF of the reference voltage circuit.

[0028] See Figure 3The differential sampling circuit of this invention includes a high-level sampling circuit, a low-level sampling circuit, and a differential sampling circuit. The input of the high-level sampling circuit is connected to the differential outputs VA and VB of the output driving circuit, and its output is the high-level voltage VOH of the input differential signal. The input of the low-level sampling circuit is connected to the differential outputs VA and VB of the output driving circuit, and its output voltage is the low-level voltage VOL of the differential signal. The input of the differential sampling circuit is connected to the outputs VOH and VOL of the high-level and low-level sampling circuits. The differential output voltage VOD is obtained by subtracting the high and low levels. The high-level sampling circuit, low-level sampling circuit, and differential sampling circuit can all employ existing circuit structures.

[0029] See Figure 4 The error amplifier circuit of this invention compares the differential output voltage swing VOD and the swing reference voltage VREF. The positive input is connected to the output VOD of the differential output sampling circuit, and the negative input is connected to the output VREF of the reference voltage circuit. The error amplifier circuit can adopt an existing circuit structure.

[0030] See Figure 5 The output drive circuit of this invention, in a specific embodiment, includes a bias current IBN, a bias current transistor PM0, drive transistors PM1, PM2, NM1, NM2, and a load resistor ROUT. The bias current IBN is a fixed current bias. The gate input of the bias current transistor PM0 is connected to the output voltage VFB of the error amplifier, allowing adjustment of the drive current in the output drive circuit. The gates of drive transistors PM1 and NM1, and the gates of PM2 and NM2, respectively receive differential signals INN and INP from the preceding stage. The drive current flowing through the 100Ω load resistor ROUT generates output differential signals VA and VB with opposite phases.

[0031] Referring to 6, the structure of a specific embodiment of the reference adjustment circuit of the present invention includes a current transistor PM3, a resistor R0, and a switching transistor NM3. The gate of the current transistor PM3 is connected to the output VFB of the error amplifier circuit, the source is connected to the power supply, the drain is connected to the positive terminal VG of the resistor R0, and the other end of the resistor R0 is grounded. The gate of NM3 is connected to the positive terminal VG of the resistor R0, the source is grounded, and the drain is connected to the output VREF of the reference voltage circuit.

[0032] The present invention also provides a method for an adjustable reference voltage generation circuit with internal feedback, the method comprising the following steps:

[0033] 1) In the first-stage internal loop, when the output VOD of the differential output sampling circuit is greater than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit becomes higher, which reduces the drive current of the PMO transistor in the output drive circuit. This reduces the differential swing of the outputs VA and VB in the output drive circuit, and consequently reduces the VOD in the output drive circuit, making the internal loop more stable. When the output VOD of the differential output sampling circuit is less than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit becomes lower, which increases the drive current of the PMO transistor in the output drive circuit. This increases the differential swing of the outputs VA and VB in the output drive circuit, and consequently increases the VOD in the output drive circuit, making the first-stage internal loop more stable.

[0034] 2) In the second-stage reference voltage adjustment loop, when the output VOD of the differential output sampling circuit is less than the output VREF of the reference voltage circuit, the output VFB of the error amplifier circuit decreases, causing the drive current of the PMO transistor in the output drive circuit to increase. This increases the differential swing of the outputs VA and VB in the output drive circuit, and consequently increases the VOD in the output drive circuit. When VOD is still less than VREF, the first-stage internal loop is unstable and cannot meet the swing requirements, so the second-stage reference voltage adjustment loop is activated. When VFB decreases, the current transistor PM3 is turned on, and the current flows through the resistor RO to generate a voltage VG. When VG is greater than the threshold voltage of the switching transistor NM3, the switching transistor NM3 is turned on. The on-resistance of the switching transistor NM3 is then connected in parallel with the positive temperature coefficient resistor RP and the negative temperature coefficient resistor RN connected in series in the reference voltage circuit, and the reference voltage VREF decreases until the output VREF of the reference voltage circuit is equal to the output VOD of the differential output sampling circuit. Both loops tend to stabilize.

[0035] The technical contents of this invention and those not specifically described in the above embodiments are the same as those in the prior art.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An adjustable reference voltage generation circuit with internal feedback, characterized in that: The adjustable reference voltage generation circuit with internal feedback includes a first-stage internal loop and a second-stage reference voltage adjustment loop. The first-stage internal loop includes a reference voltage circuit, a differential output sampling circuit, an error amplifier circuit, and an output drive circuit. The output VREF of the reference voltage circuit is connected to the error amplifier circuit, the output VOD of the differential output sampling circuit is connected to the error amplifier circuit, the output VFB of the error amplifier circuit is connected to the output drive circuit, and the differential outputs VA and VB of the output drive circuit are connected to the differential output sampling circuit. The second-stage reference voltage adjustment loop includes a reference voltage circuit, an error amplifier circuit, and a reference adjustment circuit. The circuit includes a reference voltage circuit whose output VREF is connected to an error amplifier circuit, an error amplifier circuit whose output VFB is connected to a reference adjustment circuit, and a reference adjustment circuit whose output is connected to the reference voltage circuit's output VREF. The reference adjustment circuit includes a PMOS transistor PM3, a resistor R0, and an NMOS switch NM3. The gate of the PMOS transistor PM3 is connected to the error amplifier circuit's output VFB, its source is connected to the power supply, its drain is connected to the positive terminal VG of the resistor R0, and the other end of the resistor R0 is grounded. The gate of the NMOS switch NM3 is connected to the positive terminal VG of the resistor R0, its source is grounded, and its drain is connected to the reference voltage circuit's output VREF.

2. The adjustable reference voltage generating circuit with internal feedback according to claim 1, characterized in that: The reference voltage circuit is composed of a current IEF, a positive temperature coefficient resistor RP, and a negative temperature coefficient resistor RN connected in series. The reference voltage VREF of the differential mode swing of the reference voltage circuit is generated by the voltage drop across the resistor caused by the current IEF.

3. The adjustable reference voltage generating circuit with internal feedback according to claim 2, characterized in that: The differential output sampling circuit includes a high-level sampling circuit, a low-level sampling circuit, and a differential sampling circuit. The input of the high-level sampling circuit is connected to the differential outputs VA and VB of the output driving circuit, and the output is the high-level voltage VOH of the input differential signal. The input of the low-level sampling circuit is connected to the differential outputs VA and VB of the output driving circuit, and the output voltage is the low-level voltage VOL of the differential signal. The input of the differential sampling circuit is connected to the outputs VOH and VOL of the high-level sampling circuit and the low-level sampling circuit. The differential output voltage VOD is obtained by subtracting the high and low levels.

4. The adjustable reference voltage generating circuit with internal feedback according to claim 3, characterized in that: The output drive circuit includes a bias current IBN, a bias current transistor PM0, PMOS driver transistors PM1, PM2, NMOS driver transistors NM1, NMOS driver transistors NM2, and a load resistor ROUT. The bias current IBN is a fixed current bias. The gate input of the bias current transistor PM0 is connected to the output voltage VFB of the error amplifier, and the output is connected to PMOS driver transistors PM1 and PM2. The drive current in the output drive circuit can be adjusted. The gates of PMOS driver transistors PM1 and NMOS driver transistor NM1, and the gates of PMOS driver transistors PM2 and NMOS driver transistor NM2, respectively receive differential signals INN and INP from the previous stage differential output sampling circuit. The load resistor ROUT is connected to MOS driver transistors PM1, PM2, NMOS driver transistor NM1, and NM2. The drive current flowing through the load resistor ROUT generates output differential signals VA and VB with opposite phases.

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