A driving circuit of a display panel and the display panel

Abstract

The application discloses a driving circuit of a display panel and the display panel, and relates to the technical field of display panels, and specifically discloses a driving circuit of a display panel and the display panel, which comprises a pixel circuit and a signal generating circuit; the pixel circuit comprises a driving module, an n-gate transistor and a voltage compensation module, and the output end of the signal generating circuit is electrically connected with the voltage compensation module; the signal generating circuit is responsive to a first control signal, the first voltage end is conductive with the output end of the signal generating circuit in at least part of the time period in the first stage, and the first voltage end is disconnected with the output end of the signal generating circuit in the second stage; the second voltage end is disconnected with the output end of the signal generating circuit in the first stage in response to a second control signal, and the second voltage end is conductive with the output end of the signal generating circuit in at least part of the time period in the second stage. The application can output the compensation signal without a specific display driving chip, so as to stabilize the potential of the control end of the driving module in the pixel circuit, keep the luminance of the light-emitting element stable, and improve the flicker problem of the display picture.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a driving circuit for a display panel and a display panel. Background Technology

[0002] With the development of display technology, the application of display panels is becoming more and more widespread, and correspondingly, the requirements for display panels are also becoming higher and higher. However, existing display panels have a flickering phenomenon, especially when the refresh rate is low, the flickering phenomenon is more obvious, which seriously affects the display effect of the display panel. Summary of the Invention

[0003] This invention provides a driving circuit and a display panel to stabilize the potential of the control terminal of the driving module in the pixel circuit, thereby maintaining the brightness of the light-emitting element and improving the flickering phenomenon of the display panel.

[0004] In a first aspect, the present invention provides a driving circuit for a display panel, comprising a pixel circuit and a signal generation circuit; the pixel circuit includes a driving module, an n-gate transistor, and a voltage compensation module, wherein the n-gate transistor is electrically connected to the control terminal of the driving module, and the voltage compensation module is electrically connected to an intermediate node in the n-gate transistor, the intermediate node being a common node of any two transistors in the n-gate transistor; the voltage compensation module is used to compensate the voltage of the intermediate node according to a received compensation signal, so that the voltage difference between the intermediate node and the control terminal of the driving module is stabilized within a preset range; wherein n is greater than or equal to 2; the output terminal of the signal generation circuit is electrically connected to the voltage compensation module, and the signal generation circuit includes a switching module and a first storage module; the output terminals of the switching module are respectively... The switching module is electrically connected to the output terminals of the first storage module and the signal generation circuit. It is electrically connected to a first voltage terminal and a second voltage terminal, and receives a first control signal and a second control signal respectively. The first voltage at the first voltage terminal is different from the second voltage at the second voltage terminal. The signal generation circuit operates in a first stage and a second stage. In response to the first control signal, the first voltage terminal and the output terminal of the signal generation circuit are connected for at least a portion of the time in the first stage, and disconnected from the output terminal of the signal generation circuit in the second stage. In response to the second control signal, the second voltage terminal and the output terminal of the signal generation circuit are disconnected in the first stage, and connected for at least a portion of the time in the second stage. Optionally, in the first stage, the switching module charges the first storage module according to the first control signal and the first voltage at the first voltage terminal to change the output voltage of the signal generation circuit to the first voltage. Optionally, the first voltage is greater than the second voltage.

[0005] Optionally, the switching module includes a first switching unit and a second switching unit; the control terminal of the first switching unit is connected to a first control signal, the first terminal of the first switching unit is electrically connected to a first voltage terminal, and the second terminal of the first switching unit is electrically connected to the output terminal of the switching module; the control terminal of the second switching unit is connected to a second control signal, the first terminal of the second switching unit is electrically connected to a second voltage terminal, and the second terminal of the second switching unit is electrically connected to the output terminal of the switching module. Optionally, the first switching unit includes a first transistor, and the second switching unit includes a second transistor; the gate of the first transistor serves as the control terminal of the first switching unit, the first electrode of the first transistor serves as the first terminal of the first switching unit, and the second electrode of the first transistor serves as the second terminal of the first switching unit; the gate of the second transistor serves as the control terminal of the second switching unit, the first electrode of the second transistor serves as the first terminal of the second switching unit, and the second electrode of the second transistor serves as the second terminal of the second switching unit. Optionally, in the first stage, the first control signal is at an on level, and the second control signal is at an off level; in the second stage, the first control signal is at an off level, and the second control signal includes at least two on pulses.

[0006] Optionally, the second stage includes a first interval and a second interval; the switching module is used to discharge to the second voltage terminal in the first interval according to the second control signal, so as to reduce the output voltage of the signal generation circuit to the second voltage; the first storage module is used to maintain the voltage at the output terminal of the signal generation circuit in the second interval. Optionally, the compensation signal is a periodic voltage signal, and the compensation signal of one cycle includes the voltage signal output by the signal generation circuit in the first stage, the first interval, and the second interval.

[0007] Secondly, embodiments of the present invention provide a display panel, including the driving circuit of the display panel described in any one of the first aspects.

[0008] The driving circuit of the display panel in this embodiment of the invention includes a pixel circuit and a signal generation circuit. The signal generation circuit includes a switching module and a first storage module. The switching module receives a first control signal and a second control signal, and under the control of the first and second control signals, periodically turns on and off the voltage regulation path between the first storage module and the first and second voltage terminals to adjust the output voltage of the signal generation circuit, i.e., adjust the compensation signal and output it to the voltage compensation module of the pixel circuit. The voltage compensation module compensates the voltage of the intermediate node of the n-gate transistor according to the compensation signal, so that the voltage difference between the intermediate node and the control terminal of the driving module is stabilized within a preset range. In this way, the average voltage of the intermediate node can be close to the voltage of the control terminal of the driving module, thereby effectively reducing the leakage current of the n-gate transistor, so that the voltage of the control terminal of the driving module can be maintained better, thereby ensuring the stability of the driving current generated by the driving module, keeping the brightness of the light-emitting element stable, and improving the low-frequency flicker phenomenon. In addition, the display panel of this embodiment of the invention does not require a specific display driver chip to output a periodically changing and flexibly controllable compensation signal, which can achieve the purpose of screen self-control to replace external chip control, thus expanding the application scenarios of the display panel. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 These are measured data on the brightness fluctuation of AMOLED modules under 60Hz and 5Hz conditions in related technologies;

[0011] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of the structure of a driving circuit for a display panel provided in an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram of the structure of a driving circuit for another display panel provided in an embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram of a signal generation circuit provided in an embodiment of the present invention;

[0015] Figure 6 This is a schematic diagram of another signal generation circuit provided in an embodiment of the present invention;

[0016] Figure 7 This is a schematic diagram of the voltage waveforms of a compensation signal, a first control signal, and a second control signal provided in an embodiment of the present invention;

[0017] Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0018] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0019] Figure 10 This is a schematic diagram of the voltage waveform of an intermediate node provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] As mentioned in the background section, existing display panels are prone to flickering at low frequencies. After careful research, the inventors discovered that the cause of this technical problem is:

[0022] The display panel includes pixel circuitry for light-emitting display. Each pixel circuit includes a driving transistor, a storage capacitor, and at least one switching transistor. The switching transistor is electrically connected to the gate of the driving transistor. The storage capacitor stores the voltage at the gate of the driving transistor. During the light-emitting phase, the driving transistor generates a driving current based on the gate voltage to drive the light-emitting element to emit light. However, the transistors in the pixel circuit are mostly low-temperature polysilicon (LTPS) transistors, and LTPS transistors generally have leakage current due to their inherent characteristics. Because of the leakage current in the switching transistor, the gate potential of the driving transistor cannot be maintained within a single frame, resulting in significant fluctuations. Especially at low frequencies, the voltage holding time of the storage capacitor is longer, and the leakage current of the switching transistor becomes more severe, leading to unstable gate voltage of the driving transistor. This causes unstable driving current output to the light-emitting element, resulting in large brightness variations in the light-emitting element within a refresh cycle. (See [reference needed]). Figure 1 , Figure 1This data represents measured brightness fluctuations of AMOLED (Active-matrix organic light-emitting diode) modules at 60Hz and 5Hz. Because the human eye's ability to detect flicker increases significantly below 24Hz, display panels in this technology exhibit severe flickering at low frequencies.

[0023] To address the aforementioned technical problems, the present invention proposes the following solutions:

[0024] This invention provides a driving circuit for a display panel and a display panel. Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. (Reference) Figure 2 The display panel 100 includes a driving circuit, which includes a pixel circuit 11 and a signal generation circuit 12. The pixel circuit 11 includes a driving module 110, an n-gate transistor 111, and a voltage compensation module 112. The n-gate transistor 111 is electrically connected to the control terminal G of the driving module 110, and the voltage compensation module 112 is electrically connected to an intermediate node E in the n-gate transistor 111. The intermediate node E is the common node of any two transistors in the n-gate transistor 111. The voltage compensation module 112 is used to compensate the voltage of the intermediate node E according to the received compensation signal Vs, so that the voltage difference between the intermediate node E and the control terminal G of the driving module 110 is stabilized within a preset range; where n is greater than or equal to 2.

[0025] The output terminal OUT1 of the signal generation circuit 12 is electrically connected to the voltage compensation module 112. The signal generation circuit 12 includes a switch module 120 and a first storage module 121. The output terminal of the switch module 120 is electrically connected to both the first storage module 121 and the output terminal of the signal generation circuit 12. The switch module 120 is electrically connected to the first voltage terminal P1 and the second voltage terminal P2, and is connected to the first control signal C1 and the second control signal C2, respectively. The first voltage of the first voltage terminal P1 is different from the second voltage of the second voltage terminal P2. The operation of the signal generation circuit 12 includes a first stage and a second stage.

[0026] In response to the first control signal C1, the first voltage terminal P1 and the output terminal OUT1 of the signal generation circuit 12 are turned on for at least a portion of the time in the first stage, and then turned off for at least a portion of the time in the second stage. In response to the second control signal C2, the second voltage terminal P2 and the output terminal OUT1 of the signal generation circuit 12 are turned off for at least a portion of the time in the second stage.

[0027] Specifically, the display panel 100 has a display area AA and a non-display area NAA, with the non-display area NAA surrounding the display area AA. The driving module 110 can be connected to the light-emitting element 200, thereby generating a driving current under the control of the gate voltage of the driving module 110 to drive the light-emitting element 200 to emit light. The light-emitting element 200 may include a light-emitting diode D1, the type of which is not limited, for example, an organic light-emitting diode (OLED). In practical implementation, the anode of the light-emitting diode D1 is connected to the second terminal of the driving module 110, and the cathode of the light-emitting diode D1 is connected to the cathode power supply voltage signal VSS.

[0028] Optionally, the driving module 110 includes a driving transistor DTFT, the first electrode of the driving transistor DTFT serves as the first terminal of the driving module 110, the second electrode of the driving transistor DTFT serves as the second terminal of the driving module 110, and the gate of the driving transistor DTFT serves as the control terminal G of the driving module 110.

[0029] The n-gate transistor 111 is electrically connected to the control terminal G of the driving module 110. When the n-gate transistor 111 is turned on, it can transmit the voltage applied to the n-gate transistor to the control terminal G of the driving module 110. Depending on the pixel circuit structure, the n-gate transistor can be included in different modules of the pixel circuit.

[0030] Figure 3 This is a schematic diagram of the structure of a driving circuit for a display panel provided in an embodiment of the present invention. See also: Figure 3 In some optional embodiments of the present invention, the pixel circuit includes a data writing module 113, which is electrically connected to the control terminal G of the driving module 110. The data writing module 113 is used to write a data voltage Data to the control terminal G of the driving module 110 during the data writing stage. In this case, the data writing module 113 may include an n-gate transistor 111. Figure 4 This is a schematic diagram of the driving circuit for another display panel provided in an embodiment of the present invention. See also... Figure 4In another optional embodiment of the present invention, the pixel circuit 11 includes a data writing module 113 and a threshold voltage compensation module 114. The data writing module 113 is electrically connected to the first terminal of the driving module 110, and the threshold compensation module 114 is connected to the second terminal of the driving module 110 and the control terminal G. Under the control of the first scan signal S1, the data writing module 113 can write a data voltage Data to the control terminal G of the driving module 110 through the driving module 110 and the threshold compensation module 114 during the data writing stage. The threshold voltage compensation module 114 can compensate for the threshold voltage of the driving module 110. In this case, the threshold compensation module 114 may include an n-gate transistor 111. The pixel circuit may also include a first light emission control module 115 and a second light emission control module 116. The first terminal of the first light emission control module 115 is connected to a first power supply voltage signal VDD, the second terminal of the first light emission control module 115 is connected to the first terminal of the driving module 110, and the control terminal of the first light emission control module 115 is connected to a light emission control signal EM. The first light emission control module 115 is used to turn on during the light emission stage according to the light emission control signal EM. The first end of the second light-emitting control module 116 is connected to the second end of the driving module 110, and the second end of the second light-emitting control module 116 is connected to the light-emitting element 200. The control end of the second light-emitting control module 116 is connected to the light-emitting control signal EM. The second light-emitting control module 116 is used to turn on during the light-emitting stage according to the light-emitting control signal EM.

[0031] Optionally, both of the above circuits may further include a first initialization module for initializing the control terminal of the driving circuit. The first initialization module can initialize the control terminal of the driving module during the initialization phase. The first initialization module may also include an n-gate transistor. In this embodiment, an n-gate transistor refers to a transistor that includes n gates. An n-gate transistor can be... Figures 2 to 4 The dual-gate transistor shown can also be a triple-gate transistor or more gate transistors. Compared to a single-gate transistor, an n-gate transistor has lower leakage current, allowing the potential of the control terminal G of the drive module 110 to be maintained relatively better. However, n-gate transistors still have a certain amount of leakage current.

[0032] To further reduce the leakage current of the n-gate transistor, in this embodiment, the pixel circuit also includes a voltage compensation module 112. The voltage compensation module 112 is connected to the control terminal G of the driving module 110 and the intermediate node E of the n-gate transistor 111. Optionally, the voltage compensation module 112 is used to compensate the voltage of the intermediate node E according to the received compensation signal Vs during the light-emitting stage, so that the voltage difference between the intermediate node E and the control terminal G of the driving module is stabilized within a preset range. The preset range is related to the magnitude of the compensation signal Vs; by adjusting the compensation signal Vs, the average voltage of the intermediate node E during the light-emitting stage can be made closer to the voltage of the control terminal of the driving module 110. Specifically, during the light-emitting stage, the leakage current of the n-gate transistor is mainly determined by the voltage difference between the intermediate node E and the control terminal G of the driving module 110. During the light-emitting stage, the average voltage of the intermediate node E is close to the voltage of the control terminal of the driving module 110, which can further reduce the leakage current of the n-gate transistor. As a result, the potential of the control terminal G of the driving module 110 can be maintained better during the light-emitting stage, ensuring that the driving current generated by the driving module 110 during the light-emitting stage is more stable and improving the flickering phenomenon of the display screen.

[0033] To obtain the compensation signal Vs that meets the above requirements, in this embodiment, the display panel 100 further includes a signal generation circuit 12. The output terminal OUT1 of the signal generation circuit 12 is electrically connected to the voltage compensation module 112, thereby providing the compensation signal Vs to the pixel circuit 11. Optionally, the first storage module 121 may be, but is not limited to, a capacitor, inductor, or other element with charge storage function. In all embodiments of this application, the first storage module 121 is described as a capacitor.

[0034] The switching module 120 may include multiple switches. Under the control of the first control signal C1 and the second control signal C2, the switching module 120 periodically turns on and off the voltage regulation path between the first storage module 121 and the first voltage terminal P1 and the second voltage terminal P2, so as to adjust the output voltage of the signal generation circuit output terminal OUT1. Specifically, the first control signal C1 and the second control signal C2 have a high-level state and a low-level state.

[0035] In some embodiments, the operating phases of the first control signal C1 and the second control signal C2 include a first phase and a second phase. A portion of the switches in the switching module 120 are turned on in response to the first control signal C1 for at least a portion of the time period in the first phase, so that the first voltage terminal P1 is connected to the output terminal OUT1 of the signal generation circuit for at least a portion of the time period in the first phase; while another portion of the switches are turned off in response to the second control signal C2 in the first phase, so that the second voltage terminal P2 is disconnected from the output terminal OUT1 of the signal generation circuit in the first phase. That is, in the first phase, the first voltage at the first voltage terminal P1 charges the first storage module 121, causing the compensation signal Vs output by the signal generation circuit to increase. It is understood that the first storage module 121 can also discharge to the first voltage terminal P1 through the switching module 120 in the first phase, causing the compensation signal Vs output by the signal generation circuit to decrease. The voltage compensation module 112 may include a transistor that receives the compensation signal Vs. In the first phase, whether the first storage module 121 is charged or discharged first depends on the type of transistor in the voltage compensation module 112 that receives the compensation signal Vs.

[0036] In some embodiments, some switches in the switching module 120 are turned off in response to the first control signal C1 in the second stage, causing the first voltage terminal P1 to disconnect from the output terminal OUT1 of the signal generation circuit in the second stage; while other switches are turned on in response to the second control signal C2 for at least a portion of the time period in the second stage, causing the second voltage terminal P2 to connect with the output terminal OUT1 of the signal generation circuit for at least a portion of the time period in the second stage. At this time, the first storage module 121 can discharge the stored charge to the second voltage terminal P2 in the second stage, causing the compensation signal Vs output by the signal generation circuit to decrease. It is understood that the second voltage terminal P2 can also charge the first storage module 121 through the switching module 120 in the second stage, causing the compensation signal Vs output by the signal generation circuit to increase. Whether the first storage module 121 charges or discharges first in the second stage depends on the type of transistor in the voltage compensation module 112 that receives the compensation signal Vs.

[0037] It should be noted that since the first voltage at the first voltage terminal P1 is different from the second voltage at the second voltage terminal P2, the states of the first storage module 121 are different in the first stage and the second stage. That is, if the first storage module 121 is charging in the first stage, it will discharge in the second stage; if the first storage module 121 is discharging in the first stage, it will charge in the second stage.

[0038] Furthermore, when the transistor receiving the compensation signal Vs in the voltage compensation module 121 is a P-type transistor, the first voltage is greater than the second voltage. In this case, the first storage module 121 charges in the first stage and discharges in the second stage. When the transistor receiving the compensation signal Vs in the voltage compensation module 121 is an N-type transistor, the first voltage is less than the second voltage. In this case, the first storage module 121 discharges in the first stage and charges in the second stage, so that the voltage compensation module 121 is turned on during the light-emitting stage. In this embodiment and the following embodiments, the example given is that the transistor receiving the compensation signal Vs in the voltage compensation module 121 is a P-type transistor; that is, the example given is that the first voltage is greater than the second voltage.

[0039] The driving circuit of the display panel in this embodiment of the invention includes a pixel circuit and a signal generation circuit. The signal generation circuit includes a switching module and a first storage module. The switching module receives a first control signal and a second control signal, and under the control of the first and second control signals, periodically turns on and off the voltage regulation path between the first storage module and the first and second voltage terminals to adjust the output voltage of the signal generation circuit, i.e., adjust the compensation signal and output it to the voltage compensation module of the pixel circuit. The voltage compensation module compensates the voltage of the intermediate node of the n-gate transistor according to the compensation signal, so that the voltage difference between the intermediate node and the control terminal of the driving module is stabilized within a preset range. In this way, the average voltage of the intermediate node can be close to the voltage of the control terminal of the driving module, thereby effectively reducing the leakage current of the n-gate transistor, so that the voltage of the control terminal of the driving module can be maintained better, thereby ensuring the stability of the driving current generated by the driving module, keeping the brightness of the light-emitting element stable, and improving the low-frequency flicker phenomenon. In addition, the display panel of this embodiment of the invention does not require a specific display driver chip to output a periodically changing and flexibly controllable compensation signal, which can achieve the purpose of screen self-control to replace external chip control, thus expanding the application scenarios of the display panel.

[0040] Continue to refer to Figure 3 In some embodiments, the gate of the n-gate transistor 111 is connected to the first scan signal S1, the first terminal of the n-gate transistor 111 is connected to the control terminal G of the driving module 110, and the second terminal of the n-gate transistor 111 is connected to the data voltage Data.

[0041] Continue to refer to Figure 4In some embodiments, the gate of the n-gate transistor 111 is connected to the first scan signal S1, the first terminal of the n-gate transistor 111 is connected to the second terminal of the driving module 110, and the second terminal of the n-gate transistor 111 is connected to the control terminal G of the driving module 110. In this embodiment, the operation of the pixel circuit 12 includes at least a data writing stage and a light emission stage. In the data writing stage, under the action of the first scan signal S1, the n-gate transistor 111 is turned on, and the data voltage Data is written to the control terminal G of the driving module 110 through the driving module 110 and the n-gate transistor 111.

[0042] Continue to refer to Figure 2 In some embodiments, the pixel circuit 11 is located in the display area AA of the display panel, and the switch module 120 and the first storage module 121 are both located in the non-display area NAA of the display panel, which can save the space for wiring inside the screen.

[0043] Optionally, the first storage module 121 is disposed on a flexible printed circuit (FPC) bonded to the display panel. By disposing the first storage module 121 on the flexible printed circuit board, matching capacitors can be replaced on the flexible printed circuit board as needed, improving application compatibility. Optionally, the first voltage, the second voltage, the first control signal C1, and the second control signal C2 are all output by a driver chip 10 (Display Driver IC, DDIC) disposed in the non-display area NAA of the display panel.

[0044] Continue to refer to Figure 2 In some embodiments, the signal generation circuit 12 is connected to the voltage compensation module 112 of a row of pixel circuits 13 in the display panel. In other embodiments, the signal generation circuit is electrically connected to the voltage compensation module of each pixel circuit in the display panel. In this case, the display panel may include only one signal generation circuit, which helps to reduce costs and achieve a narrow bezel in the display panel. Optionally, when the signal generation circuit 12 is connected to the voltage compensation module 112 of a row of pixel circuits 13 in the display panel 100, the starting time of the compensation signal Vs in the first stage is the same as the starting time of the light emission control signal EM. In this way, the voltage compensation process of the voltage compensation module 112 in each row of pixel circuits 11 for the intermediate node E of the n-gate transistor 111 is exactly the same, which helps to further improve the display effect.

[0045] Figure 5 This is a schematic diagram of a signal generation circuit provided in an embodiment of the present invention, for reference. Figure 5In one embodiment, the switch module 120 includes a first switch unit 1201 and a second switch unit 1202. The control terminal of the first switch unit 1201 is connected to a first control signal C1, a first terminal of the first switch unit 1201 is electrically connected to a first voltage terminal P1, and a second terminal of the first switch unit 1201 is electrically connected to the output terminal of the switch module 120. The control terminal of the second switch unit 1202 is connected to a second control signal C2, a first terminal of the second switch unit 1202 is electrically connected to a second voltage terminal P2, and a second terminal of the second switch unit 1202 is electrically connected to the output terminal of the switch module.

[0046] Specifically, the first switching unit 1201 is used to turn on or off according to the first control signal C1 to control the conduction state between the first voltage terminal P1 and the first storage module 121; the second switching unit 1202 is used to turn on or off according to the second control signal C2 to control the conduction state between the second voltage terminal P2 and the first storage module 121. By controlling the conduction time of the first switching unit 1201 and the second switching unit 1202, the magnitude and duration of the compensation signal Vs can be controlled.

[0047] In this embodiment, the first switching unit 1201 and the second switching unit 1202 are not simultaneously turned on. This is an optional implementation method provided in this embodiment. Figure 6 This is a schematic diagram of another signal generation circuit provided in an embodiment of the present invention, for reference. Figure 6 The first switching unit 1201 includes a first transistor M1, and the second switching unit 1202 includes a second transistor M2. The gate of the first transistor M1 serves as the control terminal of the first switching unit 1201, the first electrode of the first transistor M1 serves as the first terminal of the first switching unit 1201, and the second electrode of the first transistor M2 serves as the second terminal of the first switching unit 1201. Similarly, the gate of the second transistor M2 serves as the control terminal of the second switching unit 1202, the first electrode of the second transistor M2 serves as the first terminal of the second switching unit 1202, and the second electrode of the second transistor M2 serves as the second terminal of the second switching unit 1202. The first transistor M1 and the second transistor M2 can be fabricated in the same process as the transistors in the pixel circuit to simplify the fabrication process.

[0048] In all embodiments of this invention, the transistors used can be thin-film transistors or other devices with the same characteristics. In these embodiments, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal. The first terminal can be the drain, and the second terminal can be the source; alternatively, the first terminal can be the source, and the second terminal can be the drain. Optionally, in the first stage, the first control signal C1 is at a conduction level, and the second control signal C2 is at a turn-off level; in the second stage, the first control signal C1 is at a turn-off level, and the second control signal C2 includes at least two conduction pulses.

[0049] In some embodiments, the off level is a level signal that turns off the transistors controlled by the first control signal C1 and the second control signal C2; the on level is a control signal that turns on the transistors controlled by the first control signal C1 and the second control signal C2. For example, in this embodiment, the off level is a high potential, and the on level is a low potential. Correspondingly, the first transistor M1 and the second transistor M2 are P-type transistors, meaning that when the gates of the first transistor M1 and the second transistor M2 are at a low potential, the first transistor M1 and the second transistor M2 are on; when the gates of the first transistor M1 and the second transistor M2 are at a high potential, the first transistor M1 and the second transistor M2 are off. For example, zero potential is set to ground potential. Optionally, in this embodiment and the following embodiments, high potential is greater than zero potential, and low potential is less than zero potential.

[0050] In the first stage, when the first control signal C1 is at the on level and the second control signal C2 is at the off level, that is, the first transistor M1 is always on and the second transistor M2 is always off in the first stage. When the first voltage is greater than the second voltage, in the first stage, the first voltage terminal P1 charges the first storage module 121 through the first transistor M1, thereby increasing the output voltage of the signal generation circuit. By controlling the on duration of the first control signal C1 and the off duration of the second control signal C2 in the first stage, the charging time of the first storage module 121 can be controlled, which is equivalent to controlling the maximum value of the compensation signal Vs in the first stage. By controlling the magnitude of the first voltage, the rise rate of the compensation signal Vs in the first stage can be controlled. It can be understood that the maximum value of the compensation signal Vs in the first stage is less than or equal to the first voltage.

[0051] In the second stage, when the first control signal C1 is at the off level and the second control signal C2 includes at least two conduction pulses, that is, the first transistor M1 is always off in the second stage, and the second transistor M2 is on at least twice in the second stage. When the first voltage is greater than the second voltage, in the second stage, the first storage module 121 discharges through the second transistor M2 to reduce the output voltage of the signal generation circuit. By controlling the off duration of the first control signal C1 and the on duration of the second control signal C2 in the second stage, the discharge time of the first storage module 121 can be controlled, which is equivalent to controlling the minimum value of the compensation signal Vs in the second stage. It can be understood that the minimum value of the compensation signal Vs in the first stage is greater than or equal to the second voltage.

[0052] In some embodiments, the switching module 120 is configured to charge the first storage module 121 in a first stage according to a first control signal C1 and a first voltage at the first voltage terminal P1, so that the output voltage of the signal generation circuit 12 changes to the first voltage. In some embodiments, the second stage includes a first interval and a second interval; the switching module 120 is configured to discharge to the second voltage terminal P2 in the first interval according to a second control signal C2, so that the output voltage of the signal generation circuit 12 decreases to the second voltage; the first storage module 121 is configured to maintain the voltage at the output terminal OUT1 of the signal generation circuit 12 in the second interval.

[0053] Figure 7 This is a schematic diagram of the voltage waveforms of a compensation signal, a first control signal, and a second control signal provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the compensation signal Vs is a periodic voltage signal, and its cycle period is the compensation working cycle. The compensation signal Vs includes a change in voltage from a first voltage to a second voltage within the compensation working cycle; wherein the first voltage is greater than the second voltage. The specific voltage values ​​of the first and second voltages can be set according to actual needs. Figure 7 The first voltage of 4V and the second voltage of -1V in the illustrated embodiment are merely optional examples, and this embodiment does not limit them.

[0054] In some embodiments, a compensation signal Vs for one cycle includes a voltage signal output by the signal generation circuit 12 in the first stage t1, the first interval t2, and the second interval t3.

[0055] In some embodiments, during the first stage, the first control signal C1 is at an on level and the second control signal C2 is at an off level. That is, the first transistor M1 is always on during the first stage, and the second transistor M2 is always off during the first stage. The first voltage terminal P1 charges the first storage module 121 through the first transistor M1, thereby increasing the output voltage of the signal generation circuit. By controlling the on duration of the first control signal C1 during the first stage and the off duration of the second control signal C2 during the first stage, the charging time of the first storage module 121 can be controlled.

[0056] In the second stage, the first control signal C1 is at the off level. During the first interval t2 of the second stage, the second control signal C2 includes multiple conduction pulses. At this time, the first transistor M1 is not conducting, and the second transistor M2 is conducting for at least part of the time period in the first interval. The first storage module 121 gradually discharges to the second voltage terminal P2, and the compensation signal Vs gradually decreases to the second voltage. During the second interval t3 of the second stage, the second control signal C2 is at the off level, and both the first transistor M1 and the second transistor M2 are not conducting, so that the compensation signal Vs is maintained at the second voltage in the second interval.

[0057] Optionally, within the second interval t3, the second control signal C2 includes at least one conduction pulse. At this time, the first transistor M1 is not turned on, and the second transistor M2 is slightly turned on, which does not affect the voltage at the output of the signal generation circuit. That is, the compensation signal Vs will remain at the second voltage in the second interval t3. In other words, the second control signal C2 can include multiple conduction pulses in both the first interval t2 and the second interval t3. The interval between the start times of two adjacent conduction pulses in the first interval t2 is less than the interval between the start times of two adjacent conduction pulses in the second interval t3, so that the second transistor M2 is turned on for at least a part of the time period in the first interval t2, and is not turned on or is slightly turned on in the second interval t3.

[0058] In some embodiments, the duration of the first stage of the compensation signal Vs is shorter than the duration of the second stage. That is, the charging duration of the first storage module 121 is shorter than the sum of the discharging duration and the duration of holding at the second voltage, so that the average voltage of the intermediate node E is closer to the voltage of the control terminal of the drive module 110, further reducing the leakage current of the n-gate transistor 111.

[0059] Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, for reference. Figure 8 The voltage compensation module 112 includes: a compensation control unit 1121 and a compensation unit 1122.

[0060] The first terminal of the compensation control unit 1121 is connected to the compensation signal Vs, the second terminal of the compensation control unit 1121 is connected to the first terminal of the compensation unit 1122, the control terminal of the compensation control unit 1121 is connected to the light emission control signal EM, and the compensation control unit 1121 is used to respond to the light emission control signal EM during the light emission stage to transmit the compensation signal to the compensation unit 1122.

[0061] The second end of the compensation unit 1122 is connected to the control end of the drive module, and the third end of the compensation unit 1122 is connected to the intermediate node E. The compensation unit 1122 is used to provide a compensation voltage to the intermediate node E according to the compensation signal Vs, so that the voltage difference between the intermediate node E and the control end of the drive module 110 is stabilized within a preset range.

[0062] In this embodiment, the operation of the pixel circuit includes at least a data writing stage and a light-emitting stage. During the light-emitting stage, the compensation control unit 1121 receives the light-emitting control signal EM and is turned on under the action of the light-emitting control signal EM, transmitting the compensation signal Vs to the compensation unit 1122. The compensation unit 1122 provides a compensation voltage to the intermediate node E according to the received compensation signal Vs, so that the average voltage of the intermediate node E remains unchanged during the light-emitting stage, thereby keeping the voltage at the control terminal of the driving module 110 constant during the light-emitting stage, thus enabling the light-emitting element 200 to emit light stably during the light-emitting stage.

[0063] During the data writing phase, the compensation control unit 1121 is disconnected under the action of the light emission control signal EM. The compensation unit 1122 does not receive the compensation signal Vs and stops providing compensation voltage to the intermediate node E. Therefore, it will not interfere with the normal writing of the data voltage Data.

[0064] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, such as... Figure 9 As shown, the compensation control unit 1121 includes a third transistor M3; the compensation unit 1122 includes a fourth transistor M4 (i.e., the transistor that receives the compensation signal Vs as described in the above embodiment).

[0065] The gate of the third transistor M3 serves as the control terminal of the compensation control unit 1121, the first terminal of the third transistor M3 serves as the first terminal of the compensation control unit 1121, and the second terminal of the third transistor M3 serves as the second terminal of the compensation control unit 1121; the gate of the fourth transistor M4 serves as the second terminal of the compensation unit 1122, the first terminal of the fourth transistor M4 serves as the first terminal of the compensation unit 1122, and the second terminal of the fourth transistor M4 serves as the third terminal of the compensation unit 1122.

[0066] Specifically, during at least a portion of the light-emitting stage, the third transistor M3 is turned on under the action of the light-emitting control signal EM, transmitting the compensation signal Vs to the compensation unit 1122. During the data writing stage, the third transistor M3 is turned off under the action of the light-emitting control signal EM to disconnect the connection between the compensation unit 1122 and the compensation signal Vs, preventing the compensation signal Vs from interfering with the normal writing of the data voltage Data, thereby realizing the control of the compensation unit 1122, that is, realizing the provision of compensation voltage to the intermediate node E as needed.

[0067] In one embodiment, during the light-emitting stage, when the voltage of the compensation signal Vs is higher than the turn-on voltage, the compensation unit 1122 is in the on state; when the voltage of the compensation signal Vs is less than or equal to the turn-on voltage, the compensation unit 1122 is in the off state; the turn-on voltage is less than a first voltage and greater than a second voltage. This turn-on voltage can be equal to (VD + |Vth|), where VD is the voltage at the first terminal of the n-gate transistor 111 (for ease of explanation, the first terminal of the n-gate transistor 111 is shown as the first node D); taking the fourth transistor M4 as a P-type transistor as an example, |Vth| represents the threshold voltage of the fourth transistor M4 and is a negative number. When the compensation unit 1122 (fourth transistor M4) is in the on state, as... Figure 10 As shown, the voltage VE at intermediate node E changes with the compensation signal Vs; as the compensation signal Vs decreases, the voltage VE at intermediate node E also decreases. When Vs = VE = (VD + |Vth|), the fourth transistor M4 is turned off. After the fourth transistor M4 is turned off, the compensation signal Vs continues to decrease, and... Figure 7 The voltage drops to the second voltage at the boundary between the first interval t2 and the second interval t3, and remains at the second voltage during the second interval t3. During this process, there is a voltage difference between the first and second terminals of the fourth transistor M4, and the fourth transistor M4 has leakage current. The voltage of the intermediate node E gradually decreases to VD, VD-|Vth|, and then continues to decrease to the adjustment voltage Vx. By fine-tuning the duration for which the compensation signal Vs maintains the second voltage, the magnitude of the adjustment voltage Vx can be changed, so that the average voltage of the intermediate node E remains balanced within the compensation working cycle. The average voltage of the intermediate node E is close to the voltage at the second terminal of the n-gate transistor 111, thereby keeping the voltage at the control terminal of the drive module 110 relatively stable and reducing the leakage current of the n-gate transistor 111.

[0068] Furthermore, depending on the actual situation, the compensation unit 1122 may also include an energy storage capacitor C. The first end of the energy storage capacitor C is connected to the intermediate node E, and the second end of the energy storage capacitor C is used to receive the second power supply voltage signal VDD2. Optionally, the second power supply voltage signal VDD2 and the first power supply voltage signal VDD are the same power supply voltage signal, such as both being the first power supply voltage signal VDD, for ease of circuit design. When the fourth transistor M4 of the compensation unit 1122 is in the on state, the voltage of the intermediate node E is positively correlated with the voltage of the compensation signal Vs, and the compensation unit 1122 stores the voltage of the intermediate node E. When the fourth transistor M4 of the compensation unit 1122 is in the off state, the compensation unit 1122 releases the stored charge to keep the average voltage of the intermediate node E constant during the compensation working cycle. In actual implementation, refer to... Figure 7 The embodiment shown sets a compensation signal Vs. Within one compensation signal working cycle, the compensation signal Vs changes from a first voltage H to a second voltage L, and then maintains the second voltage L for a preset duration.

[0069] Continue to refer to Figure 9 The pixel circuit 11 further includes a data writing module 113, a threshold voltage compensation module 114, a first light emission control module 115, and a second light emission control module 116; the threshold voltage compensation module 114 includes an n-gate transistor. The control terminal of the data writing module 113 is connected to a first scan signal S1, the first terminal of the data writing module 113 is connected to a data voltage Data, and the second terminal of the data writing module 113 is connected to the first terminal of the driving module 110. For example, the data writing module 113 may include a fifth transistor M5, the gate of the fifth transistor M5 receives the first scan signal S1, the first electrode of the fifth transistor M5 serves as the first terminal of the data writing module 113, and the second electrode of the fifth transistor M5 serves as the second terminal of the data writing module 113.

[0070] During the data writing phase, under the action of the first scan signal S1, the fifth transistor M5 and the n-gate transistor 111 are turned on, and the data voltage Data is written to the control terminal of the drive module via the fifth transistor M5, the drive module 110, and the n-gate transistor 111. Thus, by setting the fifth transistor M5, the data voltage Data can be controlled to be input during the data writing phase, preventing the data voltage Data from affecting the light emission effect during the light emission phase. The control terminal of the threshold voltage compensation module 114 is connected to the first scan signal S1. The first terminal of the threshold voltage compensation module 114 is electrically connected to the second terminal of the drive module 110, and the second terminal of the threshold voltage compensation module 114 is electrically connected to the control terminal G of the drive module 110. The first terminal of the first light emission control module 115 is connected to the first power supply voltage signal VDD. The second terminal of the first light emission control module 115 is connected to the first terminal of the drive module 110, and the control terminal of the first light emission control module 115 is connected to the light emission control signal EM. The first light emission control module 115 is used to turn on during the light emission phase according to the light emission control signal EM. For example, the first light-emitting control module 115 may include a sixth transistor M6, with its first electrode serving as the first terminal of the first light-emitting control module 115, its second electrode serving as the second terminal of the first light-emitting control module 116, and its gate serving as the control terminal of the sixth transistor M6. The first terminal of the second light-emitting control module 116 is connected to the second terminal of the driving module 110, and its second terminal is connected to the light-emitting element 200. The control terminal of the second light-emitting control module 116 receives a light-emitting control signal EM; the second light-emitting control module 116 is used to conduct during the light-emitting phase according to the light-emitting control signal EM. For example, the second light-emitting control module 116 may include a seventh transistor M7, with its first electrode serving as the first terminal of the second light-emitting control module 116, its second electrode serving as the second terminal of the second light-emitting control module 117, and its gate serving as the control terminal of the second light-emitting control module 116. In some embodiments, the pixel circuit 11 further includes a second storage module 117. A first terminal of the second storage module 117 is connected to a first power supply voltage signal VDD, and a second terminal of the second storage module 117 is connected to the control terminal G of the driving module 110. In some embodiments, the second storage module 117 includes a capacitor Cst. The first terminal of the capacitor Cst serves as the first terminal of the second storage module 117, and the second terminal of the capacitor Cst serves as the second terminal of the second storage module 117. The capacitor Cst is used to store the voltage at the control terminal of the driving module 110 when writing data voltage Data, so as to provide it to the control terminal of the driving module 110 during the light-emitting phase.In some embodiments, the pixel circuit further includes a first initialization module 118 and a second initialization module 119; the control terminal of the first initialization module 118 is connected to a second scan signal S2, the first terminal of the first initialization module 118 is connected to an initialization voltage signal Vref, and the second terminal of the first initialization module 118 is connected to the control terminal G of the driving module 110; the control terminal of the second initialization module 119 is connected to a third scan signal S3, the first terminal of the second initialization module 119 is connected to an initialization voltage signal Vref, and the second terminal of the second initialization module 119 is connected to the light-emitting element 200.

[0071] For example, the first initialization module 118 may include an eighth transistor M8, with its first terminal serving as the first terminal of the first initialization module 118, its second terminal serving as the second terminal of the first initialization module 118, and its gate serving as the control terminal of the first initialization module 118. In this embodiment, the eighth transistor M8 may be a dual-gate transistor, combined with... Figure 9 The eighth transistor M8 includes two sub-transistors M8-1 and M8-2, whose gates are shorted. By setting the eighth transistor M8 as a dual-gate transistor, the impact of the leakage current of the eighth transistor M8 when it is turned off on the voltage stored on the capacitor Cst can be reduced, making it easier to maintain the voltage stored on the capacitor Cst. In low grayscale conditions, the voltage at the control terminal G of the drive module 110 can be finely adjusted to improve the voltage adjustment accuracy. For example, the second initialization module 119 may include a ninth transistor M9. The first terminal of the ninth transistor M9 serves as the first terminal of the second initialization module 119, the second terminal of the ninth transistor M9 serves as the second terminal of the first initialization module 118, and the gate of the ninth transistor M9 serves as the control terminal of the second initialization module 119.

[0072] Optionally, the duration of the first interval t2 is shorter than the duration of the second interval t3. This allows for a longer voltage drop time at intermediate node E within the second interval t3, enabling the average voltage of intermediate node E to approach the potential of the control terminal of the drive module. Optionally, in some optional embodiments of the present invention, the durations of the first stage t1, the first interval t2, and the second interval t3 are variable and can be adjusted by those skilled in the art according to actual needs.

[0073] Furthermore, within the same light-emitting driving cycle, the effective duration of the light-emitting control signal EM is n times the working cycle of the compensation signal, where n is a positive integer. Thus, within the effective duration of the light-emitting control signal EM, at least one charge-discharge cycle is completed for the intermediate node E. By repeatedly and rapidly adjusting the voltage of the intermediate node E, the voltage fluctuation of the intermediate node E can be reduced, thereby making the voltage at the control terminal of the drive module 110 more stable, and consequently, the light-emitting effect more stable.

[0074] It should also be noted that in related technologies, OLED displays exhibit image retention issues when displaying a fixed image for an extended period. Through long-term research, the inventors discovered that this is because, in the pixel circuits of related technologies, when an OLED displays a fixed image for a long time, the first and second terminals of the n-gate transistor 111 maintain the same voltage difference for an extended period. This fixed voltage difference electric field biases the characteristics of the n-gate transistor. Even when the next frame's signal arrives, the voltage difference between the first and second terminals of the n-gate transistor 111 is still affected by the previous signal, resulting in image retention. In this embodiment, by setting the compensation signal Vs as a periodic signal, the signal input to the intermediate node E continuously flips, periodically refreshing the voltage of the intermediate node E. This breaks the bias generated by the n-gate transistor 111 due to the fixed electric field between the first and second terminals, thereby optimizing the image retention phenomenon when displaying a fixed image for an extended period.

[0075] This invention also provides a display panel. Figure 2 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 As shown, the display panel 100 includes the driving circuit provided in any embodiment of the present invention. Specifically, the display panel 100 can be, for example, an organic light-emitting diode display panel, a liquid crystal display panel, or an electronic paper display panel. The display panel 100 may include multiple rows of pixel circuits 11 and multiple signal generation circuits 12, each signal generation circuit 12 being connected to a row of pixel circuits 11 to provide a compensation signal Vs to the row of pixel circuits 11. As described above, in some other embodiments of the present invention, the display panel 100 may include only one signal generation circuit 12, which may be connected to each pixel circuit 11.

[0076] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A driving circuit for a display panel, characterized in that, include: Pixel circuits and signal generation circuits; The pixel circuit includes a driving module, an n-gate transistor, and a voltage compensation module. The n-gate transistor is electrically connected to the control terminal of the driving module, and the voltage compensation module is electrically connected to an intermediate node in the n-gate transistor. The intermediate node is a common node of any two transistors in the n-gate transistor. The voltage compensation module is used to compensate the voltage of the intermediate node according to the received compensation signal, so that the voltage difference between the intermediate node and the control terminal of the driving module is stabilized within a preset range; where n is greater than or equal to 2. The output terminal of the signal generation circuit is electrically connected to the voltage compensation module. The signal generation circuit includes a switching module and a first storage module. The output terminal of the switching module is electrically connected to the first storage module and the output terminal of the signal generation circuit, respectively. The switching module is electrically connected to the first voltage terminal and the second voltage terminal respectively, and is respectively connected to the first control signal and the second control signal; the first voltage of the first voltage terminal is different from the second voltage of the second voltage terminal; the operation of the signal generation circuit includes a first stage and a second stage; In response to the first control signal, the first voltage terminal is connected to the output terminal of the signal generation circuit for at least a portion of the time period in the first stage, and the first voltage terminal is disconnected from the output terminal of the signal generation circuit in the second stage. In response to the second control signal, the second voltage terminal is disconnected from the output terminal of the signal generation circuit in the first stage, and the second voltage terminal is connected to the output terminal of the signal generation circuit for at least a portion of the time period in the second stage.

2. The driving circuit for the display panel according to claim 1, characterized in that, The switching module is used in a first stage to charge the first storage module according to the first control signal and the first voltage of the first voltage terminal, so that the output voltage of the signal generation circuit changes to the first voltage.

3. The driving circuit for the display panel according to claim 2, characterized in that, The first voltage is greater than the second voltage.

4. The driving circuit for the display panel according to claim 1 or 2, characterized in that, The switching module includes a first switching unit and a second switching unit; the control terminal of the first switching unit is connected to the first control signal, the first terminal of the first switching unit is electrically connected to the first voltage terminal, and the second terminal of the first switching unit is electrically connected to the output terminal of the switching module. The control terminal of the second switching unit is connected to the second control signal, the first terminal of the second switching unit is electrically connected to the second voltage terminal, and the second terminal of the second switching unit is electrically connected to the output terminal of the switching module.

5. The driving circuit for the display panel according to claim 4, characterized in that, The first switching unit includes a first transistor, and the second switching unit includes a second transistor; The gate of the first transistor serves as the control terminal of the first switching unit, the first electrode of the first transistor serves as the first terminal of the first switching unit, and the second electrode of the first transistor serves as the second terminal of the first switching unit. The gate of the second transistor serves as the control terminal of the second switching unit, the first electrode of the second transistor serves as the first terminal of the second switching unit, and the second electrode of the second transistor serves as the second terminal of the second switching unit.

6. The driving circuit for the display panel according to claim 1 or 2, characterized in that, In the first stage, the first control signal is at the on level, and the second control signal is at the off level; In the second stage, the first control signal is at the off level, and the second control signal includes at least two turn-on pulses.

7. The driving circuit for the display panel according to claim 6, characterized in that, The second stage includes a first interval and a second interval; The switching module is used to discharge to the second voltage terminal according to the second control signal in the first interval, so as to reduce the output voltage of the signal generation circuit to the second voltage; the first storage module is used to maintain the voltage of the output terminal of the signal generation circuit in the second interval.

8. The driving circuit for the display panel according to claim 7, characterized in that, The compensation signal is a periodic voltage signal, and one cycle of the compensation signal includes the voltage signal output by the signal generation circuit in the first stage, the first interval, and the second interval.

9. The driving circuit for the display panel according to claim 7, characterized in that, In the second interval, the second control signal is at the off level; or, In the second interval, the second control signal includes at least one turn-on pulse.

10. The driving circuit for the display panel according to claim 7, characterized in that, The second control signal includes multiple conduction pulses in both the first interval and the second interval, and the time interval between the start times of two adjacent conduction pulses in the first interval is less than the time interval between the start times of two adjacent conduction pulses in the second interval.

11. The driving circuit for the display panel according to claim 1, characterized in that, The duration of the first stage is shorter than the duration of the second stage.

12. The driving circuit for the display panel according to claim 7, characterized in that, The duration of the first interval is shorter than the duration of the second interval.

13. The driving circuit for the display panel according to claim 7, characterized in that, The durations of the first phase, the first interval, and the second interval are variable.

14. The driving circuit for the display panel according to claim 1, characterized in that, The pixel circuit is located in the display area of ​​the display panel, and the switch module and the first storage module are both located in the non-display area of ​​the display panel.

15. The driving circuit for the display panel according to claim 14, characterized in that, The first storage module is disposed on a flexible circuit board bonded to the display panel.

16. The driving circuit for the display panel according to claim 14, characterized in that, The first voltage, the second voltage, the first control signal, and the second control signal are all output by a driver chip located in the non-display area of ​​the display panel.

17. The driving circuit for the display panel according to claim 1, characterized in that, The signal generation circuit is connected to the voltage compensation module of a row of pixel circuits in the display panel.

18. The driving circuit for the display panel according to claim 1, characterized in that, The signal generation circuit is electrically connected to the voltage compensation module of each pixel circuit in the display panel.

19. The driving circuit for the display panel according to claim 1, characterized in that, The voltage compensation module includes: a compensation control unit and a compensation unit; The first end of the compensation control unit is connected to the compensation signal, the second end of the compensation control unit is connected to the first end of the compensation unit, the control end of the compensation control unit is connected to the light emission control signal, and the compensation control unit is used to turn on during the light emission stage to transmit the compensation signal to the compensation unit. When the voltage of the compensation signal is higher than the conduction voltage, the compensation unit is in the conducting state; when the voltage of the compensation signal is less than or equal to the conduction voltage, the compensation unit is in the off state; the conduction voltage is less than the first voltage and greater than the second voltage. The second end of the compensation unit is connected to the control end of the drive module, and the third end of the compensation unit is connected to the intermediate node; the compensation unit is used to provide a compensation voltage to the intermediate node according to the compensation signal.

20. The driving circuit for the display panel according to claim 19, characterized in that, The compensation control unit includes a third transistor; the compensation unit includes a fourth transistor; The gate of the third transistor serves as the control terminal of the compensation control unit, the first electrode of the third transistor serves as the first terminal of the compensation control unit, and the second electrode of the third transistor serves as the second terminal of the compensation control unit. The gate of the fourth transistor serves as the second terminal of the compensation unit, the first terminal of the fourth transistor serves as the first terminal of the compensation unit, and the second terminal of the fourth transistor serves as the third terminal of the compensation unit.

21. The driving circuit for the display panel according to claim 19, characterized in that, The pixel circuit further includes a data writing module, a threshold voltage compensation module, a first light emission control module, and a second light emission control module; the threshold voltage compensation module includes the n-gate transistor; The control terminal of the data writing module is connected to the first scan signal, the first terminal of the data writing module is connected to the data voltage, and the second terminal of the data writing module is connected to the first terminal of the driving module. The control terminal of the threshold voltage compensation module is connected to the first scanning signal, the first terminal of the threshold voltage compensation module is electrically connected to the second terminal of the drive module, and the second terminal of the threshold voltage compensation module is electrically connected to the control terminal of the drive module. The first terminal of the first light-emitting control module is connected to a first power supply voltage signal, the second terminal of the first light-emitting control module is connected to the first terminal of the driving module, and the control terminal of the first light-emitting control module is connected to a light-emitting control signal; the first light-emitting control module is used to turn on during the light-emitting phase according to the light-emitting control signal. The first end of the second light-emitting control module is connected to the second end of the driving module, the second end of the second light-emitting control module is connected to the light-emitting element, and the control end of the second light-emitting control module is connected to the light-emitting control signal; the second light-emitting control module is used to turn on during the light-emitting stage according to the light-emitting control signal.

22. The driving circuit for the display panel according to claim 21, characterized in that, The pixel circuit also includes a second storage module, the first end of which is connected to a first power supply voltage signal, and the second end of which is connected to the control terminal of the drive module.

23. The driving circuit for the display panel according to claim 21, characterized in that, The pixel circuit also includes a first initialization module and a second initialization module; The control terminal of the first initialization module is connected to the second scan signal, the first terminal of the first initialization module is connected to the initialization voltage signal, and the second terminal of the first initialization module is connected to the control terminal of the drive module. The control terminal of the second initialization module is connected to the third scanning signal, the first terminal of the second initialization module is connected to the initialization voltage signal, and the second terminal of the second initialization module is connected to the light-emitting element.

24. The driving circuit for the display panel according to claim 22, characterized in that, The compensation unit also includes an energy storage capacitor, the first end of which is connected to the intermediate node, and the second end of which is used to receive a second power supply voltage signal.

25. The driving circuit for the display panel according to claim 24, characterized in that, The second power supply voltage signal and the first power supply voltage signal are the same power supply voltage signal.

26. A display panel, characterized in that, The driving circuit includes the display panel according to any one of claims 1-25.

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