System for characterizing a transistor circuit

Abstract

System (100) for characterizing a transistor circuit (110) by finding a local minimum of the transistor circuit (110) with respect to a transmission characteristic. The system comprises a bias voltage generator (120) for generating a flipping signal, a multiplier (140) configured for multiplying an electrical signal as a function of a drain-source current of the transistor circuit (110) with a waveform alternating between two predefined values in synchrony with the flipping signal, a first integrator (130) configured for integrating the electrical signal from the multiplier (140), and wherein if there are more integrators (130), a linear combination of the output signals of the integrators is provided to a further integrator (130), an adder (150) configured for summing the flipping signal and the integrated signal and configured for outputting the sum to the gate of the transistor circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of transistor circuits whose transfer characteristics have a local minimum. More specifically, the present invention relates to a system for finding a local minimum of the transfer characteristics of such transistor circuits. BACKGROUND

[0002] Finding a local minimum of a transistor circuit whose transfer characteristics have a local minimum can be achieved by scanning the gate source voltage and measuring the drain source current through the transistor circuit. This allows finding a specific gate source voltage where the current is a minimum. It would be advantageous if the time for finding this specific voltage could be reduced.

[0003] An example of such a transistor circuit is a graphene FET which has a local minimum at the Dirac voltage. US 8638163 B2 discloses an apparatus and method wherein a semiconductor device is used to generate a test voltage. A graphene transistor is configured to receive a gate source voltage based on the test voltage and a detector is configured to detect whether the gate source voltage is the Dirac voltage of the graphene transistor. Thus, the detector detects whether the graphene transistor is cut-off based on the drain source voltage and / or the drain source current. Again, it would be advantageous if the time for finding a specific voltage, in this case the Dirac voltage, could be reduced.

[0004] Therefore, there is a need for an alternative system for determining a local minimum of a transistor circuit whose transfer characteristics have a local minimum. SUMMARY

[0005] It is an object of embodiments of the present invention to provide a system for determining a local minimum of a transistor circuit whose transfer characteristics have a local minimum.

[0006] The above object is achieved by the method and apparatus according to the present invention.

[0007] Embodiments of the present invention relate to a system for characterizing a transistor circuit.

[0008] The transistor circuit comprises a gate, a source and a drain and is configured such that a transfer function of a drain source current versus gate source voltage has a local minimum for a specific voltage.

[0009] The system is configured for measuring the specific voltage and comprises:

[0010] a transistor circuit;

[0011] a bias voltage generator configured to generate a flipping signal that flips between a positive predefined bias voltage v G and a negative predefined bias voltage v G around a given bias point;

[0012] one or more integrators;

[0013] a multiplier configured to generate an electrical signal by multiplying an electrical signal that is a function of the drain-source current of the transistor circuit with a waveform that alternates between two predefined values positive A and negative A, which is alternated in sync with the flipping signal.

[0014] a first integrator of the one or more integrators is configured to integrate the electrical signal from the multiplier and, if there are more integrators, a linear combination of the output signals of the integrators is provided to a further integrator.

[0015] Further, the system comprises a summer configured to sum the flipping signal with the integrated signal or a processed version of the integrated signal and configured to output the sum to the gate of the transistor circuit, wherein the integrated signal is obtained by a linear combination of the outputs of the one or more integrators.

[0016] In embodiments of the invention, the transistor circuit comprises:

[0017] a first transistor and a second transistor;

[0018] a first voltage converter configured to convert the voltage at the gate of the transistor circuit or the voltage at the source of the transistor circuit into a gate-source voltage between the gate of the first transistor and the source of the first transistor according to a transfer function having a first slope;

[0019] a second voltage converter configured to convert the voltage at the gate of the transistor circuit or the voltage at the source of the transistor circuit into a gate-source voltage between the gate of the second transistor and the source of the second transistor according to a transfer function having a second slope.

[0020] The first slope and the second slope have opposite signs.

[0021] Further, if the first voltage converter is configured to convert the voltage at the source of the first transistor, the transistor circuit can comprise a third voltage converter. The third voltage converter is configured to apply a voltage at the drain of the first transistor such that a stable drain-source voltage is obtained for the first transistor.

[0022] Furthermore, if the second voltage converter is configured for converting the voltage at the source of the second transistor, the transistor circuit can comprise a fourth voltage converter. This fourth voltage converter is configured for applying a voltage at the drain of the second transistor such that a stable drain-source voltage is obtained for the second transistor.

[0023] In embodiments of the application, the first transistor or the second transistor can be exposed to and sensitive to a chemical composition.

[0024] In embodiments of the application, the first transistor and the second transistor are metal oxide semiconductor FETs or bipolar transistors.

[0025] In embodiments of the application, the transistor circuit is a graphene FET.

[0026] In embodiments of the application, the system comprises a sample-and-hold circuit for sampling and holding the integrated signal for obtaining a processed version of the integrated signal.

[0027] In embodiments of the application, the system comprises exactly one integrator.

[0028] In embodiments of the application, the system comprises exactly two integrators, wherein the input signal of the second integrator is the sum of the output signal of the first integrator and the output signal of the second integrator multiplied by a predefined constant a1.

[0029] In embodiments of the application, the predefined bias voltage is such that the sum obtained by the adder is in a quadratic region of the transistor circuit characteristic.

[0030] In embodiments of the application, the predefined bias voltage is such that the sum obtained by the adder is in a linear region of the transistor circuit characteristic.

[0031] In embodiments of the application, in a first stage, the predefined bias voltage can be such that the sum obtained by the adder is in a linear region of the transistor circuit characteristic, and in a second stage, the predefined bias voltage can be such that the sum obtained by the adder is in a quadratic region of the transistor circuit characteristic.

[0032] In embodiments of the application, the system comprises a quantizer configured for quantizing the integrated signal at a predefined sampling frequency and a digital-to-analog converter for converting the quantized signal into an analog signal for summing with the flipped signal at the adder.

[0033] In an embodiment of the invention, the digital-to-analog converter flips between a first predefined reference voltage for digital 0 input and a second predefined reference voltage for digital 1 input, wherein the first and second predefined reference voltages, as well as a predefined bias voltage, are selected such that the flipping of the predefined bias voltage generates a voltage in the left linear region of the transistor circuit and a voltage in the right linear region of the transistor circuit.

[0034] In embodiments of the invention, the digital-to-analog converter (DAC) toggles between a first predefined reference voltage for digital 0 input and a second predefined reference voltage for digital 1 input. The first predefined reference voltage and predefined bias voltage are selected such that toggling the predefined bias voltage generates a voltage in the left-hand portion of the secondary region and a voltage in the same left-hand portion of the secondary region. The second predefined reference voltage and predefined bias voltage are selected such that toggling the predefined bias voltage generates a voltage in the right-hand portion of the secondary region of the transistor circuit and a voltage in the same right-hand portion of the secondary region.

[0035] In embodiments of the present invention, the quantizer is a predefined number N. q A multi-bit quantizer with N bits, where the digital-to-analog converter has N bits. q Bit.

[0036] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features from the dependent claims may be suitably combined with features of the independent claims and other dependent claims, and not merely as expressly set forth in the claims.

[0037] These and other aspects of the invention will be apparent from the following description of one or more embodiments, and are illustrated by reference to the following description of one or more embodiments. Attached Figure Description

[0038] Figure 1 A schematic diagram of a transistor is shown, along with a graph illustrating the drain-source current as a function of the transistor's gate voltage.

[0039] Figure 2A A transistor circuit comprising a voltage converter at the gate of a transistor is shown according to an embodiment of the present invention.

[0040] Figure 2B A transistor circuit according to an embodiment of the present invention is shown, which includes a voltage converter at the source of the transistor and optionally at the drain of the transistor.

[0041] Figure 3The relationship between the drain-source current of a GFET and the gate voltage, and its approximation, are shown.

[0042] Figure 4 A schematic diagram of a device for integrating the transistor circuit current for a system, according to an embodiment of the present invention, is shown.

[0043] Figure 5 A basic first-order measurement loop for a system for measuring a specific voltage of a transistor circuit according to an embodiment of the present invention is shown.

[0044] Figure 6 A block diagram of a first-order linear system according to an embodiment of the present invention is shown.

[0045] Figure 7 A schematic diagram of a second-order system according to an embodiment of the present invention is shown.

[0046] Figure 8 A block diagram of a second-order system according to an embodiment of the present invention is shown.

[0047] Figure 9 The output voltage of a system utilizing a high-gain modulation of a second-order system with a bandwidth of 70 Hz is shown according to an embodiment of the present invention.

[0048] Figure 10 It shows Figure 9 An enlarged version.

[0049] Figure 11 It is shown that it is also used to obtain Figure 9 The simulation results show the frequency response of the second-order system.

[0050] Figure 12 The diagram illustrates the time-varying output voltage of a system utilizing a small-gain modulation of a second-order system with a 70Hz bandwidth, according to an embodiment of the present invention.

[0051] Figure 13 It shows Figure 12 An enlarged version.

[0052] Figure 14 The frequency response of a system utilizing high-gain modulation of a second-order system with a 7Hz bandwidth, according to an embodiment of the present invention, is shown.

[0053] Figure 15 It shows Figure 14 The system's output voltage.

[0054] Figure 16 It shows Figure 15 An enlarged version.

[0055] Figure 17A schematic diagram of an exemplary system for measuring a specific gate voltage that generates a minimum current in a transistor circuit, according to an embodiment of the present invention, is shown. The system includes a 1-bit quantizer and a digital-to-analog converter.

[0056] Figure 18 The characteristics of a GFET and its linear approximation for use by a system including a quantizer and a digital-to-analog converter, according to an embodiment of the present invention, are shown.

[0057] Figure 19 The decimation filter of a system according to an embodiment of the present invention is shown being converted into a voltage output.

[0058] Figure 20 Showing scaled to Figure 19 A plot of the stable output of the decimation filter.

[0059] Figure 21 A plot is shown where a reference voltage is scaled to the stable output of the decimation filter, the reference voltage being compared with the voltage used to obtain... Figure 20 The plotted reference voltage is closer to the specific voltage.

[0060] Figure 22 A schematic diagram of an exemplary system for measuring a specific voltage in a transistor circuit according to an embodiment of the present invention is shown. The system includes N q Bit quantizer and N q Bit-to-digital converter.

[0061] Figure 23 The diagram illustrates a plot of the decimation filter output, varying according to the number of samples used for simulation, based on an embodiment of the present invention, showing N... q Bit quantizer and N q The operation of a bit-to-digital-to-analog converter system.

[0062] Figure 24 It shows the relationship with Figure 23 The same simulation is plotted, scaled to the stable output of the decimation filter.

[0063] Figure 25 It shows the relationship with Figure 23 The simulation output is the same as the 5-bit quantizer output in the original simulation, varying with the number of samples.

[0064] Any reference numerals in the claims should not be construed as limiting the scope.

[0065] In different accompanying drawings, the same reference numerals refer to the same or similar elements. Detailed Implementation

[0066] The invention will be described with reference to specific embodiments and particular drawings, but the invention is not limited thereto but is defined only by the claims. The described drawings are merely illustrative and not restrictive. In the drawings, some elements may be enlarged and not drawn to scale for illustrative purposes. Dimensions and relative dimensions do not correspond to an actual reduction in scale for the practice of the invention.

[0067] The terms "first," "second," etc., used in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe a temporal, spatial, hierarchical, or any other order. It should be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can operate in an order different from that described or illustrated herein.

[0068] It should be noted that the term "comprising" as used in the claims should not be construed as limiting itself to the means listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the features, integers, steps, or components stated as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the scope of the statement "a device comprising means A and B" should not be limited to a device consisting solely of components A and B. It means that, for the purposes of this invention, the only relevant components of the device are A and B.

[0069] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrase "in an embodiment" or "in an embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, but may refer to different embodiments. Furthermore, in one or more embodiments, as will be apparent to those skilled in the art from this disclosure, particular features, structures, or characteristics may be combined in any suitable manner.

[0070] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of simplification and to aid in understanding one or more of the various inventive aspects. However, this method of disclosure should not be construed as reflecting an intention to claim more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the inventive aspect lies in fewer features than all the features of a single foregoing disclosed embodiment. Thus, the claims appended to the Detailed Description are thereby explicitly incorporated into this Detailed Description, wherein each claim itself represents a separate embodiment of the invention.

[0071] Furthermore, while some embodiments described herein include features found in other embodiments but not in those other embodiments, combinations of features from different embodiments are intended to fall within the scope of the invention and form different embodiments as will be understood by those skilled in the art. For example, any embodiment of the claimed embodiments in the appended claims may be used in any combination.

[0072] Numerous specific details are set forth in the specification provided herein. However, it should be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0073] In embodiments of the present invention, when referring to the secondary region of the transistor circuit, the reference is to the region in which the current versus gate characteristic can be approximated by a second-order curve.

[0074] In the case of a linear region of a reference transistor circuit in an embodiment of the present invention, the reference is made to a region in which the current characteristics relative to the gate can be approximated by two linear functions.

[0075] Embodiments of the present invention relate to a system 100 for characterizing a transistor circuit including a gate, source, and drain. The transistor circuit is configured such that the transfer function of the drain-source current varying with respect to the gate-source voltage has a local minimum with respect to a specific voltage. The system 100 is configured to measure this specific voltage.

[0076] An exemplary embodiment of such system 100 is in Figure 5 , Figure 7 , Figure 17 and Figure 22 It is shown in the middle.

[0077] The system according to an embodiment of the present invention includes:

[0078] Transistor circuit 110;

[0079] Bias voltage generator 120, configured to generate a flip signal with a positive predefined bias voltage v around a given bias point. G With negative predefined bias voltage v G Flip between;

[0080] One or more integrators 130;

[0081] Multiplier 140 is configured to generate an electrical signal by multiplying an electrical signal, which is a function of the drain-source current of transistor circuit 110, with a waveform that alternates between two predefined values, positive A and negative A, synchronously with a flip signal, wherein a first integrator 130 of one or more integrators 130 is configured to integrate the electrical signal from multiplier 140, or, if more integrators 130 are present, to provide a linear combination of the output signals of the integrators to further integrators 130;

[0082] Adder 150 is configured to sum the inverted signal and an integral signal or a processed version of the integral signal, and is configured to output the sum as the gate-source voltage of a transistor circuit, wherein the integral signal is obtained by linearly combining the outputs of one or more integrators 130.

[0083] In embodiments of the invention, the gate voltage or source voltage can be flipped to obtain a gate-source voltage flip corresponding to the flip signal. When the source voltage is flipped, the drain voltage can be flipped simultaneously, so that the drain-source voltage remains stable. Flipping the source voltage can be advantageous for common-gate operation. In such a configuration, the common gate of one or more transistor circuits can be held at a fixed potential, and a feedback voltage (i.e., the sum of the flip signal, the integral signal, or a processed version thereof) can be applied to the source. Then, a version of the feedback voltage should also be applied to the drain simultaneously, so that a stable drain-source voltage is obtained. This is also advantageous for common-gate operation. When the source voltage is flipped without flipping the drain voltage, the instability of the drain-source voltage can be compensated by post-processing to remove errors caused by the instability of the drain-source voltage.

[0084] An advantage of embodiments of the present invention is that a specific voltage related to a local minimum of the transfer function of a transistor circuit can be obtained from the integrated signal or a processed version of the integrated signal.

[0085] System 100 according to embodiments of the present invention may include different types of transistor systems. The inventors have discovered specific transistor circuits according to embodiments of the present invention, which can be used to detect and / or quantify chemical components such as, for example, biomolecules or ions. The transistor circuits may be sensitive to different kinds of chemical components (e.g., different types of biomolecules or different kinds of ions).

[0086] In the field of sensing, field-effect transistors (FETs) can be used with gate electrodes that are sensitive to one or more chemical components. When the gate electrode is exposed to a liquid or gas containing one or more chemical components, these chemical components interact with the gate electrode in a certain way, causing the FET to change its electrical characteristics, such as, for example, the drain-source current Ids, which is a factor of the gate-source voltage V. GS and drain-source voltage V DS The function f: I DS =f(V DS V GS ).

[0087] The usual approach is to initialize the function I. DS =f1(V DS V GS The value is known, or measured before the transistor is exposed to the medium.

[0088] After exposure to the medium and the interaction between the molecules to be detected and the gate, V DS V GS with I DS The relationship between them was modified to I DS =f2(V DS V GS The inventors observed that, in most cases, f2 was shifted relative to f1.

[0089] In the classic method, the shift between f2 and f1 is measured and analyzed. This is time-consuming and requires some complex hardware / software work. Figure 1 The left figure shows a classic n-channel field-effect transistor with gate (G), source (S), and drain (D) terminals. The right figure shows the drain-source current Ids based on the gate-source voltage V. GS And change (I) DS =f(V GS The characteristics of )). At a given bias point V b At this point, the drain-source current can be derived from the bias voltage: I DS =f(V b ).

[0090] The inventors have discovered that by combining transistors in a transistor circuit, the drain-source current of the transistor circuit, which varies with the gate-source voltage, has a local minimum.

[0091] Figure 2AAn example of this is illustrated in the figure. Transistor circuit 110 includes a first transistor 111 and a second transistor 112, the first transistor 111 and the second transistor 112 having a shared source forming the source of transistor circuit 110 and a shared drain forming the drain of transistor circuit 110. A first voltage converter 113 converts the voltage at the gate of transistor circuit 110 into the voltage at the gate of first transistor 111 according to a transfer function having a first slope, and a second voltage converter 114 converts the voltage at the gate of transistor circuit 110 into the voltage at the gate of second transistor 112 according to a transfer function having a second slope. The first slope and the second slope have opposite signs.

[0092] Alternatively, the first voltage converter 113 and the second voltage converter 114 may be connected to the source of the first transistor 111 and the source of the second transistor 112, respectively, to create a gate-source voltage. Figure 2B An example of this is illustrated in the figure. In this case, additionally, the transistor circuit may include a third voltage converter 113' and a fourth voltage converter 114', which are respectively connected to the drain of the first transistor 111 and the drain of the second transistor 112, to drive the drain with a version of the signal on the source of the first and second transistors, so as to achieve a constant drain-source voltage for the first transistor and a constant drain-source voltage for the second transistor, thereby allowing a stable drain-source current to be obtained. Similarly, this is also advantageous for common-gate operation under the consideration of a dual-transistor circuit.

[0093] Maintaining a constant drain-source voltage is not strictly necessary. Systems according to embodiments of the invention can also operate with some form of modulation of the drain-source voltage. This results in a shift in the detected minimum conduction point, but this is acceptable in various applications. For example, a user might be interested in the drift before and after exposure to a target chemical, and the measured drift modulated by the drain-source voltage might be the same as the actual voltage drift for a specific voltage (e.g., the Dirac voltage). In embodiments of the invention, the system can be configured to post-process the found minimum to compensate for variations in the drain-source voltage.

[0094] The transistor circuit 110 in Figure 2 may be sensitive to any type of exposure. The two transistors can be the same type of transistor. They can be, for example, two n-channel transistors (as shown in the schematic diagram), or they can be, for example, two p-channel transistors, two depletion-mode transistors, or two zero-threshold voltage transistors.

[0095] A transistor can be, for example, composed of a threshold voltage V. th To characterize the threshold voltage V th It can be positive, negative, or even zero.

[0096] In embodiments of the present invention, the transistor has a nonlinear current characteristic relative to the control voltage, which at the operating point V b Nearby, their I = f(V) characteristic polynomial expansion has a quadratic term. Any transistor can be used. They can also be bipolar transistors or MOSFET transistors, which can also operate in their subthreshold ( <V th It is used within the range.

[0097] The first voltage converter 113 uses the following formula to convert the voltage V at the gate of the transistor circuit. GS This is converted to the voltage at the gate of the first transistor 111:

[0098] V GS1 =V b +G(V GS -V d )

[0099] This function defines the first transistor at the control voltage V. GS =V d The minimum conduction point (gate voltage V) appears at this location. b The operating point is located at (). The voltage V applied between the gate and source of the first transistor is (). GS1 Based on a given slope (G) and control voltage V GS Increase.

[0100] The second voltage converter 114 uses the following formula to convert the voltage V at the gate of the transistor circuit. GS This is converted to the voltage at the gate of the second transistor 112:

[0101] V GS2 =V b -G(V GS -V d )

[0102] The voltage V applied between the gate and source of the second transistor GS2 Based on the opposite slope or gain factor (-G) with control voltage V GS reduce.

[0103] The drain-source current of the first transistor is shown in Figure 2 and is a function of the gate-source voltage, expressed as I. ds = f(T1). It has a positive slope due to the first voltage converter. The drain-source current of the second transistor is shown in Figure 2 and is a function of the gate-source voltage, expressed as I. ds= f(T2). It has a negative slope due to the second voltage converter. For unexposed transistors, the traces are mirrored in the vertical direction because they are in their initial state.

[0104] The combined drain-source current of the two transistors is the sum of the drain-source currents of each individual transistor, and is expressed as I. ds = f(T1,T2). This final trace of the transistor circuit is characterized by the current having a local minimum and the current having a quadratic property around that minimum.

[0105] If the voltage-current characteristic of one transistor in a transistor shifts, then the local minimum will shift to a value similar to V. d Different other locations. For example, this might occur when the first or second transistor is exposed to and sensitive to a chemical component. When a sensitive transistor is exposed to a chemical component (e.g., biomolecules or ions), this will cause a shift in the transfer function, and therefore also a shift in the local minimum. The advantage is that the specific voltage at which this minimum occurs can be measured using a system according to an embodiment of the invention.

[0106] In Figure 2, one transistor can be exposed to and sensitive to a chemical component, while the other transistor is not exposed to the same chemical component. The chemical component can be present in a given medium, such as a liquid, gel, or gas.

[0107] In the transistor circuit illustrated in Figure 2, the transistors can also be, for example, graphene transistors, in which both transistors are exposed to a dielectric, but only one transistor is functionalized, for example, to be more sensitive to a given kind of chemical component (e.g., biomolecules), while the other transistor is not.

[0108] In embodiments of the present invention, a single graphene field-effect transistor (GFET) can also be used as transistor circuit 110 (see [link]). Figure 3 (Illustration in the figure). Therefore, the reason is that a single GFET has a local minimum in its current-voltage characteristics. In this case, the specific gate-source voltage at which the drain-source current is at a local minimum is the Dirac voltage of the GFET. Using a system according to an embodiment of the invention, the GFET is integrated within a closed-loop system that acts as a low-pass filter, delivering an output voltage equal to the Dirac voltage of the GFET. The loop can be a Σ-Δ modulator that delivers a digital value of the Dirac voltage. In embodiments of the invention, the Dirac voltage is shifted during the exposure of the GFET to the chemical composition to which the GFET is sensitive.

[0109] If, in the transistor circuit illustrated in Figure 2, two graphene transistors are used, one exposed and the other not, or one functionalized and the other not, this results in the superposition of two nonlinear functions, both possessing Dirac points, and their combination sharing a common Dirac point. This common Dirac point shifts during exposure when the exposure alters the electrical characteristics of the exposed graphene transistor. This is not illustrated in the right-hand plot of Figure 2, which instead shows the current-voltage characteristics of a conventional MOS transistor. In the embodiment of the invention with the transistor circuit illustrated in Figure 2, both transistors can generate transfer functions, which, in the case of MOS transistors, can be approximated, for example, by a second-order transfer function near the minimum conduction point:

[0110] I DS =I1+a1(V GS -V d )+b1(V GS -V d ) 2 +I2-a2(V GS -V d )

[0111] +b2(V GS -V d ) 2

[0112] I DS =I1+I2+(a1-a2)(V GS -V d )+(b1+b2)(V GS -V d ) 2

[0113] If the electrical characteristics of one of the transistors are modified, the minimum conduction point shifts. If transistor T2 is exposed, this could be a2, a2, or b2.

[0114] These equations and the following equation are valid when the transistor is a MOS transistor. If two GFETs are used, similar equations can be derived.

[0115] In a specific case of a strongly reverse-biased MOS transistor, using the transistor's threshold voltages Vth1 and Vth2, the following I can be derived: ds =f(V GS )characteristic:

[0116] I ds =a1(V GS1 -V th1 ) 2+a2(V GS2 -V th2 ) 2

[0117] I ds =a1(V b +G(V GS -V d )-V th1 ) 2 +a2(V b -G(V GS -V d )-V th2 ) 2

[0118] In embodiments of the invention, the transistor circuit can be configured such that the minimum on-point of the system is set at the gate voltage V before the same matching transistors are exposed. GS =V d =0. Then, the following equation can be derived:

[0119] I ds =a1(V b +GV GS -V th1 ) 2 +a2(V b -GV GS -V th2 ) 2

[0120] If the gain a2 or the threshold V th2 If the transistor T2 is modified, for example, exposed to chemical components, the minimum conduction point is shifted.

[0121] The specific voltage V at the minimum conduction point GSmc The equation above can be calculated by... ds By taking the first derivative and setting it to zero, we obtain:

[0122]

[0123] The transistor circuit shown in Figure 2 will have a local minimum (minimum conduction point) at a specific voltage. When one of the transistors is sensitive and exposed to chemical components, the specific voltage changes.

[0124] The advantage is that the specific voltage can be obtained using a system 100 including the transistor circuit according to an embodiment of the present invention.

[0125] In embodiments of the present invention, the transistor in the transistor circuit can be a chemically sensitive transistor (CHEMFET) or an ion-sensitive transistor (ISFET), but it can also be a graphene transistor (GFET) in a differential method. New application areas can also be supported, such as areas where graphene transistors are not sufficiently sensitive (e.g., measurements at very high temperatures or in harsh media).

[0126] In embodiments of the invention, the first transistor or the second transistor may be exposed to and sensitive to a chemical component. In embodiments of the invention, only one transistor may be exposed to and sensitive to a chemical component.

[0127] In embodiments of the invention, the first transistor and the second transistor may be exposed to a chemical component, and only one transistor is sensitive to that chemical component. For example, in the case of two (graphene) transistors, only one transistor may be functionalized while the other transistor is not functionalized, and both are exposed.

[0128] In embodiments of the invention, only one of the first or second transistors may be exposed to the chemical component, and both the first and second transistors are sensitive to the chemical component. For example, the two transistors may be identical (e.g., two identical chemFETs), and only one transistor is exposed to the chemical component.

[0129] Figure 3 The MIT model 10 of GFET is shown. The model was proposed in "Mackin, C. (2018) Graphene chemical and biological sensors: Modeling, systems, and applications" of the MIT doctoral dissertation. Figure 3 The fitting is shown by simple linear and quadratic approximations.11

[0130] At Dirac point (V d Around the gate voltage, the current characteristic relative to the gate voltage can be approximated by a second-order curve:

[0131] I DS (V G ) = I DS0 +α(V G -V d ) 2

[0132] Moving away from the Dirac point, this property becomes more linear and can be approximated by two lines:

[0133] IDS (V G ) = I DS1 -2αV1(V G -(V d -V1))V G ≤V d -V1I DS (V G ) = I DS1 +2αV1(V G -(V d +V1))V G ≥V d +V1

[0134] The junction between these three parts is at the gate voltage V. d -V1 and V d +V1. At these points, I DS =I DS1 =I DS0 +α(V1) 2 And the slope (transconductance) is 2αV1.

[0135] I DS (V G )={I DS1 -2αV1(V G -(V a -V1)) If V G

[0136] ≤V d -V1; I DS0 +α(V G -V d ) 2 If V d -V1 <V G

[0137] <V d +V1;I DS1 +2αV1(V G -(V d +V1)) If V G ≥V d +V1}

[0138] In a system according to an embodiment of the invention, wherein transistor circuit 110 is a GFET, an analog low-pass filter loop automatically adjusts the gate voltage to the Dirac point. The advantage of this method is that it can achieve low-noise, high-resolution measurements of the Dirac point in approximately the same time as the cited prior art systems would spend for each single step of their gate voltage ramp. In embodiments of the invention, simple analog / digital circuitry can be used, resulting in low power consumption.

[0139] A system 100 according to an embodiment of the present invention for measuring a specific voltage (e.g., Dirac voltage) of a transistor circuit 110 (e.g., a graphene field-effect transistor or the transistor circuit shown in FIG. 2) includes: the transistor circuit 110; and a bias voltage generator 120 configured to generate a flip signal having a positive predefined bias voltage v around a given bias point. G With negative predefined bias voltage v G The bias point is thus determined by the average level of the switching signal generated by the bias voltage generator. A given bias point can be, for example, zero volts. However, the invention is not limited to this. The given bias point can also be different from zero.

[0140] Furthermore, system 100 includes a multiplier 140 configured to generate an electrical signal by multiplying an electrical signal, which is a function of the drain-source current of a transistor circuit, with a waveform alternating between two predefined values, +A and -A, such as the channel current I of a graphene field-effect transistor 110. DS Or the current I through transistors T1 and T2 in the circuit of Figure 2. DS The waveform alternates synchronously with the gate voltage flip signal. Depending on the frequency of the gate voltage flip and the characteristics (frequency response) of the transistor circuit, the alternating waveform applied to the multiplier can thus be delayed (phase shifted) relative to the gate voltage flip signal. A predefined value A can be, for example, equal to 1. However, the invention is not limited thereto. Furthermore, other values ​​of A are also possible. Factor A is the multiplication factor of the signal to be integrated. This signal can be the drain current of the transistor circuit (e.g., the drain current of a GFET), the product of drain currents, the output of a transimpedance amplifier, and this signal is referred to as the transistor circuit signal. This signal is integrated by an integrator that also has a gain factor. In embodiments of the invention, A is selected such that the product of all multiplication factors applied to the transistor circuit signal does not at any time cause the first integrator to saturate. This total gain factor affects the loop bandwidth and stability. The feedback or feedforward factor is preferably selected to achieve the desired bandwidth and stability, thereby taking into account the characteristics of the transistor circuit and all multiplication factors involved in the integration of the transistor circuit signal. In exemplary embodiments of the invention, A can be, for example, in the range between 0.001 and 1000.

[0141] In addition, system 100 includes one or more integrators 130, wherein a first integrator 130 of the one or more integrators 130 is configured to integrate an electrical signal from multiplier 140, and wherein if more integrators 130 are present, a linear combination of the output signals of the integrators is provided to a further integrator 130.

[0142] In addition, system 100 includes adder 150, which is configured to sum the inverted signal of bias voltage generator 120 with an integral signal or a processed version of the integral signal, wherein the integral signal is obtained by linearly combining the outputs of one or more integrators 130.

[0143] In an embodiment of the invention, the system includes a sample-and-hold circuit for sampling and holding an integrated signal to obtain a processed version of the integrated signal.

[0144] In embodiments of the invention, the integral signal may be sampled before the toggle signal applied to the multiplier flips from -A to +A (or from +A to -A), and held for one full cycle of the toggle signal applied to the multiplier (at the same frequency as the toggle voltage applied to the gate, but possibly with a delay) until the next toggle from -A to +A (or from +A to -A). However, the invention is not limited thereto. A sample-and-hold circuit is not strictly necessary, and if present, a different sampling time than specified above may be chosen.

[0145] In an embodiment of the invention, the last integrator in the loop can be implemented using a switched capacitor circuit for providing sampling and holding functions.

[0146] In such systems, according to embodiments of the invention, a loop is formed. In order for the loop to converge to a stable gate voltage at a specific voltage that is at a local minimum, the low-pass filter loop must integrate a quantity that is 0 when the gate voltage is at the specific voltage and has a linear dependence on the gate voltage near the specific voltage.

[0147] Near a specific voltage, the current characteristic relative to the gate voltage is a second-order curve, so its derivative is a linear function of the gate voltage, which is zero at a local minimum of the current.

[0148] Therefore, this loop can handle the quantity ΔI DS (V G ) = I DS (V G +v G )-I DS (V G -v G ), where v G It is a predefined bias voltage that allows the current difference to be used with V. G Expressed as the derivative of the current at a given point:

[0149] ΔI DS (V G )=2α(V G -V d(2v) G )

[0150] Therefore, the system must handle the difference between two current measurements performed at slightly different gate voltages. These current measurements must be performed sequentially. The gate voltage (V) applied to the transistor circuit... GS Also known as V Gate (V 棚极 )) can be found in V G +v G With V G -v G The difference is periodically flipped between V and V, and the difference can be obtained by... G -v G The inverted integrating current is applied to the gate to perform calculations within the integrator.

[0151]

[0152] rect(t-nT)={0t <nT 1t≥nT}

[0153]

[0154] ∫M(t)dt=0

[0155] M(t) 2 =1

[0156] M(t) is a square wave oscillating between A = +1 and -A = -1, with a period of T and a duty cycle of 50%.

[0157] ∫M(t)I DS (t)dt=∫M(t)[1 DS (V G )+2α(V G -V d )M(t)v G ]dt

[0158] =I DS (V G )∫M(t)dt+∫2α(V G -V d )v G M(t) 2 dt

[0159] =∫2α(V G -V d )v G dt

[0160] The integral of the drain-source current of the transistor circuit at Figure 4The diagram is shown in the figure. The basic first-order measurement loop of a system according to an embodiment of the invention for measuring a specific voltage at a local minimum (e.g., the Dirac voltage in the case of a GFET transistor circuit) is shown in the figure. Figure 5 The diagram is shown. It illustrates a transistor circuit 110 (represented by a characteristic plot of the transistor circuit 110 having local minima of the current-voltage characteristics), a bias voltage generator 120, a first integrator 130, a multiplier 140, and an adder 150. In this example, the bias point of the bias voltage generator is 0, and as a result, the integrated signal in this example will be a specific voltage corresponding to the local minimum. If the bias point is not zero, the integrated signal will be the specific voltage minus the bias point.

[0161] The integrator integrates the difference between the currents of two transistor circuits corresponding to two different gate voltages, so as to integrate the slope of the current characteristic with respect to the gate voltage rather than the current itself.

[0162] Figure 5 The basic loops shown in the diagram form a first-order linear system, and its block diagram is shown in... Figure 6 As shown in the image.

[0163] This loop can be extended to any order. In an embodiment of the invention, the system includes exactly two integrators, wherein the input signal of the second integrator is the sum of the output signal of the first integrator and the output signal of the second integrator multiplied by a predefined constant a1. Figure 7 An example of this is illustrated in the figure. It shows a transistor circuit 110 (which could be, for example, a GFET or a transistor circuit as illustrated in Figure 2), a bias voltage generator 120, a first integrator 130a, a second integrator 130b, a multiplier 140, an adder 150, a multiplier 191 for multiplying the output signal of the second integrator 130b by a predefined constant a1, and an adder 192 for adding the output signal of the first integrator 130a to the output signal of the second integrator 130b.

[0164] The corresponding block diagram of the second-order system is in Figure 8 The diagram is shown in the figure. In this block diagram, K1 holds the product multiplication factor of possible mutual impedance factors, the amplitude (A) of the multiplication waveform, and the capacitor used in the implementation of the continuous-time integrator. K2 holds the time constant of the second continuous-time integrator.

[0165] In embodiments of the invention, the system has a sufficiently small predefined bias voltage modulation such that the modulation is within the secondary region of the transistor circuit characteristics (e.g., GFET characteristics).

[0166] When difference I DS (V G+v G )-I DS (V G -v G The predefined bias voltage v involved in ) G >2V1 and the gate voltage are located in the two linear regions of the transistor circuit characteristics V G -v G ≤V d -V1 and v G +v G ≥V d In +V1, the linear system description is valid.

[0167] in this case,

[0168] I DS (V G +v G )-I DS (V G -v G )

[0169] =I DS1 +2αV1(V G -(V d +V1))-[I DS1 -2αV1(V G -(V d -V1))]

[0170] =4αV1(V G -V d )

[0171] The difference from the previous case is that the gain is 4αV1 instead of 4αv. G .

[0172] Using large gate voltage modulation allows for the search for a specific voltage within a large gate voltage range.

[0173] In embodiments of the present invention, the loop can be implemented using a continuous-time integrator or a discrete-time integrator.

[0174] The following Matlab simulation results illustrate the behavior of the described second-order system where the transistor circuit is a GFET. The MIT model 10 for the GFET has a voltage at V... d The Dirac point is α = 0.61 V. The approximation 11 described in the document has the following parameters: α = 0.0016 A / V. 2 V1 = 0.0457V, I DS0 =23μA. These parameters are used for Figure 3 The parameters of the model in the text.

[0175] The first loop is constructed with a bandwidth of approximately 70 Hz. The predefined bias voltage is + / - 0.2 V at 1 kHz (i.e., large gate voltage modulation). Loop parameters are calculated considering a gain of 4αV1. Figure 9 and Figure 10 Simulation results show that the filter output reaches the Dirac voltage in less than 50 ms (see [reference]). Figure 7 A residual oscillation of + / -1mV exists at 1kHz (see...). Figure 10 , it is Figure 9 (Amplified version between 0.607V and 0.612V). Figure 11 The frequency response of the second-order system is shown.

[0176] The following simulation results show a predefined bias voltage v with the same 70Hz bandwidth, but using 0.01V instead of 0.2V. G The second loop design (i.e., small gate voltage modulation) is considered. This is in the case of a gain value of 4αv. G The loop parameters are calculated under these conditions. Therefore, the integrator time constant differs from the integrator time constant used with a larger bias voltage. Figure 12 The plot shows the stability at the output of the second-order system modulated by a small gate voltage. Starting from the discharge integrator, the correct value is reached within 100 milliseconds. The loop initially operates outside the secondary GFET current region, where the current difference ΔI... DS (V G )=-2αV1 is constant, not related to V G Proportional. Only if V G The loop only begins to function upon entering the secondary region. This will be explained further in the following paragraphs.

[0177] The residual oscillation of a second-order system with a 70Hz bandwidth and a small gate voltage modulation at 1kHz has an amplitude of 2mV. This is in Figure 13 The figure is shown in the middle. Figure 13 It shows Figure 12 An amplified version, between 0.598V and 0.618V.

[0178] Using a smaller filter bandwidth can reduce oscillations. Figure 14 , Figure 15 and Figure 16 Results are shown for a loop with a bandwidth of less than 7 Hz and modulated using a large gate signal. The filter stabilizes within 500 ms, with residual oscillations of 15 μV. Figure 14 The frequency response of a second-order system with a 7Hz bandwidth and utilizing large gate voltage modulation is shown. Figure 15The figure shows the stable Matlab simulation results of a second-order system with a 7Hz bandwidth and large gate voltage modulation. Figure 15 The figure shows Matlab simulation results of the residual oscillations of a second-order system modulated with a large gate voltage at a 7Hz bandwidth output. The residual oscillations can be reduced by introducing a sample-and-hold circuit; however, this is not strictly necessary.

[0179] In an embodiment of the invention, system 100 includes a quantizer 160 configured to quantize an integral signal at a predefined sampling frequency. Furthermore, system 100 includes a digital-to-analog converter 170 for converting the quantized signal into an analog signal for summing with a flipped signal at adder 150.

[0180] Therefore, the low-pass filter loop is transformed into a Σ-Δ modulator. This is because of the current difference ΔI. DS A linear relationship with the gate voltage is feasible.

[0181] Figure 17 A schematic diagram of an exemplary system for measuring a specific voltage corresponding to a local minimum of the current in a transistor circuit (which may be, for example, a GFET) is shown according to an embodiment of the present invention. The system includes a second-order Σ-Δ ADC.

[0182] Figure 17 System 100 includes a transistor circuit 110, a bias voltage generator 120, a digital-to-analog converter 170, and an adder 150 for summing a signal from the bias voltage generator 120 and a signal from the digital-to-analog converter 170. The output of the adder 150 is connected to the gate of the transistor circuit 110. Additionally, system 100 includes a waveform generator 142 configured to generate a waveform alternating between +A and -A; and a multiplier 140 configured to multiply the waveform generated by the waveform generator with an electrical signal that is, for example, a function of the channel current of a GFET, or the sum of the two channel currents of the two transistors of the transistor circuit 110. Additionally, the system includes: a first integrator 130a for integrating the signal from multiplier 140; and a second integrator 130b for integrating a sum obtained using adder 192, the sum being the sum of the signal from the first integrator 130a, the quantized output of the second integrator multiplied by a predefined factor a1 using multiplier 191. Furthermore, the system includes a 1-bit quantizer for quantizing the output signal of the second integrator 130b. Additionally, the system includes a decimation filter 180 at the output of the quantizer.

[0183] exist Figure 17 In the exemplary embodiment illustrated, the ∑-Δ loop does not smoothly regulate the gate voltage to a specific voltage (e.g., in the case of a GFET, this specific voltage is the Dirac point), but rather operates within two fixed voltage V values ​​over a region where the linear relationship between the current difference and the gate voltage is effective. ref1 With V ref2 Between switching gate voltage V G Therefore, the output of the 1-bit quantizer is connected to the switch of the digital-to-analog converter 170, which is set at V. ref1 With V ref2 Switch between them and connect them alternately to adder 150.

[0184] Then, transistor circuit 110 operates only at four possible different voltages: V ref1 ±v G and V ref2 ±v G , where v G These are predefined voltages from the bias voltage generator 120. These will generate only two distinct values ​​for the current difference:

[0185] ΔI DS1 =ΔI DS (V ref1 ) = I DS (V ref1 +v G )-I DS (V ref1 -v G )

[0186] ΔI DS2 =ΔI DS (V ref2 ) = I DS (V ref2 +v G )-I DS (V ref2 -v G )

[0187] For the linear relationship to be valid, the gate voltage must be selected as follows. If a small gate voltage modulation v is used... G (That is, within the secondary region of the transistor circuit), all four gate voltages must be located in the central secondary portion of the transistor circuit characteristics. In an embodiment of the invention, small v G Signal modulation is used in the secondary region such that at a first predefined voltage, the gate voltage flips between two levels to the left of a specific voltage (the gate voltage is less than the specific voltage V). d Furthermore, at the second predetermined voltage, both levels will be to the right of a specific voltage (the gate voltage is greater than the specific voltage V).d ).

[0188] To make the linear relationship valid, if a large gate voltage modulation v is used G (That is, within the linear region of the transistor circuit), all four gate voltages must be outside the central quadratic region of the transistor circuit characteristics:

[0189] V ref1 +v G >V d (Right-linear region)

[0190] V ref1 -v G <V d (Left linear region)

[0191] V ref2 +v G >V d (Right-linear region)

[0192] V ref2 -v G <V d (Left linear region)

[0193] In an embodiment of the present invention, the Σ-Δ loop modulates the frequency with the gate voltage. Sampling is performed. This is done by... Figure 17 The sampling trigger signal 162 is shown in the figure. The ∑-Δ loop delivers a bit stream that alternates between 0 and 1. Let D be the ratio between the number of 1s in the bit stream and the total number of bits.

[0194] The ∑-Δ loop will adjust D so that ΔI DS The average value is 0. Therefore, ΔI DS With transistor circuit I DS Compared to V Gs The slope of the characteristic is proportional and becomes 0 at a specific voltage. The Σ-Δ modulator generates its feedback signal such that the quantity integrated by the integrator averages to 0.

[0195] I DS =DΔI DS2 +(1-D)ΔI DS1

[0196] Assuming large gate voltage modulation:

[0197] I DS =D4αV1(V ref2 -V d )+(1-D)4αV1(V ref1 -V d )

[0198] I DS =0, therefore:

[0199] D(V ref2 -V d )+(1-D)(V ref1 -V d ) = 0

[0200] D(V ref2 -V ref1 )+V ref1 -V d =0

[0201] V d =D(V) ref2 -V ref1 )+V ref1

[0202] This invention is not limited to second-order Σ-Δ modulators. Σ-Δ modulators of different orders can also be used.

[0203] In embodiments of the present invention, the integrator may be a continuous-time integrator or a discrete-time integrator.

[0204] According to embodiments of the present invention and Figure 17 The Matlab simulation of the exemplary system, illustrated in the figure, applied to a GFET described by the MIT model, has been performed. The Dirac point is at 0.61V, and the limit of the quadratic region is V1 = 0.045V.

[0205] If the converter can be from V ref1 To V ref2 If the system can accurately convert across the entire reference voltage range, it will be able to measure voltages from V... ref1 To V ref2 The range of the Dirac voltage of the GFET or the minimum value of the two T values ​​in transistor circuit 110. I DS The voltage (i.e., the specific voltage of the transistor circuit).

[0206] If the system operates using large gate modulation, the following conditions must be met:

[0207] V ref1 +v G It should be in the right linear region, therefore:

[0208]

[0209] V ref1 -v G It should be in the left linear region, therefore:

[0210]

[0211] V ref2 +v G It should be in the right linear region, therefore:

[0212]

[0213] V ref2 -v G It should be in the left linear region, therefore:

[0214]

[0215] Therefore, in this exemplary embodiment of the invention, a predefined bias voltage (also referred to as a modulation voltage) v G The following conditions must be met:

[0216] v G ≥V ref2 -V ref1 +V1

[0217] For this simulation, the following value has been used: V ref1 =0.55V, V ref2 =0.65V and v G =0.145V. Sampling frequency F s =1kHz. In embodiments of the invention, the system includes a decimation filter. For example, the decimation filter may be a sinc3 filter with an oversampling rate of 256.

[0218] Given the values ​​given above, the GFET operates at the following gate voltages:

[0219] V ref1 +v G =0.695V

[0220] V ref1 -v G =0.405V

[0221] V ref2 +v G =0.795V

[0222] V ref2 -v G =0.505V

[0223] from Figure 18 As can be seen from the plot, these values ​​are within the limits of the linear approximation. The plot shows the relationship between the drain current and the drain current for accurate model 10 and approximation 11. The output of the decimation filter gives a Dirac point measurement of 0.6099V.

[0224] Figure 19The output of the decimation filter, converted to voltage, is shown. The filter output stabilizes within 3*256 samples, corresponding to a settling time of 768 ms.

[0225] Figure 20 A plot showing the stable output scaled to the decimation filter is displayed.

[0226] In an alternative embodiment of the invention, a reference voltage that is closer to the actual Dirac voltage can be selected. For example, the following values ​​can be selected: V ref1 =0.58V, V ref2 =0.63V and v G =0.095V. In this example, the GFET operates with 4 gate voltages, where the linear approximation is better preserved, resulting in a better estimate of the Dirac point. This is in Figure 21 The image is shown in the middle. Figure 21 This shows a plot of the values ​​referenced above scaled to the stable output of the decimation filter.

[0227] In an embodiment of the present invention, the quantizer 160 has a predefined number N. q A multi-bit quantizer, wherein the digital-to-analog converter 170 has N bits. q Bit. Figure 22 An exemplary embodiment of such a system is shown in the figure. Except that the quantizer is N... q Bit quantizer and digital-to-analog converter 170 with N q Aside from the fact that it is a bit, the diagram is similar to Figure 17 The diagram is shown in the image.

[0228] The multi-bit method allows for the search for a specific voltage over a wide range. In embodiments of the invention, the initial stabilization of the loop will be responsible for the initial guess of the specific voltage, and the DAC will ultimately toggle between only 2 or 3 levels.

[0229] In an embodiment of the invention, the multi-bit quantizer within the Σ-Δ loop is a low-resolution ADC. In this embodiment, it converts not only the output of the current integrator but also a linear combination of the outputs of several integrators. In this example, the output voltage of the second integrator is converted.

[0230] In embodiments of the present invention, the output of the low-resolution multi-bit quantizer is directly connected to the low-resolution DAC without any processing by the control circuit configured to determine the voltage value applied to the control electrode of the control circuit.

[0231] As explained earlier, the current difference ΔI DS With two reference voltages V ref1 V ref2The linear relationship between them must be valid so that a single bit ∑-Δ delivers the correct value for the Dirac voltage.

[0232] If a multi-bit quantizer is used in a Σ-Δ loop, the reference voltage can be extended beyond the effective region of the linear relationship.

[0233] Instead of feedback [V] ref1 V ref2 With only two distinct gate voltages at the extreme points of the range, this loop will provide feedback. There are 10 different possible DAC voltages, which are uniformly distributed in the range [V]. ref1 V ref2 ] within, N q This refers to the number of bits of the quantizer used within the loop. After a certain settling time, the loop will automatically converge to a point where the feedback gate voltage toggles only between those possible feedback voltages, all of which are located near a specific voltage. In embodiments of the invention, the number of bits of the quantizer is chosen such that several consecutive DAC voltages are within the effective region of the linear relationship between the current difference and the gate voltage.

[0234] In the following simulation, the transistor circuit is a GFET. The following simulation diagram illustrates the use of a small gate voltage modulation (v G The multi-bit ∑-Δ (=5mV) operation can use a 5-bit quantizer and a 32-level DAC to provide digital codes for Dirac voltages ranging from 0V to 1V. The GFET model is the same as before. For small gate modulation, in the gate voltage range [V d -0.045; V d In [+0.045], the current difference is linear with respect to the gate voltage. The DAC step size is 1V / 32 = 30mV, ensuring that two or three DAC levels are within this gate voltage range.

[0235] Figure 23 A plot of the decimation filter output as it varies with the number of samples is shown. Figure 24 The scaling of the output of the decimation filter is shown. Figure 25 The output of the 5-bit quantizer varies depending on the number of samples.

[0236] Using small v G The modulated signal, preferably at the IDS of the GFET relative to V G Within the quadratic region of the characteristic, there exist several consecutive DAC voltages such that the slope (the integrated quantity) is proportional to the applied gate voltage. This is a condition for forming a linear feedback system and having accurate measurement of the Dirac voltage as a series of DAC voltages. In practice, several DAC voltages output Vdac+ / -v GPreferably, it is located in the secondary region.

[0237] Please note that the system may start in a linear region with a constant slope. In this region, there will be no actual feedback, but the integrator will guide the DAC voltage towards the Dirac voltage. Only when the DAC voltage enters the curved portion of the characteristic curve will there be an actual feedback signal and the loop will stabilize. The closer to the second-order characteristic, the more accurate the measurement of the Dirac point.

[0238] System 100 may include an upper-level system (e.g., a controller) for selecting a reference voltage for system 100, such that the loop always begins with the first stage, where a predefined bias voltage v G The system is selected such that the sum obtained by the adder lies within the linear region of the graphene field-effect transistor's characteristics and stabilizes to a first Dirac voltage, preferably within the quadratic region. In the second stage, the upper-level system is configured to select a predefined bias voltage such that the sum obtained by the adder lies within the quadratic region of the graphene field-effect transistor's characteristics. The system then stabilizes to a second Dirac voltage, which can be more accurate than or at least as accurate as the first obtained Dirac voltage. Thus, a system for performing Dirac point measurements using a two-stage method is obtained.

Claims

1. A system (100) for characterizing a transistor circuit (110), said transistor circuit (110) comprising a gate, a source, and a drain, wherein, The transistor circuit is configured such that the transfer function of the drain-source current relative to the gate-source voltage has a local minimum with respect to a specific voltage, wherein the system is configured to measure the specific voltage, the system comprising: -The transistor circuit (110), - A bias voltage generator (120) configured to generate a flip signal with a positive predefined bias voltage v around a given bias point. G With negative predefined bias voltage v G Flip between, -One or more integrators (130), - A multiplier (140), which is configured to generate an electrical signal by multiplying an electrical signal, which is a function of the drain-source current of the transistor circuit (110), with a waveform that alternates between two predefined values, positive A and negative A, synchronously with the flip signal. - wherein, the first integrator (130) of the one or more integrators (130) is configured to integrate the electrical signal from the multiplier (140), and wherein, if more integrators (130) are present, a linear combination of the output signals of one or more integrators and the output signal of the first integrator is provided to the further integrators (130). - Adder (150), the adder (150) is configured to sum the inverted signal with an integral signal or a processed version of the integral signal, and is configured to output the sum as the gate-source voltage of the transistor circuit, wherein the integral signal is obtained by linearly combining the outputs of the one or more integrators (130).

2. The system (100) according to claim 1, wherein, The transistor circuit (110) includes: - First transistor (111) and second transistor (112), - A first voltage converter (113), configured to convert the voltage at the gate of the transistor circuit (110) or the voltage at the source of the transistor circuit (110) into a gate-source voltage between the gate and source of the first transistor (111) according to a transfer function having a first slope. - A second voltage converter (114), configured to convert the voltage at the gate of the transistor circuit (110) or the voltage at the source of the transistor circuit (110) into a gate-source voltage between the gate and source of the second transistor (112) according to a transfer function having a second slope. - Wherein, the first slope and the second slope have opposite signs.

3. The system (100) according to claim 2, wherein, The first transistor (111) or the second transistor (112) is exposed to and sensitive to a chemical component; or the first transistor (111) and the second transistor (112) are exposed to a chemical component, and only one is sensitive to the chemical component; or the first transistor (111) or the second transistor (112) is exposed to a chemical component, and the first transistor (111) and the second transistor (112) are sensitive to the chemical component.

4. The system (100) according to any one of claims 2 or 3, wherein, The first transistor (111) and the second transistor (112) are metal-oxide-semiconductor FETs or bipolar transistors.

5. The system (100) according to claim 1, wherein, The transistor circuit (110) is a graphene FET.

6. The system (100) of claim 1, the system comprising a sample and hold circuit for sampling and holding the integral signal to obtain the processed version of the integral signal.

7. The system (100) according to claim 1, wherein the system includes exactly one integrator (130).

8. The system (100) according to claim 1, wherein the system comprises exactly two integrators (130a, 130b), wherein, The input signal of the second integrator (130b) is the sum of the following: the output signal of the first integrator (130a) and the output signal of the second integrator multiplied by a predefined constant a1.

9. The system (100) according to claim 1, wherein, The predefined bias voltage ensures that the sum obtained by the adder is within the quadratic region of the transistor circuit characteristics.

10. The system (100) according to claim 1, wherein, The predefined bias voltage ensures that the sum obtained by the adder is within the linear region of the transistor circuit characteristics.

11. The system (100) according to claim 1, wherein, In the first stage, the predefined bias voltage causes the sum obtained by the adder to be in the linear region of the transistor circuit characteristics, and in the second stage, the predefined bias voltage causes the sum obtained by the adder to be in the quadratic region of the transistor circuit characteristics.

12. The system (100) according to claim 1, wherein the system (100) comprises: A quantizer (160) is configured to quantize the integral signal at a predefined sampling frequency; And a digital-to-analog converter (170) for converting the quantized signal into an analog signal for summing with the inverted signal at the adder (150).

13. The system (100) according to claim 12, wherein, The digital-to-analog converter (170) flips between a first predefined reference voltage for digital 0 input and a second predefined reference voltage for digital 1 input, wherein the first predefined reference voltage, the second predefined reference voltage, and the predefined bias voltage are selected such that the flipping of the predefined bias voltage generates a voltage in the left linear region of the transistor circuit and a voltage in the right linear region of the transistor circuit.

14. The system (100) according to claim 12, wherein, The digital-to-analog converter (170) flips between a first predefined reference voltage for digital 0 input and a second predefined reference voltage for digital 1 input, wherein the first predefined reference voltage and the predefined bias voltage are selected such that the flipping of the predefined bias voltage generates a voltage in the left portion of the secondary region and a voltage in the same left portion of the secondary region, and wherein the second predefined reference voltage and the predefined bias voltage are selected such that the flipping of the predefined bias voltage generates a voltage in the right portion of the secondary region of the transistor circuit and a voltage in the same right portion of the secondary region.

15. The system (100) according to claim 12, wherein, The quantizer (160) is a predefined number of N... q A multi-bit quantizer, wherein the digital-to-analog converter (170) has N bits. q Bit.

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