Method, system, terminal and medium for adjusting and matching input frame rate and output frame rate of display system

Abstract

The input frame rate and output frame rate adjustment and matching method, system, terminal and medium of the display system provided by the present application include: obtaining the input frame rate of the display system, using a line synchronization signal counter to count the line synchronization signal corresponding to the input frame rate in real time to obtain the number of cycles of continuous appearance of the line synchronization signal corresponding to the input frame rate; detecting the output frame rate of the display system, and when the field synchronization signal corresponding to the output frame rate appears, comparing the number of cycles of continuous appearance of the line synchronization signal corresponding to the input frame rate with a preset value, so as to adjust the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result, so that the output frame rate of the display system is consistent with the input frame rate. The present application adjusts the output frame rate of the display system to be consistent with the input frame rate, so that the display delay does not exceed the delay that the small buffer can support, and the display content can be displayed correctly.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method, system, terminal and medium for adjusting and matching input frame rate and output frame rate of a display system. Background Art

[0002] At present, the input frame rate of the electronic rearview mirror cannot be fully controlled because the camera signal is input from outside the system; its input frame rate drifts with the drift of the external system clock. The display system is determined by the crystal oscillator of the system, so its output frame rate is inconsistent with the input frame rate of the camera. The usual solution is to use a large buffer. When the buffer size is large enough to accommodate the entire frame content as an exchange medium, you can wait for a complete frame of signal to be received before sending it for display, so there will be no sense of fragmentation of the displayed content. However, such a system requires at least a buffer of two frames, and such a buffer is generally very large and can only be placed in the memory space outside the chip, resulting in a large display delay (at least a delay of one frame of signal), a large occupation of the system bandwidth, increased power consumption, and low memory usage efficiency.

[0003] At present, the patent "A display device with further improved variable refresh rate function" with publication number US11798508B2 in the prior art involves display frame rate adjustment, but the problem it needs to solve is to match the backlight, display frame rate and image source, reduce flicker and enhance contrast; the patent "System and technology for synchronizing the frame rate of direct content from the camera and the refresh rate of the display" with publication number US2023 / 0360227A1 also involves frame rate adjustment, but the problem it needs to solve is that in the augmented reality system, the low-speed camera data is interpolated to match the high-speed display frame rate; the patent "Frame rate switching method, device and storage medium" with publication number CN114461051A mainly reduces power consumption from the perspective of low power consumption by reducing the display frame rate. Because the display frame rate is reduced, the frequency of the display data generation process can also be reduced accordingly. However, the use of a small buffer to reduce the delay of the electronic rearview mirror has not been solved, so it is necessary to solve the problem of inconsistency between the output frame rate and the input frame rate of the display system. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a method, system, terminal and medium for adjusting and matching the input frame rate and output frame rate of a display system, so as to solve the technical problem of inconsistency between the output frame rate and the input frame rate of the display system in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a method for adjusting and matching the input frame rate and output frame rate of a display system, including: obtaining the input frame rate of the display system, using a line synchronization signal counter to count the line synchronization signal corresponding to the input frame rate in real time to obtain a numerical value of the number of periods in which the line synchronization signal corresponding to the input frame rate appears continuously; detecting the output frame rate of the display system, and when a field synchronization signal corresponding to the output frame rate appears, comparing the numerical value of the number of periods in which the line synchronization signal corresponding to the input frame rate appears continuously with a preset value, so as to adjust the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result, so that the output frame rate of the display system is consistent with the input frame rate.

[0006] In some embodiments of the first aspect of the present application, a line synchronization signal counter is used to count the line synchronization signal corresponding to the input frame rate in real time to obtain a period value of the continuous occurrence of the line synchronization signal corresponding to the input frame rate. The process includes: if the field synchronization signal corresponding to the input frame rate of the display system appears, the period value is cleared to zero; if the line synchronization signal corresponding to the input frame rate of the display system appears, the period value is increased by one.

[0007] In some embodiments of the first aspect of the present application, the process of comparing the number of consecutive cycles of the line synchronization signal corresponding to the input frame rate with a preset value to adjust the cycle length of the field synchronization signal corresponding to the output frame rate according to the comparison result includes: if the number of cycles is less than the preset value, increasing the cycle length of the field synchronization signal corresponding to the output frame rate; if the number of cycles is greater than the preset value, reducing the cycle length of the field synchronization signal corresponding to the output frame rate; if the number of cycles is equal to the preset value, there is no need to adjust the cycle length of the field synchronization signal corresponding to the output frame rate.

[0008] In some embodiments of the first aspect of the present application, the method for adjusting the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result includes: using a control algorithm based on the comparison result to obtain an adjustment value of the period length of the field synchronization signal corresponding to the output frame rate; adjusting the period length of the field synchronization signal corresponding to the output frame rate according to the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate.

[0009] In some embodiments of the first aspect of the present application, the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate includes: a combination of any one or more of a front shoulder adjustment value, a rear shoulder adjustment value and a pulse width adjustment value of the field synchronization signal corresponding to the output frame rate.

[0010] In some embodiments of the first aspect of the present application, the control algorithm includes: any one or more combinations of a PID algorithm, an adaptive control algorithm, a fuzzy control algorithm, and a neural network control algorithm.

[0011] In some embodiments of the first aspect of the present application, the process of obtaining the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate by using a control algorithm based on the comparison result includes: obtaining the difference between the period value and a preset value based on the comparison result, and obtaining deviation data based on the difference combined with proportional calculation, integral calculation, and differential calculation; and allocating the front shoulder adjustment range, rear shoulder adjustment range, and pulse width adjustment range of the field synchronization signal corresponding to the output frame rate based on the deviation data to obtain the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate.

[0012] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an input frame rate and output frame rate adjustment and matching system of a display system, including: a real-time counting module, used to obtain the input frame rate of the display system, and use a line synchronization signal counter to count the line synchronization signal corresponding to the input frame rate in real time to obtain the number of cycles of continuous appearance of the line synchronization signal corresponding to the input frame rate; a detection and adjustment module, used to detect the output frame rate of the display system, when the field synchronization signal corresponding to the output frame rate appears, compare the number of cycles of continuous appearance of the line synchronization signal corresponding to the input frame rate with a preset value, so as to adjust the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result, so that the output frame rate of the display system is consistent with the input frame rate.

[0013] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides an electronic terminal, including: a processor and a memory; the memory is used to store computer programs, and the processor is used to execute the computer programs stored in the memory, so that the terminal executes the input frame rate and output frame rate adjustment and matching method of the display system.

[0014] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a method for adjusting and matching the input frame rate and output frame rate of the display system.

[0015] As described above, the input frame rate and output frame rate adjustment and matching method, system, terminal and medium of the display system of the present application have the following beneficial effects: by adjusting the period length of the field synchronization signal corresponding to the output frame rate, the output frame rate of the display system is adjusted to be consistent with the input frame rate collected by the system camera, and the display delay can be made not to exceed the delay that the small buffer can support, and the display content can be displayed correctly. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Shown is a flow chart of a method for adjusting and matching the input frame rate and output frame rate of a display system in one embodiment of the present application.

[0017] Figure 2 Shown is a working timing diagram of a display system in one embodiment of the present application.

[0018] Figure 3 Shown is a schematic diagram of a VSYNC detection and adjustment circuit design corresponding to an output frame rate in an embodiment of the present application.

[0019] Figure 4 Shown is a diagram of a VSYNC detection and adjustment circuit implementation corresponding to the output frame rate in one embodiment of the present application.

[0020] Figure 5 Shown is a circuit diagram for implementing a PID algorithm in one embodiment of the present application.

[0021] Figure 6 Shown is a graph of input frame rate and output frame rate tracking results of a display system in one embodiment of the present application.

[0022] Figure 7 Shown is a structural schematic diagram of an input frame rate and output frame rate adjustment and matching system of a display system in one embodiment of the present application.

[0023] Figure 8 Shown is a schematic diagram of the structure of an electronic terminal in one embodiment of the present application. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0025] It should be noted that in the following description, with reference to the accompanying drawings, several embodiments of the present application are described in the accompanying drawings. It should be understood that other embodiments may also be used, and mechanical composition, structure, electrical and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present application is limited only by the claims of the published patents. The terms used here are only for describing specific embodiments and are not intended to limit the present application. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0026] In this application, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix", "hold" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0027] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the technical solution in the embodiments of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0029] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0030] <1> Frame Rate: Frame rate, also known as refresh rate, is the frequency (rate) at which bitmap images in units of frames appear continuously on the display. It indicates how many times the screen image is redrawn per second, that is, how many times the screen is refreshed per second. It is measured in Hz (Hertz). A high refresh rate can achieve a smoother and more realistic display effect.

[0031] <2> VSYNC signal (Vertical synchronization): It comes from the field synchronization signal of traditional cathode ray tube TV. Whenever a field synchronization signal comes, the focus of the cathode ray tube will return to the upper left corner of the screen, and then display a picture through progressive scanning. VSYNC signal also has a significant impact on the frame display of Android applications. This article will analyze the generation process of VSYNC signal from the code. Field synchronization signal refers to the signal that determines the start of a frame.

[0032] <3> HSYNC (Horizontal synchronization): refers to the signal that determines the start of a line. When this signal is valid, it means that a new line of data begins to be displayed.

[0033] <4> FP (front porch): mainly refers to the signal part without effective display content before the effective signal at the start of the frame. Generally, one line of scanning time is used as a unit.

[0034] <5> BP (back porch) mainly refers to the signal part without effective display content after the effective signal at the start of the frame. Generally, one line of scanning time is used as a unit.

[0035] <6> PID algorithm: PID algorithm (Proportional-Integral-Derivative Algorithm) is a classic control algorithm widely used in the field of industrial automation. It is based on the control of the proportion, integration and differentiation of the system error to achieve precise dynamic control. PID includes three aspects of control, namely proportional control (P), integral control (I) and derivative control (D). Proportional, integral and derivative control work together to eliminate deviations quickly, accurately and smoothly to achieve good control effects.

[0036] <7> Adaptive control algorithm: Adaptive control is a closed-loop control method that automatically adjusts control parameters according to the dynamic characteristics of the system. It detects the system status and performance indicators in real time and adaptively adjusts the controller parameters to achieve the optimal control effect. The advantage of adaptive control is that it can adapt to changes in system parameters and the influence of external interference, and has good robustness and control performance.

[0037] <8> Fuzzy control algorithm: Fuzzy control is a closed-loop control method based on fuzzy logic. It maps fuzzy input to fuzzy output by establishing a fuzzy rule base, and obtains the actual control input by defuzzification. The advantage of fuzzy control is that it can process imprecise and fuzzy information and is suitable for complex and nonlinear system control. Fuzzy control is also adaptive and robust, and can maintain good control performance under the condition of system parameter changes and external interference.

[0038] <9> Neural network control algorithm: Neural network control algorithm is a control method based on artificial neural network, which realizes the control of control system by simulating the neural network structure and operation mode of human brain. Neural network control algorithm is mainly divided into two categories: forward neural network and reverse neural network. Neural network control algorithm performs well in dealing with nonlinear, multivariable and high uncertainty situations, and is particularly suitable for complex industrial process control.

[0039] The embodiment of the present invention provides a method, system, terminal and medium for adjusting and matching the input frame rate and output frame rate of a display system. As for the implementation of the method for adjusting and matching the input frame rate and output frame rate of a display system, the embodiment of the present invention will describe an exemplary implementation scenario of adjusting and matching the input frame rate and output frame rate of a display system.

[0040] like Figure 1 FIG. 1 is a flow chart showing a method for adjusting and matching the input frame rate and the output frame rate of a display system according to an embodiment of the present invention, which mainly includes the following steps:

[0041] Step S11: acquiring the input frame rate of the display system, and using a line synchronization signal counter to count the line synchronization signal corresponding to the input frame rate in real time to obtain a value of the number of cycles during which the line synchronization signal corresponding to the input frame rate continuously appears.

[0042] It should be explained that when the display system refreshes the image, a field synchronization signal VSYNC and a line synchronization signal HSYNC are generated at the beginning of each frame of the image. The field synchronization signal VSYNC indicates the start of scanning a frame. A frame is an image displayed by the display system. The line synchronization signal HSYNC indicates the start of scanning a line. The cycle length of a field synchronization signal VSYNC includes multiple line synchronization signals HSYNC.

[0043] Combination Figure 2 The field synchronization signal VSYNC and the line synchronization signal HSYNC and related parameters are explained. One cycle of the field synchronization signal VSYNC represents the time of one frame of image, the line synchronization signal HSYNC represents the total number of lines of one frame of image, and one cycle of the data enable signal DE represents the number of valid lines of one frame of image. Among them, Tv represents the length of one cycle of the field synchronization signal VSYNC, which is the interval between the falling edge of the field synchronization signal VSYNC and the falling edge of the next field synchronization signal VSYNC; Tvw represents the pulse width of the field synchronization signal VSYNC; Tvbp represents the back shoulder of the field synchronization signal VSYNC; and Tvfp represents the front shoulder of the field synchronization signal VSYNC.

[0044] Furthermore, the field synchronization signal VSYNC is used to let the electron gun controller know that a new frame of image is about to start, and the line synchronization signal HSYNC is used to let the electron gun controller know that a new row of pixels is about to start. The data enable signal DE is valid color data in the data enable area, and those not in the enable range are displayed in black.

[0045] It should be noted that the display system includes but is not limited to mobile phones, tablet computers, laptop computers, PDAs, portable media players (PMPs), navigation devices, wearable devices, smart bracelets, handheld game consoles, pedometers, smart home appliances, digital TVs, electronic rearview mirrors, and desktop computers.

[0046] After receiving the trigger signal, the line synchronization signal counter records in real time the number of cycles in which the line synchronization signal HSYNC appears continuously, and uses the line synchronization signal counter to count in real time the line synchronization signal corresponding to the input frame rate to obtain the number of cycles in which the line synchronization signal corresponding to the input frame rate appears continuously. The process includes: if the field synchronization signal corresponding to the input frame rate of the display system appears, the number of cycles is cleared to zero; if the line synchronization signal corresponding to the input frame rate of the display system appears, the number of cycles is increased by one.

[0047] It should be noted that the input frame rate is the frame rate of the image collected by the camera and sent to the display system. Figure 3 For example, the field synchronization signal VSYNC corresponding to the input frame rate of the display system is CAM_VSYNC, the line synchronization signal HSYNC corresponding to the input frame rate is CAM_HSYNC, and CAM_HCNT is the line synchronization signal counter of the camera.

[0048] It should be explained that when the field synchronization signal CAM_VSYNC corresponding to the input frame rate of the display system appears, the value of the CAM_HCNT counter is cleared to 0, and then the cycle counting is performed according to the line synchronization signal CAM_HSYNC corresponding to the input frame rate. When the line synchronization signal CAM_HSYNC appears, the counter CAM_HCNT is increased by 1.

[0049] Step S12: Detect the output frame rate of the display system. When a field synchronization signal corresponding to the output frame rate appears, compare the number of consecutive periods of the line synchronization signal corresponding to the input frame rate with a preset value, and adjust the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result, so that the output frame rate of the display system is consistent with the input frame rate.

[0050] It should be noted that Figure 3 For example, the field synchronization signal VSYNC corresponding to the output frame rate is LCD_VSYNC, and the output frame rate is detected and adjusted, mainly adjusting the period length of the field synchronization signal LCD_VSYNC corresponding to the output frame rate. By adjusting the period length of LCD_VSYNC, the field synchronization signal LCD_VSYNC corresponding to the output frame rate can be made consistent with the field synchronization signal CAM_VSYNC corresponding to the input frame rate, so that the output frame rate of the display system is consistent with the input frame rate.

[0051] In some examples, the process of comparing the number of consecutive cycles of the line synchronization signal corresponding to the input frame rate with a preset value to adjust the cycle length of the field synchronization signal corresponding to the output frame rate based on the comparison result includes: if the number of cycles is less than the preset value, increasing the cycle length of the field synchronization signal corresponding to the output frame rate; if the number of cycles is greater than the preset value, reducing the cycle length of the field synchronization signal corresponding to the output frame rate; if the number of cycles is equal to the preset value, there is no need to adjust the cycle length of the field synchronization signal corresponding to the output frame rate.

[0052] It should be noted that when the field synchronization signal LCD_VSYNC corresponding to the output frame rate appears, the real-time cycle number of the line synchronization signal CAM_HSYNC corresponding to the input frame rate recorded by the line synchronization signal counter CAM_HCNT is obtained. According to the real-time cycle number recorded by the line synchronization signal counter CAM_HCNT, the cycle length of the field synchronization signal CAM_VSYNC can be obtained, and the cycle length of the field synchronization signal CAM_VSYNC can also be monitored.

[0053] Then compare the current real-time cycle count value with a preset value. The preset value is the cycle count value of the horizontal synchronization signal CAM_HSYNC corresponding to the input frame rate within the cycle length of a vertical synchronization signal CAM_VSYNC corresponding to the input frame rate, which is the Q value in the figure. The parameter Q is the value of CAM_HCNT when it is desired to output the vertical synchronization signal LCD_VSYNC of the display system (such as an LCD). Comparing the real-time cycle count value with the preset value is actually comparing the cycle length of the vertical synchronization signal LCD_VSYNC corresponding to the output frame rate with the cycle length of the vertical synchronization signal LCD_VSYNC corresponding to the input frame rate.

[0054] It can be understood that different frame rates respectively correspond to different cycle lengths of the vertical synchronization signal VSYNC. Therefore, adjusting the frame rate can be achieved by adjusting the cycle length of the vertical synchronization signal VSYNC corresponding to the frame rate. In this embodiment, change the cycle length of the vertical synchronization signal LCD_VSYNC corresponding to the output frame rate to be consistent with the cycle length of the vertical synchronization signal LCD_VSYNC corresponding to the input frame rate, ultimately achieving the effect of matching the output frame rate with the input frame rate.

[0055] Take Figure 3 as an example, it is the schematic diagram of the detection and adjustment circuit for the vertical synchronization signal LCD_VSYNC corresponding to the output frame rate. At this time, the vertical synchronization signals CAM_VSYNC, LCD_VSYNC, and the horizontal synchronization signal CAM_HSYNC are all active high. Each time LCD_VSYNC appears, check the current value of CAM_HCNT, and compare the current value of CAM_HCNT with the preset value Q. The specific comparison results include the following various situations:

[0056] Situation 1: Taking LCD_VSYNC_B1 as an example, if the current CAM_HCNT < Q at this time, it means that the current display frame rate is too fast, and it is necessary to increase the cycle length of the vertical synchronization signal LCD_VSYNC_B1 corresponding to the output frame rate;

[0057] Situation 2: Taking LCD_VSYNC_A1 as an example, if the current CAM_HCNT > Q at this time, it means that the current display frame rate is too slow, and it is necessary to decrease the cycle length of the vertical synchronization signal LCD_VSYNC_A1 corresponding to the output frame rate;

[0058] Situation 3: Taking LCD_VSYNC_GOOD as an example, if the current CAM_HCNT == Q at this time, it means that the current display frame rate is almost appropriate, that is, the output frame rate and the input frame rate are consistent, and there is no need to adjust the cycle length of the vertical synchronization signal LCD_VSYNC_GOOD corresponding to the output frame rate.

[0059] In one embodiment of the present application, the method for adjusting the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result includes: obtaining an adjustment value of the period length of the field synchronization signal corresponding to the output frame rate using a control algorithm based on the comparison result; and adjusting the period length of the field synchronization signal corresponding to the output frame rate according to the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate.

[0060] In some examples, the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate includes: the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate includes: a combination of any one or more of a front shoulder adjustment value, a rear shoulder adjustment value, and a pulse width adjustment value of the field synchronization signal corresponding to the output frame rate.

[0061] Specifically, combined Figure 4 Description, for a specific embodiment of adjusting the period length of the field synchronization signal corresponding to the output frame rate, the specific circuit implementation is as follows:

[0062] Step 1: input the field synchronization signal CAM_VSYNC and the line synchronization signal CAM_HSYNC corresponding to the frame rate, and input them into the CAM_HCNT counter to count the number of real-time cycles, wherein the Q value is a preset value;

[0063] Step 2: LATCH is activated by the field synchronization signal LCD_VSYNC corresponding to the input and output frame rate, that is, when LCD_VSYNC appears, the real-time cycle value of CAM_HCNT is latched and recorded as Q', and then the cycle value Q' is compared with the preset value Q to generate data Diff;

[0064] Step 3: ADJUST_MOD allocates the front porch adjustment range, the back porch adjustment range and the pulse width adjustment range of the field synchronization signal LCD_VSYNC corresponding to the output frame rate according to the input Diff to obtain Cfg_FP (front porch adjustment value), Cfg_BP (back porch adjustment value) and Cfg_PW (pulse width adjustment value);

[0065] Step 4: In LCD_RASTER, the main thing is to match the dot matrix pixels (PIXELS_IN (RGB)) with the timing of VSYNC, HSYNC, and DE, and output LCD_R / G / B, LCD_DE. At the same time, new LCD_VSYNC and LCD_HSYNC are generated according to Cfg_FP (front shoulder adjustment value), Cfg_BP (back shoulder adjustment value), and Cfg_PW (pulse width adjustment value).

[0066] It should be explained that the Diff generated in step 2 includes three situations, as follows:

[0067] Case 1: If Q'>Q (i.e., Diff<0), the time of field blanking needs to be reduced.

[0068] Case 2: If Q'<Q (i.e., Diff>0), the time of field blanking needs to be increased.

[0069] Case 3: If Q'=Q (i.e., Diff=0), the time of field blanking should not be changed.

[0070] Among them, the field blanking time refers to the cycle length of LCD_VSYNC that needs to be adjusted. Adjusting the cycle length of LCD_VSYNC is essentially adjusting the time length of the field synchronization signal LCD_VSYNC corresponding to the output frame rate. Specifically, the field blanking time is adjusted through the obtained Cfg_FP (front porch adjustment value), Cfg_BP (back porch adjustment value), and Cfg_PW (pulse width adjustment value).

[0071] In an embodiment of the present application, the control algorithm includes any one or a combination of multiple of the following: PID algorithm, adaptive control algorithm, fuzzy control algorithm, neural network control algorithm. In this embodiment, the PID algorithm is preferably used. The PID algorithm can quickly, accurately, and stably eliminate the deviation, achieving a good control effect, and the calculation is simpler and the efficiency is higher.

[0072] In an embodiment of the present application, the process of obtaining the adjustment value of the cycle length of the field synchronization signal corresponding to the output frame rate by using the control algorithm based on the comparison result includes: obtaining the difference between the cycle value and the preset value based on the comparison result, and obtaining the deviation data according to the difference by combining proportional calculation, integral calculation, and differential calculation; distributing based on the deviation data according to the front porch adjustment range, back porch adjustment range, and pulse width adjustment range of the field synchronization signal corresponding to the output frame rate to obtain the adjustment value of the cycle length of the field synchronization signal corresponding to the output frame rate.

[0073] It should be explained that taking the PID algorithm as an example for the control algorithm used, in Figure 4 ADJUST_MOD, according to the input Diff, it is distributed based on the front porch adjustment range, back porch adjustment range, and pulse width adjustment range of the field synchronization signal LCD_VSYNC corresponding to the output frame rate to obtain the specific implementation circuit of Cfg_FP (front porch adjustment value), Cfg_BP (back porch adjustment value), and Cfg_PW (pulse width adjustment value) as Figure 5 shown:

[0074] The first step: The difference obtained by comparing the cycle value Q' with the preset value Q is the Diff value. The Diff value is calculated through the I branch, P branch, and D branch and then added together to generate the Modif signal;

[0075] Step 2: Modif signal and historical offset data are accumulated to generate new offset data;

[0076] Step 3: In ReMap, the new offset data is allocated according to the front shoulder adjustment range (FP_RANGE), the back shoulder adjustment range (BP_RANGE), and the VSYNC pulse width adjustment range (PW_RANGE) to obtain the values ​​of Cfg_FP, Cfg_BP, and Cfg_PW.

[0077] It should be noted that the adjustment range of the relevant parameters of the field synchronization signal LCD_VSYNC corresponding to the output frame rate is limited, and depending on the frame rate, the corresponding adjustment range of the field synchronization signal LCD_VSYNC is also different, as shown in Table 1 or Table 2 below, which is the adjustment range of the relevant parameters of the field synchronization signal VSYNC.

[0078] Table 1 Adjustment range of field synchronization signal related parameters

[0079]

[0080] Table 2 Adjustment range of field synchronization signal related parameters

[0081]

[0082] The adjustment range of the field synchronization signal LCD_VSYNC corresponding to different frame rates is also different, and the range to be adjusted when the period length of the field synchronization signal LCD_VSYNC corresponding to the output frame rate is adjusted to be consistent with the input frame rate is also different, which is specifically manifested in the different sizes of the Diff value. Therefore, the obtained Cfg_FP (front shoulder adjustment value), Cfg_BP (back shoulder adjustment value) and Cfg_PW (pulse width adjustment value) may have the following situations according to their respective adjustment ranges:

[0083] Case 1: Only one of the front shoulder, back shoulder and pulse width of the field synchronization signal LCD_VSYNC needs to be adjusted to adjust the period length of the field synchronization signal LCD_VSYNC. In this case, the adjustment value of the front shoulder is preferably used;

[0084] Case 2: The front porch, back porch and pulse width of the field synchronization signal LCD_VSYNC are limited by their respective corresponding adjustment ranges, but the Diff value is large. At this time, it is not possible to adjust according to only one of the adjustment values. It is necessary to obtain the three adjustment values ​​of Cfg_FP, Cfg_BP and Cfg_PW to adjust the period length of the field synchronization signal LCD_VSYNC together;

[0085] Case 3: The leading shoulder, trailing shoulder and pulse width of the field synchronization signal LCD_VSYNC are limited by their respective corresponding adjustment ranges. It may be possible that only one of Cfg_FP and Cfg_BP, or Cfg_FP and Cfg_PW, or Cfg_BP and Cfg_PW can be generated. The cycle length of the field synchronization signal LCD_VSYNC is adjusted according to the actual adjustment value obtained.

[0086] In order to correctly track the frame rate of the input system, a special circuit logic is used to track the camera input signal VSYNC. The tracking goal is to adjust the VSYNC signal corresponding to the output frame rate of the display system LCD to a fixed line synchronization signal after the VSYNC corresponding to the input frame rate. Figure 6 As shown in FIG. 1 , it is a tracking diagram of the output frame rate and input frame rate of the display system, wherein the horizontal line is the VSYNC period corresponding to the input frame rate, and the broken line is the VSYNC period corresponding to the tracked output frame rate. It can be concluded that the length of the VSYNC period corresponding to the output frame rate is adjusted to the specific adjustment range of the length of the VSYNC period corresponding to the input frame rate.

[0087] It should be emphasized that the buffer is used as the medium of the video transmission process in this application to keep the input frame rate and the output frame rate consistent, and to reduce the delay of the display system displaying the image, and to avoid problems such as frame drops in the display content. In order to solve the problems of large display delay, large memory, and high power consumption when using a large buffer, a small buffer that is much smaller than the size of the entire frame content is used. The small buffer can be placed in the SRAM (Static Random-Access Memory) memory with fast access and low power consumption inside the chip. Among them, the large buffer can include at least one frame of content, while the small buffer can only include much less than one frame of content. When using a small buffer, the output frame rate of the display system must be adjusted to be consistent with the input frame rate collected by the system camera, and the display delay cannot exceed the delay that the size of the small buffer can support, otherwise it cannot be displayed correctly.

[0088] Therefore, in this embodiment, a special circuit logic is used to track and detect the field synchronization signal and the line synchronization signal corresponding to the input frame rate and the output frame rate respectively, and the period length of the field synchronization signal corresponding to the output frame rate is adjusted so that the output frame rate of the display system is consistent with the input frame rate. This can achieve the output frame rate of the display system being adjusted to be consistent with the input frame rate captured by the system camera, and the display delay can be made not to exceed the delay that the small buffer can support, and the display content can be displayed correctly.

[0089] like Figure 7FIG. 1 is a schematic diagram showing a structure of an input frame rate and output frame rate adjustment and matching system 700 of a display system in an embodiment of the present invention. In this embodiment, the input frame rate and output frame rate adjustment and matching system 700 of the display system includes:

[0090] A real-time counting module 701 is used to obtain an input frame rate of a display system, and use a line synchronization signal counter to count the line synchronization signal corresponding to the input frame rate in real time to obtain a value of the number of cycles in which the line synchronization signal corresponding to the input frame rate appears continuously;

[0091] The detection and adjustment module 702 is used to detect the output frame rate of the display system. When the field synchronization signal corresponding to the output frame rate appears, the value of the number of consecutive periods of the line synchronization signal corresponding to the input frame rate is compared with a preset value, so as to adjust the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result, so that the output frame rate of the display system is consistent with the input frame rate.

[0092] It should be understood that the division of the various modules or units of the above system is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or physically separated. Moreover, these modules or units can be implemented in the form of software calling through processing elements; they can also be implemented in the form of hardware; some modules or units can be implemented in the form of software calling through processing elements, and some modules or units can be implemented in the form of hardware.

[0093] For example, the above modules or units may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processors that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0094] Since the implementation of the input frame rate and output frame rate adjustment and matching system of the display system in this embodiment is similar to the implementation of the input frame rate and output frame rate adjustment and matching method of the display system provided above, it will not be described in detail.

[0095] like Figure 8 As shown, a schematic diagram of the structure of an electronic terminal in an embodiment of the present application is shown. The electronic terminal 80 provided in this example includes: a memory 81 and a processor 82. The memory 81 is used to store computer programs; the processor 82 runs the computer program to implement the input frame rate and output frame rate adjustment and matching method of the display system.

[0096] Optionally, the number of the memories 81 may be one or more, and the number of the processors 82 may be one or more.

[0097] Optionally, the processor 82 in the electronic terminal 80 may be configured as follows: Figure 1 The steps described above load one or more instructions corresponding to the process of the application program into the memory 81, and the processor 82 runs the application program stored in the first memory 81, thereby realizing various functions in the input frame rate and output frame rate adjustment and matching method of the display system.

[0098] Optionally, the memory 81 may include but is not limited to high-speed random access memory and non-volatile memory. For example, one or more disk storage devices, flash memory devices or other non-volatile solid-state storage devices; the processor 82 may include but is not limited to a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0099] Optionally, the processor 82 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0100] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the input frame rate and output frame rate adjustment and matching method of the display system is implemented.

[0101] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0102] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0103] In summary, the input frame rate and output frame rate adjustment and matching method, system, terminal and medium provided by the present application include: obtaining the input frame rate of the display system, using a line synchronization signal counter to count the line synchronization signal corresponding to the input frame rate in real time to obtain the number of cycles of the line synchronization signal corresponding to the input frame rate; detecting the output frame rate of the display system, when the field synchronization signal corresponding to the output frame rate appears, comparing the number of cycles of the line synchronization signal corresponding to the input frame rate with the preset value, so as to adjust the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result, so that the output frame rate of the display system is consistent with the input frame rate. The present application adjusts the period length of the field synchronization signal corresponding to the output frame rate so that the output frame rate of the display system is consistent with the input frame rate, so that the output frame rate of the display system can be adjusted to be consistent with the input frame rate collected by the system camera, and the display delay can be made not to exceed the delay that the small buffer can support, and the display content can be displayed correctly. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0104] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A method for adjusting and matching the input frame rate and output frame rate of a display system, characterized in that: include: Acquire the input frame rate of the display system, and use a line synchronization signal counter to count the line synchronization signal corresponding to the input frame rate in real time to obtain a value of the number of cycles of continuous appearance of the line synchronization signal corresponding to the input frame rate; including: if the field synchronization signal corresponding to the input frame rate of the display system appears, the value of the cycle is cleared to zero; if the line synchronization signal corresponding to the input frame rate of the display system appears, the value of the cycle is increased by one; The output frame rate of the display system is detected, and when a field synchronization signal corresponding to the output frame rate appears, the value of the number of cycles during which the horizontal synchronization signal corresponding to the input frame rate appears continuously is compared with a preset value, so as to adjust the cycle length of the field synchronization signal corresponding to the output frame rate according to the comparison result, so that the output frame rate of the display system is consistent with the input frame rate; Wherein, if the value of the number of cycles is less than the preset value, the cycle length of the field synchronization signal corresponding to the output frame rate is increased; if the value of the number of cycles is greater than the preset value, the cycle length of the field synchronization signal corresponding to the output frame rate is reduced; if the value of the number of cycles is equal to the preset value, there is no need to adjust the cycle length of the field synchronization signal corresponding to the output frame rate; Based on the comparison result, a control algorithm is used to obtain an adjustment value of the period length of the field synchronization signal corresponding to the output frame rate; and the period length of the field synchronization signal corresponding to the output frame rate is adjusted according to the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate.

2. The method for adjusting and matching the input frame rate and the output frame rate of a display system according to claim 1, characterized in that: The adjustment value of the period length of the field synchronization signal corresponding to the output frame rate includes: any one or more combinations of a front porch adjustment value, a rear porch adjustment value and a pulse width adjustment value of the field synchronization signal corresponding to the output frame rate.

3. The method for adjusting and matching the input frame rate and output frame rate of a display system according to claim 1, characterized in that: The control algorithm includes: any one or more combinations of a PID algorithm, an adaptive control algorithm, a fuzzy control algorithm, and a neural network control algorithm.

4. The method for adjusting and matching the input frame rate and output frame rate of a display system according to claim 1, characterized in that: The process of obtaining the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate by using a control algorithm based on the comparison result includes: Based on the comparison result, a difference between the number of period values ​​and a preset value is obtained, and deviation data is obtained according to the difference in combination with proportional calculation, integral calculation, and differential calculation; Based on the deviation data, the front porch adjustment range, the rear porch adjustment range and the pulse width adjustment range of the field synchronization signal corresponding to the output frame rate are allocated to obtain the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate.

5. A display system input frame rate and output frame rate adjustment matching system, characterized in that: include: A real-time counting module is used to obtain an input frame rate of a display system, and use a line synchronization signal counter to count the line synchronization signal corresponding to the input frame rate in real time to obtain a value of the number of cycles of continuous appearance of the line synchronization signal corresponding to the input frame rate; including: if a field synchronization signal corresponding to the input frame rate of the display system appears, the value of the cycle is cleared to zero; if a line synchronization signal corresponding to the input frame rate of the display system appears, the value of the cycle is increased by one; a detection and adjustment module, configured to detect the output frame rate of the display system, and when a field synchronization signal corresponding to the output frame rate appears, compare the value of the number of consecutive periods of the line synchronization signal corresponding to the input frame rate with a preset value, so as to adjust the period length of the field synchronization signal corresponding to the output frame rate according to the comparison result, so as to keep the output frame rate of the display system consistent with the input frame rate; Wherein, if the value of the number of cycles is less than the preset value, the cycle length of the field synchronization signal corresponding to the output frame rate is increased; if the value of the number of cycles is greater than the preset value, the cycle length of the field synchronization signal corresponding to the output frame rate is reduced; if the value of the number of cycles is equal to the preset value, there is no need to adjust the cycle length of the field synchronization signal corresponding to the output frame rate; Based on the comparison result, a control algorithm is used to obtain an adjustment value of the period length of the field synchronization signal corresponding to the output frame rate; and the period length of the field synchronization signal corresponding to the output frame rate is adjusted according to the adjustment value of the period length of the field synchronization signal corresponding to the output frame rate.

6. An electronic terminal, characterized in that: include: Processor and memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory, so that the terminal executes the input frame rate and output frame rate adjustment and matching method of the display system according to any one of claims 1 to 4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the input frame rate and output frame rate adjustment and matching method of the display system according to any one of claims 1 to 4 is implemented.

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