Method for forming semiconductor device and semiconductor device

Abstract

The present invention relates to a method for forming a semiconductor device and a semiconductor device. In the method for forming the semiconductor device, a stacked chip unit is first formed, and then at least one of the stacked chip units is bonded to the surface of a packaging wafer through chip-wafer bonding, and a first filling and covering layer is formed on the surface of the packaging wafer and the stacked chip units thereon to perform wafer reshaping, obtaining a first reshaped wafer. This forming method stacks a stacked chip unit with chip-level dimensions and a packaging wafer with wafer-level dimensions, enabling high-density chip stacking. Moreover, the stacked chip unit can be continuously bonded to the first reshaped wafer through chip-wafer bonding, which can further improve the chip stacking density, has high process efficiency, helps reduce process costs and shorten the manufacturing cycle. The semiconductor device can be fabricated by using the above method for forming a semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device and a semiconductor device. Background Art

[0002] With the advent of the era of information data explosion, the market demand for memory continues to grow, and the demand for applying stacking technology to achieve high storage density under the same-size device is also increasing. The stacking technology enables multiple chips to be vertically interconnected, doubling the number of transistors per unit area, greatly improving the integration level, shortening the global wiring, increasing the interconnection speed, reducing the response time, and achieving energy consumption reduction. In addition, the stacked chips can be heterogeneous and can achieve complex system functions.

[0003] In a known multi-chip stacking process, after obtaining a single chip to be stacked, microbumps are formed on one surface of each chip, and UBM (under bump metal) connection pads are formed on the other surface. The two surfaces are electrically connected through TSV vias in the chip. Then, the chips are assembled, and these chips are stacked one by one on the packaging wafer, with the surface of each chip having microbumps facing downwards, where the microbumps are connected to the UBM connection pads of the packaging wafer or the underlying chip.

[0004] However, in the above multi-chip stacking process, since it is difficult to reduce the distance (pitch size) between UBM connection pads (the conventional minimum can only reach about 40 μm), the connection density per unit chip area is limited. Moreover, in order to fabricate UBM connection pads on the surface of the chips to be stacked, each chip needs to go through the process of temporarily bonding a carrier wafer on the other surface and removing the carrier wafer before stacking, increasing the process cost and resulting in a longer manufacturing cycle.

[0005] Therefore, there is still a need to propose a better solution to achieve high-density chip stacking while improving process reliability and reducing process cost. Summary of the Invention

[0006] The present invention provides a method for forming a semiconductor device, which can achieve high-density chip stacking and contribute to improving process reliability and reducing process cost. The present invention further provides a semiconductor device.

[0007] On the one hand, the present invention provides a method for forming a semiconductor device, including:

[0008] Forming a stacked chip unit, the stacked chip unit including a plurality of chips stacked and interconnected along the thickness direction;

[0009] Providing a packaging wafer and performing chip-wafer bonding to bond at least one of the stacked chip units on the surface of the packaging wafer; and

[0010] A first filling and covering layer is formed on the surface of the encapsulated wafer and the stacked chip units on the encapsulated wafer to perform wafer reshaping, obtaining a first reshaped wafer, and the first reshaped wafer includes a layer of the stacked chip units stacked on the encapsulated wafer.

[0011] Optionally, the forming method further includes:

[0012] Repeating the processes of chip-wafer bonding and wafer reshaping on the first reshaped wafer to stack more than two layers of the stacked chip units on the encapsulated wafer.

[0013] Optionally, forming the stacked chip units includes: stacking and interconnecting a plurality of device wafers to form a stacked wafer; and cutting the stacked wafer along the thickness direction to obtain the stacked chip units.

[0014] Optionally, in the stacked wafer, each of the device wafers includes a front surface for forming electronic components and a back surface opposite to the front surface, and the front surfaces of all the device wafers face the same direction.

[0015] Optionally, the stacked wafer includes a first device wafer, a second device wafer,..., an nth device wafer stacked in sequence along the thickness direction, where n is an integer greater than or equal to 2; wherein, the first device wafer, the second device wafer,..., the nth device wafer all include an interconnecting structure formed on the front surface and a bonding structure connecting the interconnecting structures on the front surface, and the second device wafer,..., the nth device wafer further include an interconnecting structure formed on the back surface and a bonding structure connecting the interconnecting structures on the back surface; among two adjacent device wafers, the bonding structure located on the front surface of one device wafer and the bonding structure located on the back surface of the other device wafer are bonded and electrically connected.

[0016] Optionally, bonding the mth device wafer to the (m - 1)th device wafer includes:

[0017] Bonding the front surface of the mth device wafer to a carrier;

[0018] Thinning the mth device wafer from the back surface;

[0019] Forming TSV vias from the back surface of the mth device wafer;

[0020] Forming corresponding interconnecting structures and bonding structures connected to the corresponding interconnecting structures on the back surface of the mth device wafer, wherein the TSV vias connect the interconnecting structures on the front surface and the back surface of the mth device wafer;

[0021] Bond the back side of the m-th device wafer to the front side of the (m - 1)-th device wafer; and

[0022] Remove the carrier substrate, where m is greater than or equal to 2 and less than or equal to n.

[0023] Optionally, before dicing the stacked wafers, thin the first device wafer from the back side.

[0024] Optionally, when bonding the stacked chip units to the package wafer, bond the package wafer using a bonding structure formed on the front side of the n-th device wafer.

[0025] Optionally, the forming method further includes:

[0026] Form TSV vias from the back side of the first device wafer portion in the first reshaped wafer, and the TSV vias are connected to the interconnect structure on the front side of the first device wafer portion; and

[0027] Form a wafer-level size bonding structure on the back side of the first device wafer portion to connect the TSV vias, so as to stack the stacked chip units again by chip-wafer bonding on the side of the first reshaped wafer away from the package wafer.

[0028] Optionally, after the stacking of the stacked chip units to be bonded is completed and after the stacked chip units are stacked on the package wafer, the forming method further includes: forming metal pads on the side of the package wafer facing away from the stacked chip units.

[0029] On the one hand, the present invention provides a semiconductor device, and the semiconductor device includes:

[0030] A package substrate;

[0031] At least one layer of stacked chip units stacked on the package substrate, each layer of the stacked chip units includes at least one of the stacked chip units, and each stacked chip unit includes a plurality of chips stacked and interconnected in the thickness direction; and

[0032] At least one layer of filling and covering layers, respectively located around each layer of the stacked chip units.

[0033] Optionally, the semiconductor device includes at least two layers of the stacked chip units stacked on the package substrate, and adjacent two layers of the stacked chip units are connected by a bonding structure.

[0034] In the method for forming a semiconductor device provided by the present invention, a stacked chip unit is first formed. The stacked chip unit includes a plurality of chips stacked and interconnected. Then, at least one of the stacked chip units is bonded to a package wafer through chip-wafer bonding, and a first filling and covering layer is formed on the surface of the package wafer and the stacked chip units thereon to perform wafer reshaping, obtaining a first reshaped wafer. This forming method stacks a stacked chip unit with chip-level dimensions and a package wafer with wafer-level dimensions, enabling high-density chip stacking, having relatively high process reliability, and helping to reduce process costs. Moreover, the stacked chip unit can be continuously bonded to the first reshaped wafer through chip-wafer bonding, which can further increase the chip stacking density, has high process efficiency, and helps to reduce process costs and shorten the manufacturing cycle.

[0035] The semiconductor device provided by the present invention includes a package substrate and at least one layer of the stacked chip units stacked on the surface of the package substrate. A filling and covering layer is provided around each layer of the stacked chip units. The package substrate can have wafer-level dimensions or chip-level dimensions, which helps to reduce process costs and shorten the manufacturing cycle while achieving high-density multi-layer chip stacking. Description of the Drawings

[0036] Figure 1 is a schematic flow chart of the method for forming a semiconductor device according to an embodiment of the present invention.

[0037] Figure 2 is a schematic cross-sectional structure diagram of bonding a first device wafer and a second device wafer in the method for forming a semiconductor device according to an embodiment of the present invention.

[0038] Figure 3 is a schematic cross-sectional structure diagram of stacked wafers in the method for forming a semiconductor device according to an embodiment of the present invention.

[0039] Figure 4 is a schematic cross-sectional structure diagram of the stacked wafers after thinning in the method for forming a semiconductor device according to an embodiment of the present invention.

[0040] Figure 5 is a schematic cross-sectional structure diagram of transferring the stacked wafers to a dicing frame in the method for forming a semiconductor device according to an embodiment of the present invention.

[0041] Figure 6 is a schematic cross-sectional structure diagram of dicing the stacked wafers to form stacked chip units in the method for forming a semiconductor device according to an embodiment of the present invention.

[0042] Figure 7 is a schematic cross-sectional structure diagram of bonding a package wafer and a carrier in the method for forming a semiconductor device according to an embodiment of the present invention.

[0043] Figure 8 It is a schematic cross-sectional structure diagram after bonding at least one of the stacked chip units on the surface of the packaging wafer in the method for forming a semiconductor device according to an embodiment of the present invention.

[0044] Figure 9 It is a schematic cross-sectional structure diagram after forming a first filling cover layer in the method for forming a semiconductor device according to an embodiment of the present invention.

[0045] Figure 10 It is a schematic cross-sectional structure diagram after bonding at least one of the stacked chip units on the surface of the first reshaped wafer in the method for forming a semiconductor device according to an embodiment of the present invention.

[0046] Figure 11 It is a schematic cross-sectional structure diagram after forming a second filling cover layer in the method for forming a semiconductor device according to an embodiment of the present invention.

[0047] Figure 12 It is a schematic cross-sectional structure diagram after bonding a carrier plate on the top stacked chip unit in the method for forming a semiconductor device according to an embodiment of the present invention.

[0048] Figure 13 It is a schematic cross-sectional structure diagram after forming a metal pad on the side of the packaging wafer away from the stacked chip unit in the method for forming a semiconductor device according to an embodiment of the present invention.

[0049] Description of reference numerals:

[0050] 110 - First dielectric layer; 120 - First metal bonding pad; 130 - Second dielectric layer; 140 - Second metal bonding pad; 150 - Third dielectric layer; 160 - Third metal bonding pad; 200 - Packaging wafer; 300 - First filling cover layer; 400 - Second filling cover layer; 500 - Metal pad; 10, 11, 12, 13 - Carrier plate; 20, 40, 50 - TSV vias; 30 - Cutting frame. Detailed description of the invention

[0051] The following further describes in detail the method for forming a semiconductor device and the semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0052] The embodiments of the present invention include a method for forming a semiconductor device. The following further describes Figures 1 to 13 the method for forming the semiconductor device.

[0053] Refer to Figure 1, in step S1, a stacked chip unit is formed, and the stacked chip unit includes a plurality of chips stacked and interconnected. The number of chips stacked in the stacked chip unit can be specifically set according to the design of the semiconductor device and the process capabilities. In some embodiments, forming each of the stacked chip units includes: stacking and interconnecting a plurality of device wafers to form a stacked wafer; then, cutting the stacked wafer in the thickness direction to obtain the stacked chip unit.

[0054] In the stacked wafer, the device wafers may include electronic components formed by semiconductor processes. By interconnecting a plurality of stacked device wafers, the electronic components on each device wafer can be interconnected. Exemplarily, storage elements are formed on the device wafers, and the storage devices may include non-volatile memories or random memories, etc. The non-volatile memories may include NOR flash memories, NAND flash memories, ferroelectric memories, or phase change memories, etc. Other types of active or passive devices may also be formed on the device wafers. As Figure 2 shown in the first device wafer W1 and the second device wafer W2 in, each of the device wafers in the stacked wafer may include a front side for forming electronic components and a back side opposite to the front side. When forming the stacked wafer, as needed, the front side of one device wafer may be bonded to the front side of another device wafer, and / or the front side of one device wafer may be bonded to the back side of another device wafer. In some embodiments, after forming the stacked wafer, the front sides of all the device wafers face the same direction.

[0055] Specifically, the stacked wafer includes a first device wafer W1, a second device wafer W2,..., an nth device wafer Wn stacked in sequence along the thickness direction of each device wafer, where n is an integer greater than or equal to 2. When forming the stacked wafer, for example, first bond the back side of the second device wafer W2 to the front side of the first device wafer W1, and then bond the front side of the second device wafer W2 to the back side of the third device wafer W3, and so on, until the front side of the (n - 1)th device wafer Wn - 1 is bonded to the back side of the nth device wafer Wn. Optionally, n is less than or equal to 12.

[0056] Referring to Figure 2 , the first device wafer W1, for example, has an interconnect structure FC1 formed on its front side, and the second device wafer W2 has an interconnect structure FC2 formed on its front side. The interconnect structures FC1 and FC2 may include patterned metal layers (such as redistribution layers, RDLs) isolated by a dielectric material and conductive plugs connecting adjacent metal layers. The metal layers and conductive plugs can provide connection functions between the doped regions, circuits, and input / outputs in the corresponding device wafers. The specific connection settings of the interconnect structures FC1 and FC2 may be different. For clarity, Figure 1 andFigure 2 Only some metal layers in the interconnect structures FC1 and FC2 are shown.

[0057] Before bonding the front side of the first device wafer W1 to the back side of the second device wafer W2, the front side of the second device wafer W2 can be temporarily bonded (such as by adhesive bonding or fusion bonding) to a carrier 10 first, then the back side of the second device wafer W2 is thinned, and a TSV process is performed from the back side of the second device wafer W2 to form TSV vias 20 connected to the interconnect structure FC2 in the second device wafer W2. And, if necessary, an interconnect structure BC2 can be formed on the back side of the second device wafer W2. The interconnect structure BC2 can include patterned metal layers (such as redistribution layers, RDLs) isolated by a dielectric material and conductive plugs connecting adjacent metal layers. For clarity, Figure 2 Only some metal layers in the interconnect structure BC2 are shown. In addition, before bonding, a bonding structure FL1 connecting the interconnect structure FC1 is also formed on the front side of the first device wafer W1, and a bonding structure BL2 connecting the interconnect structure BC2 is also formed on the back side of the second device wafer W2. During bonding, by bonding the bonding structure FL1 and the bonding structure BL2, the first device wafer W1 and the second device wafer W2 are stacked and interconnected. The bonding structure FL1 can include a first dielectric layer 110 covering the interconnect structure FC1 and a first metal bonding pad 120 formed in the first dielectric layer 110. The first metal bonding pad 120 can be connected to the interconnect structure FC1 through corresponding conductive plugs. The bonding structure BL2 can include a second dielectric layer 130 covering the interconnect structure BC2 and a second metal bonding pad 140 formed in the second dielectric layer 130. The second metal bonding pad 140 can be connected to the interconnect structure BC2 through corresponding conductive plugs. When bonding the bonding structure FL1 and the bonding structure BL2, the first dielectric layer 110 can be bonded and fixed to the opposite second dielectric layer 130 or the second metal bonding pad 140 by hybrid bonding, and the first metal bonding pad 120 can be bonded and fixed to the opposite second metal bonding pad 140 or the second dielectric layer 130. By bonding and connecting the first metal bonding pad 120 to the opposite second metal bonding pad 140, the first device wafer W1 and the second device wafer W2 are interconnected.

[0058] Referring to Figure 2, after stacking the second device wafer W2 on the first device wafer W1, the carrier plate 10 can be removed to expose the front side of the second device wafer W2. Further, when a relatively large number of device wafers need to be stacked in the stacked chip unit, a bonding structure FL2 can be formed on the exposed front side of the second device wafer W2. The bonding structure FL2 can include a third dielectric layer 150 formed on the front of the second device wafer W2 and a third metal bonding pad 160 formed in the third dielectric layer 150. The third metal bonding pad 160 can be connected to the interconnect structure FC2 through corresponding conductive plugs; then, a third device wafer W3, a fourth device wafer W4,..., an nth device wafer Wn are sequentially stacked on the front of the second device wafer W2 by a process similar to the foregoing process. In the above process, bonding the mth device wafer (m is greater than or equal to 2 and less than or equal to n) to the (m - 1)th device wafer includes: first, bonding the front of the mth device wafer to a carrier plate; then, thinning the mth device wafer from the back; then, forming TSV vias from the back of the mth device wafer; then, forming corresponding interconnect structures and bonding structures connected to the corresponding interconnect structures on the back of the mth device wafer, wherein the TSV vias connect the interconnect structures on the front and the back of the mth device wafer; then, bonding the back of the mth device wafer to the front of the (m - 1)th device wafer; after that, removing the carrier plate on the front of the mth device wafer.

[0059] As Figure 3 shown, in one embodiment, a stacked wafer is formed by using the above process, denoted as WS. One end of the stacked wafer WS is the first device wafer W1, and the other end is the nth device wafer Wn. The upper surface of the stacked wafer WS is, for example, the front of the nth device wafer Wn, and the lower surface is the back of the first device wafer W1. An interconnect structure FCn and a bonding structure FLn connected to the interconnect structure FCn are formed on the front of the nth device wafer Wn. In the stacked wafer WS, each of the n device wafers, namely the first device wafer W1, the second device wafer W2,..., the nth device wafer Wn, includes an interconnect structure formed on the front and a bonding structure connecting the front interconnect structure. Optionally, the (n - 1) device wafers from the second device wafer W2 to the nth device wafer further include an interconnect structure formed on the back and a bonding structure connecting the back interconnect structure. In the stacked wafer WS, between two adjacent device wafers, the bonding structure located on the front of one device wafer and the bonding structure located on the back of the other device wafer are bonded and electrically connected through metal bonding pads.

[0060] After forming the stacked wafer WS, the stacked wafer WS is cut along the thickness direction to obtain a stacked chip unit, which may specifically include: referring to Figure 4, before cutting, temporarily bond (such as by adhesion or fusion bonding) one side of the n-th device wafer Wn of the stacked wafer WS to a carrier plate 11, and then thin the back surface of the first device wafer W1; refer to Figure 5 , transfer the stacked wafer WS after thinning the first device wafer W1 to a dicing frame 30 (for example, make the first device wafer W1 contact the dicing frame 30), and remove the carrier plate 11; refer to Figure 6 , perform a cutting process to cut the stacked wafer WS in the thickness direction to obtain at least one stacked chip unit (denoted as CS). Refer to Figure 6 , the stacked chip unit CS includes a plurality of stacked and interconnected chips, and each stacked chip unit CS has a bonding structure FLn formed on the front surface of the n-th device wafer Wn portion (the n-th device wafer Wn portion refers to the portion of the above-mentioned n-th device wafer remaining in the stacked chip unit CS after being diced).

[0061] The formation process of the stacked chip unit is exemplarily described above. It can be understood that in subsequent steps, the stacked chip unit adopted can select appropriate chip types and stacking quantities according to the requirements of semiconductor devices, and the stacked chip unit adopted in subsequent steps can be obtained by dicing one stacked wafer or multiple stacked wafers.

[0062] Refer to Figure 1 , in step S2, provide a packaging wafer and perform chip-wafer bonding to bond at least one of the stacked chip units CS on the surface of the packaging wafer.

[0063] The packaging wafer may include a logic circuit for interconnecting with the stacked chip unit CS. The packaging wafer is, for example, a logic wafer, or the packaging wafer is a bonded wafer formed by stacking a logic wafer and a memory wafer. Refer to Figure 7 , in some embodiments, the packaging wafer 200 includes a front surface for forming electronic components and a back surface opposite to the front surface, and an interconnect structure FC-1 and a bonding structure FL-1 connected to the interconnect structure FC-1 are formed on the front surface for facilitating bonding with the above-mentioned stacked chip unit CS. Before bonding with the stacked chip unit CS, the back surface of the packaging wafer 200 can be thinned first, a TSV via hole 40 connected to the interconnect structure FC-1 and an interconnect structure BC-1 located on the back surface and connected to the TSV via hole 40 are formed in the packaging wafer 200, and then a carrier plate 12 is bonded to the back surface of the packaging wafer 200.

[0064] Refer to Figure 8, Next, chip-wafer bonding is performed. The bonding structure FL-1 on the front side of the package wafer 200 and the bonding structure FLn on the stacked chip unit CS can be utilized to bond the two in a manner such as hybrid bonding. In some other embodiments, the chip-wafer bonding can also adopt a microbump connection method or other connection methods. When bonding the stacked chip unit CS to the package wafer 200, the bonding structure FLn formed on the front side of the nth device wafer Wn portion can be used to bond with the package wafer 200, so that the back side of the first device wafer W1 portion in the stacked chip unit CS is away from the package wafer 200.

[0065] After bonding at least one stacked chip unit CS on the surface of the package wafer 200, there are areas on the surface of the package wafer 200 that are not covered by the stacked chip unit CS. Refer to Figure 9 , In step S3, a first filling and covering layer 300 is formed on the surface of the package wafer 200 and the stacked chip unit CS on the package wafer 200 for wafer reshaping to obtain a first reshaped wafer (denoted as RW1). The first reshaped wafer RW1 includes the package wafer 200 and one layer of the stacked chip unit CS stacked thereon. Forming the first filling and covering layer 300 may include the following process: depositing a dielectric material on the package wafer 200 to fill the areas on the package wafer 200 not covered by the stacked chip unit CS and cover the surface of the stacked chip unit CS. The top surface of the dielectric material is, for example, higher than the top surface of the stacked chip unit CS. The dielectric material may include one of inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, or may also include an organic material; then a planarization process is performed to improve the flatness of the surface of the dielectric material on the side away from the package wafer 200, and the remaining dielectric material is the first filling and covering layer 300. The first filling and covering layer 300 can play a role in fixing the first layer of the stacked chip unit CS stacked on the package wafer 200, and by forming the first filling and covering layer 300, the overall of the package wafer 200 and the first layer of the stacked chip unit CS stacked thereon reaches the wafer-level size.

[0066] In some embodiments, the processes of chip-wafer bonding and wafer reshaping can be repeated on the first reshaped wafer RW1 to stack more than two layers of the stacked chip unit CS on the package wafer 200.

[0067] Refer to Figure 9, before subsequent chip-wafer bonding, the following processes may be included: form TSV vias 50 from the side of the first reshaped wafer RW1 away from the package wafer 200 (specifically, the back side of the first device wafer W1 portion of the stacked chip unit CS here), the TSV vias 50 are connected to the interconnect structure (specifically, the interconnect structure FC1 here) in the first reshaped wafer RW1. After that, a bonding structure BL1 connecting the TSV vias 50 may be formed on the back side of the first device wafer W1 portion. Optionally, before forming the bonding structure BL1, an interconnect structure BC1 may be first formed on the back side of the first device wafer W1 portion, and then the bonding structure BL1 is formed, so that the bonding structure BL1 is connected to the TSV vias 50 through the interconnect structure BC1. The bonding structure BL1 covers each stacked chip unit CS and the first filling and covering layer 300 in the first reshaped wafer RW. The bonding structure BL1 includes a dielectric layer and metal bonding pads formed in the dielectric layer, and the bonding structure BL1 has a wafer-level size. Using the bonding structure BL1, the stacked chip units CS can be stacked again by chip-wafer bonding on the side of the first reshaped wafer RW1 away from the package wafer 200. The first reshaped wafer RW1 may include the bonding structure BL1.

[0068] To form more chip stacks, refer to Figure 10 , perform chip-wafer bonding again, bond at least one stacked chip unit CS on the surface of the first reshaped wafer RW1. In this chip-wafer bonding process, each stacked chip unit CS is bonded to the bonding structure BL1, and the bonding method is, for example, hybrid bonding or micro-bump connection. Hybrid bonding is preferably used to increase the density of connection points.

[0069] After bonding at least one of the stacked chip units CS on the surface of the first reshaped wafer RW1, refer to Figure 11 , form a second filling and covering layer 400 on the surface of the first reshaped wafer RW1 and the stacked chip units CS on the first reshaped wafer RW1 for wafer reshaping to form a second reshaped wafer, which is denoted as RW2. The second reshaped wafer RW2 includes the package wafer 200 and two layers of the stacked chip units CS stacked on the package wafer 200. The formation of the second filling and covering layer 400 may include the following processes: deposit a dielectric material on the first reshaped wafer RW1, so that the dielectric material fills the area of the first reshaped wafer RW1 not covered by the stacked chip units CS and covers the surface of the stacked chip units CS. The top surface of the dielectric material is, for example, higher than the top surface of the stacked chip units CS on the first reshaped wafer RW1; then a planarization process is performed to improve the flatness of the surface of the dielectric material away from the first reshaped wafer RW1. The remaining dielectric material on the first reshaped wafer RW1 is the second filling and covering layer 400.

[0070] According to the stacking requirements of semiconductor devices, when there are still remaining stacked chip units CS to be assembled after the above two chip-wafer bonding and wafer reshaping processes, the above chip-wafer bonding and wafer reshaping processes can be cycled to stack more than two layers of the stacked chip units CS on the encapsulation wafer 200.

[0071] After stacking the stacked chip units CS to be bonded on the encapsulation wafer 200 through the above process, the method for forming the semiconductor device may further include: forming metal pads on the side of the encapsulation wafer 200 facing away from the stacked chip units CS. Specifically, referring to Figure 12 , after the stacked chip units CS in the top layer (the last stacked layer) are stacked and a corresponding filling and covering layer is formed to obtain a reshaped wafer ( Figure 12 only shows two layers of stacked chip units CS, and exemplarily, the stacked chip unit CS in the layer relatively far from the encapsulation wafer 200 is used as the top-layer stacked chip unit CS), bond a carrier plate 13 to one side of the stacked chip unit CS in the top layer to perform processes on one side of the encapsulation wafer 200; referring to Figure 13 , remove the carrier plate 12 on one side of the encapsulation wafer 200, and then, form a dielectric layer on the exposed surface of the encapsulation wafer 200 and metal pads 500 that penetrate through the dielectric layer and are connected to the interconnect structure (here, the interconnect structure BC-1 located on the back of the encapsulation wafer 200) on the encapsulation wafer 200. The metal pads 500 can be used to connect to circuits outside the semiconductor device.

[0072] After the above process, at least one layer of stacked chip units CS is stacked on the encapsulation wafer 200. Each layer of the stacked chip units CS includes a plurality of chips stacked and interconnected along the thickness direction. This forming method stacks chip-level sized stacked chip units with wafer-level sized encapsulation wafers, can achieve high-density chip stacking, has relatively high process reliability, and helps to reduce process costs. By chip-wafer bonding and wafer reshaping, a combination of wafer-wafer stacking and chip-wafer stacking methods can improve process efficiency while achieving high-density chip stacking, which helps to reduce process costs and shorten the manufacturing cycle.

[0073] According to requirements, after stacking at least one layer of stacked chip units CS on the encapsulation wafer 200, a cutting process can be performed along the thickness direction of the wafer-level structure to obtain a chip-level structure. The chip-level structure may include an encapsulation substrate obtained by cutting the encapsulation wafer 200 and at least one layer of stacked chip units CS stacked on the encapsulation substrate. Each layer of the stacked chip units CS may include one or more of the above-mentioned stacked chip units CS.

[0074] An embodiment of the present invention further includes a semiconductor device. The manufacturing of the semiconductor device employs the formation method of the semiconductor device described in the above embodiment. While achieving high-density chip stacking, it helps to reduce the process cost and shorten the manufacturing cycle. Refer to Figure 13 , the semiconductor device includes:

[0075] A package substrate, for example obtained from a package wafer 200, the package substrate having a wafer-level size or a chip-level size;

[0076] At least one layer of stacked chip units CS stacked on the package substrate. Each layer of the stacked chip units CS includes at least one stacked chip unit CS, and each stacked chip unit CS includes a plurality of chips stacked and interconnected in the thickness direction; and

[0077] At least one layer of filling and covering layer (such as the first filling and covering layer 300 or the second filling and covering layer 400), respectively located around each layer of the stacked chip units CS.

[0078] In addition, the semiconductor device may further include a metal pad 500 formed on a side of the package substrate facing away from the stacked chip units CS. The package substrate may include a logic circuit, and the logic circuit may be interconnected with the circuits in the stacked chip units CS on the package substrate. The semiconductor device includes, for example, a high-bandwidth memory (HBM).

[0079] In some embodiments, the semiconductor device includes at least two layers of stacked chip units CS stacked on the package substrate, and adjacent two layers of stacked chip units CS are connected by a bonding structure. Refer to Figure 13 , in adjacent two layers of the stacked chip units, a layer of stacked chip units CS relatively close to the package wafer 200 and the filling and covering layer (such as the first filling and covering layer 300) are covered by a wafer-level bonding structure (such as the bonding structure BL1), and each of the stacked chip units CS in a layer of stacked chip units CS relatively far from the package wafer 200 is bonded to the wafer-level bonding structure. For the filling and covering layers respectively located around adjacent two layers of stacked chip units CS, such as the first filling and covering layer 300 and the second filling and covering layer 400, a wafer-level bonding structure BL1 is formed between them, and thus they do not directly contact, that is, the filling and covering layers respectively located around adjacent two layers of stacked chip units CS are arranged at intervals.

[0080] It should be noted that the various embodiments in this specification are described in a progressive manner. The key points of each embodiment are the differences from other embodiments. The same and similar parts among the various embodiments can be referred to each other.

[0081] The above description is only a description of the preferred embodiments of the present invention and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention all fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, Comprising: Forming a stacked chip unit, the stacked chip unit including a plurality of chips stacked and interconnected in a thickness direction, the plurality of chips being electrically connected by bonding; Providing a packaging wafer and performing chip-wafer bonding to bond at least one of the stacked chip units on the surface of the packaging wafer; And Forming a first filling and covering layer on the surface of the packaging wafer and the stacked chip unit on the packaging wafer to perform wafer reshaping, obtaining a first reshaped wafer, the first reshaped wafer including one layer of the stacked chip units stacked on the packaging wafer; Repeating the processes of the chip-wafer bonding and the wafer reshaping on the first reshaped wafer to stack at least two layers of the stacked chip units on the packaging wafer, wherein, after forming the first reshaped wafer, a wafer-level interconnect structure and a wafer-level bonding structure connected to the stacked chip units in the first reshaped wafer are formed on a side of the first reshaped wafer away from the packaging wafer by using a wafer-level process, and at least one of the stacked chip units is bonded on the surface of the first reshaped wafer by using the wafer-level bonding structure; Wherein, the wafer-level bonding structure includes a dielectric layer and metal bonding pads formed in the dielectric layer, the dielectric layer straddles each of the stacked chip units in the first reshaped wafer and covers the wafer-level interconnect structure, and the metal bonding pads penetrate through the dielectric layer and are connected to the wafer-level interconnect structure.

2. The forming method according to claim 1, characterized in that, Forming the stacked chip unit includes: Stacking and interconnecting a plurality of device wafers to form a stacked wafer; and Cutting the stacked wafer in the thickness direction to obtain the stacked chip unit.

3. The forming method according to claim 2, wherein In the stacked wafer, each of the device wafers includes a front surface for forming electronic components and a back surface opposite to the front surface, and the front surfaces of all the device wafers face the same direction.

4. The forming method according to claim 3, characterized in that, The stacked wafer includes a first device wafer, a second device wafer,..., an nth device wafer stacked in sequence in the thickness direction, where n is an integer greater than or equal to 2; wherein, the first device wafer, the second device wafer,..., the nth device wafer all include an interconnect structure formed on the front surface and a bonding structure connecting the interconnect structure on the front surface, and the second device wafer,..., the nth device wafer further include an interconnect structure formed on the back surface and a bonding structure connecting the interconnect structure on the back surface; in two adjacent device wafers, the bonding structure located on the front surface of one device wafer and the bonding structure located on the back surface of the other device wafer are bonded and electrically connected.

5. The forming method according to claim 4, wherein, Bonding the mth device wafer to the (m - 1)th device wafer includes: Bonding the front surface of the mth device wafer to a carrier; Thinning the mth device wafer from the back surface; Forming TSV vias from the back surface of the mth device wafer; Forming a corresponding interconnect structure and a bonding structure connected to the corresponding interconnect structure on the back surface of the mth device wafer, and the TSV vias connect the interconnect structure on the front surface and the interconnect structure on the back surface of the mth device wafer; Bonding the back surface of the mth device wafer and the front surface of the (m - 1)th device wafer; and Remove the carrier substrate, where m is greater than or equal to 2 and less than or equal to n.

6. The forming method according to claim 4, wherein Before dicing the stacked wafers, thin the first device wafer from the back side.

7. The forming method according to claim 4, wherein When bonding the stacked chip units to the package wafer, bond the package wafer using the bonding structure formed on the front side of the nth device wafer.

8. The forming method according to claim 7, wherein, Further comprising: Form TSV vias from the back side of the first device wafer portion in the first reshaped wafer, the TSV vias being connected to the interconnect structure on the front side of the first device wafer portion; and Form a wafer-level bonding structure of wafer-level size connecting the TSV vias on the back side of the first device wafer portion, so as to facilitate stacking the stacked chip units again by chip-wafer bonding on the side of the first reshaped wafer away from the package wafer.

9. The forming method according to claim 1, wherein After stacking the stacked chip units on the package wafer, further comprising: forming metal pads on the side of the package wafer facing away from the stacked chip units.

10. A semiconductor device, characterized in that, Comprising: A package substrate; At least two layers of stacked chip units stacked on the package substrate, each layer of the stacked chip units comprising at least one of the stacked chip units, each of the stacked chip units comprising a plurality of chips stacked and interconnected along the thickness direction, the plurality of chips being electrically connected by bonding, and the stacked chip units being bonded to the package substrate; A wafer-level interconnect structure formed between the bottom two layers of the stacked chip units on the package substrate and connecting the bottom layer of the stacked chip units; A wafer-level bonding structure comprising a dielectric layer and metal bonding pads formed in the dielectric layer, the dielectric layer spanning the bottom layer of the stacked chip units and covering the wafer-level interconnect structure, the metal bonding pads passing through the dielectric layer and connecting to the wafer-level interconnect structure, and the wafer-level bonding structure being bonded to the stacked chip units of the layer above the bottom layer; and At least two layers of filling and covering layers located around each layer of the stacked chip units.

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