Data writing method, device, terminal equipment and storage medium

Abstract

The present application is applicable to the field of data processing technology, and provides a data writing method, device, terminal equipment and storage medium, the method comprising: obtaining data to be written, a scrambling key and a destination address where the data to be written needs to be written; scrambling the destination address to obtain a scrambling address; using one of the scrambling key and the scrambling address to scramble the data to be written to obtain first scrambled data; using the other of the scrambling key and the scrambling address to scramble the first scrambled data to obtain target data; writing the target data to the destination address. The present application adds scrambled data of the destination address to the written data, making the written data more difficult to crack, and increasing the security of the data to be written after writing.

Description

Technical Field

[0001] The present application belongs to the field of data processing technology, and in particular, relates to a data writing method, device, terminal equipment and storage medium. Background Art

[0002] Data writing is the process of moving or copying data from where it is used or generated to where it is stored.

[0003] When writing data, in order to ensure the security of the data, the data is usually encrypted and written. Currently, when writing data, a key is generally extracted from a key table, and then the key is used to encrypt the data to be written; however, this encryption method is relatively simple, resulting in the encrypted data being easily cracked, and the data security is poor. Summary of the invention

[0004] The embodiments of the present application provide a data writing method, apparatus, terminal device and storage medium, which can improve the current situation where the security of written data is poor due to the simple data encryption method.

[0005] In a first aspect, an embodiment of the present application provides a data writing method, comprising:

[0006] Obtaining data to be written, a scrambling key, and a destination address to which the data to be written needs to be written;

[0007] Scrambling the destination address to obtain a scrambled address;

[0008] Using one of the scrambling key and the scrambling address to scramble the data to be written to obtain first scrambled data;

[0009] Using the other of the scrambling key and the scrambling address to scramble the first scrambled data to obtain target data;

[0010] The target data is written to the destination address.

[0011] In a second aspect, an embodiment of the present application provides a data writing device, including:

[0012] An information acquisition module, used to acquire the data to be written, the scrambling key and the destination address to which the data to be written needs to be written;

[0013] A first scrambling module, used for scrambling the destination address to obtain a scrambled address;

[0014] A second scrambling module, configured to scramble the data to be written by using one of the scrambling key and the scrambling address to obtain first scrambled data;

[0015] A third scrambling module, configured to scramble the first scrambled data using the other of the scrambling key and the scrambling address to obtain target data;

[0016] A data writing module is used to write the target data to the destination address.

[0017] In a third aspect, an embodiment of the present application provides a terminal device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the data writing method described in any one of the first aspects above when executing the computer program.

[0018] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the data writing method described in any one of the first aspects above is implemented.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed on a terminal device, enables the terminal device to execute the data writing method described in any one of the above-mentioned first aspects.

[0020] The beneficial effect of the first aspect embodiment of the present application compared with the prior art is as follows: after obtaining the data to be written, the scrambling key and the destination address to which the data to be written needs to be written, the present application scrambles the destination address to obtain the scrambled address; uses the scrambling key and one of the scrambling addresses to scramble the data to be written to obtain first scrambled data; uses the scrambling key and the other of the scrambling addresses to scramble the first scrambled data to obtain target data; and writes the target data to the destination address.

[0021] Compared with the prior art that only uses a key to scramble the data to be written, the present application scrambles the destination address, and then uses the scrambled destination address and the obtained scrambling key to scramble the data to be written to obtain the target data of the data to be written. Since the scrambled data of the destination address is added to the written data, the written data is related to the destination address, making the written data more difficult to crack, thereby increasing the security of the data to be written after writing.

[0022] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 is a flow chart of a data writing method provided by an embodiment of the present application;

[0025] Figure 2 It is a flowchart of a method for scrambling a destination address provided in an embodiment of the present application;

[0026] Figure 3 It is a flowchart of a method for obtaining a scrambled address based on an address group provided in an embodiment of the present application;

[0027] Figure 4 is a flowchart of a shift operation method of a scrambled address group provided by another embodiment of the present application;

[0028] Figure 5 is a flowchart of a method for obtaining target data provided by an embodiment of the present application;

[0029] Figure 6 is a flowchart of a method for obtaining target data by using third scrambled data provided by an embodiment of the present application;

[0030] Figure 7 is a schematic diagram of the structure of a scrambling circuit provided in an embodiment of the present application;

[0031] Figure 8 is a structural schematic diagram of a data writing device provided by an embodiment of the present application;

[0032] Fig. 9 It is a structural diagram of a terminal device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0033] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0034] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0035] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0036] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0037] At present, in order to ensure the security of the written data, it is necessary to encrypt the data to be written, and when encrypting the written data, a key is often used to encrypt the data to be written, and then the data to be written encrypted with the key is stored. In the above encryption method, once the key is leaked or cracked, the data to be written will be leaked, which seriously affects the security of the data to be written.

[0038] Based on the above reasons, the present application proposes a data writing method, which not only uses a key to scramble the data to be written, but also scrambles the destination address where the data to be written needs to be written; then, the final target data of the data to be written is obtained according to the above scrambled data to be written and the scrambled destination address, and the target data is written and stored. The present application not only uses a key to scramble the data to be written, but also uses the scrambled destination address to further scramble it. The data finally written is related to the destination address, which increases the difficulty of decryption and greatly improves the security of the data to be written.

[0039] Specifically, the method of the present application can be applied to a chip of an electronic device, and the electronic device may be a computer or a laser radar, etc.

[0040] Figure 1 A schematic flow chart of the data writing method provided by the present application is shown, referring to Figure 1 , the method is described in detail as follows:

[0041] S101: Acquire data to be written, a scrambling key, and a destination address to which the data to be written needs to be written.

[0042] In this embodiment, the data to be written may be configuration data, control data, or environmental data collected by an environmental sensor, etc. The environmental sensor may include a laser radar, a camera, a temperature sensor, and the like.

[0043] In this embodiment, the data to be written and the destination address of the data to be written can be obtained from the bus of the electronic device. The data to be written can be data with a number of bits such as 32 bits or 64 bits. The number of bits of the destination address is the same as the number of bits of the data to be written.

[0044] Specifically, when the present application is applied to a chip, the chip may include a first XOR operation unit, a first preset number of first replacement boxes and a cyclic shift unit. In addition, the chip may also include a second XOR operation unit, a second preset number of second replacement boxes and a signature unit.

[0045] The chip is burned with a key table during manufacturing, and the key table includes at least one key. In the present embodiment, the key table includes at least two keys. After the electronic device is turned on, the chip selects any key from the key table as the scrambling key to be used when the electronic device is running this time to scramble the data to be written. For example, in some embodiments, the chip includes a random number generator; the chip selects a key of a corresponding sequence from the key table using a random number generated by the random number generator as the scrambling key. Since a key is randomly selected as the scrambling key, the scrambling keys used for different data to be written may be different, which can increase the difficulty of cracking the data, that is, improve the security of the data.

[0046] In some embodiments, the chip obtains the scrambling key after obtaining the data to be written and the destination address to which the data to be written needs to be written.

[0047] S102: Scramble the destination address to obtain a scrambled address.

[0048] In this embodiment, the destination address may be binary data, and there is initial data on each address bit in the destination address. For example, the destination address may be 0000101000000000000000000000000001, etc.

[0049] In the present application, the scrambling process for the destination address may include the following methods.

[0050] For example, in some embodiments, each initial data in the destination address is scrambled to obtain a scrambled destination address.

[0051] For example, in some other embodiments, the initial data on the preset address bits in the destination address are scrambled to obtain the scrambled destination address. For example, if the destination address is 32 bits, the initial data on bit7, bit15, bit23 and bit31 in the destination address are scrambled to obtain the scrambled destination address.

[0052] In this embodiment, the destination address is scrambled using the scrambling information. Specifically, the scrambling information and the initial data in the destination address are bit-wise calculated to obtain the scrambled destination address.

[0053] The scrambling information may be preset scrambling data; or, the scrambling information may be initial data included in the destination address itself; or, the scrambling information may be preset scrambling data and initial data included in the destination address itself. When scrambling initial data on different address bits, different scrambling information may be used. For example, data a is used to scramble initial data on bit2; data b is used to scramble initial data on bit3; data a and data b are different.

[0054] S103: Scramble the data to be written using one of the scrambling key and the scrambling address to obtain first scrambled data.

[0055] In this embodiment, scrambling is a method of processing digital signals, generally using a scrambling code to process the original data to obtain new data. Compared with the original data, the new data is scattered in time and frequency.

[0056] In this embodiment, the data to be written is scrambled using a scrambling key to obtain first scrambled data, or the data to be written is scrambled using a scrambling address to obtain first scrambled data.

[0057] In this embodiment, the scrambling process may be a bitwise operation process, and the bitwise operation may be a bitwise exclusive OR operation, a bitwise exclusive OR operation, a bitwise AND operation, or a bitwise OR operation.

[0058] In practical applications, if the method is applied to a chip, the above step S103 can also be implemented in a first XOR operation unit. Specifically, the first XOR operation unit in the chip performs a bitwise XOR operation on the scrambling key and the data to be written to obtain the first scrambled data.

[0059] S104: Using the other of the scrambling key and the scrambling address to scramble the first scrambled data to obtain target data.

[0060] In this embodiment, if the scrambling key is used to scramble the data to be written in step S103, then the scrambling address is used to scramble the first scrambled data in step S104 to obtain the target data.

[0061] If the data to be written is scrambled using the scrambled address in step S103, the first scrambled data is scrambled using the scrambled key in step S104 to obtain the target data.

[0062] S105: Writing the target data to the destination address.

[0063] In this embodiment, the target data is sent to a storage module for storage. The storage module may be a double data rate synchronous dynamic random access memory (DDR).

[0064] In an embodiment of the present application, after obtaining the data to be written, the scrambling key and the destination address to which the data to be written needs to be written, the destination address is scrambled to obtain the scrambled address; the data to be written is scrambled using the scrambling key and one of the scrambling addresses to obtain the first scrambled data; the first scrambled data is scrambled using the scrambling key and the other of the scrambling addresses to obtain the target data; the target data is written to the destination address. Compared with the prior art that only uses the key to scramble the data to be written; the present application will scramble the destination address, and then use the scrambled destination address and the obtained scrambling key to scramble the data to be written to obtain the target data of the data to be written. Since the scrambled data of the destination address is added to the written data, the written data is related to the destination address, making the written data more difficult to crack, and increasing the security of the data to be written after writing.

[0065] In a possible implementation, the implementation process of step S103 may include:

[0066] The scrambling key and the data to be written are subjected to a bitwise operation to obtain the first scrambled data.

[0067] Specifically, the scrambling key and the data to be written are subjected to a bitwise XOR operation to obtain the first scrambled data of the data to be written. It can be understood that the above-mentioned bitwise operation is not limited to a bitwise XOR operation; in other embodiments of the present application, the above-mentioned bitwise operation can also be a bitwise XOR operation, a bitwise AND operation, or a bitwise OR operation; in other words, the scrambling key and the data to be written can also be subjected to a bitwise OR operation to obtain the first scrambled data of the data to be written; or, the scrambling key and the data to be written are subjected to a bitwise AND operation to obtain the first scrambled data of the data to be written; or, the scrambling key and the data to be written are subjected to a bitwise XOR operation to obtain the first scrambled data of the data to be written.

[0068] For example, if the data to be written is 32-bit data, a bitwise XOR operation is performed on the data to be written and the scrambling key to obtain first scrambled data, and the first scrambled data is 32-bit data.

[0069] Accordingly, the implementation process of step S104 may include:

[0070] The scrambled address and the first scrambled data are subjected to a bitwise operation to obtain target data.

[0071] Next, the above step S102 is further explained. Figure 2 As shown, in a possible implementation manner, the implementation process of step S102 may include:

[0072] S1021: Divide the destination address into a first preset number of address groups, wherein each of the address groups includes initial data of at least two address bits in the destination address.

[0073] In this embodiment, the destination address is split to obtain various address groups. The first preset number can be set as needed.

[0074] The address group is composed of data from the i-th address bit to the j-th address bit in the destination address, wherein 0≤i<j, j≤k, k is the total number of bits of the destination address, and each address bit has an initial data.

[0075] For example, the destination address is 32 bits, specifically: 01000100001111001001011110100010, and the destination address is divided into four address groups, namely 01000100; 00111100; 10010111; 10100010.

[0076] S1022: Scramble each initial data in each of the address groups to obtain a corresponding scrambled address group. Specifically, obtain a preset scrambling value, use the preset scrambling value to scramble each initial data to obtain scrambled initial data. The scrambled initial data constitute each scrambled address group.

[0077] In some embodiments, each of the address groups is input into a substitution box for scrambling to obtain a scrambled address group. Specifically, each of the address groups is input into a substitution box (S-box) for data substitution, that is, there is an address group in each S-box. Among them, the S-box is a basic component in the field of cryptography, and its function is to realize nonlinear substitution of data.

[0078] In practical applications, if the method is applied to a chip, the above step S1022 can also be implemented in a first replacement box. Specifically, each of the address groups is input into a first replacement box to perform scrambling processing on each initial data to obtain a scrambled address group.

[0079] In a possible implementation, the implementation process of step S1022 may include:

[0080] The following operation is performed on the initial data of each address bit in each of the address groups: using at least one initial data and / or preset constant in the address group where the target address bit is located, an XOR operation is performed on the initial data of the target address bit to obtain replacement data of the target address bit, and the replacement data of each target address bit in the address group constitutes an scrambled address group; wherein the target address bit is any address bit in the address group.

[0081] Specifically, the above process can be implemented through the following steps 1 to 2.

[0082] Step 1: For the initial data on the nth address bit, the nth address bit belongs to the mth address group, and a preset number of initial data is selected from each initial data in the mth address group, wherein the selected preset number of initial data may be the initial data on the address bit other than the nth address bit. In this embodiment, the preset number is an integer greater than 1; the preset number can be set as needed, for example, the preset number may be 2, 3, or 4, etc.

[0083] As an example, for the first address group, the first address group consists of the 0th address bit to the 7th address bit in the destination address. The initial data on the 4th address bit, the 5th address bit, the 6th address bit and the 7th address bit are selected as the scrambled data for scrambling the initial data on the 0th address bit. The initial data on the 0th address bit, the 5th address bit, the 6th address bit and the 7th address bit are selected as the scrambled data for scrambling the initial data on the 1st address bit. And so on, no further details are given here.

[0084] Step 2: Perform an XOR operation on the selected preset number of initial data and the initial data on the above nth address bit to obtain the replacement data of the nth address bit, and the replacement data corresponding to each address bit in the mth address group constitutes the scrambled mth address group.

[0085] As an example, for the first address group, the first address group is composed of data on the 0th address bit to the 7th address bit in the destination address, and the data on each address bit can be scrambled in the following manner to obtain corresponding replacement input data. The scrambling methods of the remaining address groups are roughly the same and will not be repeated here.

[0086] b′ 0 = b 0 ⊕ b 4 ⊕ b 5 ⊕ b 6 ⊕ b 7 = 0;

[0087] b′ 1 = b 1 ⊕ b 5 ⊕ b 6 ⊕ b 7 ⊕ b 0 = 1;

[0088] b′ 2 = b 2 ⊕ b 6 ⊕ b 7 ⊕ b 0 ⊕ b 1 = 0;

[0089] b′ 3 = b 3 ⊕ b 7 ⊕ b 0 ⊕ b 1 ⊕ b 2 = 1;

[0090] b′ 4 = b 4 ⊕ b 0 ⊕ b 1 ⊕ b 2 ⊕ b 3 = 0;

[0091] b′ 5 = b 5 ⊕ b 1 ⊕ b 2 ⊕ b 3 ⊕ b 4 = 0;

[0092] b′ 6 = b 6 ⊕ b 2 ⊕ b 3 ⊕ b 4 ⊕ b 5 = 1;

[0093] b′ 7 = b 7 ⊕ b 3 ⊕ b 4 ⊕ b 5 ⊕ b 6 = 0.

[0094] Among them, b′ 0is the replacement data at the 0th address, b′ 1 b′ is the replacement data at the first address bit; 2 b′ is the replacement data at the second address bit; 3 b′ is the replacement data at the third address bit; 4 b′ is the replacement data at the 4th address bit; 5 b′ is the replacement data at the 5th address bit; 6 b′ is the replacement data at the 6th address bit; 7 b is the replacement data on the 7th address bit; 0 To b 7 It is the initial data corresponding to the 0th to 7th address bits in the destination address.

[0095] In an embodiment of the present application, the initial data in the address group is scrambled using the data in the address group, thereby breaking up the initial data in the address group; since each replacement data corresponds to multiple initial data, it is difficult to crack the replacement data, which makes it more difficult to forcibly crack the replacement data, and the target data cannot be simply cracked according to the destination address, so the security of subsequent target data can be further improved.

[0096] In some embodiments, the implementation process of the above step 2 may also include:

[0097] The preset constant corresponding to the nth address bit is obtained, and the selected preset number of initial data and the preset constant are XOR-ed with the initial data on the nth address bit to obtain replacement data for the nth address bit.

[0098] As an example, for the first address group, the first address group is composed of data on the 0th address bit to the 7th address bit in the destination address, and the data on each address bit can be scrambled in the following manner to obtain corresponding replacement data. The scrambling methods of the remaining address groups are roughly the same and will not be repeated here.

[0099] b′ 0 =b 0 ⊕b 4 ⊕b 5 ⊕b 6 ⊕b 7 ⊕c 0 =0;

[0100] b′ 1 =b 1 ⊕b 5 ⊕b 6 ⊕b 7 ⊕b 0 ⊕c 1 =1;

[0101] b′ 2 =b 2 ⊕b 6 ⊕b 7 ⊕b 0 ⊕b 1 ⊕c 2 =0;

[0102] b′ 3 =b 3 ⊕b 7 ⊕b 0 ⊕b 1 ⊕b 2 ⊕c 3 =1;

[0103] b′ 4 =b 4 ⊕b 0 ⊕b 1 ⊕b 2 ⊕b 3 ⊕c 4 =0;

[0104] b′ 5 =b 5 ⊕b 1 ⊕b 2 ⊕b 3 ⊕b 4 ⊕c 5 =0;

[0105] b′ 6 =b 6 ⊕b 2 ⊕b 3 ⊕b 4 ⊕b 5 ⊕c 6 =1;

[0106] b′ 7 =b 7 ⊕b 3 ⊕b 4 ⊕b 5 ⊕b 6 ⊕c 7 =1.

[0107] Among them, c 0 to c 7 is a preset constant.

[0108] S1023: Obtain the scrambled address based on the first preset number of scrambled address groups.

[0109] In some embodiments, all scrambled address groups form a scrambled address. The arrangement order of the scrambled address groups is determined based on the arrangement order of the address groups in the destination address.

[0110] In other embodiments, Figure 3 As shown, the implementation process of step S1023 may include the following steps S201 to S203.

[0111] S201: Acquire data of a preset address bit in each scrambled address group; wherein the preset address bit is a pre-set or selected address bit in the address group, for example, it may be the highest address bit or the lowest address bit.

[0112] In this embodiment, the scrambled address group is composed of replacement data, and each replacement data corresponds to an address bit in the destination address.

[0113] For example, the first address group includes 8 replacement data; the 8 replacement data are replacement data at the 0th address bit to the 7th address bit. The highest address bit in the first address group is the 7th address bit, and the lowest address bit is the 0th address bit. The second address group includes 8 replacement data; the 8 replacement data are replacement data at the 8th address bit to the 15th address bit. The highest address bit in the second address group is the 15th address bit, and the lowest address bit is the 8th address bit.

[0114] S202: Determine the number of shifts based on the data of the preset address bits in each scrambled address group.

[0115] In this embodiment, the data of each preset address bit is arranged from low to high or from high to low according to the address bit; the arranged data of the preset address bit is converted into decimal data to obtain the shift number.

[0116] As an example, Figure 4 As shown, if the destination address is 32 bits, the scrambled address groups are arranged in order from high to low, and the second interference data composed of the scrambled address groups is obtained. For example, the second interference data is: 01000100_00111100_10010111_10100010, and each address group is separated by an underscore to facilitate the schematic reading; the replacement data on the highest address bit in each scrambled address group is taken to obtain bit31, bit23, bit15, and bit7 are 0, 0, 1, and 1 respectively; 0, 0, 1, and 1 are arranged in order from high to low in the splicing unit; and the arranged data is converted into decimal data, and the number of shifts is 3.

[0117] S203: Perform a cyclic shift operation on the second scrambled data based on the shift number to obtain the scrambled address, wherein the second scrambled data is composed of the scrambled address groups.

[0118] In this embodiment, the cyclic shift operation may include a left cyclic shift operation and a right cyclic shift operation. The left cyclic shift operation is to move the y replacement data of the lowest bit in the second scrambled data to the leftmost side of the second scrambled data; y is the number of shifts. The right cyclic shift operation is to move the y replacement data of the highest bit in the second scrambled data to the rightmost side of the second scrambled data.

[0119] As an example, Figure 4 As shown, if the number of shifts is 3, the cyclic shift operation is a left cyclic shift operation. The second scrambled data is: 01000100_00111100_10010111_10100010; the cyclic shift control unit moves the three replacement data 010 on the rightmost side to the leftmost side, and the second scrambled data after the shift is 01001000_10000111_10010010_11110100.

[0120] In the embodiment of the present application, after obtaining the second scrambled data, a cyclic shift operation is performed on the second scrambled data to obtain a scrambled address, so that the destination address is more difficult to crack, thereby making the target data scrambled by the scrambled address more secure.

[0121] In practical applications, if the method is applied to a chip, the above steps S201 to S203 can also be implemented by a cyclic shift unit in the chip. Specifically, the data of the preset address bits in each scrambled address group is obtained by the cyclic shift unit; the number of shifts is determined by the cyclic shift unit based on the data of the preset address bits in each scrambled address group; based on the number of shifts, the second scrambled data is cyclically shifted by the cyclic shift unit to obtain the scrambled address.

[0122] like Figure 5 As shown, in a possible implementation manner, the implementation process of step S104 may include:

[0123] S301: Perform a bitwise operation on the first scrambled data and the other of the scrambling key and the scrambling address to obtain third scrambled data, wherein the bitwise operation is a bitwise exclusive OR operation, a bitwise AND operation, or a bitwise OR operation.

[0124] In this embodiment, if the first scrambled data has been obtained using the scrambling key in step S103, this step uses the scrambling address to perform a bitwise operation on the first scrambled data. If the first scrambled data has been obtained using the scrambling address in step S103, this step uses the scrambling key to perform a bitwise operation on the first scrambled data to obtain the third scrambled data.

[0125] In practical applications, if the method is applied to a chip, the above step S301 can also be implemented by a second XOR operation unit in the chip. Specifically, the second XOR operation unit uses the other of the scrambling key and the scrambling address to perform a bitwise XOR operation with the first scrambled data to obtain the third scrambled data.

[0126] S302: Obtain the target data based on the third scrambled data.

[0127] In some embodiments, the third scrambled data may be used as the target data. Of course, in other embodiments of the present application, the third scrambled data may be scrambled again and / or digitally signed to obtain the target data.

[0128] like Figure 6 As shown, in some embodiments, the implementation process of step S302 may include:

[0129] S3021: Divide the third scrambled data into a second preset number of data groups, wherein each of the data groups includes at least two data in the third scrambled data.

[0130] In this embodiment, the implementation method of this step is similar to the implementation method of the above-mentioned step S1021. Please refer to the description of the above-mentioned step S1021 and will not be repeated here.

[0131] S3022: Scramble each data in each of the data groups to obtain a corresponding scrambled data group.

[0132] In this embodiment, the implementation method of this step is similar to the implementation method of the above-mentioned step S1022. Please refer to the description of the above-mentioned step S1022, which will not be repeated here.

[0133] In practical applications, if the method is applied to a chip, the above step S3022 can also be implemented by a second replacement box in the chip. Specifically, each data group is input into a second replacement box to scramble each data to obtain a corresponding scrambled data group.

[0134] S3023: Obtain fourth scrambled data based on the second preset number of scrambled data groups.

[0135] In this embodiment, the implementation method of this step is similar to the implementation method of the above step S1023. Please refer to the description of the above step S1023 and will not be repeated here.

[0136] S3024: Obtain the target data based on the fourth scrambled data.

[0137] In some embodiments, the fourth scrambled data may serve as the target data.

[0138] In other embodiments, the fourth scrambled data may be digitally signed to obtain target data. A digital signature (also known as a public key digital signature) is a digital string that can only be generated by the sender of the information and cannot be forged by others. This digital string is also a valid proof of the authenticity of the information sent by the sender of the information. A digital signature is a method for authenticating digital information. A digital signature may include a hash algorithm signature or a secure hash algorithm signature, etc.

[0139] In practical applications, if the method is applied to a chip, the above step S3024 can also be implemented by a signature unit in the chip. Specifically, the fourth scrambled data is digitally signed by the signature unit to obtain the target data.

[0140] In the embodiment of the present application, the fourth scrambled data is digitally signed to obtain the target data; so that when the target data is subsequently read, the target data can be verified to determine whether the target data has been tampered with.

[0141] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0142] Corresponding to the data writing method described in the above embodiment, the method of the present application can be performed as follows: Figure 7 The scrambling circuit shown is implemented. The above data writing method is specifically described in conjunction with the scrambling circuit.

[0143] The key selection unit selects a key used in this operation from a pre-stored key table as a scrambling key for scrambling the data to be written.

[0144] The data acquisition unit acquires the data to be written from the bus.

[0145] The first XOR operation unit performs a bitwise XOR operation on the scrambling key selected by the key selection unit and the data to be written acquired by the data acquisition unit to obtain the first scrambled data for the first scrambling of the data to be written. Of course, in other embodiments, the data acquisition unit can be omitted; accordingly, the first XOR unit can directly acquire the data to be written from the bus.

[0146] The address acquisition unit acquires the destination address to which the data to be written needs to be written from the bus, and divides the destination address into a first preset number of address groups, and assigns each address group to an S-box for data replacement to obtain the replaced address group. Four S-boxes are shown in the figure, but in actual use, it may not be limited to four S-boxes. Of course, in other embodiments, the address acquisition unit may be omitted; accordingly, the first preset number of S-boxes can acquire the destination address from the bus, and since the data that can be stored in each S-box is limited, it can divide the destination address into the first preset number of address groups when acquiring the destination address.

[0147] The cyclic shift unit performs cyclic shift processing on the second scrambled data composed of the permuted address groups in the multiple S-boxes, for example, cyclic shifting to the left to obtain the scrambled address. The specific method of the cyclic shift processing to the left is referred to the above step S1023, which will not be repeated here.

[0148] The second XOR operation unit performs a bitwise XOR operation on the first scrambled data and the scrambled address to obtain third scrambled data of the data to be written.

[0149] The third scrambled data is divided into a second preset number of data groups, each data group is assigned to an S-box for data replacement to obtain replaced data groups. All replaced data groups constitute the fourth scrambled data.

[0150] The signature unit performs hash signature processing on the fourth scrambled data to obtain target data.

[0151] The double rate synchronous dynamic random access memory stores target data.

[0152] In an embodiment of the present application, the data writing method is implemented in a scrambling circuit, and each hardware module in the scrambling circuit executes corresponding process steps on the acquired information without embedding too many algorithms to calculate the data to be written and the destination address; therefore, the present application can automatically complete the data scrambling when the chip writes data to the external memory, and will not generate new delays, with good timeliness, and when reading the data, reverse data descrambling and recovery can be performed, thereby protecting the security of the data to be written.

[0153] Corresponding to the data writing method described in the above embodiment, Figure 8 A structural block diagram of a data writing device provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0154] Reference Figure 8The device 400 may include: an information acquisition module 410, a first scrambling module 420, a second scrambling module 430, a third scrambling module 440 and a data writing module 450.

[0155] The information acquisition module 410 is used to acquire the data to be written, the scrambling key and the destination address where the data to be written needs to be written;

[0156] A first scrambling module 420, configured to scramble the destination address to obtain a scrambled address;

[0157] A second scrambling module 430 is used to scramble the data to be written using one of the scrambling key and the scrambling address to obtain first scrambled data;

[0158] A third scrambling module 440 is used to scramble the first scrambled data using the other of the scrambling key and the scrambling address to obtain target data;

[0159] The data writing module 450 is used to write the target data to the destination address.

[0160] In a possible implementation, the second scrambling module 430 may be specifically used to:

[0161] The scrambling key and the data to be written are subjected to a bitwise operation to obtain the first scrambled data, wherein the bitwise operation is a bitwise exclusive OR operation, a bitwise exclusive OR operation, a bitwise AND operation or a bitwise OR operation.

[0162] In a possible implementation, the second scrambling module 430 includes a first XOR operation unit, and the second scrambling module 430 may be specifically configured to: perform a bitwise XOR operation on the scrambling key and the data to be written through the first XOR operation unit to obtain the first scrambled data.

[0163] In a possible implementation, the first scrambling module 420 may specifically include:

[0164] a grouping unit, configured to group the destination address into a first preset number of address groups, wherein each of the address groups includes initial data of at least two address bits in the destination address;

[0165] A scrambling unit, used for scrambling each initial data in each of the address groups to obtain a corresponding scrambled address group;

[0166] A data generating unit is used to obtain the scrambled address based on the first preset number of scrambled address groups.

[0167] In a possible implementation, the scrambling unit may be specifically used for:

[0168] The following operation is performed on the initial data of each address bit in each of the address groups: using at least one initial data and / or preset constant in the address group where the target address bit is located, an XOR operation is performed on the initial data of the target address bit to obtain replacement data of the target address bit, and the replacement data of each target address bit in the address group constitutes an scrambled address group; wherein the target address bit is any address bit in the address group.

[0169] In a possible implementation, the scrambling unit includes a first preset number of first replacement boxes, and the scrambling unit can be specifically configured to: input each of the address groups into a first replacement box to scramble each initial data to obtain a scrambled address group.

[0170] In a possible implementation, the data generating unit may be specifically used to:

[0171] Acquire data of a preset address bit in each scrambled address group, wherein the preset address bit is the highest address bit or the lowest address bit;

[0172] Determining the number of shifts based on the data of the preset address bits in each scrambled address group;

[0173] Based on the shift number, a cyclic shift operation is performed on the second scrambled data to obtain the scrambled address, wherein the second scrambled data is composed of the scrambled address groups. In a possible implementation,

[0174] The data generation unit includes a cyclic shift unit, and the data generation unit can be specifically used for:

[0175] Acquire the data of the preset address bits in each scrambled address group through the cyclic shift unit;

[0176] Determining the number of shifts by the cyclic shift unit based on the data of the preset address bits in each scrambled address group;

[0177] Based on the shift number, the cyclic shift unit performs a cyclic shift operation on the second scrambled data to obtain the scrambled address.

[0178] In a possible implementation, the third scrambling module 440 may be specifically used to:

[0179] Performing a bitwise operation on the first scrambled data and one of the scrambling key and the scrambling address to obtain third scrambled data, wherein the bitwise operation is a bitwise exclusive OR operation, a bitwise AND operation, or a bitwise OR operation;

[0180] Based on the third scrambled data, the target data is obtained.

[0181] In a possible implementation, the third scrambling module 440 may be specifically used to:

[0182] Dividing the third scrambled data into a second preset number of data groups, wherein each of the data groups includes at least two data of the third scrambled data;

[0183] Scrambling each data in each of the data groups to obtain a corresponding scrambled data group;

[0184] Based on the second preset number of scrambled data groups, obtaining fourth scrambled data;

[0185] Based on the fourth scrambled data, the target data is obtained.

[0186] In a possible implementation, the third scrambling module 440 may be specifically used to:

[0187] The fourth scrambled data is digitally signed to obtain the target data.

[0188] In a possible implementation, the third scrambling module 440 includes a second XOR operation unit, and the third scrambling module 440 can be specifically used to: use the second XOR operation unit to perform a bitwise XOR operation on the other of the scrambling key and the scrambling address and the first scrambled data to obtain third scrambled data.

[0189] In a possible implementation, the third scrambling module 440 includes a second preset number of second replacement boxes, and the third scrambling module 440 can be specifically used to: input each of the data groups into a second replacement box to scramble each data to obtain a corresponding scrambled data group.

[0190] In a possible implementation, the third scrambling module 440 further includes a signature unit, and the third scrambling module 440 can be specifically used to: perform digital signature processing on the fourth scrambled data through the signature unit to obtain the target data. It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application, and their specific functions and technical effects can be specifically referred to in the method embodiment part, and will not be repeated here.

[0191] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0192] The present application also provides a terminal device, see Fig. 9 The terminal device 500 may include: at least one processor 510, a memory 520, and a computer program stored in the memory 520 and executable on the at least one processor 510. When the processor 510 executes the computer program, the steps in any of the above-mentioned method embodiments are implemented, for example Figure 1 Steps S101 to S105 in the illustrated embodiment. Alternatively, when the processor 510 executes the computer program, the functions of each module / unit in the above-mentioned device embodiments are implemented, for example Figure 8 The functions of the information acquisition module 410 to the data writing module 450 are shown.

[0193] Exemplarily, the computer program may be divided into one or more modules / units, one or more modules / units are stored in the memory 520, and executed by the processor 510 to complete the present application. The one or more modules / units may be a series of computer program segments capable of completing specific functions, and the program segments are used to describe the execution process of the computer program in the terminal device 500.

[0194] Those skilled in the art will understand that Fig. 9 It is only an example of a terminal device and does not constitute a limitation on the terminal device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components, such as input and output devices, network access devices, buses, etc.

[0195] The processor 510 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0196] The memory 520 may be an internal storage unit of the terminal device, or an external storage device of the terminal device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. The memory 520 is used to store the computer program and other programs and data required by the terminal device. The memory 520 may also be used to temporarily store data that has been output or is to be output.

[0197] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0198] The data writing method provided in the embodiment of the present application can be applied to terminal devices such as computers, tablet computers, laptops, netbooks, personal digital assistants (PDAs), etc. The embodiment of the present application does not impose any restrictions on the specific type of terminal devices.

[0199] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0200] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0201] In the embodiments provided in the present application, it should be understood that the disclosed terminal equipment, devices and methods can be implemented in other ways. For example, the terminal equipment embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0202] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0203] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0204] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by one or more processors, the steps of each of the above-mentioned method embodiments can be implemented.

[0205] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by one or more processors, the steps of each of the above-mentioned method embodiments can be implemented.

[0206] Similarly, as a computer program product, when the computer program product runs on a terminal device, the terminal device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0207] The computer program includes computer program code, which may be in source code form, object code form, executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer readable media do not include electric carrier signals and telecommunication signals.

[0208] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A data writing method, characterized in that: include: Obtaining data to be written, a scrambling key, and a destination address to which the data to be written needs to be written; Scrambling the destination address to obtain a scrambled address; Using one of the scrambling key and the scrambling address to scramble the data to be written to obtain first scrambled data; Using the other of the scrambling key and the scrambling address to scramble the first scrambled data to obtain target data; as well as Writing the target data to the destination address; The scrambling the destination address to obtain a scrambled address includes: Dividing the destination address into a first preset number of address groups, wherein each of the address groups includes initial data of at least two address bits in the destination address; Scrambling each of the initial data in each of the address groups to obtain a corresponding scrambled address group; and Obtaining the scrambled address based on the first preset number of scrambled address groups; The obtaining the scrambled address based on the first preset number of scrambled address groups includes: Acquire data of a preset address bit in each scrambled address group, wherein the preset address bit is the highest address bit or the lowest address bit; Determining the number of shifts based on the data of the preset address bits in each scrambled address group; and Based on the shift number, a cyclic shift operation is performed on the second scrambled data to obtain the scrambled address, wherein the second scrambled data is composed of the scrambled address groups.

2. The data writing method according to claim 1, characterized in that: The step of using one of the scrambling key and the scrambling address to scramble the data to be written to obtain first scrambled data includes: The scrambling key and the data to be written are subjected to a bitwise operation to obtain the first scrambled data, wherein the bitwise operation is a bitwise exclusive OR operation, a bitwise exclusive OR operation, a bitwise AND operation or a bitwise OR operation.

3. The data writing method according to claim 1, characterized in that: The scrambling of each of the initial data in each of the address groups to obtain a corresponding scrambled address group includes: The following operation is performed on the initial data of each address bit in each of the address groups: using at least one initial data and / or preset constant in the address group where the target address bit is located, an XOR operation is performed on the initial data of the target address bit to obtain replacement data of the target address bit, and the replacement data of each target address bit in the address group constitutes an scrambled address group; wherein the target address bit is any address bit in the address group.

4. The data writing method according to claim 1, characterized in that: The data writing method is applied to a chip, the chip comprising a first XOR operation unit, a first preset number of first replacement boxes and a cyclic shift unit; The step of using one of the scrambling key and the scrambling address to scramble the data to be written to obtain first scrambled data includes: Performing a bitwise XOR operation on the scrambling key and the data to be written by the first XOR operation unit to obtain the first scrambled data; The scrambling of each initial data in each address group to obtain a corresponding scrambled address group includes: inputting each address group into a first replacement box to scramble each initial data to obtain a scrambled address group; The obtaining the scrambled address based on the first preset number of scrambled address groups includes: Acquire the data of the preset address bits in each scrambled address group through the cyclic shift unit; Determining the number of shifts by the cyclic shift unit based on the data of the preset address bits in each scrambled address group; Based on the shift number, the cyclic shift unit performs a cyclic shift operation on the second scrambled data to obtain the scrambled address.

5. The data writing method according to any one of claims 1 to 4, characterized in that: The step of using the other of the scrambling key and the scrambling address to scramble the first scrambled data to obtain target data includes: Performing a bitwise operation on the first scrambled data and the other of the scrambling key and the scrambling address to obtain third scrambled data, wherein the bitwise operation is a bitwise exclusive OR operation, a bitwise AND operation, a bitwise exclusive OR operation, or a bitwise OR operation; Based on the third scrambled data, the target data is obtained.

6. The data writing method according to claim 5, characterized in that: The obtaining the target data based on the third scrambled data comprises: Dividing the third scrambled data into a second preset number of data groups, wherein each of the data groups includes at least two data of the third scrambled data; Scrambling each data in each of the data groups to obtain a corresponding scrambled data group; Based on the second preset number of scrambled data groups, obtaining fourth scrambled data; Based on the fourth scrambled data, the target data is obtained.

7. The data writing method according to claim 6, characterized in that: The obtaining the target data based on the fourth scrambled data comprises: The fourth scrambled data is digitally signed to obtain the target data.

8. The data writing method according to claim 6, characterized in that: The data writing method is applied to a chip, the chip comprising a second XOR operation unit, a second preset number of second replacement boxes and a signature unit; The step of performing a bitwise operation on the other of the scrambling key and the scrambling address and the first scrambled data to obtain the third scrambled data comprises: performing a bitwise XOR operation on the other of the scrambling key and the scrambling address and the first scrambled data by the second XOR operation unit to obtain the third scrambled data; The scrambling of each data in each data group to obtain a corresponding scrambled data group includes: inputting each data group into a second replacement box to scramble each data to obtain a corresponding scrambled data group; The obtaining the target data based on the fourth scrambled data includes: performing a digital signature process on the fourth scrambled data by the signature unit to obtain the target data.

9. A data writing device, characterized in that: include: An information acquisition module, used to acquire the data to be written, the scrambling key and the destination address to which the data to be written needs to be written; A first scrambling module, used for scrambling the destination address to obtain a scrambled address; A second scrambling module, configured to scramble the data to be written by using one of the scrambling key and the scrambling address to obtain first scrambled data; A third scrambling module, configured to scramble the first scrambled data using the other of the scrambling key and the scrambling address to obtain target data; as well as A data writing module, used for writing the target data to the destination address; The first scrambling module specifically includes: a grouping unit, configured to group the destination address into a first preset number of address groups, wherein each of the address groups includes initial data of at least two address bits in the destination address; a scrambling unit, configured to scramble each of the initial data in each of the address groups to obtain a corresponding scrambled address group; and a data generating unit, configured to obtain the scrambled address based on the first preset number of scrambled address groups; The data generation unit is specifically used for: Acquire data of a preset address bit in each scrambled address group, wherein the preset address bit is the highest address bit or the lowest address bit; Determining the number of shifts based on the data of the preset address bits in each scrambled address group; and Based on the shift number, a cyclic shift operation is performed on the second scrambled data to obtain the scrambled address, wherein the second scrambled data is composed of the scrambled address groups.

10. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the data writing method according to any one of claims 1 to 8 is implemented.

11. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the data writing method according to any one of claims 1 to 8 is implemented.

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