Test method and test system
By adjusting the signal edge and sampling clock state of the gating signal in the memory chip, the problem of difficulty in testing different memory types in the prior art is solved, and effective testing and lifespan extension of memory are achieved.
Patent Information
- Application Number
- CN202310958035.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2022-11-24
- Filing Date
- 2023-08-01
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2043-08-01
AI Technical Summary
Existing technologies make it difficult to adjust the delay time between the data strobe signal and the clock signal in the memory chip in write equalization mode, making it difficult to effectively study and test two different types of memory.
By adjusting the signal edge of the gating signal in write equalization mode, sampling the clock state in the memory chip, and determining the memory type based on the data signal, including the rising and falling edges of the fixed or moving gating signal, a shmoo diagram is generated to compensate the memory chip.
It enables effective testing of memory chips, can identify and compensate for different types of memory, extends the lifespan of memory, and improves the accuracy of testing.
Smart Images
Figure CN118072773B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a method and an electronic system. In particular, the present application relates to a testing method and a testing system. BACKGROUND
[0002] Under normal circumstances, the memory is in a write leveling mode, and the clock state of the clock signal changes with the rising edge of the data strobe signal (DQS) and is not fed back to the memory controller synchronously.
[0003] Some memories have the opposite behavior, that is, the clock state of the clock signal changes with the falling edge of the data strobe signal (DQS). It is difficult for those skilled in the art to study the aforementioned two types of memories in the write leveling mode, so as to adjust the delay time between the data strobe signal (DQS) and the clock signal.
[0004] Therefore, the above-mentioned technology still has many defects, and the rest suitable testing methods need to be developed by those skilled in the art. SUMMARY
[0005] One aspect of the present application relates to a testing method. The testing method comprises the following steps: accessing a memory chip to make the memory chip enter a write leveling mode; inputting a strobe signal to the memory chip in the write leveling mode; adjusting a plurality of signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip in the write leveling mode; generating a data signal according to the strobe signal in the write leveling mode; and determining a plurality of types of the memory according to the data signal in the write leveling mode.
[0006] In some embodiments, the ratio of the first duty cycle of the high voltage level of the clock signal and the second duty cycle of the low voltage level of the clock signal is not equal to one.
[0007] In some embodiments, the step of adjusting a plurality of signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip in the write leveling mode comprises fixing the rising edge of the strobe signal; and moving the falling edge of the strobe signal to sample the clock state of the clock signal, so as to detect the first change value of the data signal and the second change value of the data signal.
[0008] In some embodiments, the step of adjusting a plurality of signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip in the write leveling mode comprises fixing the falling edge of the strobe signal; and moving the rising edge of the strobe signal to sample the clock state of the clock signal, so as to detect the first change value of the data signal and the second change value of the data signal.
[0009] In some embodiments, the step of generating the data signal according to the selection signal in the write leveling mode includes latching the data signal if one of the first transition of the data signal and the second transition of the data signal is detected.
[0010] In some embodiments, the step of determining the plurality of types of the memory according to the data signal in the write leveling mode includes generating two shmoo plots according to the first transition of the data signal, the second transition of the data signal, and the selection signal.
[0011] In some embodiments, the step of determining the plurality of types of the memory according to the data signal in the write leveling mode further includes determining that the first type of the memory chip is that the clock state of the clock signal changes with the falling edge of the selection signal if the first transition of the data signal is detected.
[0012] In some embodiments, the step of determining the plurality of types of the memory according to the data signal in the write leveling mode further includes determining that the second type of the memory chip is that the clock state of the clock signal changes with the rising edge of the selection signal if the second transition of the data signal is detected.
[0013] In some embodiments, the testing method further includes compensating the memory chip according to the plurality of types of the memory chip in the write leveling mode.
[0014] In some embodiments, the step of compensating the memory chip according to the plurality of types of the memory chip in the write leveling mode includes adjusting the delay time of the selection signal relative to the clock signal in the write leveling mode.
[0015] Another aspect of the present disclosure relates to a testing system. The testing system includes a memory chip and a memory controller. The memory controller is coupled to the memory chip. The memory controller is configured to access the memory chip to enter the memory chip into a write leveling mode. The memory controller is configured to input a selection signal to the memory chip in the write leveling mode. The memory controller is configured to adjust a plurality of signal edges of the selection signal in the write leveling mode to sample a clock state of a clock signal in the memory chip. The memory chip is configured to generate a data signal according to the selection signal in the write leveling mode. The memory controller is configured to determine a plurality of types of the memory according to the data signal in the write leveling mode.
[0016] In some embodiments, a ratio of the first duty cycle of the high voltage level of the clock signal and the second duty cycle of the low voltage level of the clock signal is not equal to one.
[0017] In some embodiments, the memory controller is further configured to fix a rising edge of the strobe signal and to move a falling edge of the strobe signal to sample a clock state of the clock signal, thereby detecting a first transition value of the data signal and a second transition value of the data signal.
[0018] In some embodiments, the memory controller is further configured to fix a falling edge of the strobe signal and to move a rising edge of the strobe signal to sample a clock state of the clock signal, thereby detecting a first transition value of the data signal and a second transition value of the data signal.
[0019] In some embodiments, the memory chip is further configured to latch the data signal if one of the first transition value of the data signal and the second transition value of the data signal is detected.
[0020] In some embodiments, the memory controller is further configured to generate two shmoo plots based on the first transition value of the data signal, the second transition value of the data signal, and the strobe signal.
[0021] In some embodiments, the memory controller is further configured to determine that the memory chip is of a first type if the first transition value of the data signal is detected, wherein the clock state of the clock signal changes with the falling edge of the strobe signal.
[0022] In some embodiments, the memory controller is further configured to determine that the memory chip is of a second type if the second transition value of the data signal is detected, wherein the clock state of the clock signal changes with the rising edge of the strobe signal.
[0023] In some embodiments, the memory controller is further configured to compensate for the memory chip based on a plurality of types of the memory chip in a write leveling mode.
[0024] In some embodiments, the memory controller is further configured to adjust a delay time of the strobe signal relative to the clock signal in a write leveling mode. BRIEF DESCRIPTION OF DRAWINGS
[0025] The subject matter of the present case will be more readily understood with reference to the following paragraphs and the following drawings, wherein:
[0026] Figure 1 a circuit block diagram of a test system according to some embodiments of the present case;
[0027] Figure 2 a flowchart of steps of a test method according to some embodiments of the present case;
[0028] Figure 3 a signal timing diagram of a test system according to some embodiments of the present case;
[0029] Figure 4AA shmoo plot schematic diagram of a test system according to some embodiments of the present application;
[0030] Figure 4B A shmoo plot schematic diagram of a test system according to some embodiments of the present application;
[0031] Figure 5 A signal timing schematic diagram of a test system according to some embodiments of the present application;
[0032] Figure 6A A shmoo plot schematic diagram of a test system according to some embodiments of the present application; and
[0033] Figure 6B A shmoo plot schematic diagram of a test system according to some embodiments of the present application. DETAILED DESCRIPTION
[0034] The spirit of the present application will be further clearly understood from the following detailed description when taken in conjunction with the drawings and the detailed description, and any person skilled in the art can make changes and modifications to the technology taught by the present application without departing from the spirit and scope of the present application.
[0035] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The singular forms "a," "this," "the," "the," and "the" as used herein also include the plural forms.
[0036] As used herein, "include," "includes," "have," "has," "contain," "contains," and the like are open-ended terms that are intended to mean including but not limited to.
[0037] As used herein, the terms have their ordinary meaning in the field of use, in the context of the content of the present application and in the context of the special content, unless otherwise indicated. Some of the terms used to describe the present application are discussed below or elsewhere in the specification to provide additional guidance to those skilled in the art in describing the present application.
[0038] Figure 1 A circuit block schematic diagram of a test system 100 according to some embodiments of the present application. In some embodiments, referring to Figure 1 , the test system 100 includes a memory chip 111, a memory chip 112, and a memory controller 120. The memory chip 111 is coupled to the memory chip 112. The memory controller 120 is coupled to the memory chip 111 and the memory chip 112. It should be noted that the number of memory chips 111 and memory chips 112 can be changed according to the actual design, and is not limited to Figure 1The embodiments are not limited thereto. The following paragraphs are mainly explained with the aid of the memory chip 111.
[0039] In some embodiments, the memory controller 120 is configured to access the memory chip 111 to enter the memory chip 111 into a write leveling mode. The memory controller 120 is configured to input a data strobe signal DQS to the memory chip 111 in the write leveling mode.
[0040] Next, the memory controller 120 is configured to adjust a plurality of signal edges of the data strobe signal DQS to sample a clock state of a clock signal CLK in the memory chip 111 in the write leveling mode.
[0041] Further, the memory chip 111 is configured to generate a data signal DQ according to the data strobe signal DQS in the write leveling mode. The memory controller 120 is configured to determine a type of the memory chip 111 according to the data signal DQ in the write leveling mode.
[0042] In some embodiments, the memory controller 120 is further configured to compensate the memory chip 111 according to the type of the memory chip 111 in the write leveling mode. In some embodiments, the memory controller 120 is further configured to adjust a delay time of the data strobe signal DQS relative to the clock signal CLK in the write leveling mode.
[0043] In some embodiments, the memory chip 111 and the memory chip 112 both comprise synchronous dynamic random access memory (SDRAM). In some embodiments, the memory chip 111 and the memory chip 112 both can be double data rate (DDR) synchronous dynamic random access memory (SDRAM). In some embodiments, the memory chip 111 and the memory chip 112 can be third generation double data rate synchronous dynamic random access memory to fifth generation double data rate synchronous dynamic random access memory, or next generation double data rate synchronous dynamic random access memory.
[0044] In some embodiments, the data strobe signal DQS and the data signal DQ are both bidirectional transmission signals.
[0045] In some embodiments, to make the test system 100 of the present case easy to understand, please refer to Figure 1 . Figures 1 to 6B . Figure 2 A step flow diagram of a test method 200 according to some embodiments of the present case is shown. Figure 3 and Figure 5 A signal timing diagram of the test system 100 according to some embodiments of the present case is shown. Figure 4A、 Figure 4B 、 Figure 6A and Figure 6B is a shmoo plot schematic diagram of a test system according to some embodiments. In some embodiments, the test method 200 includes steps 210-250, which will be described later.
[0046] In step 210, accessing the memory chips to enter a write leveling mode. In some embodiments, referring to Figure 1 and Figure 2 , each of the memory chip 111 and the memory chip 112 is accessed by the memory controller 120 of the test system 100 to enter a write leveling mode.
[0047] It should be noted that the purpose of the write leveling mode of the memory chip is to evenly use each block of the memory chip to avoid a specific block from becoming a damaged block due to overuse, thereby prolonging the service life of the memory chip.
[0048] In step 220, inputting a strobe signal to the memory chip in the write leveling mode. In some embodiments, referring to Figure 1 and Figure 2 , the strobe signal DQS is inputted to the memory chip 111 or the memory chip 112 by the memory controller 120 of the test system 100 in the write leveling mode.
[0049] In step 230, adjusting a plurality of signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip in the write leveling mode. In some embodiments, referring to Figures 1 to 3 , the plurality of signal edges of the strobe signal DQS is adjusted by the memory controller 120 of the test system 100 to sample the clock state of the clock signal CLK in the memory chip 111 and the memory chip 112 in the write leveling mode.
[0050] In some embodiments, referring to Figure 3 , the inverse clock signal CLKb is an inverse signal of the clock signal CLK. The inverse strobe signal DQSb is an inverse signal of the strobe signal DQS. It should be noted that a phase difference Φ (or a delay time) is formed between the clock signal CLK and the strobe signal DQS.
[0051] In some embodiments, referring to Figure 3 , a ratio of a first working period H of a high voltage level and a second working period L of a low voltage level of the clock signal CLK is not equal to one. The first working period H and the second working period L form a complete working period T of the clock signal CLK.
[0052] In some embodiments, referring to Figure 1 and Figure 3 , the ratio of the first duty cycle H of the high voltage level and the second duty cycle L of the low voltage level of the clock signal CLK can be adjusted by the memory controller 120.
[0053] In some embodiments, referring to Figure 1 and Figure 3 , and referring to the clock signal CLK and the DQS signal, the memory controller 120 is further configured to fix the rising edge RE1 of the DQS signal and to move the falling edge FE1 of the DQS signal to sample the clock state of the clock signal CLK, so as to detect the first change value of the data signal DQ and the second change value of the data signal DQ.
[0054] In some embodiments, the memory controller 120 is further configured to move the falling edge FE1 of the DQS signal to sample the clock signal CLK in at least one complete duty cycle T of the clock signal CLK.
[0055] In some embodiments, referring to Figure 1 and Figure 5 , and referring to the clock signal CLK and the DQS signal, the memory controller 120 is further configured to fix the falling edge FE1 of the DQS signal and to move the rising edge RE2 of the DQS signal to sample the clock state of the clock signal CLK, so as to detect the first change value of the data signal DQ and the second change value of the data signal DQ.
[0056] In some embodiments, the memory controller 120 is further configured to move the rising edge RE2 of the DQS signal to sample the clock signal CLK in at least one complete duty cycle T of the clock signal CLK.
[0057] In step 240, in the write equalization mode, the data signal is generated according to the DQS signal. In some embodiments, referring to Figure 1 and Figure 2 , the memory chip 111 and the memory chip 112 generate the data signal DQ according to the DQS signal in the write equalization mode, respectively.
[0058] In some embodiments, if one of the first change value of the data signal DQ and the second change value of the data signal DQ is detected, the memory chip 111 and the memory chip 112 are further configured to latch the data signal DQ.
[0059] In some embodiments, referring to Figure 1 , Figure 3 and Figures 4A to 4BWhen the memory controller 120 is also used to move the falling edge FE1 of the strobe signal DQS to sample the clock signal CLK, the falling edge FE1 of the strobe signal DQS samples the falling edge of the clock signal CLK, thereby causing the memory chip 111 and the memory chip 112 to generate a first change value of the data signal DQ.
[0060] Next, when the memory controller 120 continuously moves the falling edge FE1 of the strobe signal DQS to sample the clock signal CLK, the falling edge FE1 of the strobe signal DQS samples the rising edge of the clock signal CLK, thereby causing the memory chip 111 and the memory chip 112 to generate a second change value of the data signal DQ.
[0061] In some embodiments, if either a first change value or a second change value of the data signal DQ is detected, the memory controller 120 may further latch the data signal DQ.
[0062] In some embodiments, please refer to Figure 1 , Figure 3 and Figures 4A to 4B The memory controller 120 is used to generate, based on the first change value of the data signal DQ, such as Figure 4A The first shmoo diagram is shown.
[0063] In some embodiments, the memory controller 120 is configured to generate, based on a second change value of the data signal DQ, such as Figure 4B The second shmoo diagram is shown. It should be noted that... Figure 4A and Figure 4B The vertical axis of the shmoo plot shows the working period (or absolute clock period tCK) of the clock signal CLK, in nanoseconds (ns). The horizontal axis represents the ratio of the two write equalization time parameters (tWLS / tWLH).
[0064] In some embodiments, please refer to Figure 1 , Figure 5 and Figures 6A to 6B When the memory controller 120 is also used to move the rising edge RE2 of the strobe signal DQS to sample the clock signal CLK, the rising edge RE2 of the strobe signal DQS samples the rising edge of the clock signal CLK, thereby causing the memory chips 111 and 112 to generate a first change value of the data signal DQ.
[0065] Next, when the memory controller 120 is also used to continuously move the rising edge RE2 of the strobe signal DQS to sample the clock signal CLK, the rising edge RE2 of the strobe signal DQS samples the falling edge of the clock signal CLK, so as to make the memory chip 111 and the memory chip 112 generate the second change value of the data signal DQ.
[0066] In some embodiments, referring to Figure 1 , Figure 5 and Figures 6A to 6B , the memory controller 120 is used to generate a first shmoo diagram according to the first change value of the data signal DQ as shown in Figure 6A .
[0067] In some embodiments, the memory controller 120 is used to generate a second shmoo diagram according to the second change value of the data signal DQ as shown in Figure 6B . It should be noted that the vertical axis of the shmoo diagrams shown in Figure 6A and Figure 6B is the operating period (or absolute clock period tCK) of the clock signal CLK, which is in units of nanoseconds (ns). The horizontal axis is the ratio of the two write leveling time parameters (tWLS / tWLH).
[0068] In step 250, according to the data signal in the write leveling mode, the types of the memory are determined. In some embodiments, referring to Figure 1 and Figure 2 , the memory controller 120 of the test system 100 determines the types of the memory chip 111 and the memory chip 112 according to the data signal DQ in the write leveling mode.
[0069] In some embodiments, referring to Figure 1 , Figures 4A to 4B , if the first change value of the data signal DQ as shown in FIG. 4A is detected, the memory controller 120 is also used to determine that the first type of the memory chip 111 and the memory chip 112 is that the clock state of the clock signal CLK changes with the falling edge of the strobe signal DQS.
[0070] In some embodiments, referring to Figure 1 , Figures 6A to 6B , if the second change value of the data signal DQ as shown in FIG. 6B is detected, the memory controller 120 is also used to determine that the first type of the memory chip 111 and the memory chip 112 is that the clock state of the clock signal CLK changes with the rising edge of the strobe signal DQS.
[0071] According to the foregoing embodiments, the test system and the test method are provided to adjust the duty cycle of the clock signal and the signal edge of the DQS signal of the memory, so as to study two memories and improve the write leveling mode of the memory.
[0072] Although the present application has been disclosed with reference to the detailed embodiments, the present application is not limited to the detailed embodiments. Therefore, the scope of the present application should be defined by the appended claims, not by the detailed embodiments.
[0073] Various modifications and improvements can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application. Based on the foregoing embodiments, all modifications and improvements made to the present application are also encompassed within the scope of the present application.
[0074]
Symbol Description
[0075] 100: test system
[0076] 111: memory chip
[0077] 112: memory chip
[0078] 120: memory controller
[0079] DQS: DQS signal
[0080] CLK: clock signal
[0081] DQ: data signal
[0082] 200: method
[0083] 210-250: steps
[0084] CLKb: inverted clock signal
[0085] DQSb: inverted DQS signal
[0086] RE1-RE2: rising edge
[0087] FE1-FE2: falling edge
[0088] H: first duty cycle
[0089] L: second duty cycle
[0090] T: duty cycle
[0091] Φ: phase difference
Claims
1. A test method characterized by, Comprising: accessing a memory chip to enter the memory chip into a write leveling mode; in the write leveling mode, inputting a strobe signal to the memory chip; in the write leveling mode, adjusting a plurality of signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip; in the write leveling mode, generating a data signal according to the strobe signal; and in the write leveling mode, determining a plurality of types of the memory according to the data signal, wherein the adjusting of the plurality of signal edges of the strobe signal to sample the clock state of the clock signal in the memory chip in the write leveling mode comprises: fixing a falling edge of the strobe signal; and moving a rising edge of the strobe signal to sample the clock state of the clock signal, thereby detecting a first change value of the data signal and a second change value of the data signal. a ratio of a first duty cycle of a high voltage level of the clock signal and a second duty cycle of a low voltage level of the clock signal is not equal to one. the adjusting of the plurality of signal edges of the strobe signal to sample the clock state of the clock signal in the memory chip in the write leveling mode comprises:
2. The test method of claim 1, wherein, fixing a rising edge of the strobe signal; and 3. The test method of claim 2, wherein, moving a falling edge of the strobe signal to sample the clock state of the clock signal, thereby detecting a first change value of the data signal and a second change value of the data signal. the generating of the data signal according to the strobe signal in the write leveling mode comprises: latching the data signal if one of the first change value of the data signal and the second change value of the data signal is detected. the determining of the plurality of types of the memory according to the data signal in the write leveling mode comprises:
4. The test method of claim 3, wherein, generating two shmoo charts according to the first change value of the data signal, the second change value of the data signal and the strobe signal. the determining of the plurality of types of the memory according to the data signal in the write leveling mode further comprises:
5. The test method of claim 4, wherein, if the first change value of the data signal is detected, determining a first type of the memory chip as the clock state of the clock signal changes with the falling edge of the strobe signal. the determining of the plurality of types of the memory according to the data signal in the write leveling mode further comprises:
6. The test method of claim 5, wherein, if the second change value of the data signal is detected, determining a second type of the memory chip as the clock state of the clock signal changes with the rising edge of the strobe signal. further comprising:
7. The test method of claim 6, wherein, compensating the memory chip according to the plurality of types of the memory chip in the write leveling mode. the compensating of the memory chip according to the plurality of types of the memory chip in the write leveling mode comprises:
8. The test method of claim 1, wherein, adjusting a delay time of the strobe signal relative to the clock signal in the write leveling mode. comprising:
9. The test method of claim 8, wherein, a memory chip; and 10. A test system, characterized by The memory controller is coupled to the memory chip and is configured to access the memory chip to enter the memory chip into a write leveling mode. In the write leveling mode, the memory controller is configured to input a strobe signal to the memory chip. In the write leveling mode, the memory controller is configured to adjust a plurality of signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip. In the write leveling mode, the memory chip is configured to generate a data signal based on the strobe signal. In the write leveling mode, the memory controller is configured to determine a plurality of types of the memory based on the data signal. In the write leveling mode, the memory controller is further configured to fix a falling edge of the strobe signal and to move a rising edge of the strobe signal to sample the clock state of the clock signal, so as to detect a first change value of the data signal and a second change value of the data signal.
11. The test system of claim 10, wherein, A ratio of a first duty cycle of a high voltage level of the clock signal and a second duty cycle of a low voltage level of the clock signal is not equal to one.
12. The test system of claim 11, wherein, In the write leveling mode, the memory controller is further configured to fix the rising edge of the strobe signal and to move the falling edge of the strobe signal to sample the clock state of the clock signal, so as to detect the first change value of the data signal and the second change value of the data signal.
13. The test system of claim 12, wherein, If one of the first change value of the data signal and the second change value of the data signal is detected, the memory chip is further configured to latch the data signal.
14. The test system of claim 13, wherein, In the write leveling mode, the memory controller is further configured to generate two shmoo graphs based on the first change value of the data signal, the second change value of the data signal and the strobe signal.
15. The test system of claim 14, wherein, If the first change value of the data signal is detected, the memory controller is further configured to determine a first type of the memory chip as the clock state of the clock signal changes with the falling edge of the strobe signal.
16. The test system of claim 15, wherein, If the second change value of the data signal is detected, the memory controller is further configured to determine a second type of the memory chip as the clock state of the clock signal changes with the rising edge of the strobe signal.
17. The test system of claim 10, wherein, In the write leveling mode, the memory controller is further configured to compensate the memory chip based on the plurality of types of the memory chip.
18. The test system of claim 17, wherein, In the write leveling mode, the memory controller is further configured to adjust a delay time of the strobe signal relative to the clock signal.
Citation Information
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DDR controller write-in equalization method, device and system and storage computer
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