Method and apparatus for determining sub-chip of quantum chip, and electronic device

Abstract

The present disclosure provides a method and device for determining a sub-chip of a quantum chip, and an electronic device, and relates to the technical field of computers, in particular to the technical field of quantum computing and chip characterization. According to a pre-characterization map of the quantum chip, a first number of quantum bits required to be used is determined. The pre-characterization map is a 45° diagonal square tiling map configuration with a rectangular contour. The pre-characterization map includes a plurality of first nodes corresponding to a plurality of quantum bits of the quantum chip. According to the first number, first row and column number information of an initial configuration is determined. According to the first row and column number information, a plurality of candidate characterization maps are determined from the pre-characterization map. Each candidate characterization map includes a plurality of second nodes corresponding to part of the quantum bits of the quantum chip. The connectivity of a plurality of candidate sub-chips corresponding to the plurality of candidate characterization maps is determined. According to the connectivity, a target sub-chip is determined from the plurality of candidate sub-chips. According to the present disclosure, the best-performing sub-chip can be selected from the quantum chip.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of quantum computing and chip fabrication technology. Background Technology

[0002] Quantum computing has become a crucial area of ​​research and development in both academia and industry in recent years. Compared to traditional computing, quantum computing has demonstrated significant advantages in solving problems such as large number factorization. Furthermore, it holds importance for cutting-edge research in areas such as quantum many-body systems and quantum chemical simulations. In terms of hardware implementation, quantum computing offers various technological solutions, including superconducting circuits, ion traps, and photonic quantum computing. Benefiting from its long decoherence time, ease of manipulation and readout, and strong scalability, superconducting circuits are considered the most promising candidate for quantum computing hardware. Summary of the Invention

[0003] This disclosure provides a method, apparatus, and electronic device for determining sub-chips of a quantum chip.

[0004] According to one aspect of this disclosure, a method for determining a sub-chip of a quantum chip is provided, comprising:

[0005] Based on the pre-detailed pattern of the quantum chip, the first number of qubits to be used is determined. The pre-detailed pattern is a 45° oblique square tessellation configuration with a rectangular outline. The pre-detailed pattern includes multiple first nodes that correspond one-to-one with multiple qubits of the quantum chip.

[0006] Based on the first quantity, determine the number of rows and columns of the initial configuration;

[0007] Based on the first row and column number information, multiple candidate characterization patterns are determined from the pre-characterization pattern, wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip;

[0008] Determine the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns; and

[0009] The target sub-chip is determined from multiple candidate sub-chips based on connectivity.

[0010] According to another aspect of this disclosure, a device for determining a sub-chip of a quantum chip is provided, comprising:

[0011] The first determining module is used to determine the first number of qubits to be used based on the pre-detailed pattern of the quantum chip, wherein the pre-detailed pattern is a 45° oblique square tessellation configuration with a rectangular outline, and the pre-detailed pattern includes multiple first nodes that correspond one-to-one with multiple qubits of the quantum chip;

[0012] The second determining module is used to determine the number of rows and columns of the initial configuration based on the first quantity.

[0013] The third determining module is used to determine multiple candidate characterization patterns from the pre-characterization pattern based on the first row and column number information, wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip;

[0014] The fourth determining module is used to determine the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns; and

[0015] The fifth determination module is used to determine the target sub-chip from multiple candidate sub-chips based on connectivity.

[0016] According to another aspect of this disclosure, an electronic device is provided, comprising:

[0017] At least one processor; and

[0018] The memory is communicatively connected to the at least one processor; wherein,

[0019] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform any of the methods described in the present disclosure.

[0020] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to perform any of the methods according to embodiments of this disclosure.

[0021] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements any of the methods according to embodiments of this disclosure.

[0022] According to the technology disclosed herein, the sub-chip with the best performance can be selected in a quantum chip.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0024] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0025] Figure 1 This is a schematic diagram of a method for determining a sub-chip of a quantum chip according to an embodiment of the present disclosure;

[0026] Figure 2This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0027] Figure 3 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0029] Figure 5 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0030] Figure 6 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0031] Figure 7 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0032] Figure 8 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0033] Figure 9 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0034] Figure 10 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0035] Figure 11 This is a schematic diagram of a first topological structure diagram of a quantum chip pre-etched according to an embodiment of the present disclosure;

[0036] Figure 12 This is a schematic diagram of a candidate pattern of a quantum chip according to an embodiment of the present disclosure;

[0037] Figure 13 This is a schematic diagram of a candidate pattern of a quantum chip according to an embodiment of the present disclosure;

[0038] Figure 14 This is a schematic diagram of a candidate pattern of a quantum chip according to an embodiment of the present disclosure;

[0039] Figure 15 This is a schematic diagram of a target sub-chip of a quantum chip according to an embodiment of the present disclosure;

[0040] Figure 16 This is a schematic diagram of a device for determining a sub-chip of a quantum chip according to an embodiment of the present disclosure;

[0041] Figure 17 This is a block diagram of an electronic device used to implement the method for determining the sub-chip of a quantum chip according to embodiments of the present disclosure. Detailed Implementation

[0042] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0043] like Figure 1 As shown, this disclosure provides a method for determining a sub-chip of a quantum chip, including:

[0044] Step S101: Determine the first number of qubits to be used based on the pre-detailed pattern of the quantum chip, wherein the pre-detailed pattern is a 45° oblique square tessellation configuration with a rectangular outline, and the pre-detailed pattern includes multiple first nodes that correspond one-to-one with multiple qubits of the quantum chip.

[0045] Step S102: Determine the number of rows and columns of the initial configuration based on the first quantity.

[0046] Step S103: Based on the first row and column number information, determine multiple candidate characterization patterns from the pre-characterization pattern, wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip.

[0047] Step S104: Determine the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns.

[0048] Step S105: Determine the target sub-chip from multiple candidate sub-chips based on connectivity.

[0049] According to the embodiments of this disclosure, it should be noted that:

[0050] A pre-detailed pattern can be understood as a first topological structure diagram containing distance weights, pre-detailed based on the chip information of a quantum chip. The structure of the first topological structure diagram depends on the number of qubits contained in the quantum chip and the communication relationships between them. Depending on the number of qubits and the different communication relationships between them, the first topological structure diagram of the quantum chip can be determined as follows: Figure 2The rectangular tiling structure is shown. The first topological graph, containing distance weight information, can be understood as the distance weight between the qubits corresponding to the two nodes connected by the associated edges on each edge of the first topological graph. Chip information can be understood as information that can be directly read from the quantum chip, including but not limited to the number of qubits, quantum gate information, and the fidelity between each qubit. The distance weight between each qubit can be determined based on whether there is a communication relationship between the qubits and / or communication overhead.

[0051] The first quantity can be understood as the number of qubits contained in the sub-chip to be determined from the quantum chip. That is to say, the number of second nodes used to characterize the sub-chip contained in each candidate pattern is consistent with the first quantity.

[0052] A quantum subchip can be understood as a chip composed of a subset of the qubits of a quantum chip. In practical applications of quantum computers, not all the qubits on a quantum chip are necessarily used. Therefore, a subset of qubits can be selected from a given quantum chip, and a superconducting quantum subchip can be virtually constructed. This allows the qubits of the subchip to be used to perform corresponding computational tasks, saving the overall computational resources of the quantum chip.

[0053] The square tessellation of a rectangular outline can be understood as a tessellation composed of squares with equal side lengths, where each point and edge overlaps. The rectangular outline itself can be understood as a rectangle cut from the tessellation, with each side of the rectangle having a square side parallel to it. A 45° oblique square tessellation of a rectangular outline refers to a rectangle cut from the tessellation, where each side of the rectangle has a square side forming a 45° angle with it, considering only the points and edges inside the rectangle. A 45° oblique square tessellation of a rectangular outline is shown below. Figure 2 , Figure 3 As shown, it is specifically defined as:

[0054] Define the set of first nodes, i.e., the point set:

[0055] V m,n,c ={(j,k)|(j+k)mod 2=c,j=0,1,…,m-1,k=0,1,…,n-1}

[0056] Where j and k are the coordinates of the first node on the X and Y axes, m represents the number of columns of the square tessellation pattern of the rectangular outline, and n represents the number of rows of the square tessellation pattern of the rectangular outline; c represents the first angle parameter, c = 0 or 1. The first angle parameter can be understood as the shape of the target area of ​​the pre-characterized map (e.g., the lower left corner), and 0 indicates that the target area is an "X" shape (e.g., the lower left corner). Figure 2 As shown), 1 indicates that the target area is a rhombus (e.g. Figure 3 (As shown).

[0057] Define the connecting edges between each first node, i.e., the set of undirected edges:

[0058]

[0059] Here, v1 and v2 represent any two first nodes, and E represents the edge connecting the two first nodes.

[0060] Based on V m,n and E m,n , constitute as Figure 2 , Figure 3 The plan view G shown m,n,c =(V m,n,c E m,n,c That is, a 45° tessellation pattern of squares with a rectangular outline in m columns and n rows, where m and n are both positive integers.

[0061] A candidate characterization can be understood as a configuration diagram obtained by transforming the initial configuration based on a traversal search of the pre-characterization diagram, and the number of second nodes contained therein is consistent with the first number of qubits required according to the computational task. For example, such as Figure 2 As shown, the quantum chip includes Q0 to Q10. 15 There are 16 fully functional qubits, corresponding to 16 nodes in the first topological diagram. Based on the quantum gate information in the quantum chip's chip information, it can be seen that Q0 communicates with Q1, Q3 communicates with Q1 and Q4, Q6 communicates with Q4 and Q7, and Q9 communicates with Q7 and Q... 10 There is a communication relationship, Q 15 There is a communication relationship with Q2 and Q5, Q 14 It has communication relationships with Q5 and Q8, Q 13 With Q8 and Q 11 There is a communication relationship, Q 12 With Q 11 There are communication relationships: Q1 communicates with Q0, Q2, Q3, and Q5; Q4 communicates with Q6, Q8, Q3, and Q5; and Q7 communicates with Q6, Q8, Q9, and Q1. 11 There is a communication relationship, Q 10 With Q9, Q 11 There is a communication relationship. When the number of qubits required for the computational task is determined to be six, then... Figure 2 The configuration of the target sub-chip consisting of six qubits is determined in the first topological structure diagram of the quantum chip.

[0062] Connectivity can be calculated using any method available in the prior art, and no specific limitation is made here.

[0063] The specific shape of the initial configuration can be selected and adjusted as needed. The initial configuration consists of multiple third nodes and edges connecting each third node. The second number of third nodes in the initial configuration is greater than the first number of qubits required by the sub-chip. Based on the second number of third nodes in the initial configuration, a candidate characterization pattern is formed. Since the number of second nodes in the candidate characterization pattern is the same as the first number, the candidate characterization pattern shape can be formed by reducing the number of nodes based on the initial configuration.

[0064] The first row and column information includes at least the number of rows and columns in the initial configuration. For example, when Figure 4 The diagram shows the initial configuration, which has 4 rows and 4 columns. Furthermore, when... Figure 2 When the pre-drawing pattern of the quantum chip is shown, it can be based on... Figure 4 The initial configuration, in Figure 2 Multiple candidate characterization images were generated through the process.

[0065] The initial configuration includes information about the number of rows and columns in the first row, and may also include information about the second angle parameter. The second angle parameter can be understood as the shape of the target area (e.g., the lower left corner) of the initial configuration. When the second angle parameter is 0, it means that the target area is "X" shaped, and when the second angle parameter is 1, it means that the target area is a rhombus.

[0066] According to the technology of this disclosure, in quantum computers such as superconducting circuits, quantum dots, and NV (nitrogen-vacancy centers), due to topological constraints, two qubits may not necessarily form a two-qubit gate. Considering that in actual operation of quantum circuits, it is likely that not all qubits on the quantum chip will be used, a key issue is how to select suitable qubits on a given quantum chip to run the corresponding quantum circuit while ensuring optimal overall performance of the selected qubits. The method of this disclosure can effectively solve this problem. Using this method, several qubits conforming to the target configuration can be selected from a specific quantum chip to form a sub-chip, thereby optimizing the overall performance of the sub-chip and meeting the requirements of the computing task. On a rectangular outline with a 45° angled square tessellation pattern, even with a specified number of qubits for a sub-chip, the number of candidate characterization patterns is exponentially large. The method described in this disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, avoiding the exponential traversal of candidate characterization patterns. Furthermore, it can efficiently determine the target sub-chip even when the number of target qubits, t, is relatively large. The method described in this disclosure has a wide range of applications, suitable for determining sub-chips from quantum chips with different structures and technical approaches. The method described in this disclosure is highly practical, as the selection of certain qubits is a practical issue of concern in the industry now and in the future. The method described in this disclosure has high computational efficiency. Under applicable conditions, the sub-chip determination method proposed in this disclosure can efficiently calculate the optimal qubits constituting the sub-chip, with low computational complexity and high efficiency.

[0067] In one example, such as Figure 4 As shown, the pre-pattern of the quantum chip has m=4 columns, n=4 rows, and the first angle parameter = 0, which corresponds to G. m,n,c =G 4,4,0 .like Figure 5 As shown, the pre-pattern of the quantum chip has m=4 columns, n=5 rows, and the first angle parameter = 0, which corresponds to G. m,n,c =G 4,5,0 .like Figure 6 As shown, the pre-pattern of the quantum chip has m=5 columns, n=4 rows, and the first angle parameter = 0, which corresponds to G. m,n,c =G 5,4,0 .like Figure 7 As shown, the pre-pattern of the quantum chip has 5 columns, 5 rows, and the first angle parameter is 0, which corresponds to G. m,n,c =G 5,5,0 .like Figure 8 As shown, the pre-pattern of the quantum chip has m=4 columns, n=4 rows, and the first angle parameter = 1, which corresponds to G. m,n,c =G4,4,1 .like Figure 9 As shown, the pre-pattern of the quantum chip has m=4 columns, n=5 rows, and the first angle parameter = 1, which corresponds to G. m,n,c =G 4,5,1 .like Figure 10 As shown, the pre-pattern of the quantum chip has m=5 columns, n=4 rows, and the first angle parameter = 1, which corresponds to G. m,n,c =G 5,4,1 .like Figure 11 As shown, the pre-pattern of the quantum chip has 5 columns, 5 rows, and a first angle parameter of 1, corresponding to G. m,n,c =G 5,5,1 .

[0068] In one example, the method for determining the sub-chip of the quantum chip according to this disclosure embodiment includes steps S101 to S105, and further includes:

[0069] This includes information about the target sub-chip, the number of qubits contained in the target sub-chip, and the correlation information established between the qubits; and

[0070] Store the associated information.

[0071] According to the technology of the present disclosure embodiments, the number of repetitive calculations of the sub-chip can be reduced. When the same quantum circuit (quantum chip) is executed multiple times, that is, when the same number of qubits are used to perform calculations, it is not necessary to recalculate the qubits used by the sub-chip each time. Instead, the qubits can be stored locally or in the cloud in a certain data structure, and the associated information can be obtained directly from the local or cloud location, thereby quickly calling the sub-chip to perform calculation tasks.

[0072] In one embodiment, the method for determining the sub-chip of the quantum chip according to the present disclosure includes steps S101 to S105, and further includes:

[0073] Step S106: Based on the chip information of the quantum chip, determine the number of qubits and the quantum gate information of the quantum chip, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip.

[0074] Step S107 determines the first topological structure diagram of the quantum chip based on the quantity information and quantum gate information. The first topological structure diagram is composed of multiple first nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip.

[0075] Step S108: Determine the distance weights between each qubit based on the quantum gate information.

[0076] Step S109: Obtain the pre-printed pattern of the quantum chip based on the distance weight and the first topological structure diagram.

[0077] According to the embodiments of this disclosure, it should be noted that:

[0078] The quantum chip disclosed in this embodiment can be understood as a chip that has been manufactured but whose quantum chip layout is unknown. The quantum chip layout includes the arrangement and interconnection of each quantum bit. The required quantum chip can be manufactured based on the quantum chip layout.

[0079] Chip information can be understood as information that can be directly read from a quantum chip, including but not limited to information on the number of qubits, quantum gate information, and the fidelity between each qubit.

[0080] Quantitative information can characterize the total number of qubits contained in a quantum chip, or it can characterize the number of undamaged, intact qubits contained in a quantum chip.

[0081] Quantum gate information characterizes the communication relationship between the qubits of a quantum chip. It can be understood that quantum gate information can be used to know whether any two qubits are directly or indirectly connected.

[0082] The first topological structure graph is formed by multiple first nodes and edges connecting the first nodes. Each first node represents a qubit, and each first node can have corresponding coordinates in the coordinate system of the first topological structure graph. An edge connecting two adjacent first nodes indicates that the qubits corresponding to those first nodes have a communication relationship. When any two qubits are directly coupled, there is a communication relationship between them. When any two qubits are indirectly coupled through other qubits, there is a communication relationship between them and those other qubits.

[0083] The distance weight between each qubit can be determined based on whether there is a communication relationship and / or communication overhead between the qubits.

[0084] The pre-detailed pattern of a quantum chip can be understood as the distance weight between the qubits corresponding to the two first nodes connected by the associated edges on each edge of the first topology diagram.

[0085] Two directly adjacent qubits can be understood as being adjacent on a quantum chip when a two-qubit quantum gate is applied.

[0086] According to the technology of this disclosure, an efficient and systematic method for characterizing a quantum chip is provided. This method can graphically describe a pre-characterized pattern of a quantum chip using its chip information, even when the topological structure of a quantum chip already manufactured by another party is unknown. Furthermore, based on the pre-characterized pattern determined by a first topological structure and distance weights, the distance characteristics of the quantum chip can be quantitatively described, providing an operable method for efficiently drawing quantum chip topological structure diagrams. When the pre-characterized pattern of a manufactured quantum chip is unknown, it can be efficiently generated to facilitate subsequent computational tasks. In practical applications of quantum computers, not all qubits on a quantum chip are necessarily used. Therefore, how to select a portion of qubits on a given quantum chip and virtually construct a superconducting quantum sub-chip becomes a crucial issue. After generating the pre-characterized pattern of the quantum chip using the method of this disclosure, a second topological diagram of the desired sub-chip (composed of a portion of the qubits of the quantum chip) can be efficiently and systematically characterized based on the pre-characterized pattern, thereby enabling the selection of a portion of qubits on the quantum chip to form a sub-chip, which can then be used to perform subsequent computational tasks. The technology disclosed herein has a wide range of applications, applicable to quantum chips with different structures, and is not limited by the implementation method of quantum chips. The technology disclosed herein is highly systematic and architectural, capable of systematically characterizing quantum chips and quantum sub-chips, providing a system architecture for subsequent research. The technology disclosed herein is highly operable, enabling efficient and convenient drawing of topological structure diagrams of quantum chips with different structures, as well as the topological structure diagrams of their sub-chips. The technology disclosed herein is highly practical, helping researchers further study the optimal sub-chip problem on quantum chips and providing strong support for solving practical problems.

[0087] In one example, based on the quantity information in the quantum chip's chip information, it can be known that the quantum chip includes Q0 to Q... 15 There are 16 fully functional qubits. Based on the quantum gate information in the quantum chip's chip information, it can be determined that Q0 communicates with Q1, Q3 communicates with Q1 and Q4, Q6 communicates with Q4 and Q7, and Q9 communicates with Q7 and Q... 10 There is a communication relationship, Q 15 There is a communication relationship with Q2 and Q5, Q 14 It has communication relationships with Q5 and Q8, Q 13 With Q8 and Q 11 There is a communication relationship, Q 12 With Q 11 There are communication relationships: Q1 communicates with Q0, Q2, Q3, and Q5; Q4 communicates with Q6, Q8, Q3, and Q5; and Q7 communicates with Q6, Q8, Q9, and Q1. 11 There is a communication relationship, Q10 With Q9, Q 11 There is a communication relationship. Based on the above information, a graph can be drawn in a custom coordinate system as follows. Figure 2 The first topological structure diagram is shown. Further, based on the quantum gate information, the distance weights between each qubit of the quantum chip are determined. Based on the distance weights and the first topological structure diagram, a pre-detailed pattern of the quantum chip is obtained.

[0088] In one example, the first topological graph consists of a set of points containing multiple first nodes and a set of edges containing multiple edges. The multiple first nodes correspond to multiple qubits of the quantum chip. The multiple edges correspond to the communication relationships between directly adjacent qubits. Specifically, a quantum chip C with N qubits has a set of points Q on its qubits. Using the qubits as the first nodes in the first topological graph, i.e., using Q as the set of points in the first topological graph, an undirected edge is connected between two qubits that can operate a two-bit quantum gate. As the undirected edge set of the topological graph, an undirected graph G = (Q, E) is constructed, which serves as the first topological graph of the quantum chip C. Specifically, when {Q... i Q j When}∈E, then the quantum bit Q can be... i Q j When a two-qubit quantum gate is applied, the quantum bit Q is called a quantum bit. i Q j They are adjacent on the quantum chip C.

[0089] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, wherein step S108: determining the distance weight between each qubit based on quantum gate information, including:

[0090] Based on quantum gate information, each pair of directly adjacent qubits in the quantum chip is determined.

[0091] Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits.

[0092] The distance weights between each quantum bit are determined based on the fidelity.

[0093] According to the embodiments of this disclosure, it should be noted that:

[0094] The method of calculating distance weights based on fidelity can be selected and adjusted as needed. For example, let Q... i With Q j For any two adjacent qubits on the quantum chip C, the distance d(Q) between them is... i Qj It can be based on Q i With Q j The fidelity F(Q) between two qubit gates i Q j The definition is given by () and there are no restrictions here. For example:

[0095] d(Q i Q j )=1-F(Q i Q j ) or d(Q i Q j ) = -log a F(Q i Q j )

[0096] Among them, F(Q) i Q j ()∈[0,1], a is a fixed constant greater than 0 and not equal to 1. We can take a=e as a natural constant. The choice of a here will not make a practical difference to the scheme.

[0097] Determining the distance weights between each qubit can be understood as determining the distance weights between any two directly adjacent or indirectly adjacent qubits in a quantum chip.

[0098] According to the technology of this disclosure, the weight distance between any two directly adjacent qubits and the weight distance between any two indirectly adjacent qubits can be accurately calculated based on the fidelity of the two-qubit gates between directly adjacent qubits. This facilitates the planning of the target qubits required for the computational task based on the distance weights between each qubit.

[0099] In one example, the process of determining the distance weights includes:

[0100] Define the distance between adjacent qubits, and then define the distance between any two qubits based on this. Let Q be the distance between adjacent qubits. i With Q j For any two adjacent qubits on the quantum chip C, the distance d(Q) between them is... i Q j It can be based on Q i With Q j The fidelity F(Q) between two qubit gates i Q j The definition is given by () and there are no restrictions here. For example:

[0101] d(Q i Q j )=1-F(Q i Qj ) or d(Q i , Q j ) = -log a F(Q i , Q j )

[0102] where F(Q i , Q j ) ∈ [0, 1], a is a fixed constant greater than 0 and not equal to 1, and a = e can be taken as the natural constant.

[0103] Further, if each element in the quantum bit sequence is adjacent to the previous element on the quantum chip C (t, j are non - negative integers, j < t), and all elements are pairwise different, then the quantum bit sequence p is called a path connecting the quantum bits . The distance d(p) of the path p is defined as the sum of the distances between each two consecutive quantum bits in the quantum bit sequence p Thus, the distance between quantum bits can be extended to the non - adjacent case, that is, the distance between two non - directly adjacent quantum bits Q i , Q j is defined as the minimum value of the distances of the paths connecting these two quantum bits. In particular, when the path does not exist, the distance is defined as positive infinity.

[0104] d Q (Q i , Q j ) = min{d(p) | the path p ∈ Q t connects Q i and Q j , t is a non - negative integer}.

[0105] In one implementation, according to the fidelity, determine the distance weights between each quantum bit, including:

[0106] According to the fidelity, determine the first distance weight between each two directly adjacent quantum bits.

[0107] According to the first distance weight, determine the second distance weight between each two indirectly adjacent quantum bits.

[0108] Based on the first distance weight and the second distance weight, obtain the distance weights between each quantum bit.

[0109] According to the technology of this disclosure, the weight distance between any two directly adjacent qubits and the weight distance between any two indirectly adjacent qubits can be accurately calculated based on the fidelity of the two-qubit gates between directly adjacent qubits. This facilitates the planning of the target qubits required for the computational task based on the distance weights between each qubit.

[0110] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, wherein step S107: determining the first topological structure diagram of the quantum chip based on quantity information and quantum gate information, including:

[0111] The target drawing function is determined based on the quantitative information and the quantum gate information.

[0112] Based on the target drawing function, a first topological structure diagram is used to determine the target structural shape of the quantum chip.

[0113] According to the embodiments of this disclosure, it should be noted that:

[0114] The target drawing function can be understood as a drawing function that can draw the first topological structure diagram of the target structure shape. With the quantity and quantum gate information remaining constant, the target drawing function can also be different depending on the requirements. That is to say, even when the number of qubits and the communication relationships between them are fixed, different first topological structure diagrams can be obtained by adjusting the layout positions (coordinates) of the nodes corresponding to each qubit.

[0115] For example, a quantum chip includes Q0 to Q10. 15 There are 16 fully functional qubits. Based on the quantum gate information in the quantum chip's chip information, it can be determined that Q0 communicates with Q1, Q3 communicates with Q1 and Q4, Q6 communicates with Q4 and Q7, and Q9 communicates with Q7 and Q... 10 There is a communication relationship, Q 15 There is a communication relationship with Q2 and Q5, Q 14 It has communication relationships with Q5 and Q8, Q 13 With Q8 and Q 11 There is a communication relationship, Q 12 With Q 11 There are communication relationships: Q1 communicates with Q0, Q2, Q3, and Q5; Q4 communicates with Q6, Q8, Q3, and Q5; and Q7 communicates with Q6, Q8, Q9, and Q1. 11 There is a communication relationship, Q 10 With Q9, Q 11There is a communication relationship. Based on this, the target drawing function can be determined as a function capable of drawing the first topological structure diagram of the rectangular tiled structure, as needed.

[0116] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips is provided. This method can, even when the topological structure of a quantum chip already manufactured by another party is unknown, utilize the chip information of the quantum chip and a determined drawing function to graphically describe a first topological structure diagram of the quantum chip. Furthermore, based on a pre-characterized diagram determined by the first topological structure diagram and distance weights, the distance characteristics of the quantum chip can be quantitatively described, providing an operable method for efficiently drawing quantum chip topological structure diagrams. The technology of this disclosure is highly operable and can efficiently and easily draw topological structure diagrams of quantum chips with different structures, as well as the topological structure diagrams of their sub-chips.

[0117] In one implementation, the target drawing function is determined based on quantity information and quantum gate information, including:

[0118] Based on the quantity information and quantum gate information, multiple initial drawing functions are determined.

[0119] Based on preset characterization rules and multiple initial drawing functions, the target drawing function is determined.

[0120] According to the embodiments of this disclosure, it should be noted that:

[0121] With the quantity and gate information remaining constant, the drawing function can differ depending on the requirements. That is, even when the number of qubits and the communication relationships between them are fixed, multiple different initial drawing functions can be obtained by adjusting the layout positions (coordinates) of the nodes corresponding to each qubit. Each initial drawing function will produce a different first topological structure diagram.

[0122] Based on preset characterization rules, a target drawing function that meets the requirements can be selected from multiple initial drawing functions. These preset characterization rules can be selected and adjusted according to the computational task or design needs. For example, preset characterization rules may include: requiring the generated first topology graph to include intersecting edges; requiring the generated first topology graph to include intersecting edges; requiring the generated first topology to be a 45° angled square tiling structure; requiring the generated first topology to be arranged along the X-axis; requiring the generated first topology to be arranged along the Y-axis, etc.

[0123] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips and their sub-chips is provided. Based on a first topological structure diagram of the quantum chip, a distance weight is introduced to quantitatively describe the distance characteristics of the quantum chip and its sub-chips. Simultaneously, a drawing function is proposed, providing an operable method for efficiently drawing the topological structure diagram of the quantum chip and its sub-chips, and representing the relationship between the sub-chip's topological structure diagram and its parent chip. By combining the concepts of topological structure diagram and distance weight, and introducing a drawing function for the quantum chip, a novel characterization method for quantum chips is presented, and this method can be further extended to quantum sub-chips.

[0124] In one implementation, generating a first topological structure diagram of the target structure shape of the quantum chip according to a target drawing function includes:

[0125] Based on the point drawing function in the target drawing function, multiple first nodes representing each qubit are generated in the coordinate system, where each of the multiple first nodes contains corresponding coordinate information.

[0126] Based on the edge drawing function in the target drawing function, an edge is generated between the two first nodes corresponding to every two adjacent qubits, where the two first nodes belong to multiple first nodes.

[0127] Based on the positional relationships between multiple first nodes and edges, the correspondence information between multiple first nodes and multiple qubits of the quantum chip is determined.

[0128] Based on multiple first nodes, edges, and corresponding relationship information, a first topological structure diagram of the target structure shape of the quantum chip is generated.

[0129] According to the embodiments of this disclosure, it should be noted that:

[0130] The point drawing function is used to draw each first node in the first topology graph. Each first node drawn contains coordinate information.

[0131] The edge drawing function is used to draw the edges between qubits that have a communication relationship.

[0132] Determining the correspondence between multiple first nodes and multiple qubits of a quantum chip can be understood as mapping the qubits of the quantum chip corresponding to each first node. For example, a quantum chip may include Q0 to Q... 11 There are a total of 12 fully functional qubits, which correspond to 12 first nodes drawn in the first topology diagram. Among them, Q2: (0,2) represents the qubit Q2 associated with the quantum chip of the first node, and the coordinates of the first node are (0,2).

[0133] According to the technology of this disclosure, an efficient and systematic method for characterizing quantum chips and their sub-chips is provided. Based on a first topological structure diagram of the quantum chip, a distance weight is introduced to quantitatively describe the distance characteristics of the quantum chip and its sub-chips. Simultaneously, a drawing function is proposed, providing an operable method for efficiently drawing the topological structure diagram of the quantum chip and its sub-chips, and representing the relationship between the sub-chip's topological structure diagram and its parent chip. By combining the concepts of topological structure diagram and distance weight, and introducing a drawing function for the quantum chip, a novel characterization method for quantum chips is presented, and this method can be further extended to quantum sub-chips.

[0134] In one implementation, the first topological graph consists of a set of points containing multiple first nodes and a set of edges containing multiple edges. The multiple first nodes correspond to multiple qubits of the quantum chip. The multiple edges correspond to the communication relationships between directly adjacent qubits. Specifically, for a quantum chip C with N qubits, the qubits on it are defined as forming a set of points W. Using the qubits as the first nodes in the first topological graph, i.e., using W as the set of points in the first topological graph, an undirected edge is connected between two qubits that can operate a two-bit quantum gate, i.e., W is defined as the set of points in the first topological graph. As the undirected edge set of the topological graph, an undirected graph G = (Q, E) is constructed, which serves as the first topological graph of the quantum chip C. Specifically, when {Q... i Q j When}∈E, then the quantum bit Q can be... i Q j When a two-qubit quantum gate is applied, the quantum bit Q is called a quantum bit. i Q j They are adjacent on the quantum chip C.

[0135] Define the distance between adjacent qubits, and then define the distance between any two qubits based on this. Let Q be the distance between adjacent qubits. i With Q j For any two adjacent qubits on the quantum chip C, the distance d(Q) between them is... i Q j It can be based on Q i With Q j The fidelity F(Q) between two qubit gates i Q j The definition is given by () and there are no restrictions here. For example:

[0136] d(Q i Q j )=1-F(Q i Q j ) or d(Q i Q j ) = -loga F(Q i ,Q j )

[0137] where F(Q i ,Q j ) ∈ [0, 1], a is a fixed constant greater than 0 and not equal to 1, and a can be taken as a = e, the natural constant. The selection of a here will not make a practical difference to the scheme.

[0138] Furthermore, if each element in the quantum bit sequence is adjacent on the quantum chip C to the previous element (t, j are non - negative integers, j < t), and all elements are pairwise different, then the quantum bit sequence p is called a path connecting the quantum bits . The distance d(p) of the path p is defined as the sum of the distances between each two consecutive quantum bits in the quantum bit sequence p In this way, the distance between quantum bits can be extended to non - adjacent cases, that is, the distance between two non - directly adjacent quantum bits Q i ,Q j is defined as the minimum value of the distances of the paths connecting these two quantum bits. In particular, when the path does not exist, the distance is defined as positive infinity.

[0139] d Q (Q i ,Q j ) = min{d(p)| path p ∈ Q t connects Q i and Q j , t is a non - negative integer}.

[0140] When drawing the topological structure diagram of the quantum chip C on a plane, the quantum bit Q i can be drawn at the position g(Q i ) ∈ R 2 . If g: Q → R 2 is an injection, then it is called a drawing function of the quantum chip C, and its range is denoted as g(Q) = {g(Q i )|Q i ∈ Q}, where R is the set of real numbers. Based on g and g(Q), the inverse function g -1 : g(Q) → Q of g can be calculated. Here g -1 is a bijection, and then the quantum bit Q i and its drawing function image g(Q i ) can be identified.

[0141] Furthermore, we can define the target drawing function g(G) = g(Q), g(E)) for the first topological graph G = (Q, E), which is an undirected graph. The vertex set and edge set are represented by the vertex drawing function g(Q) and the edge drawing function g(E), respectively, where g(E) = {(g(Q)} i ),g(Q j )}|{Q i Q j}∈E}. Since graph G is isomorphic to graph g(G), the first topological graph G can also be equated with the target drawing function g(G) of the topological graph. Thus, a complete characterization of the quantum chip C can be obtained:

[0142] C=(Q,E,d Q ,g).

[0143] In one implementation, determining a target sub-chip from a plurality of candidate sub-chips based on connectivity includes:

[0144] Based on the distance weights between the qubits of the quantum chip, the distance weights between the qubits corresponding to each candidate pattern are determined.

[0145] Based on the distance weights between some qubits, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns is determined.

[0146] The target sub-chip is determined from multiple candidate sub-chips based on connectivity.

[0147] According to the technology of the embodiments of this disclosure, based on connectivity calculation, the most suitable sub-chip can be found quickly and accurately from the quantum chip.

[0148] In one example, based on the number of qubits required for the sub-chip, for the quantum chip C = (Q, E, d) Q Constructing a subset of qubits on g) Sub-chips can be defined similarly.

[0149] Where Q is the set of points of the quantum chip's qubits, E is the set of edges representing the communication relationships between the qubits of the quantum chip, and d Q Let be the distance weights between the qubits of the quantum chip, and g be the plotting function of the quantum chip. s The set of points representing the qubits of the sub-chip. Let d represent the set of edges that allow communication between the qubits of a sub-chip. s The distance weights between the qubits of the sub-chip. This is the function for drawing the sub-chip.

[0150] The point set Q of the sub-chip based on the point set Q of the quantum chip s We can define the first topological graph G = (Q, E) in Q. s The above restrictions, namely the second topology diagram This refers to the set of edges in the second topological graph.

[0151] Regarding d s There are several ways to define the choice: one is to choose d s =d Q One approach is to select all qubits on the quantum chip C when calculating the path; the other is based on d and Q. s ,definition Right now

[0152] At this point, when calculating the path, only set Q can be selected. s The qubits in the array.

[0153] Drawing function That is, the function g in the set Q s The limitations on the above. Similarly, the topology diagram of the sub-chip can be... Rather than drawing function like Equivalent to. inverse mapping That is, g -1 In g(Q) s Restrictions on )

[0154] In one example, the method for drawing the first topological structure diagram of a quantum chip includes: given a quantum chip C = (Q, E, d... Q Establish a Cartesian coordinate system on the plane (g). Traverse the quantum bits Q. i ∈Q, in the rectangular coordinate system g(Q) i Plot the qubit Q at () i Then iterate through the edges {Q} i Q j}∈E, connecting qubit Q i Q j .

[0155] In one example, the method for drawing the second topological structure diagram of the sub-chip includes: given a quantum chip C = (Q, E, d... Q Sub-chips on g) Traversing the Q qubit i ∈Q s Q i Change to highlighting (visual display). Then traverse the edges. Connecting qubit Q i Qj The border should be highlighted.

[0156] In one example, if quantum chip C m,n,c The topological structure diagram and a tessellation diagram G of a 45° oblique square with a rectangular outline. m,n,c Isomorphism is called quantum chip C m,n,c It is a quantum chip with a rectangular outline, consisting of m columns and n rows, arranged in a 45° angled square tessellation pattern. Let the isomorphic mapping be g:Q m,n,c →V m,n,c It can be used as a quantum chip C m,n,c The drawing function, where Q m,n,c It is a quantum chip C m,n,c The set consisting of all qubits. Based on this, let g be the set of all qubits. -1 (E m,n,c )={{g -1 (v1),g -1 (v2)}|{v1,v2}∈E m,n,c}, then the quantum chip C under study m,n,c Can be characterized as C m,n,c =(Q m,n,c ,g -1 (E m,n,c ),d,g), there are no additional restrictions on d here.

[0157] For example, when g(Q) i When )=((2i+c) / / n,(2i+c)mod n), we have g -1 (j,k)=Q (nj+k) / / 2 , where j and k satisfy (j+k)mod 2=c, / / denotes the floor division method, i.e., the largest integer not exceeding the quotient of the two numbers. For example Figure 6 As shown, on a quantum chip with a rectangular outline, featuring a 45° angled square tessellation pattern of m=5 columns and n=4 rows, the corresponding graph of each qubit and its plotted function image is displayed.

[0158] In one example, after determining the quantum chip C m,n,c =(Q m,n,c ,g -1 (E m,n,c Given that the number of qubits t required for the sub-chip is determined, d, g), d, g), and t, the number of qubits t required for the sub-chip is determined:

[0159] Define the qubits of the sub-chip and In C m,n,c adjacent paths

[0160] Define the set of qubits of the sub-chip

[0161] Define edge set

[0162] Define the metric function d p (i.e., distance weight) is or This leads to the sub-chip characterization. Can be used on sub-chip C p The connectivity α(C) p Modeling, such as or

[0163] Given a quantum chip C with a rectangular outline and a 45° angled square tessellation pattern. m,n,c =(Q m,n,c ,g -1 (E m,n,c Given the target number of qubits t∈[1,(mn+c) / / 2), find the qubit chip. Satisfying Q p There are exactly t elements such that the sub-chip C p The connectivity α(C) p (As small as possible)

[0164] To make the comparison meaningful, d p The same definition must be used, that is, either Regarding Q p It is always true, or Regarding Q p Heng was established.

[0165] In one embodiment, the method for determining a sub-chip of a quantum chip according to this disclosure includes steps S101 to S105, wherein step S101: determining a first number of qubits to be used based on a pre-pattern of the quantum chip, including:

[0166] Based on the pre-etched pattern of the quantum chip, the second row and column number information and the first angle parameter of the pre-etched pattern are determined, wherein the first angle parameter is used to characterize the image shape of the target region of the pre-etched pattern.

[0167] Based on the second row and column number information and the first angle parameter, determine the first number of qubits to be used.

[0168] According to the embodiments of this disclosure, it should be noted that:

[0169] The first angle parameter can be understood as the shape of the target area (e.g., the lower left corner) of the pre-defined map. 'c' can be used to represent the first angle parameter, where c = 0 or 1. Here, 0 indicates that the target area is an "X" shape (e.g., the lower left corner). Figure 2 As shown), 1 indicates that the target area is a rhombus (e.g. Figure 3 (As shown).

[0170] The second row and column information includes at least the number of rows and columns of the pre-etched pattern of the quantum chip. For example, when Figure 2 The image shown is a pre-drawn pattern with 4 rows and 8 columns.

[0171] According to the technology of this disclosure, by using the second row and column number information of the pre-etched pattern and the first angle parameter, a first number of qubits required for the target sub-chip to perform computing tasks can be determined on the quantum chip.

[0172] In one example, the first quantity can be calculated using the relationship between the second row and column number information and the first angle parameter, for example, t∈[1,(mn+c) / / 2), where t represents the first quantity, m represents the column number in the second row and column number information, and n represents the row number in the second row and column number information.

[0173] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, wherein step S102: determining the first row and column number information of the initial configuration according to a first quantity, including:

[0174] Step S1021: Determine the first parameter based on the first quantity.

[0175] Step S1022: Determine the first row and column information of the initial configuration based on the first parameter and the second row and column information of the pre-drawing pattern.

[0176] According to the embodiments of this disclosure, it should be noted that:

[0177] The first parameter can be understood as a constant calculated based on the first quantity.

[0178] The determination of the first row and column number information of the initial configuration based on the first parameter and the second row and column number information of the pre-characterized pattern can be understood as: determining the first row and column number information of the initial configuration based on the logical relationship between the row number and column number in the first parameter and the second row and column number information.

[0179] According to the technology of the embodiments of this disclosure, the first row and column number information that meets the computing requirements of the sub-chip can be accurately determined using the first parameter.

[0180] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, and steps S1021 and S1022, wherein step S1022: determining the first row and column number information of the initial configuration based on the first parameter and the second row and column number information of the pre-etched pattern, including:

[0181] If the first parameter and the second row and column number information of the pre-characterized image satisfy the first threshold, and the first quantity and the first parameter satisfy the second threshold, the first column number of the first group in the first row and column number information of the initial configuration is determined as the first parameter, the first row number of the first group is determined as the second parameter, the first column number of the second group is determined as the second parameter, and the first row number of the second group is determined as the first parameter.

[0182] According to the embodiments of this disclosure, it should be noted that:

[0183] According to embodiments of this disclosure, two sets of first row and column number information can be determined simultaneously. The first set of first row and column number information has the opposite row and column numbers to the second set.

[0184] The first and second thresholds can be selected and adjusted as needed, and no specific limitations are made here.

[0185] According to the technology of the embodiments of this disclosure, by utilizing the relationship between the first parameter and the second row and column number information, as well as the relationship between the first quantity and the first parameter, the first row and column number information that meets the computing requirements of the sub-chip can be accurately determined.

[0186] In one example, 'a' is defined as the first parameter, 't' as the first quantity, 'm' as the column number in the second row and column number information, and 'n' as the row number in the second row and column number information. Step S1022: Based on the first parameter and the second row and column number information of the pre-characterized pattern, determine the first row and column number information of the initial configuration, including:

[0187] If the first threshold a≤min(m,n) and the second threshold t≤a(a-1) / 2 are satisfied, then the information of the first row and column of the first group is returned, that is, the number of the first column m'=a and the number of the first row n'=a-1, and the information of the first row and column of the second group is returned, that is, the number of the first column m'=a-1 and the number of the first row n'=a.

[0188] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, and steps S1021 and S1022, wherein step S1022: determining the first row and column number information of the initial configuration based on the first parameter and the second row and column number information of the pre-etched pattern, including:

[0189] If the first parameter and the second row and column number information of the pre-characterized pattern satisfy the first threshold, and the first quantity and the first parameter do not satisfy the second threshold, then the first column number and the first row number in the first row and column number information of the initial configuration are determined to be the first parameter.

[0190] According to the embodiments of this disclosure, it should be noted that:

[0191] The first and second thresholds can be selected and adjusted as needed, and no specific limitations are made here.

[0192] According to the technology of the embodiments of this disclosure, by utilizing the relationship between the first parameter and the second row and column number information, as well as the relationship between the first quantity and the first parameter, the first row and column number information that meets the computing requirements of the sub-chip can be accurately determined.

[0193] In one example, 'a' is defined as the first parameter, 't' as the first quantity, 'm' as the column number in the second row and column number information, and 'n' as the row number in the second row and column number information. Step S1022: Based on the first parameter and the second row and column number information of the pre-characterized pattern, determine the first row and column number information of the initial configuration, including:

[0194] If the first threshold a≤min(m,n) is satisfied and the second threshold t≤a(a-1) / 2 is not satisfied, then return the first column number m'=a and the first row number n'=a.

[0195] In one embodiment, the method for determining the sub-chip of the quantum chip according to this disclosure includes steps S101 to S105, and steps S1021 and S1022, wherein step S1022: determining the first row and column number information of the initial configuration based on the first parameter and the second row and column number information of the pre-etched pattern, including:

[0196] Based on the second row and column number information of the pre-etched image, determine the total number of rows and columns of the pre-etched image.

[0197] If the first parameter and the second row and column number information do not meet the first threshold, and the total number of columns is less than the total number of rows, the first column number in the first row and column number information of the initial configuration is determined as the total number of columns, and the first row number in the first row and column number information is determined as the first parameter.

[0198] According to the embodiments of this disclosure, it should be noted that:

[0199] The total number of rows can be understood as the number of rows in the first topological structure diagram of the pre-drawing pattern of the quantum chip.

[0200] The total number of columns can be understood as the number of columns in the first topological structure diagram of the pre-drawn pattern of the quantum chip.

[0201] According to the technology of this disclosure embodiment, by utilizing the relationship between the first parameter and the second row and column number information, the first row and column number information that meets the sub-chip's computing requirements can be accurately determined.

[0202] In one example, 'a' is defined as the first parameter, 't' as the first quantity, 'm' as the column number in the second row and column number information, and 'n' as the row number in the second row and column number information. Step S1022: Based on the first parameter and the second row and column number information of the pre-characterized pattern, determine the first row and column number information of the initial configuration, including:

[0203] If the first threshold a ≤ min(m, n) is not satisfied and m < n, then return the first column number m' = m and the first row number

[0204] In one embodiment, the method for determining a sub-chip of a quantum chip according to an embodiment of the present disclosure includes steps S101 to S105, and steps S1021 and S1022, where step S1022: determining the first row-column number information of the initial configuration according to the first parameter and the second row-column number information of the pre-characterization graph, including:

[0205] Determine the total number of rows and the total number of columns of the pre-characterization graph according to the second row-column number information of the pre-characterization graph.

[0206] In the case where the first parameter and the second row-column number information do not satisfy the first threshold and the total number of columns is not less than the total number of rows, determine that the first column number in the first row-column number information of the initial configuration is the fourth parameter, and the first row number in the first row-column number information is the total number of rows.

[0207] According to the embodiment of the present disclosure, it should be noted that:

[0208] The total number of rows can be understood as the number of rows of the first topological structure diagram of the pre-characterization graph of the quantum chip.

[0209] The total number of columns can be understood as the number of columns of the first topological structure diagram of the pre-characterization graph of the quantum chip.

[0210] According to the technology of the embodiment of the present disclosure, by using the relationship between the first parameter and the second row-column number information, the first row-column number information that meets the calculation requirements of the sub-chip can be accurately determined.

[0211] In an example, define a as the first parameter, t represents the first quantity, m represents the number of columns in the second row-column number information, and n represents the number of rows in the second row-column number information. Step S1022: determining the first row-column number information of the initial configuration according to the first parameter and the second row-column number information of the pre-characterization graph, including:

[0212] If the first threshold a ≤ min(m, n) is not satisfied and m > n, then return the first column number The first row number n' = n.

[0213] In one embodiment, the method for determining a sub-chip of a quantum chip according to an embodiment of the present disclosure includes steps S101 to S105, where step S103: determining a plurality of candidate characterization graphs from the pre-characterization graph according to the first row-column number information, including:

[0214] Step S1031: determining a plurality of first configuration graphs corresponding to the initial configuration in the pre-characterization graph.

[0215] Step S1032: Determine the number of target nodes based on the first row and column number information and the second angle parameter of the initial configuration.

[0216] Step S1033: Based on the first row and column number information and the number of target nodes, determine the third node on the target boundary of the multiple first configuration diagrams.

[0217] Step S1034: Delete the third node on multiple first configuration diagrams to generate multiple candidate characterization diagrams.

[0218] In this case, the number of nodes contained in each candidate characterization is the same as the first number.

[0219] According to the embodiments of this disclosure, it should be noted that:

[0220] The first configuration diagram is a shape consistent with the initial configuration shape.

[0221] Based on the initial configuration, multiple first configuration graphs can be traversed in the first topological structure graph of the pre-determined graph. The number of multiple first configuration graphs can be adjusted as needed. For example, all first configuration graphs corresponding to the initial configuration in the pre-determined graph can be traversed exhaustively, which allows for more accurate determination of the target sub-chip with optimal connectivity based on all traversed first configuration graphs. Alternatively, traversal can be stopped after traversing a threshold number of first configuration graphs, which can improve traversal efficiency and further enhance the efficiency of determining the target sub-chip.

[0222] Determining a third node on the self-target boundary of multiple first configuration diagrams can be understood as determining a third node on the self-target boundary of each first configuration diagram. The self-target boundary of each first configuration diagram can be the boundary formed by any one or more sides of each first configuration diagram.

[0223] When it is determined that the first configuration diagram includes multiple self-target boundaries, a third node can be determined on one or more self-target boundaries of the first configuration diagram. The third node corresponds to a first node in the first topological structure diagram of the quantum chip; that is, the multiple first nodes include the third node.

[0224] Deleting a third node from multiple first configuration diagrams can be understood as deleting the third node identified in each first configuration diagram and canceling its connection with other nodes in that first configuration diagram, thereby forming a candidate characterization diagram corresponding to that first configuration diagram. This candidate characterization diagram is used to represent a candidate sub-chip. It should be noted that the "connection" mentioned here refers to the cancellation of the communication relationship between the third node and the original nodes in the first configuration. The reason why the third node and the original nodes in the first configuration could be associated is that they already had a direct communication relationship in the quantum chip. The purpose of canceling the communication relationship here is to prevent the corresponding sub-chip from using the communication relationship between the two when performing computational tasks.

[0225] The second angle parameter can be understood as the shape of the target area (e.g., the lower left corner) of the initial configuration. When the second angle parameter is 0, it means that the target area is "X" shaped. When the second angle parameter is 1, it means that the target area is rhomboid.

[0226] According to the technology of the present disclosure, on a 45° oblique square tiling pattern, even if the first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0227] In one embodiment, the method for determining a sub-chip of a quantum chip according to this disclosure includes steps S101 to S105, and steps S1031 to S1034, wherein step S1033: determining a third node on the target boundary of a plurality of first configuration diagrams based on the first row and column number information and the number of target nodes, including:

[0228] If the number of the first column in the first row and column information is less than the number of the first row, the target row of the multiple first configuration maps is determined as its own target boundary based on the pre-characterized map, wherein the target row is the outermost row located on the opposite sides of the multiple first configuration maps.

[0229] Based on the number of target nodes, determine the third node on its own target boundary.

[0230] According to the embodiments of this disclosure, it should be noted that:

[0231] The third node can be determined on the outermost rows on both sides of each first configuration diagram, or on the outermost row on one side.

[0232] According to the technology of the present disclosure, on a 45° oblique square tiling pattern, even if the first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0233] In one example, step S1033: Based on the first row and column number information and the number of target nodes, determine the third node on the target boundary of the multiple first configuration diagrams, including:

[0234] Input: The target number of qubits t, the number of columns m' and the number of rows n' of the initial configuration satisfy (m'n'-max(m',n')) / / 2 <t≤(m'n'+1) / / 2。

[0235] Output: A list of shapes (SHAPE) for a portion of a 45° angled square tessellation quantum chip containing t qubits. Specifically:

[0236] Step 1, initialize the shape list SHAPE = [];

[0237] Step 2, in parallel, for the initial configuration angle parameters c' = 0, 1, perform:

[0238] Step 2.1. If m'≤n', select σ = (m'n'+c') / / 2-t elements (nodes) from {(z,n'-1)|z=0,1,…,m'-1,(z+n'-1)mod2=c'} and {(z,0)|z=0,1,…,m'-1,zmod 2=c'} respectively. Remove these elements (nodes) from the re-initialized shape shape=[(x,y)|x=0,1,…,m'-1,y=0,1,…,n'-1,(x+y)mod2=c'] to obtain two updated shapes. Add them to the shape list SHAPE and proceed to step 2.3. Here, the two outermost σ elements can be selected, that is, the z1 elements with the smallest z value and the σ-z1 elements with the largest z value, where the non-negative integer z1 satisfies |2z1-σ|≤1.

[0239] Step 2.3: After all parallel operations in Step 2 are completed, proceed to Step 3.

[0240] Step 3: Return SHAPE as the output.

[0241] In one embodiment, the method for determining a sub-chip of a quantum chip according to this disclosure includes steps S101 to S105, and steps S1031 to S1034, wherein step S1033: determining a third node on the target boundary of a plurality of first configuration diagrams based on the first row and column number information and the number of target nodes, including:

[0242] If the number of the first column in the first row and column information is greater than the number of the first row, the target column of the multiple first configuration diagrams is determined as its own target boundary based on the pre-characterized map. The target column is the outermost column located on the opposite sides of the multiple first configuration diagrams.

[0243] Based on the number of target nodes, determine the third node on its own target boundary.

[0244] According to the embodiments of this disclosure, it should be noted that:

[0245] The third node can be determined on the outermost columns on both sides of each first configuration diagram, or on the outermost column on one side.

[0246] According to the technology of the present disclosure, on a 45° oblique square tiling pattern, even if the first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0247] In one example, step S1033: Based on the first row and column number information and the number of target nodes, determine the third node on the target boundary of the multiple first configuration diagrams, including:

[0248] Input: The target number of qubits t, the initial configuration number of columns m' and rows n' satisfying (m'n'-max(m',n')) / / 2 <t≤(m'n'+1) / / 2。

[0249] Output: A list of shapes (SHAPE) for a portion of a 45° angled square tessellation quantum chip containing t qubits. Specifically:

[0250] Step 1, initialize the shape list SHAPE = [];

[0251] Step 2, in parallel, for the initial configuration angle parameters c' = 0, 1, perform:

[0252] Step 2.2. If m'≥n', select σ = (m'n'+c') / / 2-t elements (nodes) from {(m'-1,z)|z=0,1,…,n'-1,(z+m'-1)mod2=c'} and {(0,z)|z=0,1,…,n'-1,z mod 2=c'} respectively. Remove these elements (nodes) from the re-initialized shape shape=[(x,y)|x=0,1,…,m'-1,y=0,1,…,n'-1,(x+y)mod 2=c'] to obtain two updated shapes. Add them to the shape list SHAPE and proceed to step 2.3. Here, the two outermost σ elements can be selected, that is, the z1 elements with the smallest z value and the σ-z1 elements with the largest z value, where the non-negative integer z1 satisfies |2z1-σ|≤1.

[0253] Step 2.3: After all parallel operations in Step 2 are completed, proceed to Step 3.

[0254] Step 3: Return SHAPE as the output.

[0255] In one embodiment, the method for determining a sub-chip of a quantum chip according to this disclosure includes steps S101 to S105, and steps S1031 to S1034, wherein step S1033: determining a third node on the target boundary of a plurality of first configuration diagrams based on the first row and column number information and the number of target nodes, including:

[0256] Given that the number of the first column in the first row and column information is equal to the number of the first row, the target columns and target rows of multiple first configuration diagrams are determined as their own target boundaries based on the pre-characterized diagram. The target rows are the outermost rows located on the opposite sides of the multiple first configuration diagrams, and the target columns are the outermost columns located on the opposite sides of the multiple first configuration diagrams.

[0257] Based on the number of target nodes, determine the third node on its own target boundary.

[0258] According to the embodiments of this disclosure, it should be noted that:

[0259] The third node can be determined on the outermost rows on both sides of each first configuration diagram, or on the outermost row on one side.

[0260] The third node can be determined on the outermost columns on both sides of each first configuration diagram, or on the outermost column on one side.

[0261] According to the technology of the present disclosure, on a 45° oblique square tiling pattern, even if the first number of qubits of a specified sub-chip is specified, the corresponding candidate characterization patterns are exponentially numerous. The method provided in the present disclosure first determines the initial configuration and then determines the candidate characterization patterns based on it, which can avoid the traversal of exponentially numerous candidate characterization patterns, and can still efficiently determine the target sub-chip when the number of target qubits t is relatively large.

[0262] In one example, step S1033: Based on the first row and column number information and the number of target nodes, determine the third node on the target boundary of the multiple first configuration diagrams, including:

[0263] Input: The target number of qubits t, the initial configuration number of columns m' and rows n' satisfying (m'n'-max(m',n')) / / 2 <t≤(m'n'+1) / / 2。

[0264] Output: A list of shapes (SHAPE) for a portion of a 45° angled square tessellation quantum chip containing t qubits. Specifically:

[0265] Step 1, initialize the shape list SHAPE = [];

[0266] Step 2, in parallel, for the initial configuration angle parameters c' = 0, 1, perform:

[0267] Step 2.1. If m' = n', select σ = (m'n'+c') / / 2-t elements (nodes) from {(z,n'-1)|z=0,1,…,m'-1,(z+n'-1)mod2=c'} and {(z,0)|z=0,1,…,m'-1,z mod 2=c'} respectively. Remove these elements (nodes) from the re-initialized shape shape=[(x,y)|x=0,1,…,m'-1,y=0,1,…,n'-1,(x+y)mod 2=c'] to obtain two updated shapes. Add them to the shape list SHAPE. Here, the two outermost σ elements can be selected, that is, the z1 elements with the smallest z value and the σ-z1 elements with the largest z value, where the non-negative integer z1 satisfies |2z1-σ|≤1; and

[0268] Step 2.2. If m' = n', select σ = (m'n'+c') / / 2-t elements (nodes) from {(m'-1,z)|z=0,1,…,n'-1,(z+m'-1)mod 2=c'} and {(0,z)|z=0,1,…,n'-1,z mod 2=c'} respectively. Remove these elements (nodes) from the re-initialized shape shape=[(x,y)|x=0,1,…,m'-1,y=0,1,…,n'-1,(x+y)mod 2=c'] to obtain two updated shapes. Add them to the shape list SHAPE and proceed to step 2.3. Here, the two outermost σ elements can be selected, that is, the z1 elements with the smallest z value and the σ-z1 elements with the largest z value, where the non-negative integer z1 satisfies |2z1-σ|≤1.

[0269] Step 2.3: After all parallel operations in Step 2 are completed, proceed to Step 3.

[0270] Step 3: Return SHAPE as the output.

[0271] In one embodiment, the method for determining sub-chips of a quantum chip according to this disclosure includes steps S101 to S105, wherein step S104: determining the connectivity of multiple candidate sub-chips corresponding to multiple candidate patterns, including:

[0272] Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps is calculated based on the qubits corresponding to multiple second nodes on the characterization path of multiple candidate characterization maps.

[0273] According to the embodiments of this disclosure, it should be noted that:

[0274] The connectivity algorithm can be any existing algorithm for calculating connectivity, and no specific limitation is made here.

[0275] The characterization path of a candidate characterization map can be understood as the connection line that links all the second nodes of the candidate characterization map.

[0276] Each candidate pattern represents a candidate sub-chip. The qubits corresponding to the second node in the candidate pattern and the communication relationships between these qubits can characterize the corresponding candidate sub-chip.

[0277] According to the steps of the embodiments of this disclosure, the connectivity of the candidate sub-chip corresponding to each candidate pattern can be calculated.

[0278] According to the technology of this disclosure, the connectivity calculation efficiency of the candidate sub-chip can be improved by using only the qubits corresponding to multiple second nodes on the characterization path of the candidate characterization map to calculate the connectivity of the corresponding candidate sub-chip.

[0279] In one implementation, a connectivity algorithm is used to calculate the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps, based on the qubits corresponding to multiple second nodes on the characterization path of multiple candidate characterization maps. This includes:

[0280] Based on the distance weights between multiple qubits in the pre-characterized pattern, the first distance weight between the qubits corresponding to each two adjacent second nodes on the characterization path of multiple candidate characterization patterns is determined.

[0281] The average distance weight is determined based on the first distance weight.

[0282] Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps is calculated based on the average distance weight.

[0283] According to the embodiments of this disclosure, it should be noted that:

[0284] When the candidate characterization pattern corresponds to a loop configuration, any two second nodes in the loop configuration can be used as qubits located at the two ends of the characterization path of the candidate characterization pattern.

[0285] The characterization path of a candidate characterization map can be understood as the connection line that links all the second nodes of the candidate characterization map.

[0286] Each candidate pattern represents a candidate sub-chip. The qubits corresponding to the second node in the candidate pattern and the communication relationships between these qubits can characterize the corresponding candidate sub-chip.

[0287] According to the steps of the embodiments of this disclosure, the connectivity of the candidate sub-chip corresponding to each candidate pattern can be calculated.

[0288] According to the technology of this disclosure, by using the qubits corresponding to multiple first nodes (including the qubits corresponding to second nodes) on the pre-drawn pattern of the quantum chip to calculate the connectivity of the corresponding candidate sub-chip, the accuracy of the connectivity calculation of the candidate sub-chip can be improved, making the calculated connectivity of each candidate sub-chip more valuable for reference.

[0289] In one implementation, determining a first distance weight between qubits corresponding to every two adjacent second nodes on the characterization path of multiple candidate characterization maps, based on distance weights between multiple qubits of a pre-characterized map, includes:

[0290] The second distance weight between each pair of adjacent qubits in the quantum chip is determined based on the distance weight between multiple qubits in the pre-drawn pattern.

[0291] Based on the second distance weight, the first distance weight between the qubits corresponding to each two adjacent second nodes on the characterization path of multiple candidate characterization maps is determined.

[0292] According to the embodiments of this disclosure, it should be noted that:

[0293] The distance weights can be obtained based on the information contained in the pre-detailed pattern. Specifically, the pre-detailed pattern contains information about the distance weights between any two qubits of the quantum chip.

[0294] According to the technology of the present disclosure embodiments, by utilizing the numerical information of the distance weights of each qubit contained in the pre-pattern, the connectivity of multiple candidate sub-chips corresponding to multiple candidate patterns can be calculated quickly and accurately.

[0295] It should be noted that in any embodiment of this disclosure, the parentheses () in the function represent an immutable tuple, [] represent a mutable list, and {} represent a set; the elements in the tuple and list are ordered and numbered starting from 0, while the elements in the set are unordered and non-repeating.

[0296] In one example, the method for determining the sub-chip of the quantum chip according to an embodiment of this disclosure includes the following main program:

[0297] Input: Quantum chip C m,n,c =(Q m,n,c ,g -1 (E m,n,c ),d,g), the number of target qubits t∈[1,(mn+c) / / 2), and the connectivity function α.

[0298] Output: Approximate optimal sub-chip

[0299] Step 1. Initialize the minimum connectivity α min =+∞;

[0300] Step 2. Input the number of columns m, the number of rows n, the angular parameter c, and the target number of qubits t into program 2 to obtain the initial configuration number of columns m' and the number of rows n' or two sets of solutions (m1', n1') and (m2', n2');

[0301] Step 3. If Step 2 yields m' and n', then input the target number of qubits t, the initial number of columns m', and the number of rows n' into Program 1, and record the output as the shape list SHAPE; otherwise, i.e., if Step 2 yields two solutions (m1', n1') and (m2', n2'), then (in sequence or in parallel) input the target number of qubits t, the initial number of columns m', and the initial number of rows n' into Program 1, and record the output as the shape list SHAPE; j 'and the number of rows n j Input program 1, and record the output as a shape list SHAPE j , where j = 1, 2, and let the shape list SHAPE = SHAPE1 + SHAPE2;

[0302] Step 4. Traverse the shapes shape∈SHAPE, and execute the following steps in sequence:

[0303] Step 3.1. Calculate or read from storage to obtain the minimum value x of the 0th element of all elements (nodes) of shape. min Maximum value x max The minimum value of the first element y min Maximum value y max ;

[0304] Step 3.2. Read from storage or calculate based on c' = (x0 + y0) mod 2 to obtain the initial configuration angle parameter c' of the shape, where (x0, y0) is any element (node) in the shape;

[0305] Step 3.2. Iterate through x = -x min ,-x min +1,…,m-1-x max Execute in sequence:

[0306] Step 3.2.1. Iterate through y = -y min ,-y min +1,…,n-1-y max Execute in sequence:

[0307] Step 3.2.1.1. If (x+y+c')mod2=c, then denote the set Q. p ={g -1 (shape[j]+(x,y))|j=0,1,…,t-1}, where shape[j] represents the j-th element of shape, numbered starting from 0, proceed to step 3.2.1.2; otherwise, proceed directly to step 3.2.1.3;

[0308] Step 3.2.1.2. Based on set Q p Calculate α(C) p If its value is less than α min Assign the value to α min and order Enter step 3.2.1.3; otherwise, directly enter step 3.2.1.3;

[0309] Step 3.2.1.3. After completing the traversal of steps 3.2.1 and 3.2, enter step 4;

[0310] Step 4. Return As an approximately optimal sub-chip.

[0311] Among them, program 2 includes:

[0312] If the first threshold a ≤ min(m, n) is satisfied and the second threshold t ≤ a(a - 1) / 2 is satisfied, then return the first row and column number information of the first group, that is, the first column number m' = a, the first row number n' = a - 1, and the first row and column number information of the second group, that is, the first column number m' = a - 1, the first row number n' = a.

[0313] If the first threshold a ≤ min(m, n) is satisfied and the second threshold t ≤ a(a - 1) / 2 is not satisfied, then return the first column number m' = a, the first row number n' = a.

[0314] If the first threshold a ≤ min(m, n) is not satisfied and m < n, then return the first column number m' = m, the first row number

[0315] If the first threshold a ≤ min(m, n) is not satisfied and m > n, then return the first column number The first row number n' = n.

[0316] Among them, program 1 includes:

[0317] If m' ≤ n', then select σ = (m'n' + c') / / 2 - t elements (nodes) from {(z, n' - 1)|z = 0, 1,..., m' - 1, (z + n' - 1) mod 2 = c'} and {(z, 0)|z = 0, 1,..., m' - 1, z mod 2 = c'}, remove these elements (nodes) from the re-initialized shape shape = [(x, y)|x = 0, 1,..., m' - 1, y = 0, 1,..., n' - 1, (x + y) mod 2 = c'] to obtain 2 updated shapes, add them to the shape list SHAPE, and enter step 2.3; when selecting, the σ elements at the two ends can be selected, that is, the z1 elements with the smallest z value and the σ - z1 elements with the largest value, where the non-negative integer z1 satisfies |2z1 - σ| ≤ 1;

[0318] If m'≥n', then select σ = (m'n'+c') / / 2-t elements (nodes) from {(m'-1,z)|z=0,1,…,n'-1,(z+m'-1)mod 2=c'} and {(0,z)|z=0,1,…,n'-1,z mod 2=c'} respectively. Remove these elements (nodes) from the re-initialized shape shape=[(x,y)|x=0,1,…,m'-1,y=0,1,…,n'-1,(x+y)mod 2=c'] to obtain two updated shapes. Add them to the shape list SHAPE and proceed to step 2.3. Here, the two outermost σ elements can be selected, that is, the z1 elements with the smallest z value and the σ-z1 elements with the largest z value, where the non-negative integer z1 satisfies |2z1-σ|≤1.

[0319] If m' = n', then in {(z,n'-1)|z=0,1,…,m'-1,(z+n'-1)mod 2=c'} and {(z,0)|z=0,1,…,m'-1,z mod 2=c'} respectively. Select σ = (m'n'+c') / / 2-t elements (nodes) from the reinitialized shape shape = [(x,y)|x=0,1,…,m'-1,y=0,1,…,n'-1,(x+y)mod2=c'] to obtain two updated shapes, and add them to the shape list SHAPE. Here, the two outermost σ elements can be selected, i.e., the smallest z1 and the largest σ-z1, where the non-negative integer z1 satisfies |2z1-σ|≤1. Also, in {(m'-1,z)|z=0,1,…,n'-1,(z+m'-1)mod2=c'}, respectively... Select σ = (m'n'+c') / / 2-t elements (nodes) from {2=c'} and {(0,z)|z=0,1,…,n'-1,zmod2=c'}. Remove these elements (nodes) from the reinitialized shape shape=[(x,y)|x=0,1,…,m'-1,y=0,1,…,n'-1,(x+y)mod 2=c'] to obtain two updated shapes. Add them to the shape list SHAPE and proceed to step 2.3. Here, the two outermost σ elements can be selected, that is, the z1 elements with the smallest z value and the σ-z1 elements with the largest z value, where the non-negative integer z1 satisfies |2z1-σ|≤1.

[0320] In one example, it is described as "in quantum chip C". 6,7,0Taking the search for a sub-chip with a target number of qubits t=14 as an example, the column number m=6, the row number n=7, the angular parameter c=0, and the target number of qubits t=14 are input into program 2. In program 2, a=6 is calculated, and two solutions (m1',n1')=(6,5) and (m2',n2')=(5,6) are returned. In step 3 of the main program, program 1 is called, and a shape list SHAPE containing 8 shapes is obtained, such as... Figures 12 to 14 Three of the possible shapes are shown. Figures 12 to 14 The (m',n',c') represent the shapes of the initial configurations (5,6,0), (5,6,1), and (6,5,0) with a target number of qubits t=14. In step 3.2.1.1 of the main program, when x=0 and y=1, the sub-chip C corresponding to the initial configuration (m',n',c')=(5,6,1) is... p like Figure 15 The dashed lines in the diagram represent the structures corresponding to the nodes they connect.

[0321] like Figure 16 As shown, this disclosure provides an apparatus for determining a sub-chip of a quantum chip, comprising:

[0322] The first determining module 1601 is used to determine the first number of qubits to be used based on the pre-detailed pattern of the quantum chip, wherein the pre-detailed pattern is a 45° oblique square tessellation configuration with a rectangular outline, and the pre-detailed pattern includes a plurality of first nodes corresponding one-to-one with a plurality of qubits of the quantum chip.

[0323] The second determining module 1602 is used to determine the first row and column number information of the initial configuration based on the first quantity.

[0324] The third determining module 1603 is used to determine multiple candidate characterization patterns from the pre-characterization pattern based on the first row and column number information, wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip.

[0325] The fourth determining module 1604 is used to determine the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization patterns.

[0326] The fifth determining module 1605 is used to determine the target sub-chip from multiple candidate sub-chips based on connectivity.

[0327] In one implementation, the first determining module 1601 is configured to:

[0328] Based on the pre-etched pattern of the quantum chip, the second row and column number information and the first angle parameter of the pre-etched pattern are determined, wherein the first angle parameter is used to characterize the image shape of the target region of the pre-etched pattern.

[0329] Based on the second row and column number information and the first angle parameter, determine the first number of qubits to be used.

[0330] In one implementation, the second determining module 1602 includes:

[0331] The first determining submodule is used to determine the first parameter based on the first quantity.

[0332] The second determining submodule is used to determine the first row and column number information of the initial configuration based on the first parameter and the second row and column number information of the pre-characterized pattern.

[0333] In one implementation, the second determining submodule is used to:

[0334] If the first parameter and the second row and column number information of the pre-characterized image satisfy the first threshold, and the first quantity and the first parameter satisfy the second threshold, the first column number of the first group in the first row and column number information of the initial configuration is determined as the first parameter, the first row number of the first group is determined as the second parameter, the first column number of the second group is determined as the second parameter, and the first row number of the second group is determined as the first parameter.

[0335] In one implementation, the second determining submodule is used to:

[0336] If the first parameter and the second row and column number information of the pre-characterized pattern satisfy the first threshold, and the first quantity and the first parameter do not satisfy the second threshold, then the first column number and the first row number in the first row and column number information of the initial configuration are determined to be the first parameter.

[0337] In one implementation, the second determining submodule is used to:

[0338] Based on the second row and column number information of the pre-etched image, determine the total number of rows and columns of the pre-etched image.

[0339] If the first parameter and the second row and column number information do not meet the first threshold, and the total number of columns is less than the total number of rows, the first column number in the first row and column number information of the initial configuration is determined as the total number of columns, and the first row number in the first row and column number information is determined as the first parameter.

[0340] In one implementation, the second determining submodule is used to:

[0341] Based on the second row and column number information of the pre-etched image, determine the total number of rows and columns of the pre-etched image.

[0342] If the first parameter and the number of rows and columns do not meet the first threshold, and the total number of columns is not less than the total number of rows, the first column in the first row and column information of the initial configuration is determined as the fourth parameter, and the first row in the first row and column information is determined as the total number of rows.

[0343] In one implementation, the third determining module 1603 includes:

[0344] The third determination submodule is used to determine multiple first configuration diagrams corresponding to the initial configuration in the pre-determined diagram.

[0345] The fourth determination submodule is used to determine the number of target nodes based on the first row and column number information and the second angle parameter of the initial configuration.

[0346] The fifth determination submodule is used to determine the third node on the target boundary of multiple first configuration diagrams based on the first row and column number information and the number of target nodes.

[0347] The generation determination submodule is used to delete third nodes on multiple first configuration diagrams and generate multiple candidate characterization diagrams.

[0348] In this case, the number of nodes contained in each candidate characterization is the same as the first number.

[0349] In one implementation, the fifth determining submodule is used to:

[0350] If the number of the first column in the first row and column information is less than the number of the first row, the target row of the multiple first configuration maps is determined as its own target boundary based on the pre-characterized map, wherein the target row is the outermost row located on the opposite sides of the multiple first configuration maps.

[0351] Based on the number of target nodes, determine the third node on its own target boundary.

[0352] In one implementation, the fifth determining submodule is used to:

[0353] If the number of the first column in the first row and column information is greater than the number of the first row, the target column of the multiple first configuration diagrams is determined as its own target boundary based on the pre-characterized map. The target column is the outermost column located on the opposite sides of the multiple first configuration diagrams.

[0354] Based on the number of target nodes, determine the third node on its own target boundary.

[0355] In one implementation, the fifth determining submodule is used to:

[0356] Given that the number of the first column in the first row and column information is equal to the number of the first row, the target columns and target rows of multiple first configuration diagrams are determined as their own target boundaries based on the pre-characterized diagram. The target rows are the outermost rows located on the opposite sides of the multiple first configuration diagrams, and the target columns are the outermost columns located on the opposite sides of the multiple first configuration diagrams.

[0357] Based on the number of target nodes, determine the third node on its own target boundary.

[0358] In one implementation, the fourth determining module 1604 includes:

[0359] Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps is calculated based on the qubits corresponding to multiple second nodes on the characterization path of multiple candidate characterization maps.

[0360] In one implementation, the fourth determining module 1604 includes:

[0361] The sixth determination submodule is used to determine the first distance weight between the qubits corresponding to each two adjacent second nodes on the characterization path of multiple candidate characterization maps, based on the distance weight between the multiple qubits of the pre-characterization map.

[0362] The seventh determination submodule is used to determine the average distance weight based on the first distance weight.

[0363] The computation submodule is used to calculate the connectivity of multiple candidate sub-chips corresponding to multiple candidate characterization maps based on the average distance weight using a connectivity algorithm.

[0364] In one implementation, the sixth determining submodule is used to:

[0365] The second distance weight between each pair of adjacent qubits in the quantum chip is determined based on the distance weight between multiple qubits in the pre-drawn pattern.

[0366] Based on the second distance weight, the first distance weight between the qubits corresponding to each two adjacent second nodes on the characterization path of multiple candidate characterization maps is determined.

[0367] In one implementation, it further includes:

[0368] The sixth determining module is used to determine the number of qubits and the quantum gate information of the quantum chip based on the chip information of the quantum chip. The quantum gate information represents the communication relationship between the qubits of the quantum chip.

[0369] The seventh determining module is used to determine the first topological structure diagram of the quantum chip based on the quantity information and the quantum gate information. The first topological structure diagram is composed of multiple first nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip.

[0370] The eighth determining module is used to determine the distance weights between each qubit based on the quantum gate information.

[0371] The generation module is used to obtain a pre-detailed pattern of the quantum chip based on the distance weights and the first topological structure diagram.

[0372] In one implementation, the eighth determining module is used to:

[0373] Based on quantum gate information, each pair of directly adjacent qubits in the quantum chip is determined.

[0374] Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits.

[0375] The distance weights between each quantum bit are determined based on the fidelity.

[0376] In one implementation, the seventh determining module is used to:

[0377] The target drawing function is determined based on the quantitative information and the quantum gate information.

[0378] Based on the target drawing function, a first topological structure diagram is used to determine the target structural shape of the quantum chip.

[0379] The specific functions and examples of each module and submodule of the apparatus in this disclosure can be found in the relevant descriptions of the corresponding steps in the above method embodiments, and will not be repeated here.

[0380] The acquisition, storage, and application of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0381] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0382] Figure 17 A schematic block diagram of an example electronic device 1700 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0383] like Figure 17As shown, device 1700 includes a computing unit 1701, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1702 or a computer program loaded into random access memory (RAM) 1703 from storage unit 1708. The RAM 1703 may also store various programs and data required for the operation of device 1700. The computing unit 1701, ROM 1702, and RAM 1703 are interconnected via bus 1704. Input / output (I / O) interface 1705 is also connected to bus 1704.

[0384] Multiple components in device 1700 are connected to I / O interface 1705, including: input unit 1706, such as a keyboard, mouse, etc.; output unit 1707, such as various types of displays, speakers, etc.; storage unit 1708, such as a disk, optical disk, etc.; and communication unit 1709, such as a network card, modem, wireless transceiver, etc. Communication unit 1709 allows device 1700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0385] The computing unit 1701 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1701 performs the various methods and processes described above, such as the method for determining sub-chips of a quantum chip. For example, in some embodiments, the method for determining sub-chips of a quantum chip can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1708. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1700 via ROM 1702 and / or communication unit 1709. When the computer program is loaded into RAM 1703 and executed by the computing unit 1701, one or more steps of the method for determining sub-chips of a quantum chip described above can be performed. Alternatively, in other embodiments, computing unit 1701 may be configured by any other suitable means (e.g., by means of firmware) to perform a method for determining sub-chips of the quantum chip.

[0386] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0387] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0388] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0389] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0390] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0391] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0392] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0393] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for determining a sub-chip of a quantum chip, comprising: Based on the pre-detailed pattern of the quantum chip, the first number of qubits to be used is determined, wherein the pre-detailed pattern is a rectangular outline with a 45° oblique square tessellation configuration, and the pre-detailed pattern includes a plurality of first nodes corresponding one-to-one with a plurality of qubits of the quantum chip; Based on the first quantity, determine the first row and column number information of the initial configuration; Based on the first row and column number information, multiple candidate characterization patterns are determined from the pre-characterization pattern, wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip; Determine the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization patterns; and Based on the connectivity, a target sub-chip is determined from the plurality of candidate sub-chips; Among them, based on the first row and column number information, multiple candidate characterization maps are determined from the pre-characterization map, including: In the pre-characterized diagram, a plurality of first configuration diagrams corresponding to the initial configuration are determined; The number of target nodes is determined based on the first row and column number information and the second corner parameter of the initial configuration; Based on the first row and column number information and the number of target nodes, a third node is determined on the target boundary of the plurality of first configuration diagrams; The third node is deleted from the plurality of first configuration diagrams to generate a plurality of candidate characterization diagrams; The number of nodes contained in each candidate characterization map is the same as the first number.

2. The method according to claim 1, wherein, Based on the pre-deciphered pattern of the quantum chip, determine the initial number of qubits required, including: Based on the pre-etched pattern of the quantum chip, the second row and column number information and the first angle parameter of the pre-etched pattern are determined, wherein the first angle parameter is used to characterize the image shape of the target region of the pre-etched pattern; Based on the second row and column number information and the first angle parameter, determine the first number of qubits to be used.

3. The method according to claim 1, wherein, Based on the first quantity, the first row and column number information of the initial configuration is determined, including: Based on the first quantity, determine the first parameter; Based on the first parameter and the second row and column number information of the pre-characterized pattern, the first row and column number information of the initial configuration is determined.

4. The method according to claim 3, wherein, Based on the first parameter and the second row and column number information of the pre-characterized pattern, the first row and column number information of the initial configuration is determined, including: When the first parameter and the second row and column number information of the pre-characterized pattern satisfy the first threshold, and the first quantity and the first parameter satisfy the second threshold, the first column number of the first group in the first row and column number information of the initial configuration is determined as the first parameter, the first row number of the first group is determined as the second parameter, the first column number of the second group is determined as the second parameter, and the first row number of the second group is determined as the first parameter.

5. The method according to claim 3, wherein, Based on the first parameter and the second row and column number information of the pre-characterized pattern, the first row and column number information of the initial configuration is determined, including: If the first parameter and the second row and column number information of the pre-characterized pattern satisfy the first threshold, and the first quantity and the first parameter do not satisfy the second threshold, then the first column number and the first row number in the first row and column number information of the initial configuration are determined to be the first parameter.

6. The method according to claim 3, wherein, Based on the first parameter and the second row and column number information of the pre-characterized pattern, the first row and column number information of the initial configuration is determined, including: Based on the second row and column number information of the pre-characterized image, determine the total number of rows and columns of the pre-characterized image; If the first parameter and the second row and column number information do not meet the first threshold, and the total number of columns is less than the total number of rows, the first column number in the first row and column number information of the initial configuration is determined to be the total number of columns, and the first row number in the first row and column number information is determined to be the first parameter.

7. The method according to claim 3, wherein, Based on the first parameter and the second row and column number information of the pre-characterized pattern, the first row and column number information of the initial configuration is determined, including: Based on the second row and column number information of the pre-characterized image, determine the total number of rows and columns of the pre-characterized image; If the first parameter and the second row and column number information do not meet the first threshold, and the total number of columns is not less than the total number of rows, the first column number in the first row and column number information of the initial configuration is determined as the fourth parameter, and the first row number in the first row and column number information is determined as the total number of rows.

8. The method according to claim 1, wherein, Based on the first row and column number information and the number of target nodes, a third node is determined on the target boundary of the plurality of first configuration diagrams, including: If it is determined that the number of the first column in the first row and column number information is less than the number of the first row, based on the pre-characterized map, the target row of the plurality of first configuration maps is determined as its own target boundary, wherein the target row is the row located at the outermost edge on both sides of the plurality of first configuration maps; Based on the number of target nodes, a third node is determined on the boundary of the target itself.

9. The method according to claim 1, wherein, Based on the first row and column number information and the number of target nodes, a third node is determined on the target boundary of the plurality of first configuration diagrams, including: If it is determined that the number of the first column in the first row and column number information is greater than the number of the first row, based on the pre-characterized map, the target column of the plurality of first configuration maps is determined as its own target boundary, wherein the target column is the outermost column located on the opposite sides of the plurality of first configuration maps; Based on the number of target nodes, a third node is determined on the boundary of the target itself.

10. The method according to claim 1, wherein, Based on the first row and column number information and the number of target nodes, a third node is determined on the target boundary of the plurality of first configuration diagrams, including: When it is determined that the number of the first column in the first row and column number information is equal to the number of the first row, based on the pre-characterized map, the target column and target row of the plurality of first configuration maps are determined as their own target boundaries, wherein the target row is the row located at the outermost edge on both sides of the plurality of first configuration maps, and the target column is the column located at the outermost edge on both sides of the plurality of first configuration maps; Based on the number of target nodes, a third node is determined on the boundary of the target itself.

11. The method according to claim 1, wherein, Determining the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization patterns includes: Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated based on the qubits corresponding to the multiple second nodes on the characterization paths of the multiple candidate characterization maps.

12. The method according to claim 11, wherein, Using a connectivity algorithm, based on the qubits corresponding to the multiple second nodes on the characterization paths of the multiple candidate characterization maps, the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated, including: Based on the distance weights between multiple qubits in the pre-characterized pattern, a first distance weight is determined between the qubits corresponding to each two adjacent second nodes on the characterization path of the multiple candidate characterization patterns. Based on the first distance weight, determine the average distance weight; Using the connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated based on the average distance weight.

13. The method according to claim 12, wherein, Based on the distance weights between multiple qubits in the pre-characterized pattern, a first distance weight is determined between the qubits corresponding to each pair of adjacent second nodes on the characterization path of the multiple candidate characterization patterns, including: Based on the distance weights between multiple qubits in the pre-etched pattern, a second distance weight is determined between every two adjacent qubits of the quantum chip; Based on the second distance weight, a first distance weight is determined between the qubits corresponding to each two adjacent second nodes on the characterization path of the plurality of candidate characterization maps.

14. The method according to any one of claims 1 to 13, further comprising: Based on the chip information of the quantum chip, the number of qubits and the quantum gate information of the quantum chip are determined, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip; Based on the quantity information and the quantum gate information, a first topological structure diagram of the quantum chip is determined, wherein the first topological structure diagram is composed of a plurality of first nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip; Based on the quantum gate information, determine the distance weights between each qubit; and Based on the distance weights and the first topological structure diagram, a pre-detailed pattern of the quantum chip is obtained.

15. The method according to claim 14, wherein, Based on the quantum gate information, the distance weights between each qubit are determined, including: Based on the quantum gate information, determine every two directly adjacent qubits in the quantum chip; Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits; Based on the fidelity, the distance weights between each quantum bit are determined.

16. The method of claim 14, wherein, Based on the quantity information and the quantum gate information, the first topological structure diagram of the quantum chip is determined, including: Based on the quantity information and the quantum gate information, the target drawing function is determined; Based on the target drawing function, a first topological structure diagram is used to determine the target structural shape of the quantum chip.

17. A device for determining a sub-chip of a quantum chip, comprising: The first determining module is used to determine the first number of qubits to be used based on the pre-detailed pattern of the quantum chip, wherein the pre-detailed pattern is a 45° oblique square tessellation configuration with a rectangular outline, and the pre-detailed pattern includes a plurality of first nodes corresponding one-to-one with a plurality of qubits of the quantum chip; The second determining module is used to determine the first row and column number information of the initial configuration based on the first quantity; The third determining module is used to determine multiple candidate characterization patterns from the pre-characterization pattern based on the first row and column number information, wherein each candidate characterization pattern includes multiple second nodes that correspond one-to-one with a portion of the qubits of the quantum chip; The fourth determining module is used to determine the connectivity of the multiple candidate sub-chips corresponding to the multiple candidate characterization patterns; and The fifth determining module is used to determine the target sub-chip from the plurality of candidate sub-chips based on the connectivity. The third determining module includes: The third determining submodule is used to determine a plurality of first configuration diagrams corresponding to the initial configuration in the pre-characterized diagram; The fourth determining submodule is used to determine the number of target nodes based on the first row and column number information and the second corner parameter of the initial configuration; The fifth determining submodule is used to determine a third node on the target boundary of the plurality of first configuration diagrams based on the first row and column number information and the number of target nodes; A determination submodule is used to delete the third node on the plurality of first configuration diagrams and generate a plurality of candidate characterization diagrams; The number of nodes contained in each candidate characterization map is the same as the first number.

18. The apparatus according to claim 17, wherein, The first determining module is used for: Based on the pre-etched pattern of the quantum chip, the second row and column number information and the first angle parameter of the pre-etched pattern are determined, wherein the first angle parameter is used to characterize the image shape of the target region of the pre-etched pattern; Based on the second row and column number information and the first angle parameter, determine the first number of qubits to be used.

19. The apparatus according to claim 17, wherein, The second determining module includes: The first determining submodule is used to determine the first parameter based on the first quantity; The second determining submodule is used to determine the first row and column number information of the initial configuration based on the first parameter and the second row and column number information of the pre-characterized pattern.

20. The apparatus according to claim 19, wherein, The second determining submodule is used for: When the first parameter and the second row and column number information of the pre-characterized pattern satisfy the first threshold, and the first quantity and the first parameter satisfy the second threshold, the first column number of the first group in the first row and column number information of the initial configuration is determined as the first parameter, the first row number of the first group is determined as the second parameter, the first column number of the second group is determined as the second parameter, and the first row number of the second group is determined as the first parameter.

21. The apparatus according to claim 19, wherein, The second determining submodule is used for: If the first parameter and the second row and column number information of the pre-characterized pattern satisfy the first threshold, and the first quantity and the first parameter do not satisfy the second threshold, then the first column number and the first row number in the first row and column number information of the initial configuration are determined to be the first parameter.

22. The apparatus according to claim 19, wherein, The second determining submodule is used for: Based on the second row and column number information of the pre-characterized image, determine the total number of rows and columns of the pre-characterized image; If the first parameter and the second row and column number information do not meet the first threshold, and the total number of columns is less than the total number of rows, the first column number in the first row and column number information of the initial configuration is determined to be the total number of columns, and the first row number in the first row and column number information is determined to be the first parameter.

23. The apparatus according to claim 19, wherein, The second determining submodule is used for: Based on the second row and column number information of the pre-characterized image, determine the total number of rows and columns of the pre-characterized image; If the first parameter and the second row and column number information do not meet the first threshold, and the total number of columns is not less than the total number of rows, the first column number in the first row and column number information of the initial configuration is determined as the fourth parameter, and the first row number in the first row and column number information is determined as the total number of rows.

24. The apparatus according to claim 17, wherein, The fifth determining submodule is used for: If it is determined that the number of the first column in the first row and column number information is less than the number of the first row, based on the pre-characterized map, the target row of the plurality of first configuration maps is determined as its own target boundary, wherein the target row is the row located at the outermost edge on both sides of the plurality of first configuration maps; Based on the number of target nodes, a third node is determined on the boundary of the target itself.

25. The apparatus according to claim 17, wherein, The fifth determining submodule is used for: If it is determined that the number of the first column in the first row and column number information is greater than the number of the first row, based on the pre-characterized map, the target column of the plurality of first configuration maps is determined as its own target boundary, wherein the target column is the outermost column located on the opposite sides of the plurality of first configuration maps; Based on the number of target nodes, a third node is determined on the boundary of the target itself.

26. The apparatus according to claim 17, wherein, The fifth determining submodule is used for: When it is determined that the number of the first column in the first row and column number information is equal to the number of the first row, based on the pre-characterized map, the target column and target row of the plurality of first configuration maps are determined as their own target boundaries, wherein the target row is the row located at the outermost edge on both sides of the plurality of first configuration maps, and the target column is the column located at the outermost edge on both sides of the plurality of first configuration maps; Based on the number of target nodes, a third node is determined on the boundary of the target itself.

27. The apparatus according to claim 17, wherein, The fourth determining module includes: Using a connectivity algorithm, the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps is calculated based on the qubits corresponding to the multiple second nodes on the characterization paths of the multiple candidate characterization maps.

28. The apparatus according to claim 27, wherein, The fourth determining module includes: The sixth determining submodule is used to determine the first distance weight between the qubits corresponding to each two adjacent second nodes on the marking path of the multiple candidate marking maps, based on the distance weight between the multiple qubits of the pre-marking map; The seventh determining submodule is used to determine the average distance weight based on the first distance weight; The calculation submodule is used to calculate the connectivity of multiple candidate sub-chips corresponding to the multiple candidate characterization maps based on the average distance weight using the connectivity algorithm.

29. The apparatus according to claim 28, wherein, The sixth determining submodule is used for: Based on the distance weights between multiple qubits in the pre-etched pattern, a second distance weight is determined between every two adjacent qubits of the quantum chip; Based on the second distance weight, a first distance weight is determined between the qubits corresponding to each two adjacent second nodes on the characterization path of the plurality of candidate characterization maps.

30. The apparatus according to any one of claims 17 to 29, further comprising: The sixth determining module is used to determine the number of qubits and the quantum gate information of the quantum chip based on the chip information of the quantum chip, wherein the quantum gate information characterizes the communication relationship between each qubit of the quantum chip; The seventh determining module is used to determine a first topological structure diagram of the quantum chip based on the quantity information and the quantum gate information, wherein the first topological structure diagram is composed of a plurality of first nodes representing each quantum bit and edges representing the communication relationship between every two directly adjacent quantum bits of the quantum chip; The eighth determining module is used to determine the distance weights between the qubits based on the quantum gate information; and A generation module is used to obtain a pre-detailed pattern of the quantum chip based on the distance weights and the first topology diagram.

31. The apparatus according to claim 30, wherein, The eighth determining module is used for: Based on the quantum gate information, determine every two directly adjacent qubits in the quantum chip; Based on the chip information, determine the fidelity of the two-qubit gate between every two directly adjacent qubits; Based on the fidelity, the distance weights between each quantum bit are determined.

32. The apparatus according to claim 30, wherein, The seventh determining module is used for: Based on the quantity information and the quantum gate information, the target drawing function is determined; Based on the target drawing function, a first topological structure diagram is used to determine the target structural shape of the quantum chip.

33. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 16.

34. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 16.

35. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 16.

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