A method for optimizing the vertices of a layout graphic, an electronic device, and a storage medium.

Abstract

A method, electronic device, and storage medium for optimizing vertices in a layout graphic are disclosed. The method includes the following steps: calculating the number of deletable vertices and the proportion of vertices to be retained based on the graphic's side length and a preset length threshold, or based on the angle and a preset angle threshold; calculating the deletion cost for each vertex; and deleting vertices starting with the vertex with the lowest deletion cost based on the calculated deletion cost, until the remaining number of vertices meets the required proportion of vertices to be retained, resulting in a simplified graphic after vertex deletion and outputting it. Addressing the problem that complex graphics often have a large number of vertices, increasing the number of nodes required for subsequent capacitor and resistor extraction, lengthening the extraction time, and even making it impossible to calculate results when the graphic size is particularly large, the method of this invention can significantly reduce the number of vertices in complex graphics. While ensuring accuracy, it reduces the number of nodes that need to be calculated in parasitic parameter extraction, speeds up the extraction process, and thus improves the efficiency of layout design.

Description

Technical Field

[0001] This invention relates to the field of automated design technology for semiconductor integrated circuits, and in particular to a method for optimizing layout vertices, an electronic device, and a storage medium. Background Technology

[0002] In existing technologies, to accurately calculate parasitic parameters of graphics, it is often necessary to triangulate the layout graphic and calculate the capacitance and resistance corresponding to each point using integration. The computational load of this method is closely related to the number of vertices in the input graphic; the more vertices, the longer the computation time. In previous applications, rectangular and other straight-line graphics were more commonly used, with almost no curves. The overall number of vertices in the graphic was small, and the complexity was low, so the impact on computation speed was minimal. However, with technological advancements, layouts have begun to use a large number of curves to depict graphics, leading to a continuous increase in the number of vertices and a rapid rise in layout complexity, which significantly affects the calculation speed of parasitic parameters. In computers, curves are approximated by a large number of line segments. The denser the line segments and the more vertices, the closer the graphic is to the true curve, but this also slows down the extraction of parasitic parameters and reduces the efficiency of layout design. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a method, electronic device, and storage medium for optimizing vertices of a layout graphic. This method deletes as many vertices as possible while ensuring that the overall features and connectivity of the graphic remain largely unchanged, thereby accelerating the extraction speed while ensuring the accuracy of parasitic parameter extraction, reducing subsequent processing time, and thus improving the efficiency of complex layout design.

[0004] To achieve the above objectives, the present invention provides a method for optimizing the vertices of a layout graphic, comprising:

[0005] Calculate the number of vertices that can be deleted and the proportion of vertices that need to be retained based on the side length of the graphic and a preset length threshold or based on the angle and a preset angle threshold.

[0006] Calculate the deletion cost when deleting each vertex;

[0007] Based on the calculated deletion cost, the deletion process starts with the vertex with the lowest deletion cost, until the number of remaining vertices meets the required proportion of vertices to be retained. The simplified graph after deleting vertices is then obtained and output.

[0008] Furthermore, the step of calculating the number of vertices that can be deleted and the proportion of vertices that need to be retained based on the side length of the graphic and a preset length threshold further includes:

[0009] Starting from the origin, traverse the vertices of the graph sequentially in one direction, compare the side length between the current vertex and the previous vertex with the preset length threshold. If the side length is less than the preset length threshold, the current vertex is a vertex that can be deleted.

[0010] Count the number of vertices that can be deleted and calculate the percentage of vertices that need to be retained: Percentage of vertices to be retained = (Total number of vertices - Number of vertices that can be deleted) / Total number of vertices.

[0011] Furthermore, the step of calculating the number of deletable vertices and the proportion of vertices to be retained based on the angle and a preset angle threshold further includes:

[0012] Starting from the origin, traverse the vertices of the figure in one direction and calculate the interior angle of the current vertex in the triangle formed by the current vertex and its two adjacent vertices.

[0013] Compare the interior angle with a preset angle threshold. If the interior angle is greater than the preset angle threshold, the current vertex can be deleted.

[0014] Count the number of vertices that can be deleted and calculate the percentage of vertices that need to be retained: Percentage of vertices to be retained = (Total number of vertices - Number of vertices that can be deleted) / Total number of vertices.

[0015] Furthermore, the step of calculating the deletion cost when deleting each vertex further includes:

[0016] A cost algorithm that quantitatively represents the impact of each vertex on the overall graph is used to calculate the deletion cost when deleting each vertex.

[0017] The cost algorithm includes: the angle method based on interior angle sorting; the boundary length method for calculating the length of the two edges connected to a vertex; the area method for calculating the change in the area of ​​the graphic after deleting a vertex; and the distance method for calculating the distance from the vertex to the new edge.

[0018] Furthermore, it also includes:

[0019] Iterate through all vertices and determine whether a vertex is the starting point of each shape or the intersection of multiple edges;

[0020] For vertices that are neither the starting point of the graph nor the intersection of multiple edges, a cost algorithm is used to calculate their corresponding deletion cost.

[0021] Furthermore, before the step of calculating the deletion cost when deleting each vertex, the method further includes: marking the starting point of the graph and the intersection of multiple edges as vertices that cannot be deleted, marking other vertices as vertices that can be deleted, and calculating the deletion cost.

[0022] Furthermore, it also includes: arranging the vertices of the closed figure in a clockwise or counterclockwise direction, selecting any vertex as the starting point, and marking the starting point as a vertex that cannot be deleted.

[0023] Furthermore, the step of deleting vertices based on the calculated deletion cost, starting with the vertex with the lowest deletion cost, until the number of remaining vertices meets the required proportion of vertices to be retained, and then outputting the simplified graph after deleting vertices, further includes:

[0024] 81) Sort all deletable vertices according to their deletion cost to generate a sequence of deletable vertices, starting with the vertex with the lowest deletion cost;

[0025] 82) Determine if the line connecting two adjacent vertices intersects with other edges of the figure. If they intersect, the current vertex cannot be deleted; proceed to step 85).

[0026] If they do not intersect, delete the current vertex and proceed to step 83);

[0027] 83) Based on the connection relationship of the new graph after deleting vertices, recalculate the deletion cost of the remaining vertices, sort the remaining vertices according to the new deletion cost, update the sequence of deletable vertices, and proceed to step 84).

[0028] 84) Calculate the ratio of the remaining number of vertices to the total number of vertices, and compare it with the calculated proportion of vertices to be retained. If the ratio is less than or equal to the proportion of vertices to be retained, stop deleting vertices and output the graphic containing the remaining vertices; otherwise, proceed to step 85).

[0029] 85) If the sequence of deletable vertices is empty, stop deleting vertices and output the graph containing the remaining vertices; otherwise, select the next vertex according to the sorting in the sequence of deletable vertices and return to step 82).

[0030] To achieve the above objectives, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the layout graphics vertex optimization method as described above.

[0031] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing at least one computer instruction, which is loaded and executed by a processor to implement the layout graphics vertex optimization method as described above.

[0032] The method for optimizing the vertices of a layout graphic provided by this invention has the following advantages compared with the prior art:

[0033] The method of this invention can significantly reduce the number of vertices in complex graphics without significantly affecting the graphic features. While ensuring accuracy, it reduces the number of nodes that need to be calculated in parasitic parameter extraction. This solves the problem in the prior art that, before graphic simplification, the large number of vertices in complex graphics increases the number of nodes required for subsequent capacitor and resistor extraction, lengthens the extraction time, and even makes it impossible to calculate results when the graphic size is particularly large. The method of this invention accelerates the extraction speed, thereby improving the efficiency of layout design.

[0034] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0035] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0036] Figure 1 This is a flowchart of a method for optimizing vertices of a layout graphic according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the original layout graphics according to an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram illustrating the vertex deletion cost according to an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram showing the intersection of the line connecting two adjacent vertices of a vertex with other edges of the figure according to an embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram showing the result of deleting vertices from the original layout according to an embodiment of the present invention;

[0041] Figure 6 This is a flowchart illustrating the process of deleting vertices according to an embodiment of the present invention;

[0042] Figure 7 This is a schematic diagram of an electronic device structure according to an embodiment of the present invention. Detailed Implementation

[0043] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0044] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the invention. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the invention.

[0045] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0046] It should be noted that the concepts of "first" and "second" may be mentioned in this invention only to distinguish different devices, components or parts, and are not used to limit the order of the functions performed by these devices, components or parts or their interdependence.

[0047] It should be noted that the terms "one" and "multiple" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "Multiple" should be understood as two or more.

[0048] In computers, curves are approximated by a large number of line segments. The denser the line segments and the more vertices, the closer the graph is to the true curve. However, an excessive number of vertices significantly reduces the speed of parasitic parameter extraction. Furthermore, for very short line segments, the corresponding resistance is extremely small, reaching approximately 1e-10, and removing this resistance has almost no impact on the result. Therefore, to accelerate the extraction speed, this invention proposes an optimization method for vertex representation in a layout graphic. For complex graphics with too many vertices, combined with graphics processing techniques, the graph is simplified while maintaining its overall features and connectivity. This reduces the number of vertices as much as possible while ensuring accuracy, thereby lowering subsequent processing time.

[0049] Figure 1 The following is a flowchart of a method for optimizing vertices of a layout graphic according to an embodiment of the present invention, with reference to... Figure 1 The optimization method for the vertices of the layout graphics of the present invention is described in detail.

[0050] First, in step 101, the number of vertices that can be deleted is calculated based on the side length or angle of the graphic, and the proportion of vertices that need to be retained in the graphic is calculated.

[0051] In an embodiment of the present invention, vertices to be deleted are selected according to side lengths or angles, and then, based on the total number of vertices and the number of deletable vertices, the proportion of vertices to be retained is calculated.

[0052] Selecting deletable vertices according to side lengths: Starting from the starting point, traverse the vertices of the graph in one direction in sequence. Figure 2 This is the original layout graph in this embodiment, as Figure 2 shown. For the input layout graph, assume that the vertex p2 is traversed. Let the length of the edge e1 from vertex p2 to vertex p1 be d. Set a length threshold L, and n is the number of vertices that can be deleted, with the initial value of n being 0. If d < L, then vertex p2 can be deleted, and the value of n is incremented by one.

[0053] Selecting deletable vertices according to angles: Starting from the starting point, traverse the vertices of the graph in one direction in sequence, as Figure 2 shown. Assume that the currently traversed vertex is p2. The three vertices p1, p2, and p3 form a triangle. Calculate the interior angle α of the triangle with p2 as the vertex. When α is close to 180 degrees, the sum of the edges e1 + e2 is approximately equal to e3, then p2 can be deleted; set an angle threshold θ. When α is greater than θ, p2 can be deleted. Denote p2 as a deletable point, and n is incremented by one.

[0054] Assume that the total number of vertices is N, and p = (N - n) / N. p is the proportion of vertices to be retained. At most n vertices can be deleted while maintaining the unchanged graphic features.

[0055] In step 102, calculate the deletion cost when deleting each vertex.

[0056] In an embodiment of the present invention, the deletion cost of a vertex is used to represent the influence value of the deletion starting point on the overall graph. The lower the deletion cost, the smaller the influence of deleting this vertex on the graph. A cost algorithm for quantitatively representing the influence of each vertex on the overall graph is used to calculate the deletion cost when deleting each vertex. There are various algorithms for the cost algorithm, such as the angle method of sorting according to interior angles, the boundary length method of calculating the lengths of two adjacent edges of a vertex, the area method of calculating the change in the area of the graph after deleting a point, the distance method of the distance from a vertex to a new edge, etc. There is no unique algorithm. As long as a method can quantitatively represent the influence of each vertex on the overall graph, it can be used as the cost algorithm. In this embodiment, the distance method is used for demonstration: The deletion cost corresponding to a vertex is equal to the distance between the vertex and the connection line between its two adjacent vertices.

[0057] First, iterate through all vertices, determining whether a vertex is the starting point of each shape or an intersection of multiple edges. The starting point can be any vertex in the shape, but in computers, when storing a closed shape, vertices are often arranged clockwise or counter-clockwise. Additionally, in some data structures, to represent the closure of a shape, the last vertex may be the same as the starting point, or there may be an identifier pointing from the end point to the starting point. To ensure efficiency, this algorithm avoids unnecessary operations; when deleting a vertex, it does not perform an additional check for whether it is the starting point. However, deleting a starting point cannot guarantee the maintenance of the integrity of these data structures, as damage to this integrity may result in an unclosed shape. Therefore, to ensure algorithm compatibility, starting points are not deleted. Deleting an intersection may split the shape into two, severely affecting its characteristics. Therefore, starting points and intersections need to be marked as non-deletable, thus eliminating the need for computational costs. Other vertices are marked as deletable, and their deletion costs are calculated.

[0058] Figure 3 This is a schematic diagram illustrating the vertex deletion cost according to an embodiment of the present invention, such as... Figure 3 As shown, e1 and e2 are the original edges of the graph, and p1, p2, and p3 are the vertices of the graph. Let p2 be the vertex whose deletion cost is calculated. When p2 is deleted, an edge e3 is generated connecting p1 and p3. Let d be the distance from p2 to e3, then d is the cost of deleting vertex p2. The deletion cost of all deletable vertices is calculated in this way.

[0059] In step 103, based on the deletion cost, the vertices with the lowest cost are deleted until the number of remaining vertices meets the required proportion of vertices to be retained, resulting in a simplified graph after the deletion of vertices, which is then output.

[0060] In this embodiment of the invention, the deletion cost represents the impact of deleting each point on the graphic. In order to preserve the graphic features to the greatest extent, the points with the lowest deletion cost should be deleted. Figure 6 The flowchart for deleting vertices according to an embodiment of the present invention is shown below. Figure 6 Step 103 will be explained in further detail.

[0061] In step 31, the vertices are sorted according to their deletion costs, denoted as sequence Q, and processing begins with the vertex with the lowest deletion cost. (See reference) Figure 3 Let p2 be the vertex with the lowest current cost, and its adjacent vertices on the graph be p1 and p3. First, p2 must be removed from Q by performing the following steps:

[0062] In step 32, determine whether the line connecting the two adjacent vertices of the current vertex intersects with other edges of the figure. Check whether edge e3 intersects with other edges of the figure; if no intersecting edge exists, proceed as follows: Figure 3As shown, e3 does not intersect with e1 or e2, so proceed to step 33; if there are intersecting edges, such as... Figure 4 As shown, e3 intersects with e4 and e5, so proceed to step 36.

[0063] In step 33, based on the connection relationship of the new graph after vertex p2 is deleted, the deletion costs of p1 and p3 are recalculated, and the vertices are sorted according to the new deletion costs. After updating sequence Q, step 34 is performed.

[0064] In step 34, calculate the ratio q of the remaining number of vertices to the total number of vertices.

[0065] In step 35, compare the q with the proportion of vertices to be retained calculated in step 101. If q <= p, stop deleting vertices and proceed to step 37; if q > p, proceed to step 36.

[0066] In step 36, if Q is empty, stop deleting vertices and proceed to step 37; otherwise, select the next vertex according to the sorting in Q and return to step 32.

[0067] In step 37, output the graph containing the remaining vertices.

[0068] In embodiments of the present invention, such as Figure 1 As shown, the input shape is a heptagon, with p1 as the starting point. The shape is then processed. First, the seven vertices are traversed clockwise to determine the proportion of points to be deleted. For ease of explanation, it is assumed that all seven edges are greater than a threshold, and of the seven interior angles, only angle α is greater than a threshold. Therefore, only point p2 is marked as deletable. The proportion of vertices to be retained is p = (N-1) / N.

[0069] Then as Figure 3 As shown, starting from p1, traverse the 7 vertices clockwise and calculate the deletion cost of each vertex. For vertices p1, p2, and p3 in the graph, p1 is the starting point of the graph and cannot be deleted, so its deletion cost is not calculated and it is not added to sequence Q. For p2, its two preceding and following vertices are p1 and p3. Calculate the distance d from p2 to the line connecting p1 and p3, use d as the deletion cost of p2, and store p2 in sequence Q. For p3, calculate the distance from p3 to the line connecting p2 and p5, and store p3 in sequence Q. Repeat this process for the remaining vertices. After calculating the deletion costs, sort the elements in sequence Q from smallest to largest according to their deletion costs. Then, perform the deletion process on the vertices.

[0070] by Figure 3 For example, assuming we start by processing p2, we first delete p2 from Q because p2 is marked as deletable. The newly added edge e3 does not intersect with any other edges, so we delete vertex p2 from the graph, generating the graph as shown below. Figure 5 As shown. Then according to... Figure 5Recalculate the deletion cost of p3 at positions p1 and p5, and update sequence Q based on the new deletion cost. Then calculate the proportion q of the remaining vertices. If q = p (where p is the proportion of vertices to be retained), the condition is met, and simplification stops. Figure 5 As the result, output it.

[0071] by Figure 4 For example, let's assume only p2 can be deleted. We start processing p2 by first deleting it from Q. Since p2 is marked as deletable, the newly added edge e3 intersects with e4 and e5, so p2 cannot be deleted. Processing p2 is complete. Assuming the next vertex is p3, we delete it from Q. Because p3 is not marked as deletable, we skip p3 and don't proceed with further checks. We process the subsequent vertices in sequence until the sequence Q is empty, at which point processing ends, and the output graph remains the same. Figure 4 .

[0072] This invention addresses the problem in existing technologies where, before graphical simplification, complex graphics have a large number of vertices, increasing the number of nodes required for subsequent capacitor and resistor extraction, lengthening the extraction time, and even making it impossible to calculate results when the graphics are particularly large. The method of this invention can significantly reduce the number of vertices in complex graphics without significantly affecting the graphic features. While maintaining accuracy, it reduces the number of nodes that need to be calculated in parasitic parameter extraction, speeds up the extraction process, and thus improves the efficiency of layout design.

[0073] In embodiments of the present invention, an electronic device is also provided. Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention, such as... Figure 7 As shown, the electronic device of the present invention includes a processor 701 and a memory 702, wherein,

[0074] The memory 702 stores a computer program, which, when read and executed by the processor 701, performs the steps described above in the implementation of the method for optimizing the vertex of the layout graphics.

[0075] In embodiments of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, wherein the computer program is configured to execute the steps in the layout graphics vertex optimization method embodiment described above when running.

[0076] In this embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0077] It will be understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for optimizing vertices of a layout graphic, characterized in that, Includes the following steps: Calculate the number of vertices that can be deleted and the proportion of vertices that need to be retained based on the side length of the graphic and a preset length threshold or based on the angle and a preset angle threshold. Calculate the deletion cost when deleting each vertex; Based on the calculated deletion cost, the deletion process starts from the vertex with the lowest deletion cost until the number of remaining vertices meets the required proportion of vertices to be retained. The simplified graph after deleting the vertices is then obtained and output. Before deleting the current vertex, it is determined whether the line connecting its two adjacent vertices intersects with other edges of the graph. If they intersect, the deletion of that vertex is abandoned. The step of calculating the deletion cost when deleting each vertex further includes: A cost algorithm that quantitatively represents the impact of each vertex on the overall graph is used to calculate the deletion cost when deleting each vertex. The cost algorithm includes the angle method based on interior angle sorting, the boundary length method for calculating the length of the two edges connected to a vertex, the area method for calculating the change in the area of ​​the graphic after deleting a vertex, and the distance method for calculating the distance from the vertex to the new edge.

2. The method for optimizing the vertices of a layout graphic according to claim 1, characterized in that, The step of calculating the number of vertices that can be deleted and the proportion of vertices that need to be retained based on the side length of the graphic and a preset length threshold further includes: Starting from the origin, traverse the vertices of the graph sequentially in one direction, compare the side length between the current vertex and the previous vertex with the preset length threshold. If the side length is less than the preset length threshold, the current vertex is a vertex that can be deleted. Count the number of vertices that can be deleted and calculate the percentage of vertices that need to be retained: Percentage of vertices to be retained = (Total number of vertices - Number of vertices that can be deleted) / Total number of vertices.

3. The method for optimizing the vertices of a layout graphic according to claim 1, characterized in that, The step of calculating the number of vertices that can be deleted and the proportion of vertices that need to be retained based on the angle and a preset angle threshold further includes: Starting from the origin, traverse the vertices of the figure in one direction and calculate the interior angle of the current vertex in the triangle formed by the current vertex and its two adjacent vertices. Compare the interior angle with a preset angle threshold. If the interior angle is greater than the preset angle threshold, the current vertex can be deleted. Count the number of vertices that can be deleted and calculate the percentage of vertices that need to be retained: Percentage of vertices to be retained = (Total number of vertices - Number of vertices that can be deleted) / Total number of vertices.

4. The method for optimizing the vertices of a layout graphic according to claim 1, characterized in that, Also includes: Iterate through all vertices and determine whether a vertex is the starting point of each shape or the intersection of multiple edges; For vertices that are neither the starting point of the graph nor the intersection of multiple edges, a cost algorithm is used to calculate their corresponding deletion cost.

5. The method for optimizing the vertices of a layout graphic according to claim 1, characterized in that, Before the step of calculating the deletion cost when deleting each vertex, the method further includes: marking the starting point of the graph and the intersection of multiple edges as vertices that cannot be deleted, marking other vertices as vertices that can be deleted, and calculating the deletion cost.

6. The method for optimizing the vertices of a layout graphic according to claim 5, characterized in that, Also includes: Arrange the vertices of the closed figure in a clockwise or counterclockwise direction, select any vertex as the starting point, and mark the starting point as a vertex that cannot be deleted.

7. The method for optimizing the vertices of a layout graphic according to claim 1, characterized in that, The step of deleting vertices based on the calculated deletion cost, starting with the vertex with the lowest deletion cost, until the number of remaining vertices meets the required proportion of vertices to be retained, and then outputting the simplified graph after deleting vertices, further includes: 81) Sort all deletable vertices according to their deletion cost to generate a sequence of deletable vertices, starting with the vertex with the lowest deletion cost; 82) Determine whether the line connecting two adjacent vertices intersects with other edges of the figure. If they intersect, the current vertex cannot be deleted, and proceed to step 85). If they do not intersect, delete the current vertex and proceed to step 83). 83) Based on the connection relationships of the new graph after deleting vertices, recalculate the deletion cost of the remaining vertices, sort the remaining vertices according to the new deletion cost, update the sequence of deletable vertices, and proceed to step 84). 84) Calculate the ratio of the remaining number of vertices to the total number of vertices, and compare it with the calculated proportion of vertices to be retained. If the ratio is less than or equal to the proportion of vertices to be retained, stop deleting vertices and output the graphic containing the remaining vertices; otherwise, proceed to step 85). 85) If the sequence of deletable vertices is empty, stop deleting vertices and output the graph containing the remaining vertices; otherwise, select the next vertex according to the order within the sequence of deletable vertices and return to step 82.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor is configured to execute the computer program stored in the memory to implement the layout graphic vertex optimization method according to any one of claims 1-7.

9. A computer-readable storage medium storing at least one computer instruction, the computer instruction being loaded and executed by a processor to implement the method for optimizing layout graphics vertices according to any one of claims 1-7.

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