Method for manufacturing stacked transistor, stacked transistor, and semiconductor device

Abstract

The application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device. The method comprises the following steps: providing a substrate structure, wherein the substrate structure comprises a substrate, a power rail, a shallow trench isolation structure and an active structure; the shallow trench isolation structure covers the power rail; the power rail comprises a first power rail and a second power rail; depositing a first semiconductor material in a gate region of the substrate structure to form a pseudo gate structure; removing the pseudo gate structure in a gate cut region of the stacked transistor by a cutting process; depositing a nitride material in the gate cut region to form a first gate isolation structure and a second gate isolation structure; forming a first transistor based on a first part of the active structure and the first gate isolation structure; and forming a second transistor based on a second part of the active structure and the second gate isolation structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and particularly relates to a preparation method of a stacked transistor, a stacked transistor and a semiconductor device. BACKGROUND

[0002] At present, it is a hot issue in the industry to continue to promote the miniaturization of transistors. The stacked transistor is one of the important technologies to continue the miniaturization of integrated circuits by integrating two or more layers of transistors in the vertical space to further improve the integrated density of transistors.

[0003] In some preparation processes of the stacked transistor, after the metal gate is formed, the gate isolation structure is prepared. Generally, the process required for preparing the gate isolation structure can include a gate cut-off process, but the gate cut-off process will cause the metal structure of the source-drain region to be cut off at the same time, thereby affecting the metal interconnection performance of the source-drain region. SUMMARY

[0004] The present application provides a preparation method of a stacked transistor, a stacked transistor and a semiconductor device to eliminate the influence of the metal structure of the source-drain region in the forming process of the gate isolation structure.

[0005] The method for manufacturing the stacked transistor comprises: providing a substrate structure, the substrate structure comprising: a substrate, a power rail, a shallow trench isolation structure, and an active structure; wherein the shallow trench isolation structure covers the power rail; the power rail comprises: a first power rail and a second power rail; the first power rail and the second power rail are respectively arranged on two sides of the active structure in the arrangement direction of the active structure, and the extension directions of the first power rail and the second power rail are the same as the extension direction of the active structure; the active structure has a first part and a second part, and the first part is closer to the substrate structure than the second part; depositing a first semiconductor material in the gate region of the substrate structure to form a pseudo-gate structure; removing the pseudo-gate structure in the gate cut region of the stacked transistor by a cutting process; wherein the gate cut region is located at a first edge portion and a second edge portion of the stacked transistor, and the first edge portion and the second edge portion are two edge portions arranged oppositely in the arrangement direction of the active structure; depositing a nitride material in the gate cut region to form a first gate isolation structure and a second gate isolation structure; the first gate isolation structure and the second gate isolation structure are respectively located at the first edge portion and the second edge portion; forming a first transistor based on the first part of the active structure and the first gate isolation structure; the first transistor comprises a first source-drain structure, a first gate structure, a first source-drain metal, and a first power rail connecting metal; the first power rail connecting metal connects the first power rail and the first source-drain metal; forming a second transistor based on the second part of the active structure and the second gate isolation structure; the second transistor comprises a second source-drain structure, a second gate structure, a second source-drain metal, and a second power rail connecting metal; the second power rail connecting metal connects the second power rail and the second source-drain metal.

[0006] In some possible implementation manners, the active structure further comprises: a sacrificial layer located between the first part and the second part; forming the first transistor based on the first part of the active structure and the first gate isolation structure comprises: removing the sacrificial layer in the second part of the active structure and the source-drain region; forming the first source-drain structure based on the first part of the active structure; removing a first part of the first gate isolation structure and retaining a second part of the first gate isolation structure in the source-drain region of the stacked transistor to partially expose the first power rail; wherein the first part of the first gate isolation structure is closer to the first source-drain structure than the second part of the first gate isolation structure; forming the first source-drain metal and the first power rail connecting metal respectively on the first source-drain structure and the exposed first power rail.

[0007] In some possible implementation manners, forming the first transistor based on the first part of the active structure and the first gate isolation structure further comprises: removing the sacrificial layer in the gate region; forming the first gate structure based on the first part of the active structure in the gate region of the stacked transistor; the first gate structure is between the first gate isolation structure and the second gate isolation structure.

[0008] In some possible implementations, before forming the first source-drain structure based on the first portion of the active structure, the method further includes: depositing a semiconductor material on sidewalls of a second portion of the active structure within the gate region of the stacked transistor to form a protection layer covering the second portion of the active structure and the sacrificial layer; and after forming the first source-drain structure based on the first portion of the active structure, the method further includes: removing the protection layer.

[0009] In some possible implementations, forming the second transistor based on the second portion of the active structure and the second gate isolation structure includes: forming, above the first transistor, a second source-drain structure in a source-drain region based on the second portion of the active structure of the gate region by an epitaxial growth process; removing, in the source-drain region of the stacked transistor, a first portion of the second gate isolation structure and leaving a second portion of the second gate isolation structure to partially expose a second power rail, wherein the first portion of the second gate isolation structure is closer to the second source-drain structure than the second portion of the second gate isolation structure; and forming, respectively above the second source-drain structure and the exposed second power rail, a second source-drain metal and a second power rail connection metal.

[0010] In some possible implementations, forming the second transistor based on the second portion of the active structure and the second gate isolation structure further includes: forming, in the gate region of the stacked transistor, a second gate structure based on the second portion of the active structure; and the second gate structure is between the first gate isolation structure and the second gate isolation structure.

[0011] In some possible implementations, removing the dummy gate structure in the gate cut region of the stacked transistor by a cut-off process includes: depositing a second semiconductor material in the source-drain region of the stacked transistor to form a dielectric layer structure; and removing, by the cut-off process, the dummy gate structure in the gate cut region and the dielectric layer structure in the source-drain region.

[0012] In some possible implementation manners, the substrate structure comprises: a substrate, a shallow trench isolation structure and a power supply rail; the power supply rail is partially in the substrate and partially in the shallow trench isolation structure; a substrate structure is provided, and an active structure is formed on the substrate structure, and the power supply rail is embedded in the substrate structure, comprising: a wafer is provided, and a first material layer and a second material layer are sequentially formed on the wafer; the second material layer, the first material layer and a first part of the wafer are etched, and a second part of the wafer is reserved; the etched first material layer forms a sacrificial layer; the etched second material layer forms a second part of the active structure; an oxide material is deposited on the second part of the wafer to form a first shallow trench isolation structure; the height of the first shallow trench structure is less than the height of the first part of the wafer; the first part of the wafer not wrapped by the first shallow trench structure forms a first part of the active structure; in the arrangement direction of the active structure, a part of the first shallow trench isolation structure and the second part of the wafer located on both sides of the active structure are etched respectively; a power supply rail is formed at the etched position of the wafer; the height of the power supply rail is less than the height of the first shallow trench isolation structure; an oxide material is deposited on the power supply rail to form a second shallow trench isolation structure; the height of the second shallow trench isolation structure is the same as the height of the first shallow trench isolation structure; wherein, the first shallow trench isolation structure and the second shallow trench isolation structure form the shallow trench isolation structure; the etched second part of the wafer and the first part of the wafer wrapped by the first shallow trench structure form the substrate.

[0013] In the second aspect, the embodiments of the present application provide a stacked transistor, which can be prepared by using the preparation method in any one of the embodiments of the first aspect. The stacked transistor comprises: a first transistor; and a second transistor, wherein the first transistor and the second transistor are arranged in a stack; the first active structure of the first transistor and the second active structure of the second transistor form an active structure; and the first source / drain structure of the first transistor and the second source / drain structure of the second transistor are self-aligned.

[0014] In the third aspect, the embodiments of the present application provide a semiconductor device, which comprises the stacked transistor in any one of the above embodiments.

[0015] In the embodiments of the present application, the first gate isolation structure and the second gate isolation structure are formed on both sides of the gate cut region of the active structure, and then the first transistor is formed based on the first part of the active structure and the first gate isolation structure, and the second transistor is formed based on the second part of the active structure and the second gate isolation structure, so that the metal structure of the source / drain region of the first transistor and the second transistor is not affected when the gate isolation structure is formed, thereby effectively eliminating the influence of the metal structure of the source / drain region in the forming process of the gate isolation structure.

[0016] Further, since the first transistor and the second transistor are prepared based on the first part and the second part of the active structure formed in the same process, self-alignment between the first transistor and the second transistor is achieved.

[0017] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and are not limiting to the present application. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and serve to explain the principles of the present application, together with the description.

[0019] Figure 1 An embodiment flow chart of a preparation method of a stacked transistor in the present application;

[0020] Figure 2 A top view of a stacked transistor in an embodiment of the present application;

[0021] Figure 3 A structure diagram of a stacked transistor in an embodiment of the present application;

[0022] Figures 4 to 24 A diagram of a preparation process of a stacked transistor in an embodiment of the present application.

[0023] The above figures: 10, stacked transistor; 11, first transistor; 111, first part of fin structure; 112, first power rail connection metal; 113, first power rail; 114, first gate isolation structure; 115, first source-drain structure; 116, first source-drain metal; 117, first gate structure; 118, first interlayer dielectric layer; 12, second transistor; 121, second part of fin structure; 122, second power rail connection metal; 123, second power rail; 124, second gate isolation structure; 125, second source-drain structure; 126, second source-drain metal; 127, second gate structure; 128, second interlayer dielectric layer; 21, substrate; 22, first material layer; 23, second material layer; 24, sacrificial layer; 25, first shallow trench isolation structure; 26, shallow trench isolation structure; 27, power rail trench; 28, metal interconnection layer; 29, dummy gate structure; 30, second spacer; 31, dielectric layer structure; 32, first spacer; 33, protection layer; 34, isolation layer. DETAILED DESCRIPTION

[0024] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The description below refers to the accompanying drawings, which show, by way of example, specific embodiments with which this application can be practiced. The following detailed description is not intended to limit the scope of the application, as claimed, but is merely representative of the many embodiments in which this application can be practiced.

[0025] In the context of Moore's Law, the continued scaling of transistor size is a hot topic in the industry. Stacked transistors, which integrate two or more transistors in the vertical space through three-dimensional transistor stacking, can help further improve transistor integration density and circuit performance, and is considered one of the important technologies to continue the scaling of integrated circuits.

[0026] In one embodiment, there are two schemes for the preparation process of stacked transistors, the first being a monolithic scheme and the second being a sequential scheme.

[0027] The first scheme fabricates N-channel field effect transistors (NFETs) and P-channel field effect transistors (PFETs) on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, i.e., NFET or PFET. Moreover, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this scheme is better integration density. The disadvantages of this scheme include the following two points: (1) complex process, requiring a large amount of process technology development and optimization; (2) fixed polarity of each layer of transistors, which must rely on two layers of transistors to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, poor design flexibility.

[0028] The second scheme is based on wafer bonding and layer-by-layer processing. Specifically, by bonding a wafer on top of the lower layer of transistors that have already been fabricated to prepare the upper layer of transistors, the two transistors are vertically stacked. However, the temperature during the processing of the upper layer of transistors needs to be strictly controlled to avoid affecting the lower layer of transistors and the interconnect lines. The advantage of this scheme is that, thanks to wafer bonding, the device structure, channel crystal orientation, and even the channel material of the upper and lower layers of transistors can be optimized accordingly to obtain better and more matched device performance. The disadvantages of this scheme include: it is difficult to achieve self-alignment between the upper and lower layers of transistors, and the type of each layer of transistors is fixed, making it difficult to stack transistors of different polarities or different structures, poor design flexibility.

[0029] In some preparation processes of the stacked transistors, after the formation of the metal gate is completed, the gate isolation structure is then prepared. Generally, the process required for preparing the gate isolation structure can include a gate cut-off process, but the gate cut-off process can cause the metal structure of the source-drain region to be cut off at the same time, thereby affecting the metal interconnection performance of the source-drain region.

[0030] To solve the above technical problems, the embodiment of the present application provides a preparation method of a stacked transistor, which can eliminate the influence of the gate isolation structure formation process on the metal structure of the source-drain region.

[0031] In the embodiment of the present application, the above-mentioned stacked transistor can be applied to semiconductor devices such as memories, processors, etc.

[0032] In an embodiment, the stacked transistor can include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged in a stacked manner. The first source-drain structure in the first transistor and the second source-drain structure in the second transistor can be formed by the same process of the active structure, at this time, it can be understood that the first transistor and the second transistor are self-aligned.

[0033] In the embodiment of the present application, the first transistor and the second transistor in the stacked transistor can be the same type of transistor, such as any one of the following: fin field effect transistor, full-encircling gate transistor, and planar transistor.

[0034] Figure 1 For an embodiment flowchart of the preparation method of the stacked transistor in the embodiment of the present application, referring to FIG. 1, the preparation method of the stacked transistor can include the following steps. Figure 1 As shown in FIG. 1, the preparation method of the stacked transistor can include the following steps.

[0035] S101, providing a substrate structure.

[0036] The substrate structure includes a substrate, a power rail, a shallow trench isolation structure, and an active structure. The shallow trench isolation structure covers the power rail; and the active structure is formed on the substrate.

[0037] It can be understood that, through the active structure in the substrate structure, the upper and lower stacked transistors can be formed based on the active structure in the subsequent steps. Through the power rail in the substrate structure, the power rail can be connected with the source-drain structure of the stacked transistor through the subsequent steps, and the power supply for the stacked transistor can be realized.

[0038] It can be understood that the power rail is a metal wire structure buried below the transistor, which is used to supply power for the transistor.

[0039] In the embodiments of the present application, the power supply rail includes a first power supply rail and a second power supply rail. The first power supply rail and the second power supply rail can be respectively arranged at two sides of the active structure in the arrangement direction of the active structure, and the extension direction of the first power supply rail and the second power supply rail can be the same as the extension direction of the active structure.

[0040] Here, when the transistors in the stacked transistors are fin field effect transistors, the active structure is a fin structure; when the transistors in the stacked transistors are all-around gate transistors, the active structure is a nanosheet structure; and when the transistors in the stacked transistors are planar transistors, the active structure is a bulk structure.

[0041] For example, when the active structure is a fin structure, the extension direction of the active structure refers to the extension direction of the connecting line between the fin structure and the substrate formed when the fin structure is formed by a cutting process. The arrangement direction of the active structure is perpendicular to the extension direction; in this direction, the plurality of fin structures are arranged at intervals.

[0042] For example, Figure 2 FIG. 1 is a top view of the stacked transistors in the embodiments of the present application. As shown in the figure, the top view shows a gate cut region, a fin structure, a gate structure and a source-drain structure. The gate cut region is located at two sides of the plurality of fin structures, and the gate cut region is parallel to the fin structure.

[0043] In an embodiment, the width of the gate cut region in the arrangement direction of the active structure can be slightly smaller than the width of the power supply rail in the arrangement direction of the active structure.

[0044] In the embodiments of the present application, the active structure has a first part and a second part, and the first part is connected to the substrate structure, and the second part is farther away from the substrate structure than the first part. The first part and the second part are formed by the same process, so that the first part and the second part are self-aligned. The first part is used to form a first active structure of a first transistor, and the second part is used to form a second active structure of a second transistor, so that a larger etching depth can be used when forming the active structure. For example, the height of the fin structure (which can also be a columnar structure or a bulk structure) obtained by etching can be greater than 100 nm.

[0045] It should be noted that the height of the active structure can be set according to actual conditions, and the embodiments of the present application do not make specific limitations.

[0046] In an embodiment, the power rail is embedded inside the substrate structure, partially in the substrate and partially in the shallow trench isolation structure. The providing a substrate structure in S101 includes forming a substrate and disposing a metal line on the substrate, which can form the power rail. The power rail can be embedded inside the substrate structure by depositing an oxide material on the power rail, which can form the shallow trench isolation structure. The active structure can be formed by depositing a semiconductor material on the substrate structure and etching the semiconductor material.

[0047] Here, the semiconductor material used to form the active structure can be selected according to actual needs, which is not specifically limited in the embodiments of the present application. For example, silicon (Si) material, silicon germanium (SiGe) material, etc.

[0048] It can be understood that when the type of the stacked transistor is different, the arrangement of the active structure is also different accordingly. For example, when the stacked transistor is a fin field effect transistor or a planar transistor, the active structure can be a structure made of one semiconductor material; when the stacked transistor is a fully wrapped gate transistor, the active structure can be a stacked structure made of multiple semiconductor materials, for example, a stack obtained by stacking silicon (Si) material and silicon germanium (SiGe) material.

[0049] In an embodiment, the substrate can be a silicon (Si) substrate; it can also be a silicon-on-insulator (SOI) substrate; of course, it can also be a substrate made of other semiconductor materials, which is not specifically limited in the embodiments of the present application.

[0050] In an embodiment, the active structure further includes a sacrificial layer between the first part and the second part. The steps of forming the substrate structure and the active structure include: providing a wafer and sequentially forming a first material layer and a second material layer on the wafer; etching the second material layer, the first material layer, and the first part of the wafer, and retaining the second part of the wafer. Depositing an oxide material on the second part of the wafer to form a first shallow trench isolation structure; the height of the first shallow trench structure is less than the height of the first part of the wafer. Etching a part of the first shallow trench isolation structure and the second part of the wafer on both sides of the active structure in the arrangement direction of the active structure. Forming a power rail at the etched position of the wafer; the height of the power rail is less than the height of the first shallow trench isolation structure; depositing an oxide material on the power rail to form a second shallow trench isolation structure; the height of the second shallow trench isolation structure is the same as the height of the first shallow trench isolation structure.

[0051] It can be understood that the first material layer and the second material layer can be formed by sequentially depositing the first material and the second material on the wafer. The first material is different from the material of the wafer, and the second material is different from the first material. The first part of the wafer can be reserved by etching the second material layer, the first material layer, and the first part of the wafer. The first shallow trench isolation structure can be formed by depositing an oxide material on the second part of the wafer which is not etched. In addition, the height of the first shallow trench isolation structure is less than the height of the first part of the wafer, so that the first shallow trench isolation structure can only partially wrap the first part of the wafer.

[0052] The etched first material layer forms a sacrificial layer; the etched second material layer forms a second part of the active structure; and the part of the first part of the wafer which is not wrapped by the first shallow trench structure forms a first part of the active structure.

[0053] For example, the wafer can be a silicon wafer, the first material can be a silicon germanium material, and the second material can be a silicon material. That is, the first part and the second part of the active structure can be formed of a silicon material, and the sacrificial layer can be formed of a silicon germanium material.

[0054] In the embodiments of the present application, the oxide material for forming the shallow trench isolation structure can be any one of the following: silicon dioxide (SiO2) or silicon carbide (SiCO), etc.

[0055] It should be noted that the etching process mentioned in the embodiments of the present application can include any one of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal process, which is not limited in the embodiments of the present application.

[0056] Further, by etching a part of the first shallow trench isolation structure and a part of the second part of the wafer on both sides of the active structure in the arrangement direction of the active structure, and reserving another part of the second part of the wafer, a setting groove of the power supply track can be formed on both sides of the active structure. Then, a power supply track is formed on the etched position of the wafer (the setting groove of the power supply track), and the height of the power supply track can be less than the height of the first shallow trench isolation structure. Then, an oxide material is deposited on the power supply track, so that the oxide material fills the setting groove of the power supply track, and a second shallow trench isolation structure is formed above the power supply track. The height of the second shallow trench isolation structure is the same as the height of the first shallow trench isolation structure.

[0057] The height of the second shallow trench isolation structure is the same as the height of the first shallow trench isolation structure, and the first shallow trench isolation structure and the second shallow trench isolation structure can form a shallow trench isolation structure in a substrate structure; and the etched second part of the wafer and the first part of the wafer wrapped by the first shallow trench structure can form a substrate in the substrate structure.

[0058] S102, depositing a first semiconductor material in the gate region of the substrate structure to form a dummy gate structure.

[0059] It can be understood that based on the exposed plurality of active structures, the first semiconductor material can be deposited on the active structures to form a plurality of dummy gate structures.

[0060] In some embodiments, after forming the dummy gate structure, a second spacer can be formed on both sides of the dummy gate structure. The second spacer is used to isolate the second gate structure and the second source-drain structure.

[0061] Here, the structure of the second spacer can be set according to actual needs, and the embodiments of the present application do not make specific limitations.

[0062] For example, the spacer can have a single-layer structure and be made of the same material (such as porous carbon silicon oxygen hydride (SiCOH)).

[0063] S103, removing the dummy gate structure in the gate cut region of the stacked transistor by a cutting process.

[0064] The gate cut region is located at the first edge portion and the second edge portion of the stacked transistor, and the first edge portion and the second edge portion are two edge portions arranged opposite to each other in the arrangement direction of the active structure, so that the gate isolation structure formed based on the gate cut region can realize isolation between semiconductor units.

[0065] It can be understood that based on the semiconductor structure formed by S102, the dummy gate structure in the gate cut region can be removed by the cutting process.

[0066] In an embodiment, when the dummy gate structure in the gate cut region is removed by the cutting process, the shallow trench isolation structure in the substrate structure can also be thinned. It should be noted that when the shallow trench isolation structure in the substrate structure is thinned, the depth of thinning cannot exceed the top surface of the power rail.

[0067] It can be seen that the gate cut region is also arranged on both sides of the active structure in the arrangement direction of the active structure, and the extension direction is the same as the extension direction of the active structure. The extension direction of the active structure refers to the direction in which the source-drain structure and the gate structure are alternately arranged, and the arrangement direction of the active structure is perpendicular to the extension direction of the active structure.

[0068] It should be noted that the cutting process can also cut the columnar structure or the block structure in the same way, so that the preparation method in the embodiments of the present application is applicable to the preparation of fin field effect transistors, fully wrapped gate transistors and planar transistors.

[0069] In some possible implementation, the removing the dummy gate structure in the gate cut region of the stacked transistor by the cutting-off process in S103 includes: depositing a second semiconductor material in the source-drain region of the stacked transistor respectively to form a dielectric layer structure. The dummy gate structure in the gate cut region and the dielectric layer structure in the source-drain region are removed by the cutting-off process.

[0070] It can be understood that, after the dummy gate structure is formed in the gate region and the dielectric layer structure is formed in the source-drain region, the gate cut region can be positioned, and the dummy gate structure in the gate cut region is removed by the cutting-off process.

[0071] In an embodiment, the semiconductor material for forming the dummy gate structure can be polysilicon, amorphous silicon, etc. The semiconductor material for forming the dielectric layer structure can be a dielectric material.

[0072] S103, depositing a nitride material in the gate cut region to form a first gate isolation structure and a second gate isolation structure.

[0073] It can be understood that, the nitride material can be deposited on the gate cut regions of the two ends of the stacked transistor to form the first gate isolation structure and the second gate isolation structure in the gate cut region. The first gate isolation structure is formed in the gate cut region close to the first power rail, and the second gate isolation structure is formed in the gate cut region close to the second power rail.

[0074] It can be understood that, the first gate isolation structure and the second gate isolation structure are respectively close to the first power rail and the second power rail, and the height of the first gate isolation structure and the second gate isolation structure matches the height required for preparing the upper and lower two-layer transistors, so that the upper and lower two-layer transistors can be isolated from other transistors on the wafer.

[0075] It should be noted that, by preparing the gate isolation structure between the transistors first, the source-drain metal structure and the power rail connection metal structure in the transistor do not need to be cut when the gate isolation structure is formed, so as to ensure the stability of the connection between the source-drain structure in the transistor and other structures (for example, the power rail).

[0076] In the embodiments of the present application, the nitride material for forming the gate isolation structure can be any one of the following: silicon nitride (SiN, Si3N4), boron nitride (BN), or aluminum nitride (AlN), etc.

[0077] S104, forming a first transistor based on the first part of the active structure and the first gate isolation structure.

[0078] Here, the first transistor includes a first source-drain structure, a first gate structure, a first source-drain metal, and a first power rail connection metal. The first source-drain metal is a connection metal of the first source-drain structure and a first metal interconnection layer formed in a later process. The first power rail connection metal is a connection metal of the first source-drain structure and the first power rail.

[0079] It can be understood that, after the first gate isolation structure and the second gate isolation structure are formed, the dielectric layer structure can be removed, the first source-drain structure is formed based on the first part of the active structure, and the metal structure (for example, the first source-drain metal and the first power rail connection metal) corresponding to the first source-drain structure is formed based on the first gate isolation structure.

[0080] In some embodiments, the active structure further includes a sacrificial layer between the first part and the second part. The forming of the first transistor based on the first part of the active structure and the first gate isolation structure in S104 includes removing the sacrificial layer in the second part of the active structure and the source-drain region. The first source-drain structure is formed based on the first part of the active structure. The first part of the first gate isolation structure is removed and the second part is retained in the source-drain region of the stacked transistor to partially expose the first power rail. The first part of the first gate isolation structure is closer to the first source-drain structure than the second part of the first gate isolation structure. The first source-drain metal and the first power rail connection metal are formed on the first source-drain structure and the exposed first power rail, respectively.

[0081] It can be understood that the dielectric layer structure can be removed by a selective removal process (for example, selective etching), and then the second part of the active structure in the source-drain region and the sacrificial layer in the source-drain region are etched away by an etching process to expose the first part of the active structure in the source-drain region. The first source-drain structure can be formed based on the exposed first part of the active structure. The first part of the first gate isolation structure in the source-drain region can be removed and the second part of the first gate isolation structure in the source-drain region can be retained, so that the part of the first power rail covered by the first part of the first gate isolation structure is exposed. The first source-drain metal and the first power rail connection metal can be formed by depositing metal materials on the first source-drain structure and the exposed first power rail, respectively.

[0082] Here, one end of the first power rail connection metal is connected to the first source-drain metal, and the other end is connected to the first power rail, so that the first power rail can supply power to the first transistor through the first power rail connection metal.

[0083] It should be noted that the first power rail connection metal in the embodiments of the present application can be formed after the first gate isolation structure is formed, which can ensure that the metal structure of the source / drain region in the first transistor will not be cut off when the gate isolation structure is formed by using the gate cut-off process, can effectively increase the cross-sectional area of the metal structure of the source / drain region, reduce the metal interconnection resistance, and improve the overall unit performance.

[0084] In an embodiment, forming the first source / drain structure based on the first portion of the active structure includes forming a first interlayer dielectric layer.

[0085] It should be noted that the first source / drain structure, the first source / drain metal, and the first interlayer dielectric layer can be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not make specific limitations thereto.

[0086] Illustratively, a source / drain recess can be formed at the exposed first portion of the active structure. Source / drain epitaxial growth can be performed at the source / drain recess to obtain the first source / drain structure. Metal material can be deposited above the first source / drain structure to obtain the first source / drain metal. Semiconductor material can be deposited on the side of the first source / drain structure to obtain the first interlayer dielectric layer.

[0087] Illustratively, a portion of the first active structure can be removed by etching to provide a source / drain recess of the first stacked transistor. A strained material such as silicon germanium or silicon carbide is formed by selective epitaxial growth to fill the source / drain recess of the first stacked transistor, and then a first source / drain structure is formed on the strained material by a heavy doping process.

[0088] It should be noted that, for the sake of convenience, the first source / drain structure mentioned in the embodiments of the present application is a simple term, which specifically refers to the first source structure and / or the first drain structure. In addition, the second source / drain structure, the first source / drain metal, the second source / drain metal, the source / drain recess, and the like are similar to the first source / drain structure, and "source / drain" is a simple term for "source electrode and / or drain electrode".

[0089] It should be noted that the stacked transistor includes a gate structure across the active structure, and the position of the gate structure can be divided into a gate region of the stacked transistor. The stacked transistor also includes source / drain structures located on both sides of the gate structure, and the position of the source / drain structure can be divided into a source / drain region of the stacked transistor. The gate region and the source / drain region can be arranged in a spaced manner.

[0090] In an embodiment, before forming the first source / drain structure based on the first portion of the active structure, the method further includes depositing semiconductor material at the intersection of the source / drain region and the gate region of the stacked transistor to form a protection layer covering the second portion of the active structure and the sacrificial layer.

[0091] It can be understood that, after the medium layer structure is removed, only the second part of the active structure of the source-drain region is removed, and the second part of the active structure of the gate region is still reserved, so as to be used for self-alignment formation of the second source-drain structure in a subsequent preparation step of the second transistor. At this time, a semiconductor material can be deposited on the sidewall of the second part of the active structure in the gate region of the stacked transistor, and the semiconductor material can form a protective layer in contact with the second part of the active structure of the gate region and the sacrificial layer of the gate region, so as to cover the second part of the active structure and the sacrificial layer.

[0092] Here, the protective layer can form protection for the second part of the active structure and the sacrificial layer. The protective layer can avoid that, when a process of epitaxially growing the first source-drain structure based on the first part of the active structure is used, the second source-drain structure is epitaxially grown on the second part of the active structure of the gate region in advance.

[0093] For example, the semiconductor material forming the protective layer can be silicon nitride (SiN, Si3N4).

[0094] In an embodiment, after the first source-drain structure is formed based on the first part of the active structure, the method further includes: removing the protective layer.

[0095] It can be understood that, by removing the protective layer, the second part of the active structure of the gate region and the sacrificial layer of the gate region are re-exposed, so as to facilitate formation of the second transistor based on the second part of the active structure in a subsequent step.

[0096] In an embodiment, after the first transistor is formed based on the first part of the active structure and the first gate isolation structure, the method further includes: depositing a semiconductor material in the source-drain region of the stacked transistor to form an isolation layer.

[0097] Here, the isolation layer is used to isolate the first source-drain structure and the second source-drain structure. The material forming the isolation layer can be selected according to actual needs, and the embodiments of the present disclosure do not make specific limitations on this.

[0098] In some embodiments, the first transistor formed based on the first part of the active structure and the first gate isolation structure in S104 further includes: removing the sacrificial layer in the gate region; and forming a first gate structure based on the first part of the active structure in the gate region of the stacked transistor.

[0099] Here, the first gate structure is between the first gate isolation structure and the second gate isolation structure.

[0100] It can be understood that by removing the sacrificial layer in the gate region, the first part of the active structure of the gate region can be exposed; then, the insulating material is deposited between the first gate isolation structure and the second gate isolation structure on the first part of the active structure, to form the first gate dielectric layer; and the metal material is deposited on the first gate dielectric layer, to form the first gate electrode layer. The first gate dielectric layer and the first gate electrode layer jointly constitute the first gate structure.

[0101] It should be noted that in the process of forming the first gate structure, only the gate structure needs to be formed between the first gate isolation structure and the second gate isolation structure, without the need to thin the gate isolation structure, so that the thickness of the gate isolation structure in the gate region is greater than the thickness of the gate isolation structure in the source-drain region, thereby reducing the space occupied by the gate isolation structure in the source-drain region and improving the compactness of the transistor structure. At the same time, the gate isolation structure is prepared before the source-drain metal structure is formed, which can avoid the source-drain metal structure being partially cut off in the process of preparing the gate isolation structure, thereby ensuring the integrity of the transistor structure.

[0102] It should be noted that the first gate structure can be formed by standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not make specific limitations thereto.

[0103] In the embodiments of the present application, the metal material for forming the first gate structure can be any one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), etc., and the embodiments of the present application do not make specific limitations thereto.

[0104] It should be noted that the first gate structure in the first transistor can also be formed after the second source-drain structure is formed, so as to ensure that the preparation of the source-drain region is not affected when the gate structure is formed.

[0105] S105, based on the second part of the active structure and the second gate isolation structure, a second transistor is formed.

[0106] Here, the second transistor includes a second source-drain structure, a second gate structure, a second source-drain metal, and a second power rail connection metal. The second source-drain metal is the connection metal of the second source-drain structure and the second metal interconnection layer formed in the subsequent process; and the second power rail connection metal is the connection metal of the second source-drain structure and the second power rail.

[0107] It can be understood that after the first source-drain structure, the first source-drain metal, and the first power rail connection metal of the first transistor are formed, the second source-drain structure can be formed based on the second part of the active structure, and the metal structure (for example, the second source-drain metal and the second power rail connection metal) corresponding to the second source-drain structure can be formed based on the second gate isolation structure.

[0108] In some embodiments, the second part of the active structure and the second gate isolation structure in S105 form a second transistor, including: forming a second source-drain structure in the source-drain region by an epitaxial growth process on the second part of the active structure in the gate region on the first transistor; removing the first part of the second gate isolation structure and retaining the second part to partially expose the second power rail in the source-drain region of the stacked transistor. The first part of the second gate isolation structure is closer to the second source-drain structure than the second part of the second gate isolation structure. A second source-drain metal and a second power rail connection metal are formed on the second source-drain structure and the exposed second power rail, respectively.

[0109] It can be understood that after the second part of the active structure in the source-drain region is removed, the second part of the active structure in the gate region is retained in the stacked transistor, and the second parts of the active structures in the adjacent two gate regions can be oppositely arranged. Then, the two oppositely arranged second parts of the active structures are epitaxially grown towards each other by an epitaxial growth process until the epitaxially grown parts of the active structures in the two gate regions are connected to grow the second source-drain structure in the source-drain region. Then, the first part of the second gate isolation structure close to the second source-drain structure in the source-drain region can be removed, and the second part of the second gate isolation structure far from the second source-drain structure in the source-drain region is retained to expose the part of the second power rail covered by the first part of the second source-drain structure. Then, a metal material can be deposited on the second source-drain structure and the exposed second power rail, respectively, to form a second source-drain metal and a second power rail connection metal.

[0110] It should be noted that since the second source-drain structure is epitaxially grown based on the second part of the active structure, the first source-drain structure is formed based on the first part of the active structure, and the first part and the second part of the active structure are self-aligned structures, the second source-drain structure and the first source-drain structure are self-aligned structures, which effectively improves the symmetry of the structure of the transistor.

[0111] Here, the two ends of the second power rail connection metal are connected to the second source-drain metal, and the other two ends are connected to the second power rail, so that the second power rail can supply power to the second transistor through the second power rail connection metal.

[0112] It should be noted that the second power rail connection metal in the embodiments of the present application can be formed after the second gate isolation structure is formed, which can ensure that the metal structure of the source-drain region in the second transistor will not be cut off when the gate isolation structure is formed by the gate cutting process, can effectively increase the cross-sectional area of the metal structure of the source-drain region, reduce the metal interconnection resistance, and improve the overall unit performance.

[0113] In some embodiments, the forming the second transistor based on the second part of the active structure and the second gate isolation structure in S105 further comprises:

[0114] forming a second gate structure based on the second part of the active structure in the gate region of the stacked transistor; the second gate structure is between the first gate isolation structure and the second gate isolation structure.

[0115] It should be noted that the preparation steps of the second gate structure can refer to the preparation steps of the first gate structure, and for the sake of brevity of the description, will not be repeated here.

[0116] In the embodiments of the present application, the materials of the first gate structure and the second gate structure can be made of the same or different metal materials according to actual conditions, and the embodiments of the present application do not make specific limitations thereon.

[0117] In some embodiments, after the second gate structure is prepared, a subsequent process (such as interconnection line medium deposition, metal line formation, lead-out pad formation, etc.) can be performed on the second gate structure and the second source-drain structure to form a metal interconnection layer of the stacked transistor.

[0118] In the embodiments of the present application, by first forming the first gate isolation structure and the second gate isolation structure in the gate cut region on both sides of the active structure, then forming the first transistor based on the first part of the active structure and the first gate isolation structure, and forming the second transistor based on the second part of the active structure and the second gate isolation structure, the metal structure of the source-drain region of the first transistor and the second transistor can be effectively eliminated during the formation of the gate isolation structure. At the same time, the cross-sectional area of the metal structure of the source-drain region can be increased, the metal interconnection resistance can be reduced, and the overall performance of the stacked transistor can be improved.

[0119] Further, since the first transistor and the second transistor are prepared based on the first part and the second part of the active structure formed in the same process, self-alignment between the first transistor and the second transistor is achieved.

[0120] Next, taking the active structure in the stacked transistor as a fin structure as an example, the preparation method of the stacked transistor provided in the embodiments of the present application is described. Figure 3 is a structure diagram of the stacked transistor in the embodiments of the present application. Among them, Figure 3 (a) in the (a) is a top view of the stacked transistor, and it should be noted that, for the sake of understanding, only the gate cut region, the fin structure, the gate structure, and the source-drain structure are shown in the top view; Figure 3 (b) in the (b) is a cross-sectional view of the stacked transistor along the cross-sectional direction of the gate structure (i.e. A-A' direction);Figure 3 (c) is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the source-drain structure (i.e. the B-B' direction); Figure 3 (d) is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the fin structure (i.e. the C-C' direction).

[0121] Referring to Figure 3 As shown in FIG. 1, the stacked transistor 10 includes a first transistor 11 and a second transistor 12, and the active structure in the stacked transistor 10 is a plurality of fin structures. The fin structures are divided into two parts, which are respectively denoted as a first part 111 of the fin structure and a second part 121 of the fin structure, the first part 111 of the fin structure is used to form a first active structure in the first transistor 11, and the second part 121 of the fin structure is used to form a second active structure in the second transistor 12.

[0122] The first transistor 11 and the second transistor 12 are stacked, and the first power rail connection metal 112 of the first transistor 11 is connected with a first power rail 113, and the second power rail connection metal 122 of the second transistor 12 is connected with a second power rail 123. The first power rail 113 and the second power rail 123 are respectively located on both sides of the fin structure.

[0123] The following will be described in combination with the above preparation method. Figure 3 As shown in FIG. 2, the preparation process of the stacked transistor is described. Figure 4 to 21 FIG. 2 is a schematic diagram of a preparation process of the stacked transistor in the embodiments of the present application, wherein, Figure 4 (a) to Figure 21 (a) in FIG. 3 is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the gate structure (i.e. the A-A' direction), Figure 4 (b) to Figure 21 (b) in FIG. 4 is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the source-drain structure (i.e. the B-B' direction); Figure 4 (c) to Figure 21 (c) in FIG. 5 is a cross-sectional view of the stacked transistor made along the cross-sectional direction of the fin structure (i.e. the C-C' direction).

[0124] In an example, a preparation process of the stacked transistor 10 can include the following steps:

[0125] The first step, a layer of silicon germanium material is epitaxially grown on a silicon substrate (wafer) 21 to form a first material layer 22, and then a layer of silicon material is epitaxially grown on the first material layer 22 to form a second material layer 23, to obtain a structure as shown in FIG. 6. Figure 4 The second step, for

[0126] The second step, for Figure 4The structure shown, complete the patterning and etching process, form the fin structure. Among them, first etching the second material layer 23, then etching the first material layer 22 in the middle, then etching the first part of the substrate 21, leaving the second part of the substrate 21, as shown in Figure 5 The structure shown.

[0127] It can be understood that the second material layer 23, the first material layer 22 and the first part of the substrate 21 after etching together constitute the fin structure. The second material layer 23 after etching forms the second part 121 of the fin structure, and the first material layer 22 after etching forms the sacrificial layer 24.

[0128] The third step, on the substrate 21 deposition of oxide material, until covering Figure 5 The fin structure in the first shallow trench isolation structure 25, and chemical mechanical planarization process on the surface of the first shallow trench isolation structure 25, as shown in Figure 6 The structure shown.

[0129] The fourth step, using etching process to etch Figure 6 The first shallow trench isolation structure 25 shown in Fig. 2 to a predetermined height, exposing the second part 121 of the fin structure and the sacrificial layer 24, so that the first shallow trench isolation structure 25 can cover the lower part of the first part of the substrate 21, as shown in Figure 7 The structure shown.

[0130] Among them, the upper part of the first part of the substrate 21 which is not covered by the first shallow trench isolation structure 25 forms the first part 111 of the fin structure.

[0131] It should be noted that the height of the second part 121 of the fin structure and the first part 111 of the fin structure can be greater than 100 nm.

[0132] The fifth step, using etching process in Figure 7 The first shallow trench isolation structure 25 and the substrate 21 shown in Fig. 2, etching out the power rail channel 27, as shown in Figure 8 The structure shown.

[0133] It should be noted that the power rail channel 27 is located on both sides of the fin structure in the arrangement direction of the fin structure, and the extension direction of the power rail channel is the same as the extension direction of the fin structure.

[0134] The sixth step, in Figure 8 The power rail channel 27 shown in Fig. 2 filled with power rail metal (BPR-Metal), forming the power rail (including the first power rail 113 and the second power rail 123), as shown in Figure 9 The structure shown.

[0135] The seventh step, in Figure 9Depositing oxide material on the power rail, forming a second shallow trench isolation structure, the second shallow trench isolation structure and the first shallow trench isolation structure 25 together form the shallow trench isolation structure 26 in the substrate structure in the one or more embodiments described above, obtaining a structure as shown in Figure 10 .

[0136] Further, the substrate 21 forms the substrate in the substrate structure in the one or more embodiments described above.

[0137] Eighth step, depositing polysilicon material on the gate region of the structure as shown in Figure 10 , forming a pseudo gate structure 29 common to the upper and lower fin structures, and forming a second spacer 30 on both sides of the pseudo gate structure, obtaining a structure as shown in Figure 11 .

[0138] Ninth step, depositing insulating material on the source-drain region of the structure as shown in Figure 11 , forming a dielectric layer structure 31, obtaining a structure as shown in Figure 12 .

[0139] Tenth step, removing the pseudo gate structure 29, the second spacer 30 and the dielectric layer structure 31 in the gate cut region by a gate structure cut-off process, and the shallow trench isolation structure 26 can be thinned to the top surface of the power rail; and depositing nitride material on the gate cut region, forming a first gate isolation structure 114 and a second gate isolation structure 124, obtaining a structure as shown in Figure 13 .

[0140] It should be noted that the specific position of the gate cut region can be as shown in Figure 2 .

[0141] Eleventh step, removing the dielectric layer structure 31 in the structure as shown in Figure 13 , obtaining a structure as shown in Figure 14 .

[0142] Twelfth step, removing the second part 121 of the fin structure and the sacrificial layer 24 in the source-drain region of the structure as shown in Figure 14 by an etching process, obtaining a structure as shown in Figure 15 .

[0143] Thirteenth step, removing the sacrificial layer 24 in the first spacer region of the structure as shown in Figure 15 by an etching process, and filling silicon nitride material in the first spacer region to form a first spacer 32, obtaining a structure as shown in Figure 16 .

[0144] Fourteenth step, deposit a layer of silicon nitride coating (Coat-SiN) at the intersection of the source-drain region and the gate region by isotropic deposition process to form a protective layer 33; the protective layer 33 covers the second part 121 of the fin structure of the gate region and the sacrificial layer 24, obtaining the structure as shown in Figure 17 .

[0145] It can be understood that the protective layer 33 is used to ensure that the top layer fin structure is not affected while the bottom layer source-drain structure is epitaxially grown.

[0146] Fifteenth step, epitaxially grow the first source-drain structure 115 of the first transistor 11 at the first part 111 of the fin structure as shown in Figure 17 , obtaining the structure as shown in Figure 18 .

[0147] Sixteenth step, remove the protective layer 33 as shown in Figure 18 , obtaining the structure as shown in Figure 19 .

[0148] Seventeenth step, etch a part of the first gate isolation structure 114 close to the first source-drain structure 115 to expose the first power rail 113 in the substrate structure, deposit metal material on the first source-drain structure 115 and the first power rail 113 to form the first source-drain metal 116 and the first power rail connection metal 112; and deposit semiconductor material on the periphery of the first source-drain structure 115 to form the first interlayer dielectric layer 118, obtaining the structure as shown in Figure 20 .

[0149] Eighteenth step, deposit insulating material in the source-drain region to form an isolation layer 34, obtaining the structure as shown in Figure 20 . Figure 21

[0150] The isolation layer 34 is used to isolate the first transistor 11 and the second transistor 12.

[0151] Nineteenth step, based on the second part 121 of the fin structure of the gate region as shown in Figure 21 , complete the epitaxial growth of the second source-drain structure 125, obtaining the structure as shown in Figure 22 .

[0152] Twentieth step, etch a part of the second gate isolation structure 124 close to the second source-drain structure 125 to expose the second power rail 123 in the substrate structure, and deposit metal material on the second source-drain structure 125 and the second power rail 123 to form the second source-drain metal 126 and the second power rail connection metal 122, obtaining the structure as shown in Figure 23 .

[0153] Twenty-first step, remove​Figure 23 The pseudo gate structure 29 is shown. The sacrificial layer 24 in the gate region is removed, and a dielectric material and a metal material are sequentially deposited on the fin structure in the gate region to form a first gate structure 117 and a second gate structure 127, respectively. A semiconductor material is deposited on the periphery of the second source-drain structure 125 to form a second interlayer dielectric layer 128, and a structure as shown in Figure 24 is obtained.

[0154] It should be noted that the first gate structure 117 and the second gate structure 127 are self-aligned between the first gate isolation structure 114 and the second gate isolation structure 124.

[0155] In a twenty-second step, a back-end interconnection process of the transistor is completed on the structure as shown in Figure 24 to form a metal interconnection layer 28, and a structure as shown in Figure 3 is obtained.

[0156] At this point, the first transistor and the second transistor are prepared.

[0157] In one or more embodiments of the above preparation of the stacked transistor, not only can the process flow of the stacked transistor be greatly simplified, but also the consistency of the active structure and the gate structure of the upper and lower transistors can be considered. In particular, the gate structure and the active structure of the upper and lower transistors are self-aligned and stacked. On the one hand, the long-term problems such as process complexity and alignment difficulty existing in the existing mainstream technical solutions of the stacked transistor are solved, and the industrialization of the transistor stacking technology is realized. On the other hand, the upper and lower transistors can have independent power supply networks and are connected through local interconnection. Without changing the design of the 4T track unit with extreme miniaturization, the metal wiring resources are greatly released.

[0158] Embodiments of the present application provide a semiconductor device, comprising: the stacked transistor of the above-mentioned embodiments. The specific limitations of the stacked transistor can be referred to the above-mentioned Figure 3 stacked transistor, which will not be repeated here.

[0159] Embodiments of the present application provide an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device is arranged on the circuit board. The semiconductor device comprises the above-mentioned stacked transistor. The specific limitations of the stacked transistor can be referred to the above-mentioned Figure 3 semiconductor structure, which will not be repeated here.

[0160] In the description of the application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are contained in at least one embodiment or example of the embodiments of the application. In the present application, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0161] The above only is the preferred embodiment of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for fabricating stacked transistors, characterized in that, The method includes: A substrate structure is provided, the substrate structure comprising: a substrate, a power rail, a shallow trench isolation structure, and an active structure; The shallow trench isolation structure covers the power rail; the power rail includes a first power rail and a second power rail; the first power rail and the second power rail are respectively disposed on both sides of the active structure in the arrangement direction of the active structure, and the extension direction of the first power rail and the second power rail is the same as the extension direction of the active structure; the active structure has a first part and a second part, and the first part is closer to the substrate structure than the second part. A first semiconductor material is deposited in the gate region of the substrate structure to form a pseudo-gate structure; The dummy gate structure located within the gate cut region of the stacked transistor is removed by a cutting process; wherein the gate cut region is located at the first edge portion and the second edge portion of the stacked transistor, and the first edge portion and the second edge portion are two edge portions disposed opposite to each other in the arrangement direction of the active structure; Nitride material is deposited within the gate cut region to form a first gate isolation structure and a second gate isolation structure; the first gate isolation structure and the second gate isolation structure are located at the first edge portion and the second edge portion, respectively; A first transistor is formed based on the first portion of the active structure and the first gate isolation structure; the first transistor includes a first source-drain structure, a first gate structure, a first source-drain metal, and a first power rail connection metal; the first power rail connection metal connects the first power rail and the first source-drain metal. A second transistor is formed based on the second portion of the active structure and the second gate isolation structure; the second transistor includes a second source-drain structure, a second gate structure, a second source-drain metal, and a second power rail connection metal; the second power rail connection metal connects the second power rail and the second source-drain metal. The active structure further includes a sacrificial layer located between the first portion and the second portion; wherein forming a first transistor based on the first portion of the active structure and the first gate isolation structure includes: removing the second portion of the active structure and the sacrificial layer in the source-drain region; forming a first source-drain structure based on the first portion of the active structure; removing the first portion of the first gate isolation structure and retaining the second portion in the source-drain region of the stacked transistor to partially expose the first power rail; wherein the first portion of the first gate isolation structure is closer to the first source-drain structure than the second portion of the first gate isolation structure; and forming a first source-drain metal and a first power rail connection metal on the first source-drain structure and the exposed first power rail, respectively.

2. The method according to claim 1, characterized in that, The method of forming a first transistor based on the first portion of the active structure and the first gate isolation structure further includes: Remove the sacrificial layer within the gate region; In the gate region of the stacked transistor, a first gate structure is formed based on a first portion of the active structure; the first gate structure is located between the first gate isolation structure and the second gate isolation structure.

3. The method according to claim 1, characterized in that, Before forming the first source-drain structure based on the first portion of the active structure, the method further includes: Semiconductor material is deposited on the sidewall of the second portion of the active structure within the gate region of the stacked transistor to form a protective layer covering the second portion of the active structure. After forming a first source-drain structure based on the first part of the active structure, the method further includes: Remove the protective layer.

4. The method according to claim 1, characterized in that, The second transistor is formed based on the second portion of the active structure and the second gate isolation structure, including: Based on the second portion of the active structure in the gate region, a second source / drain structure is formed in the source / drain region by an epitaxial growth process. In the source-drain region of the stacked transistor, a first portion of the second gate isolation structure is removed, and a second portion is retained to partially expose the second power rail; wherein the first portion of the second gate isolation structure is closer to the second source-drain structure than the second portion of the second gate isolation structure. A second source / drain metal and a second power rail connection metal are formed on the second source / drain structure and the exposed second power rail, respectively.

5. The method according to claim 4, characterized in that, The second transistor, formed based on the second portion of the active structure and the second gate isolation structure, further includes: In the gate region of the stacked transistor, a second gate structure is formed based on the second portion of the active structure; the second gate structure is located between the first gate isolation structure and the second gate isolation structure.

6. The method according to claim 1, characterized in that, The removal of the dummy gate structure located within the gate cut region of the stacked transistors by the cutting process includes: A second semiconductor material is deposited in the source and drain regions of the stacked transistors to form a dielectric layer structure; The pseudo-gate structure located within the gate cutting region and the dielectric layer structure within the source / drain region are removed by a cutting process.

7. The method according to claim 1, characterized in that, The provision of a substrate structure includes: A wafer is provided, and a first material layer and a second material layer are sequentially formed on the wafer; The second material layer, the first material layer, and a first portion of the wafer are etched, while the second portion of the wafer is retained; the etched first material layer forms the sacrificial layer; the etched second material layer forms the second portion of the active structure. An oxide material is deposited on the second portion of the wafer to form a first shallow trench isolation structure; the height of the first shallow trench structure is less than the height of the first portion of the wafer; the first portion of the wafer not enclosed by the first shallow trench structure forms the first portion of the active structure. In the arrangement direction of the active structure, the first shallow trench isolation structure located on both sides of the active structure and a portion of the second part of the wafer are respectively etched; A power rail is formed at the etched location on the wafer; the height of the power rail is less than the height of the first shallow trench isolation structure. An oxide material is deposited on the power rail to form a second shallow trench isolation structure; the height of the second shallow trench isolation structure is the same as the height of the first shallow trench isolation structure. The first shallow trench isolation structure and the second shallow trench isolation structure form the shallow trench isolation structure; the second part of the etched wafer and the first part of the wafer wrapped by the first shallow trench structure form the substrate.

8. A stacked transistor, fabricated using the fabrication method according to any one of claims 1 to 7, characterized in that, include: First transistor; The second transistor is provided in a stacked configuration of the first crystal and the second transistor. Wherein, the first active structure of the first transistor and the second active structure of the second transistor constitute an active structure, and the first source-drain structure of the first transistor and the second source-drain structure of the second transistor are self-aligned.

9. A semiconductor device, characterized in that, include: The stacked transistor as described in claim 8.

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