Data transfer system based on DMA

Abstract

The present invention relates to the technical field of data transmission, and particularly to a DMA-based data transmission system, which includes a software module and a hardware module. The software module includes N first storage areas and R second storage areas; the hardware module includes a DMA engine, N first transmission channels, and R second transmission channels; the DMA engine is respectively connected to the software module, N first transmission channels, and R second transmission channels; the software module is used to store data D in HM n ; n The DMA engine is used to obtain data D n and cache D n into the PF n of P n ; P n is used to transmit D n in the PF n to a first target device; Q r is used to receive data E r in a second target device, cache E r into the QF r of Q r ; the DMA engine is used to transmit E r to the software module; the software module is used to store E r in CM r . The present invention reduces the DMA transmission delay and improves the effective data transmission rate.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a DMA-based data transmission system. Background Art

[0002] In the process of executing data transfer (DMA), the existing data transmission system usually needs software to initiate DMA operations, and the software and hardware need to interact frequently, which increases the DMA transmission delay. In addition, the existing data transmission system transmits data through the data channel from the software to the end of the system bus. Once the data path is blocked, it will affect the normal operation of the software and reduce the effective data transmission rate. Therefore, how to reduce DMA transmission delay and increase the effective data transmission rate has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present invention aims to provide a DMA-based data transmission system, which reduces DMA transmission delay and improves the effective data transmission rate.

[0004] According to a first aspect of the present invention, a DMA-based data transmission system is provided, comprising a software module and a hardware module, wherein the software module comprises N first storage areas {HM 1 ,HM 2 ,…,HM n ,…,HM N} and R second storage areas {CM 1 ,CM 2 ,…,CM r ,…,CM R}, where HM n The nth first storage area, n ranges from 1 to N, CM r is the rth second storage area, and the value range of r is 1 to R;

[0005] The hardware module includes a DMA engine, N first transmission channels {P 1 ,P 2 ,…,P n ,…,P N}, R second transmission channels {Q 1 ,Q 2 ,…,Q r ,…,Q R}, P n is the nth first transmission channel, Q r is the rth second transmission channel, P n The corresponding buffer PF is set in n , Q r A corresponding buffer QF is set in r ;

[0006] The DMA engine is respectively connected to the software module, the N first transmission channels and the R second transmission channels;

[0007] The software module is used to provide HM n Data stored in D n ;

[0008] The DMA engine is used to obtain data D n , D n Cache to P n PF n middle;

[0009] P n For PF n D n transmitting to a first target device;

[0010] Q r For receiving data E in the second target device r , E r Cache to Q r QF r middle;

[0011] The DMA engine is used to transfer Er to CM r middle;

[0012] The software module is used to r Read E r .

[0013] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the data transmission system based on DMA provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0014] The system of the present invention divides DMA transmission into the stage of transmission in the software module, the stage of transmission in the hardware module, and the stage of transmission from the hardware stage to the target device. The congestion of any stage will not directly affect the data transmission process of other transmission stages. Under the condition of a certain bandwidth, the effective data transmission rate is improved. In addition, the system of the present invention reduces the interaction process between the hardware module and the software module, and reduces the DMA transmission delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of a DMA-based data transmission system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0018] The embodiment of the present invention provides a data transmission system based on DMA, such as Figure 1 As shown, it includes a software module and a hardware module, wherein the software module includes N first storage areas {HM 1 ,HM 2 ,…,HM n ,…,HM N} and R second storage areas {CM 1 ,CM 2 ,…,CM r ,…,CM R}, where HM n is the nth first storage area, where n ranges from 1 to N, and N is the total number of first storage areas. r is the rth second storage area, the value range of r is 1 to R, and R is the total number of second storage areas.

[0019] The hardware module includes a DMA (Data Memory Access) engine, N first transmission channels {P 1 ,P 2 ,…,P n ,…,P N}, R second transmission channels {Q 1 ,Q 2 ,…,Q r ,…,Q R}, P n is the nth first transmission channel, Q r is the rth second transmission channel, P n The corresponding buffer PF is set in n , Qr is provided with a corresponding buffer QF r , PF n , QF r Specifically, it can be set as FIFO. A corresponding buffer is set in each transmission channel, so that whether the software module is temporarily blocked or the path from the hardware module to the target device is temporarily blocked, it will not affect the data transmission of the hardware module. In addition, when the path from the hardware module to the target device is temporarily blocked, it will not affect the normal operation of the software module. N ≤ K - 1, R < K - 1, where K is the number of communication channels corresponding to DMA. One communication channel can set a first transmission channel and a second transmission channel at the same time. It should be noted that one of the channels of DMA needs to be used when configuring the registers of the hardware module at the initial moment, and this channel cannot set the first transmission channel and the second transmission channel. Some status information of the hardware module needs to be transmitted to the software module, so it also needs to occupy a channel in the same direction as the second transmission channel in a communication channel, and a first transmission channel can also be set in this channel. Therefore, N ≤ K - 1, R < K - 1.

[0020] The DMA engine is respectively connected to the software module, N first transmission channels and R second transmission channels. The system mainly performs the operations of DMA writing data and DMA reading data. The software module is used to store data D n into HM n . It should be noted that D n generally refers to all data that needs to be stored into HM n . The DMA engine is used to obtain data D n , cache D n into PF n of P n ; P n is used to transmit D n in PF n to the first target device; thus realizing the operation of DMA writing data. Q r is used to receive data E r in the second target device. E r generally refers to all data that needs to be stored into CM r . Cache E r into QF r of Q r ; the DMA engine is used to move Er to CM r ; the software module is used to read E r from CM r ; thus realizing the operation of DMA reading data. The first target device and the second target device can be the same device or different devices. Figure 1In the example, simplification is performed to simplify the first target device and the second target device into one target device, but it can be understood that the target device is not limited to one, and the first target device and the second target device can be different target devices.

[0021] It should be noted that the system divides DMA transmission into the stage of transmission in the software module, the stage of transmission in the hardware module, and the stage of transmission from the hardware stage to the target device. The congestion of any stage will not directly affect the data transmission process of other transmission stages, thereby improving the effective data transmission rate.

[0022] The system of the embodiment of the present invention reduces the interaction between the hardware module and the software module and reduces the DMA delay. In order to further reduce the mutual dependence between the hardware module and the software module, data transmission can be achieved by maintaining pointers without frequent interaction between the hardware module and the software module. As an embodiment, HM n Including the corresponding producer pointer HP n and the consumer pointer HC n , HP n For HM n The address where the current data is stored, HC n For HM n The address of the currently read data in the HP n and CC r ; The hardware module is used to maintain HC n and CP r Among them, the producer is the party that generates data, and the consumer is the party that uses data. r Including the corresponding producer pointer CP r and consumer pointer CC r , CP r Used to point to CM r The address where the current data is stored, CC r Used to point to CM r The address of the currently read data in the storage area. According to the producer and consumer pointers corresponding to each storage area, it can be determined whether there is data that can be read at present, and whether there is storage space to continue writing data.

[0023] As an embodiment, during the process of executing the DMA write operation, the system:

[0024] The software module is used for HP n and HC n To HM n Write D n , Update HP n, and the updated HP n Synchronize to the hardware module. Based on HP n and HC n It can be determined whether there is enough space to write D n .

[0025] The hardware module is used to compare HC n and HP n , judge HM n Is there any D to be transported? n , if it exists, then determine the current PF n Is there any D to be transported? n If the corresponding storage space exists, the DMA engine initiates the transfer of the data from the software direction to the hardware direction. n The data transfer from software to hardware is initiated by the hardware module, not the software module, thus reducing the interaction between software and hardware.

[0026] The DMA engine is used to transfer data from the software direction to the hardware direction. n The operation instructions obtain the D to be transported n , the D to be transported n Cache to P n PF n In the hardware module, the HC n , and the updated HC n Synchronize to the software module.

[0027] As an embodiment, during the process of performing a DMA read operation, the system:

[0028] The software module is used for CC-based r and CP r From CM r Read data and update CC r , and the updated CC r Synchronize to the hardware module. r and CP r It can be determined whether there is currently a readable E r , if it exists, then from CM r Read data and update CC r .

[0029] The hardware module is used to compare the current CC r and CP r , judge CM r Is there any E to be transported? r The corresponding storage space, if it exists, determines QF rIs there any E to be transported? r If the corresponding storage space exists, the DMA engine initiates the transfer of E from the hardware direction to the software direction. r Operation instructions; transfer from hardware to software r The operation instructions are also initiated by the hardware module, without the need for the software module, thus reducing the interaction between software and hardware.

[0030] The DMA engine is used to transfer data from the hardware direction to the software direction. r The operation instruction obtains the E to be transported from the second target device r , the E to be transported r Cache to Q r QF r It is also used to convert E r From QF r Transport to CM r middle.

[0031] The software module is used to r Read E r , completing the DMA read operation.

[0032] After the hardware module completes the DMA read operation, it updates the CP r , the updated CP r Synchronize to the software module.

[0033] As an embodiment, the software module further includes a third storage area SM, and the hardware module further includes a status register, a status information transmission channel, a P n The corresponding control state machine PL n , Q r The corresponding control state machine QL r , each PL n and QL r Both are connected to the state information transmission channel.

[0034] The status register is used to store the latest updated HP sent by the software module. n and current CC r , so that the hardware module can obtain the latest HP n and CC r .

[0035] PL n Used to obtain updated HC n , and the updated HC n The state information is transmitted to the SM of the software module through the state information transmission channel; it should be noted that HC n It can also carry the identifier of the corresponding transmission channel.

[0036] QL r Used to obtain updated CP r , and the updated CP r The state information is transmitted to the SM of the software module through the state information transmission channel; it should be noted that CP r It can also carry the identifier of the corresponding transmission channel.

[0037] As an embodiment, the software module includes a status acquisition thread, and the status acquisition thread is used to poll the SM to obtain the HC in the SM. n and CP r It should be noted that the state acquisition thread polling SM will not frequently use the host CPU, which can improve CPU utilization.

[0038] As an embodiment, the DMA engine is an XDMA engine, and XDMA includes four communication channels {CH 1 ,CH 2 ,CH 3 ,CH 4}, CH 1 It is the first communication channel of XDMA and is used to configure the hardware module at the initial moment, specifically the configuration register. 2 The second communication channel of XDMA, CH 2 Including HM 1 and CM 1 , CH 3 The third communication channel of XDMA, CH 3 Including HM 2 and CM 2 , CH 4 The third communication channel of XDMA, the status information transmission channel is set on CH 4 middle.

[0039] As an embodiment, the DMA engine communicates based on a PCIE bus, which can further increase the data transmission rate.

[0040] Different transmission channels can be selected for use according to their usage, or different channels can be divided according to data priority to further improve data transmission efficiency. 2 Used to transmit the highest priority data, CH 3 Used to transmit data other than the highest priority data.

[0041] As an embodiment, the system includes a routing module, the routing module is connected to the hardware module and the target device, and the routing module is used to transmit the PF n D n Transmit to the first target device, or receive data E in the second target device r , E r Transmitted to the hardware module. It should be noted that, through the routing module, any target device can transfer data with any storage area of ​​the software module.

[0042] The system of the embodiment of the present invention divides DMA transmission into the stage of transmission in the software module, the stage of transmission in the hardware module, and the stage of transmission from the hardware stage to the target device. The congestion of any stage will not directly affect the data transmission process of other transmission stages. Under the condition of a certain bandwidth, the effective data transmission rate is improved. In addition, the system of the present invention reduces the interaction process between the hardware module and the software module, and reduces the DMA transmission delay.

[0043] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A DMA-based data transmission system, characterized in that: It includes a software module and a hardware module, wherein the software module includes N first storage areas {HM1, HM2, ..., HM n ,…,HM N } and R second storage areas {CM1, CM2, ..., CM r ,…,CM R }, where HM n The nth first storage area, n ranges from 1 to N, CM r is the rth second storage area, and the value range of r is 1 to R; The hardware module includes a DMA engine, N first transmission channels {P1, P2, ..., P n ,…,P N }, R second transmission channels {Q1, Q2, ..., Q r ,…,Q R }, P n is the nth first transmission channel, Q r is the rth second transmission channel, P n The corresponding buffer PF is set in n , Q r A corresponding buffer QF is set in r ; The DMA engine is respectively connected to the software module, the N first transmission channels and the R second transmission channels; The software module is used to provide HM n Data stored in D n ; The DMA engine is used to obtain data D n , D n Cache to P n PF n middle; P n For PF n D n transmitting to a first target device; Q r For receiving data E in the second target device r , E r Cache to Q r QF r middle; The DMA engine is used to transfer E r Transport to CM r middle; The software module is used to r Read E r ; HM n Including the corresponding producer pointer HP n and consumer pointer HC n , HP n For HM n The address where the current data is stored, HC n For HM n The address where the current read data arrives; CM r Including the corresponding producer pointer CP r and consumer pointer CC r , CP r Used to point to CM r The address where the current data is stored, CC r Used to point to CM r The address where the current read data arrives; The software module is used to maintain HP n and CC r ; The hardware module is used to maintain HC n and CP r ; When the system performs a DMA write operation: The software module is used for HP n and HC n To HM n Write D n , Update HP n , and the updated HP n Synchronizing to the hardware module; The hardware module is used to compare HC n and HP n , judge HM n Is there any D to be transported? n , if it exists, then determine the current PF n Is there any D to be transported? n If the corresponding storage space exists, the DMA engine initiates the transfer from the software direction to the hardware direction. n Operation instructions; The DMA engine is used to transfer data from the software direction to the hardware direction. n The operation instructions obtain the D to be transported n , the D to be transported n Cache to P n PF n In the hardware module, the HC n , and the updated HC n Synchronize to the software module.

2. The system according to claim 1, characterized in that When the system performs a DMA read operation: The software module is used for CC-based r and CP r From CM r Read data and update CC r , and the updated CC r Synchronizing to the hardware module; The hardware module is used to compare the current CC r and CP r , judge CM r Is there any E to be transported? r The corresponding storage space, if it exists, determines QF r Is there any E to be transported? r If the corresponding storage space exists, the DMA engine initiates the transfer from the hardware direction to the software direction. r Operation instructions; The DMA engine is used to transfer data from the hardware direction to the software direction. r The operation instruction obtains the E to be transported from the second target device r , the E to be transported r Cache to Q r QF r It is also used to convert E r From QF r Transport to CM r middle; The software module is used to r Read E r , complete the DMA read operation; After the hardware module completes the DMA read operation, it updates the CP r , the updated CP r Synchronize to the software module.

3. The system according to claim 1, characterized in that The software module also includes a third storage area SM, and the hardware module also includes a status register, a status information transmission channel, a P n The corresponding control state machine PL n , Q r The corresponding control state machine QL r , each PL n and QL r are all connected to the state information transmission channel; The status register is used to store the latest updated HP sent by the software module. n and current CC r ; PL n Used to obtain updated HC n , and the updated HC n Transmitted to the SM of the software module through the state information transmission channel; QL r Used to obtain updated CP r , and the updated CP r The status information is transmitted to the SM of the software module through the status information transmission channel.

4. The system according to claim 3, characterized in that The software module includes a status acquisition thread, which is used to poll the SM to obtain the HC in the SM. n and CP r .

5. The system according to claim 3, characterized in that The DMA engine is an XDMA engine, XDMA includes 4 communication channels {CH1, CH2, CH3, CH4}, CH1 is the first communication channel of XDMA, used to configure the hardware module at the initial moment, CH2 is the second communication channel of XDMA, CH2 includes HM1 and CM1, CH3 is the third communication channel of XDMA, CH3 includes HM2 and CM2, CH4 is the fourth communication channel of XDMA, and the status information transmission channel is set in CH4.

6. The system according to claim 5, characterized in that CH2 is used to transmit the highest priority data, and CH3 is used to transmit other data except the highest priority data.

7. The system according to claim 1, characterized in that The DMA engine communicates based on the PCIE bus.

8. The system according to claim 1, characterized in that The system includes a routing module, which is connected to the hardware module and the target device, and is used to transmit the PF n D n Transmit to the first target device, or receive data E in the second target device r , E r Transmitted to the hardware module.

Images