An oxide array substrate and a method for manufacturing the same

Abstract

The application provides an oxide array substrate and a preparation method thereof. The array substrate comprises a glass substrate, a bottom gate, a first gate insulating layer, a semiconductor layer, a second gate insulating layer, a top gate and a drive circuit trace, a first intermediate insulating layer, a first transparent conductive layer, a third metal layer, a second intermediate insulating layer and a second transparent conductive layer. The first semiconductor unit of the semiconductor layer is provided with a conductor area at both ends, and the second semiconductor unit corresponds to the bottom gate. The top gate is located above the first semiconductor unit. The first source and drain of the third metal layer are connected with the conductor area, the second source and drain are connected with the second semiconductor unit, and the metal unit one is connected with the drive circuit trace. The film layer structure corresponding to the top gate is a drive circuit area TFT, the film layer structure corresponding to the bottom gate is a display area TFT, and the film layer structure corresponding to the drive circuit trace is a metal wire area. The application can improve the problem of large parasitic capacitance in the existing structure, and has the advantages of low cost, simple structure, high film utilization rate and the like.

Description

[Technical Field]

[0001] This invention relates to the field of liquid crystal display technology, specifically to an oxide array substrate and its preparation method. [Background Technology]

[0002] In the field of liquid crystal displays (LCDs), FFS (Fringe Field Switching) technology is a liquid crystal display technology that utilizes the edge electric field generated between the top strip pixel electrodes and the bottom planar COM electrodes (Bottom COM) or between the top COM pixel electrodes and the bottom planar pixel electrodes (Bop COM) on the TFT substrate. This allows liquid crystal molecules between the electrodes and directly above the electrodes to rotate on a plane parallel to the glass substrate. LCD panels employing the FFS pixel structure feature high transmittance, high viewing angle, high contrast, and high color gamut, making it the primary pixel structure type for high-end LCD panels.

[0003] Thin-film transistors (Mox-TFTs) fabricated using metal-oxide-semiconductor materials have become one of the important development technologies for array substrates in display panels due to their advantages such as low leakage current, high field-effect mobility, and good regional uniformity. Existing array substrates fabricated using Mox-TFTs generally employ bottom-gate TFT structures, such as etch-block (ESL) and back-channel (BCE) types, or top-gate TFT structures, such as self-aligned top-gate types. Different types of TFTs have their own structural advantages when applied to array substrates. Back-channel bottom-gate TFTs have advantages such as simple structure, short process flow, low cost, and high yield. However, due to the large overlap area between the gate and source / drain electrodes in the bottom-gate structure, and the fact that the gate and source / drain electrodes are only separated by a gate insulating layer, the small spacing results in a large parasitic capacitance between the upper and lower metal lines, increasing power consumption and hindering the development of high-resolution, high-refresh-rate display panels. In the self-aligned top-gate TFT structure, there is virtually no overlap between the gate and the source / drain. A thicker intermediate insulating layer is provided between the upper and lower metals, resulting in a smaller overall parasitic capacitance. However, the self-aligned top-gate TFT structure is relatively complex and the fabrication process is quite cumbersome. An additional light-shielding layer is also required in the liquid crystal display panel to reduce the impact of backlight on the light leakage of the semiconductor material. This metal layer only serves as a light-shielding layer, resulting in a high processing time but low film utilization, which is not conducive to cost reduction. [Summary of the Invention]

[0004] One of the technical problems to be solved by the present invention is to provide an oxide array substrate that can improve the problems of large parasitic capacitance and single function of light-shielding layer in the existing structure, and also has the advantages of low cost, simple structure and high thin film utilization.

[0005] The present invention achieves one of the above-mentioned technical problems in the following way:

[0006] An oxide array substrate, the oxide array substrate comprising: a glass substrate,

[0007] A first metal layer is disposed on the glass substrate, and the first metal layer includes a bottom gate.

[0008] A first gate insulating layer is disposed on the first metal layer;

[0009] A semiconductor layer is disposed on the first gate insulating layer. The semiconductor layer includes a first semiconductor unit and a second semiconductor unit. The two ends of the first semiconductor unit are respectively conductive to form conductive regions. The position of the second semiconductor unit corresponds to the position of the bottom gate.

[0010] A second gate insulating layer is disposed on the semiconductor layer;

[0011] A second metal layer is disposed on the second gate insulating layer. The second metal layer includes a top gate and driving circuit traces. The top gate is located above the first semiconductor cell.

[0012] A first intermediate insulating layer is disposed on the second metal layer. The first intermediate insulating layer has a first through-hole, a second through-hole, and a third through-hole. There are two first through-holes, which are respectively located on both sides of the top gate and penetrate downward through the second gate insulating layer, exposing the upper surface of the conductor regions at both ends of the first semiconductor unit. There are two second through-holes, which are respectively located above the second semiconductor unit and penetrate downward through the second gate insulating layer, exposing the upper surface of the second semiconductor unit. The third through-hole is located above the driving circuit trace, exposing the upper surface of the driving circuit trace.

[0013] A first transparent conductive layer is disposed on the first intermediate insulating layer;

[0014] A third metal layer is disposed on the first intermediate insulating layer. The third metal layer includes a first source, a first drain, a second source, a second drain, and a first metal unit. The first source and the first drain are respectively connected to the corresponding conductor regions through corresponding first vias. The second source and the second drain are respectively connected to the two ends of the second semiconductor unit through corresponding second vias. One end of the second drain is also connected to one end of the first transparent conductive layer. The first metal unit is connected to the driving circuit traces through a third via.

[0015] A second intermediate insulating layer is disposed on the first transparent conductive layer and the third metal layer. The second intermediate insulating layer has a fourth through hole, which is located above the first metal unit and exposes the upper surface of the first metal unit.

[0016] The second transparent conductive layer is disposed on the second intermediate insulating layer and is connected to the metal unit through the fourth through hole;

[0017] The film structure corresponding to the top gate is the driving circuit area TFT, the film structure corresponding to the bottom gate is the display area TFT, and the film structure corresponding to the driving circuit trace is the metal line area.

[0018] Furthermore, the non-channel regions at both ends of the first semiconductor unit are subjected to ion doping treatment to make the region conductive, forming a conductive region.

[0019] The second technical problem to be solved by the present invention is to provide a method for preparing an oxide array substrate. The oxide array substrate prepared by the method can improve the problems of large parasitic capacitance and single function of light-shielding layer in the existing structure, and also has the advantages of low cost, simple structure and high thin film utilization.

[0020] The present invention achieves the second technical problem mentioned above in the following way:

[0021] A method for fabricating an oxide array substrate, comprising the following steps:

[0022] Step 1: Form a first metal layer on a glass substrate to fabricate the bottom gate and related driving signal lines;

[0023] Step 2: Form a first gate insulating layer on the first metal layer; the first gate insulating layer in the display area serves as the bottom gate TFT gate insulating layer, and the first gate insulating layer in the driving circuit area serves as the active layer, i.e., the buffer layer below the first semiconductor unit;

[0024] Step 3: A semiconductor layer is formed on the first gate insulating layer, and a first semiconductor unit and a second semiconductor unit are fabricated. Then, the left and right ends of the first semiconductor unit are conductiveized to form a conductive region.

[0025] Step 4: Form a second gate insulating layer on the semiconductor layer as the gate insulating layer of the top gate TFT;

[0026] Step 5: Form a second metal layer on the second gate insulating layer, and fabricate the top gate and drive circuit traces, or other signal traces;

[0027] Step 6: Form a first intermediate insulating layer on the second metal layer;

[0028] Step 7: Form a first transparent conductive layer on the first intermediate insulating layer and prepare a pixel electrode; then prepare a first through-hole, a second through-hole and a third through-hole on the first intermediate insulating layer, and expose the upper surface of the conductor region at both ends of the first semiconductor unit, the upper surface of the second semiconductor unit, and the upper surface of the driving circuit trace, respectively.

[0029] Step 8: A third metal layer is formed on the first intermediate insulating layer, and a first source, a first drain, a second source, a second drain, and a metal unit 1 are fabricated; wherein the first source and the first drain are respectively connected to the corresponding conductor regions through corresponding first vias; the second source and the second drain are respectively connected to both ends of the second semiconductor unit through corresponding second vias; one end of the second drain is also overlapped with the adjacent end of the first transparent conductive layer; the metal unit 1 is connected to the driving circuit trace through a third via;

[0030] Step 9: Form a second intermediate insulating layer on the third metal layer and prepare a fourth through hole to expose the upper surface of the first metal unit;

[0031] Step 10: Form a second transparent conductive layer on the second intermediate insulating layer to prepare a common electrode. The common electrode is connected to the metal unit through a fourth through hole.

[0032] Furthermore, the first metal layer, the second metal layer, and the third metal layer are selected from aluminum, molybdenum, titanium, nickel, copper, silver, and tungsten to form a single-layer structure, or a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

[0033] Furthermore, the first gate insulating layer, the second gate insulating layer, the first intermediate insulating layer, and the second intermediate insulating layer are single-layer or multi-layer structures, and the materials are inorganic oxides or insulating compounds.

[0034] Furthermore, the first transparent conductive layer and the second transparent conductive layer are made of ITO.

[0035] The present invention has the following advantages:

[0036] This invention proposes a novel metal oxide TFT array substrate structure, in which top-gate and bottom-gate TFT devices are respectively provided at the corresponding positions of the driving circuit area and the display area in the array substrate. Therefore, this array substrate structure retains the low parasitic capacitance driving advantage of the top-gate structure and overcomes the disadvantage of the single function of the added light-shielding layer in the existing structure. Furthermore, the second transparent conductive layer is further away from the lower metal layer, which can further reduce the parasitic capacitance effect between the common electrode and the lower metal layer. At the same time, this invention also has the advantage of low manufacturing cost, which is suitable for the low-cost development of high-resolution and high-refresh-rate display panels.

[0037] In addition, the present invention performs conductor treatment on both ends of the semiconductor layer at the top gate TFT position, which can reduce the contact resistance of the source and drain contact regions. [Attached Image Description]

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0039] Figure 1 This is a schematic diagram of the structure of an oxide array substrate according to the present invention.

[0040] Figure 2 This is a flowchart of steps 1-5 of a method for preparing an oxide array substrate according to the present invention.

[0041] Figure 3 This is a flowchart of steps 6-10 of the method for preparing an oxide array substrate according to the present invention.

[0042] Explanation of reference numerals in the attached figures:

[0043] Glass substrate 1;

[0044] First metal layer 2, bottom gate 21;

[0045] First gate insulating layer 3;

[0046] Semiconductor layer 4, first semiconductor unit 41, second semiconductor unit 42, conductor region 43;

[0047] Second gate insulating layer 5;

[0048] Second metal layer 6, top gate 61, drive circuit trace 62;

[0049] First intermediate insulating layer 7, first through hole 71, second through hole 72, third through hole 73;

[0050] First transparent conductive layer 8;

[0051] Third metal layer 9, first source 91, first drain 92, second source 93, second drain 94, metal unit 1 95;

[0052] Second intermediate insulating layer 10, fourth through hole 101;

[0053] Second transparent conductive layer 11;

[0054] The driving circuit area is TFT 100, the display area is TFT 200, and the metal line area is 300.

Detailed Implementation Methods

[0055] The following will be combined with the appendix Figure 1-3The technical solution of the present invention will be clearly and completely described in detail with specific embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments used, unless otherwise specified, are all commercially available conventional products.

[0056] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0057] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0058] Please see Figure 1 As shown, the present invention relates to an oxide array substrate, the oxide array substrate comprising: a glass substrate 1,

[0059] A first metal layer 2 is disposed on the glass substrate 1, and the first metal layer 2 includes a bottom gate 21;

[0060] A first gate insulating layer 3 is disposed on the first metal layer 2;

[0061] Semiconductor layer 4 is disposed on the first gate insulating layer 3. The semiconductor layer 4 includes a first semiconductor unit 41 and a second semiconductor unit 42. The two ends of the first semiconductor unit 41 are respectively conductive to form a conductor region 43. The position of the second semiconductor unit 42 corresponds to the position of the bottom gate 21.

[0062] A second gate insulating layer 5 is disposed on the semiconductor layer 4;

[0063] The second metal layer 6 is disposed on the second gate insulating layer 5. The second metal layer 6 includes a top gate 61 and a driving circuit trace 62. The top gate 61 is located above the first semiconductor unit 41.

[0064] A first intermediate insulating layer 7 is disposed on the second metal layer 6. The first intermediate insulating layer 7 has a first through-hole 71, a second through-hole 72, and a third through-hole 73. There are two first through-holes 71, which are located on both sides of the top gate 61 and penetrate downward through the second gate insulating layer 5, exposing the upper surface of the conductor regions 43 at both ends of the first semiconductor unit 41. There are two second through-holes 72, which are located above the second semiconductor unit 42 and penetrate downward through the second gate insulating layer 5, exposing the upper surface of the second semiconductor unit 42. The third through-hole 73 is located above the driving circuit trace 62 and exposes the upper surface of the driving circuit trace 62.

[0065] A first transparent conductive layer 8 is disposed on the first intermediate insulating layer;

[0066] A third metal layer 9 is disposed on the first intermediate insulating layer 7. The third metal layer 9 includes a first source 91, a first drain 92, a second source 93, a second drain 94, and a metal unit 95. The first source 91 and the first drain 92 are respectively connected to the corresponding conductor region 43 through corresponding first vias 71. The second source 93 and the second drain 94 are respectively connected to both ends of the second semiconductor unit 42 through corresponding second vias 72. One end of the second drain 94 is also connected to one end of the first transparent conductive layer 8. The metal unit 95 is connected to the driving circuit trace 62 through the third via 73.

[0067] The second intermediate insulating layer 10 is disposed on the first transparent conductive layer 8 and the third metal layer 9. The second intermediate insulating layer 10 has a fourth through hole 101, which is located above the metal unit 95 and exposes the upper surface of the metal unit 95.

[0068] The second transparent conductive layer 11 is disposed on the second intermediate insulating layer 10 and is connected to the metal unit 95 through the fourth through hole 101;

[0069] The film structure corresponding to the top gate 61 is the driving circuit area TFT 100, the film structure corresponding to the bottom gate 21 is the display area TFT 200, and the film structure corresponding to the driving circuit trace 62 is the metal line area 300.

[0070] In a preferred embodiment, the non-channel regions at both ends of the first semiconductor unit 41 are subjected to ion doping treatment to make the region conductive, forming a conductor region 43.

[0071] See Figure 2 As shown, in a preferred embodiment, when one end of the second drain 114 overlaps with the second transparent conductive layer 10, the fourth through hole 94 is disposed close to the metal unit 115, and the metal unit 115 is also connected to the first transparent conductive layer 8 through the fourth through hole 94. At this time, the first transparent conductive layer 8 is a common electrode, and the second transparent conductive layer 10 is a pixel electrode.

[0072] See Figure 2-3 As shown, the present invention also relates to a method for fabricating an oxide array substrate, the method comprising the following steps:

[0073] Step 1: A first metal layer 2 is formed on a glass substrate 1 to fabricate a bottom gate 21 and related driving signal lines;

[0074] Step 2: Form a first gate insulating layer 3 on the first metal layer 2; the first gate insulating layer 3 in the display area serves as the bottom gate TFT gate insulating layer, and the first gate insulating layer 3 in the driving circuit area serves as the active layer, i.e., the buffer layer below the first semiconductor unit 41.

[0075] Step 3: A semiconductor layer 4 is formed on the first gate insulating layer 3, and a first semiconductor unit 41 and a second semiconductor unit 42 are prepared. Then, the left and right ends of the first semiconductor unit 41 are conductiveized to form a conductive region 43. The present invention conducts the semiconductor layer at the top gate TFT position to reduce the contact resistance of the source and drain contact regions.

[0076] Step 4: Form a second gate insulating layer 5 on the semiconductor layer 4 as the gate insulating layer of the top gate TFT;

[0077] Step 5: Form a second metal layer 6 on the second gate insulating layer 5, and fabricate the top gate 61 and the driving circuit trace 62, or other signal traces;

[0078] Step 6: Form a first intermediate insulating layer 7 on the second metal layer 6;

[0079] Step 7: Form a first transparent conductive layer 8 on the first intermediate insulating layer 7 and prepare a pixel electrode; then prepare a first through hole 71, a second through hole 72 and a third through hole 73 on the first intermediate insulating layer 7, and expose the upper surface of the conductor region 43 at both ends of the first semiconductor unit 41, the upper surface of the second semiconductor unit 42 and the upper surface of the driving circuit trace 62, respectively.

[0080] Step 8: A third metal layer 9 is formed on the first intermediate insulating layer 7, and a first source 91, a first drain 92, a second source 93, a second drain 94, and a metal unit 95 are fabricated; wherein the first source 91 and the first drain 92 are respectively connected to the corresponding conductor region 43 through the corresponding first through-hole 71; the second source 93 and the second drain 94 are respectively connected to both ends of the second semiconductor unit 42 through the corresponding second through-hole 72; one end of the second drain 94 is also connected to the adjacent end of the first transparent conductive layer 8; the metal unit 94 is connected to the driving circuit trace 62 through the third through-hole 73;

[0081] Step 9: Form a second intermediate insulating layer 10 on the third metal layer 9 and prepare a fourth through hole 101 to expose the upper surface of the metal unit 95.

[0082] Step 10: Form a second transparent conductive layer 11 on the second intermediate insulating layer 10 to prepare a common electrode. The common electrode is connected to the metal unit 95 through the fourth through hole 101.

[0083] In a preferred embodiment, the first metal layer 2, the second metal layer 6, and the third metal layer 9 are selected from aluminum, molybdenum, titanium, nickel, copper, silver, and tungsten to form a single-layer structure, or a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

[0084] In a preferred embodiment, the first gate insulating layer 3, the second gate insulating layer 5, the first intermediate insulating layer 7, and the second intermediate insulating layer 10 are single-layer or multi-layer structures, and the materials are inorganic oxides or insulating compounds.

[0085] In a preferred embodiment, the first transparent conductive layer 8 and the second transparent conductive layer 11 are made of ITO.

[0086] In summary, this invention proposes a novel metal oxide TFT array substrate structure, in which top-gate and bottom-gate TFT devices are respectively provided at the corresponding positions of the driving circuit area and the display area in the array substrate. Therefore, this array substrate structure retains the low parasitic capacitance driving advantage of the top-gate structure and overcomes the disadvantage of the single function of the added light-shielding layer in the existing structure. Furthermore, the second transparent conductive layer is further away from the lower metal layer, which can further reduce the parasitic capacitance effect between the common electrode and the lower metal layer. At the same time, this invention also has the advantage of low manufacturing cost, and is suitable for the low-cost development of high-resolution and high-refresh-rate display panels.

[0087] In addition, the present invention performs conductor treatment on both ends of the semiconductor layer at the top gate TFT position, which can reduce the contact resistance of the source and drain contact regions.

[0088] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An oxide array substrate, characterized in that: The oxide array substrate includes: a glass substrate. A first metal layer is disposed on the glass substrate, and the first metal layer includes a bottom gate. A first gate insulating layer is disposed on the first metal layer; A semiconductor layer is disposed on the first gate insulating layer. The semiconductor layer includes a first semiconductor unit and a second semiconductor unit. The two ends of the first semiconductor unit are respectively conductive to form conductive regions. The position of the second semiconductor unit corresponds to the position of the bottom gate. A second gate insulating layer is disposed on the semiconductor layer; A second metal layer is disposed on the second gate insulating layer. The second metal layer includes a top gate and driving circuit traces. The top gate is located above the first semiconductor cell. A first intermediate insulating layer is disposed on the second metal layer. The first intermediate insulating layer has a first through-hole, a second through-hole, and a third through-hole. There are two first through-holes, which are respectively located on both sides of the top gate and penetrate downward through the second gate insulating layer, exposing the upper surface of the conductor regions at both ends of the first semiconductor unit. There are two second through-holes, which are respectively located above the second semiconductor unit and penetrate downward through the second gate insulating layer, exposing the upper surface of the second semiconductor unit. The third through-hole is located above the driving circuit trace, exposing the upper surface of the driving circuit trace. A first transparent conductive layer is disposed on the first intermediate insulating layer; A third metal layer is disposed on the first intermediate insulating layer. The third metal layer includes a first source, a first drain, a second source, a second drain, and a first metal unit. The first source and the first drain are respectively connected to the corresponding conductor regions through corresponding first vias. The second source and the second drain are respectively connected to the two ends of the second semiconductor unit through corresponding second vias. One end of the second drain is also connected to one end of the first transparent conductive layer. The first metal unit is connected to the driving circuit traces through a third via. A second intermediate insulating layer is disposed on the first transparent conductive layer and the third metal layer. The second intermediate insulating layer has a fourth through hole, which is located above the first metal unit and exposes the upper surface of the first metal unit. The second transparent conductive layer is disposed on the second intermediate insulating layer and is connected to the metal unit through the fourth through hole; The film structure corresponding to the top gate is the driving circuit area TFT, the film structure corresponding to the bottom gate is the display area TFT, and the film structure corresponding to the driving circuit trace is the metal line area.

2. The oxide array substrate according to claim 1, characterized in that: The non-channel regions at both ends of the first semiconductor unit are subjected to ion doping treatment to make the region conductive, forming a conductive region.

3. A method for fabricating an oxide array substrate, characterized in that: The array substrate prepared by the method is an oxide array substrate as described in claim 1 or 2, and the method steps are as follows: Step 1: Form a first metal layer on a glass substrate to fabricate the bottom gate and related driving signal lines; Step 2: Form a first gate insulating layer on the first metal layer; the first gate insulating layer in the display area serves as the bottom gate TFT gate insulating layer, and the first gate insulating layer in the driving circuit area serves as the active layer, i.e., the buffer layer below the first semiconductor unit; Step 3: A semiconductor layer is formed on the first gate insulating layer, and a first semiconductor unit and a second semiconductor unit are fabricated. Then, the left and right ends of the first semiconductor unit are conductiveized to form a conductive region. Step 4: Form a second gate insulating layer on the semiconductor layer as the gate insulating layer of the top gate TFT; Step 5: Form a second metal layer on the second gate insulating layer, and fabricate the top gate and drive circuit traces, or other signal traces; Step 6: Form a first intermediate insulating layer on the second metal layer; Step 7: Form a first transparent conductive layer on the first intermediate insulating layer and prepare a pixel electrode; then prepare a first through-hole, a second through-hole and a third through-hole on the first intermediate insulating layer, and expose the upper surface of the conductor region at both ends of the first semiconductor unit, the upper surface of the second semiconductor unit, and the upper surface of the driving circuit trace, respectively. Step 8: A third metal layer is formed on the first intermediate insulating layer, and a first source, a first drain, a second source, a second drain, and a metal unit 1 are fabricated; wherein the first source and the first drain are respectively connected to the corresponding conductor regions through corresponding first vias; the second source and the second drain are respectively connected to both ends of the second semiconductor unit through corresponding second vias; one end of the second drain is also overlapped with the adjacent end of the first transparent conductive layer; the metal unit 1 is connected to the driving circuit trace through a third via; Step 9: Form a second intermediate insulating layer on the third metal layer and prepare a fourth through hole to expose the upper surface of the first metal unit; Step 10: Form a second transparent conductive layer on the second intermediate insulating layer to prepare a common electrode. The common electrode is connected to the metal unit through a fourth through hole.

4. The method for fabricating an oxide array substrate according to claim 3, characterized in that: The first metal layer, the second metal layer, and the third metal layer are selected from aluminum, molybdenum, titanium, nickel, copper, silver, and tungsten to form a single-layer structure, or a multi-layer structure composed of two or more of the above materials, or an alloy composed of two or more of the above materials.

5. The method for fabricating an oxide array substrate according to claim 3, characterized in that: The first gate insulating layer, the second gate insulating layer, the first intermediate insulating layer, and the second intermediate insulating layer are single-layer or multi-layer structures, and the materials are inorganic oxides or insulating compounds.

6. The method for fabricating an oxide array substrate according to claim 3, characterized in that: The first and second transparent conductive layers are made of ITO.

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