Chip Comprehensive Computing Power Testing Method, Electronic Device, Storage Medium and Device

Abstract

The present invention discloses a chip comprehensive computing power test method, electronic equipment, storage medium and device. The method includes: transmitting the road test scene data of the database / vehicle sensor to the chip, and performing the chip comprehensive computing power test based on the comprehensive computing power algorithm model; obtaining the chip computing power influence factor based on the data flow and processing logic of the chip; re-importing the road test scene data into the chip based on the data re-injection method, calculating the chip comprehensive computing power and the impact value on the comprehensive computing power when each chip computing power influence factor is in different states while keeping other chip computing power influence factors unchanged; establishing a chip comprehensive computing power estimation model based on the impact value, chip computing power influence factor and chip comprehensive computing power; and evaluating the chip based on the chip comprehensive computing power estimation model. The present invention tests the chip comprehensive computing power of a single chip computing power influence factor in different states by means of data re-injection, thereby improving the accuracy and reliability of the test.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and more specifically, relates to a method for testing the comprehensive computing power of a chip, an electronic device, a storage medium, and a device. Background Art

[0002] With the rapid development of intelligence, the functions of intelligent connected vehicles are becoming increasingly complex. For higher levels of autonomous driving, the amount of data collected and transmitted is larger, and the computing power requirements for in-vehicle computing chips are also higher. The industry generally believes that the computing power required for L2-level autonomous driving is below 10 TOPS, the computing power required for L3-level is about 30 - 60 TOPS, the computing power required for L4-level exceeds 100 TOPS, and the computing power requirement for L5-level exceeds 1000 TOPS.

[0003] In the context of the rapid development of autonomous driving technology, driving safety has become the top priority. Whether the design of the software and hardware of the computing platform itself is sufficient to support the normal operation of the vehicle's automated functions in extreme scenarios has become one of the factors affecting autonomous driving safety; whether the computing power of the in-vehicle computing chip itself and the corresponding algorithms are sufficient to support the vehicle to have accurate and real-time perception capabilities, thus ensuring the driving safety of autonomous vehicles. Taking perception as an example, autonomous vehicles need to perceive the environment within 360° around the vehicle body, and its perception range is very wide, including the recognition, tracking, prediction of moving objects, semantic segmentation, modeling, and positioning of the driving environment, and it also needs to work reliably under different weather conditions and lighting conditions. This poses extremely harsh requirements on the comprehensive computing power of the in-vehicle computing platform and the reliability and accuracy of the corresponding perception algorithms. Currently, there is still a lack in the industry of a standard that keeps pace with the times and can effectively evaluate the comprehensive computing power performance of in-vehicle computing chips, especially the comprehensive chip computing power testing method based on automotive application scenarios that the industry urgently needs is still blank.

[0004] The information disclosed in the background art section of the present invention is only intended to deepen the understanding of the general background art of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to propose a method for testing the comprehensive computing power of a chip, an electronic device, a storage medium, and a device, so as to realize the rapid testing of the comprehensive computing power of the chip on the premise that the AI computing unit of the computing chip is maximally squeezed and comprehensively considering the factors affecting the chip computing power, and to realize the rapid evaluation of the actual comprehensive computing power of the chip according to the test results.

[0006] To achieve the above object, the present invention proposes a method for testing the comprehensive computing power of a chip, an electronic device, a storage medium, and a device.

[0007] According to a first aspect of the present invention, a method for testing the comprehensive computing power of a chip is proposed, including:

[0008] Transmitting the road test scenario data of the database / vehicle sensor to the chip based on the data interface between the sensor and the chip, and performing a comprehensive computing power test on the chip based on the comprehensive computing power algorithm model;

[0009] Based on the data flow direction and processing logic of the chip during the test, analyzing the chip computing power influencing factors that affect the comprehensive computing power of the chip when the occupancy rate of the AI acceleration unit of the chip reaches the limit;

[0010] Based on the data backfilling method, re-importing the road test scenario data into the chip, and calculating the corresponding comprehensive computing power of the chip when each chip computing power influencing factor is in different states while other chip computing power influencing factors remain unchanged;

[0011] Based on the comprehensive computing power of the chip and the theoretical comprehensive computing power of the chip, calculating the influence value of each chip computing power influencing factor in different states on the comprehensive computing power;

[0012] Based on the influence value, the chip computing power influencing factor, and the comprehensive computing power of the chip, establishing a comprehensive computing power estimation model for the chip;

[0013] Based on the hardware configuration and application scenario requirements of the chip to be estimated, determining the states of each chip computing power influencing factor, and then calculating the actual comprehensive computing power of the chip to be estimated corresponding to each chip computing power influencing factor based on the comprehensive computing power estimation model of the chip.

[0014] Optionally, the calculating the corresponding comprehensive computing power of the chip when each chip computing power influencing factor is in different states specifically includes:

[0015] S1. Setting multiple states of a single chip computing power influencing factor;

[0016] S2. Re-importing the road test scenario data into the chip based on the data backfilling method;

[0017] S3. Calculating the comprehensive computing power of the chip when the chip computing power influencing factor is in one state while the states of other chip computing power influencing factors remain unchanged;

[0018] S4. Changing the state of the chip computing power influencing factor, repeating S2 - S3, and respectively obtaining the corresponding comprehensive computing power of the chip when the chip computing power influencing factor is in different states;

[0019] S5. Replacing the chip computing power influencing factor, repeating S1 - S4 until the corresponding comprehensive computing power of the chip when each chip computing power influencing factor is in different states is obtained.

[0020] Optionally, the chip computing power influencing factors include:

[0021] a contribution factor and a constraint factor;

[0022] The contribution factor includes: CPU frequency, number of cores, DDR bandwidth, on-chip storage, form of in-vehicle camera interface, resolution of in-vehicle camera, number of chip cores, and data input form;

[0023] The constraint factor includes: power consumption / temperature, accuracy of the comprehensive computing power algorithm model, image data communication delay, and image processing frame rate.

[0024] Optionally, the calculation expression for the chip's comprehensive computing power is:

[0025] T ij = f ij × M;

[0026] where T ij is the chip's comprehensive computing power corresponding to the i-th chip computing power influencing factor in the j-th state, f is the processing frame rate corresponding to the i-th chip computing power influencing factor in the j-th state, and M is the model calculation amount of the comprehensive computing power algorithm model.

[0027] Optionally, the calculation expression for the influence value is:

[0028]

[0029] where τ ij is the influence value of the i-th chip computing power influencing factor on the chip's comprehensive computing power in the j-th state, e is a constant, and α is the theoretical comprehensive computing power of the test chip.

[0030] Optionally, the calculation expression for the actual comprehensive computing power is:

[0031] T gi = T l × τ ij ;

[0032] T gi is the actual comprehensive computing power of the chip to be estimated corresponding to the i-th chip computing power influencing factor, and T l is the theoretical comprehensive computing power of the chip to be estimated.

[0033] Optionally, the calculation expression for the model calculation amount is:

[0034] M = H × W × (C in × k 2 + 1) × C out ;

[0035] Wherein, H is the height value of the output feature map, W is the width value of the output feature map, C in and C out are the number of input channels and the number of output channels respectively, and K is the size of the convolutional kernel.

[0036] According to the second aspect of the present invention, a chip comprehensive computing power testing device is proposed, including:

[0037] A data interface between the sensor and the chip, which is used to transmit the road test scenario data of the database / vehicle sensor to the chip based on the data interface and perform chip comprehensive computing power testing based on the comprehensive computing power algorithm model;

[0038] A testing module, which is used to perform chip comprehensive computing power testing based on the comprehensive computing power algorithm model;

[0039] An analysis module, based on the data flow and processing logic of the chip during the testing process, analyzes the chip computing power impact factors that affect the chip comprehensive computing power when the occupancy rate of the AI acceleration unit of the chip reaches the limit;

[0040] A data backfilling module, which is used to re-import the road test scenario data into the chip based on the data backfilling method;

[0041] A first calculation module, which is used to calculate the corresponding chip comprehensive computing power when each of the chip computing power impact factors is in different states under the condition that other chip computing power impact factors remain unchanged;

[0042] A second calculation module, which is used to calculate the influence value of each chip computing power impact factor on the comprehensive computing power when it is in different states based on the chip comprehensive computing power and the theoretical comprehensive computing power of the chip;

[0043] A building module, which is used to establish a chip comprehensive computing power estimation model based on the influence value, the chip computing power impact factor and the chip comprehensive computing power;

[0044] A determination and estimation module, which is used to determine the states of each chip computing power impact factor based on the hardware configuration and application scenario requirements of the chip to be estimated, and then calculate the actual chip comprehensive computing power of the chip to be estimated corresponding to each chip computing power impact factor based on the chip comprehensive computing power estimation model.

[0045] According to the third aspect of the present invention, an electronic device is proposed, and the electronic device includes:

[0046] At least one processor; and,

[0047] A memory communicatively connected to the at least one processor; wherein,

[0048] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the chip comprehensive computing power test method according to any one of the first aspect.

[0049] According to a fourth aspect of the present invention, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute the chip comprehensive computing power test method according to any one of the first aspect.

[0050] The beneficial effects of the present invention are as follows: The present invention transmits the road test scenario data of the database to the chip through the data interface between the sensor and the chip, realizing the real simulation of the sensor transmitting data to the chip; by transmitting the road test scenario data of the database / sensor to the chip, the simulation comprehensive computing power test and the real vehicle comprehensive computing power test are realized; through the data backfilling method, the chip comprehensive computing power under different states of a single chip computing power influencing factor is quickly tested, and the influence value of each chip computing power influencing factor on the chip comprehensive computing power under different states is obtained through the test results, and then a chip comprehensive computing power estimation model is established to realize the rapid evaluation of the actual comprehensive computing power of different chips; the present invention can quickly test the chip comprehensive computing power on the premise that the chip AI computing unit is maximally squeezed and comprehensively considering the factors affecting the chip computing power, and realize the rapid evaluation of the actual comprehensive computing power of the chip according to the test results, improving the accuracy and reliability of the test, providing data support for the chip selection of vehicle manufacturers, and solving the short board of the automotive industry chain.

[0051] The system of the present invention has other characteristics and advantages, which will be obvious from the accompanying drawings incorporated herein and the subsequent specific embodiments, or will be described in detail in the accompanying drawings incorporated herein and the subsequent specific embodiments. These drawings and specific embodiments are jointly used to explain the specific principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] By describing the exemplary embodiments of the present invention in more detail in conjunction with the accompanying drawings, the above and other objects, features, and advantages of the present invention will become more obvious. In the exemplary embodiments of the present invention, the same reference numerals generally represent the same components.

[0053] Figure 1 A flowchart showing the steps of a chip comprehensive computing power test method according to the present invention is shown.

[0054] Figure 2 A flowchart showing the steps of a chip comprehensive computing power test method according to Embodiment 1 of the present invention is shown.

[0055] Figure 3Schematic diagram showing the relationship between the chip data flow and processing logic of Embodiment 1 of the present invention and the computing power impact factors.

[0056] Figure 4 Schematic diagram showing the data evaluation matrix according to Embodiment 1 of the present invention.

[0057] Figure 5 Schematic diagram showing a chip integrated computing power test device according to Embodiment 3 of the present invention. Detailed implementation manners

[0058] The present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0059] As Figure 1 shown, a chip integrated computing power test method according to the present invention includes:

[0060] Transmitting the road test scenario data of the database / vehicle sensor to the chip based on the data interface between the sensor and the chip, and performing a chip integrated computing power test based on the integrated computing power algorithm model;

[0061] Analyzing the chip computing power impact factors that affect the chip integrated computing power when the occupancy rate of the AI acceleration unit of the chip reaches the limit based on the data flow direction and processing logic of the chip during the test;

[0062] Reimporting the road test scenario data into the chip based on the data backfilling method, and calculating the corresponding chip integrated computing power when each chip computing power impact factor is in a different state while other chip computing power impact factors remain unchanged;

[0063] Calculating the influence value of each chip computing power impact factor on the integrated computing power when it is in a different state based on the chip integrated computing power and the theoretical integrated computing power of the chip;

[0064] Establishing a chip integrated computing power estimation model based on the influence value, chip computing power impact factors, and chip integrated computing power;

[0065] Determining the state of each chip computing power impact factor based on the hardware configuration and application scenario requirements of the chip to be estimated, and then calculating the actual chip integrated computing power of the chip to be estimated corresponding to each chip computing power impact factor based on the chip integrated computing power estimation model.

[0066] Specifically, the present invention transmits the road test scenario data of the database to the chip through the data interface between the sensor and the chip, truly simulating the data transmission from the sensor to the chip, achieving the simulation test based on real road test data in the laboratory, improving the accuracy of the simulation test. The present invention can not only support the simulation test, but also transmit the data collected by the sensor to the chip through the data interface between the sensor and the chip for real vehicle test; then, according to the data flow direction of the road test data in the chip and the processing logic of the chip for the road test data, analyze the chip computing power influencing factors that affect the overall chip computing power when the occupancy rate of the AI acceleration unit in the chip reaches the limit, and then quickly test the overall chip computing power in different states of a single chip computing power influencing factor through the data backfilling method, realizing the quick test of the overall chip computing power on the premise that the AI computing unit in the chip is maximally squeezed and comprehensively considering the factors affecting the chip computing power; then, obtain the influence values of each chip computing power influencing factor on the overall chip computing power in different states through the test results, and further establish an overall chip computing power estimation model to quickly evaluate the actual overall computing power of different chips, improving the accuracy and reliability of the test, providing data support for the chip selection of vehicle manufacturers, and solving the short board of the automotive industry chain.

[0067] In one example, calculating the overall chip computing power corresponding to each chip computing power influencing factor in different states specifically includes:

[0068] S1. Set multiple states of a single chip computing power influencing factor;

[0069] S2. Re-import the road test scenario data into the chip based on the data backfilling method;

[0070] S3. With the states of other chip computing power influencing factors remaining unchanged, calculate the overall chip computing power when the chip computing power influencing factor is in one state;

[0071] S4. Change the state of the chip computing power influencing factor, repeat S2 - S3, and respectively obtain the overall chip computing power corresponding to the chip computing power influencing factor in different states;

[0072] S5. Replace the chip computing power influencing factor, repeat S1 - S4 until the overall chip computing power corresponding to each chip computing power influencing factor in different states is obtained.

[0073] Specifically, the present invention first selects a chip computing power influencing factor, sets its state during multiple tests, and then re - imports the same road - test scenario data into the chip through data back - filling. Under the condition that the states of other chip computing power influencing factors remain unchanged, a comprehensive computing power test is carried out to obtain the chip's comprehensive computing power corresponding to this state of the chip computing power influencing factor. Among them, the chip's comprehensive computing power is the chip's comprehensive computing power when the occupancy rate of the chip's AI acceleration unit reaches the limit. Then, the state of this chip computing power influencing factor is changed, and the same road - test scenario data is re - imported into the chip through data back - filling. Under the condition that the states of other chip computing power influencing factors remain unchanged, a comprehensive computing power test is carried out to obtain the chip's comprehensive computing power corresponding to the changed state of the chip computing power influencing factor. Through cyclic testing, the chip's comprehensive computing powers corresponding to different states of the chip computing power influencing factor are obtained; finally, another chip computing power influencing factor is replaced to calculate its chip's comprehensive computing powers in its own different states until the chip's comprehensive computing powers corresponding to each chip computing power influencing factor in its own different states are obtained.

[0074] In one example, the chip computing power influencing factors include:

[0075] Contribution factors and constraint factors;

[0076] The contribution factors include: CPU frequency, number of cores, DDR bandwidth, on - chip storage, form of in - vehicle camera interface, resolution of in - vehicle camera, number of chip cores, and form of data input;

[0077] The constraint factors include: power consumption / temperature, accuracy of the comprehensive computing power algorithm model, image data communication delay, and image processing frame rate.

[0078] Specifically, the chip computing power influencing factors include contribution factors and constraint factors; the contribution factors include CPU frequency, number of cores, DDR bandwidth, on - chip storage, form of in - vehicle camera interface, resolution of in - vehicle camera, number of chip cores, and form of data input; the constraint factors include power consumption / temperature, accuracy of the comprehensive computing power algorithm model, image data communication delay, and image processing frame rate. The chip computing power influencing factors; in addition to the above - mentioned contribution factors and constraint factors, there is also a comprehensive computing power algorithm model. The comprehensive computing power algorithm model affects the chip's comprehensive computing power from two aspects, namely the convolution kernel size and the number of channels. Different convolution kernel sizes and numbers of channels affect the model calculation amount of the comprehensive computing power algorithm model, and thus affect the chip's comprehensive computing power. When testing the comprehensive computing power of the contribution factors and constraint factors, the comprehensive computing power algorithm model remains unchanged, and the influence of the comprehensive computing power algorithm model on the chip's comprehensive computing power does not need to be considered.

[0079] In one example, the calculation expression of the chip's comprehensive computing power is:

[0080] T ij =fij ×M;

[0081] Wherein, T ij is the comprehensive chip computing power corresponding to the i-th chip computing power influencing factor in the j-th state, f is the processing frame rate corresponding to the i-th chip computing power influencing factor in the j-th state, and M is the model calculation amount of the comprehensive computing power algorithm model.

[0082] Specifically, the calculation of the comprehensive chip computing power through this expression is carried out when the occupancy rate of the AI acceleration unit of the chip reaches the limit, and when calculating the comprehensive chip computing power of the contribution factor and the constraint factor, the comprehensive computing power algorithm model remains unchanged, that is, the model calculation amount of the comprehensive computing power algorithm model remains unchanged, and it is not necessary to consider the influence of the comprehensive computing power algorithm model on the comprehensive chip computing power.

[0083] In an example, the calculation expression of the influence value is:

[0084]

[0085] Wherein, τ ij is the influence value of the i-th chip computing power influencing factor on the comprehensive chip computing power in the j-th state, e is a constant, and α is the theoretical comprehensive computing power of the test chip.

[0086] In an example, the calculation expression of the actual comprehensive computing power is:

[0087] T gi = T l ×τ ij ;

[0088] T gi is the actual comprehensive computing power of the chip to be estimated corresponding to the i-th chip computing power influencing factor, and T l is the theoretical comprehensive computing power of the chip to be estimated.

[0089] In an example, the calculation expression of the model calculation amount is:

[0090] M = H × W × (C in × K 2 + 1) × C out ;

[0091] Wherein, H is the height value of the output feature map, W is the width value of the output feature map, C in and C out are the number of input channels and the number of output channels respectively, and K is the convolution kernel size.

[0092] Specifically, according to this expression, it can be seen that when the output feature map remains unchanged, the convolution kernel size and the number of channels affect the model's computational complexity, and thus affect the overall computing power of the chip. Therefore, it is also necessary to consider the impact of the overall computing power algorithm model on the overall computing power of the chip. When other chip computing power influencing factors and road test scenario data remain unchanged, calculate the overall computing power of the chip corresponding to different convolution kernel sizes, as well as the overall computing power of the chip corresponding to different numbers of channels, so as to obtain the impact values of different convolution kernel sizes and the same number of channels on the overall computing power.

[0093] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0094] Embodiment 1

[0095] As Figure 2 shown, this embodiment provides a method for testing the overall computing power of a chip, including:

[0096] Simulation testing and real vehicle testing, where the simulation testing is to test the overall computing power of the computing chip through the real road test scenario data and the VTD software simulation scenario data backfilling system in the laboratory, reducing the cumbersome work of data collection and increasing the testing efficiency; the real vehicle testing comprehensively considers the influence of various environmental factors during the vehicle's driving process, and tests the overall computing power through the vehicle equipped with the overall computing power testing system of the computing chip in the actual road typical scenario.

[0097] 1. Analysis and processing logic of the data stream of the automotive-grade computing chip: The analysis of the data stream and processing logic is the first step in the overall computing power testing. This step can analyze the factors affecting the computing power, including contributing factors and constraint factors. The contributing factors are mainly the improvements in computing power brought by the hardware, and the constraint factors are the constraints on the computing power by the test result indicators. As Figure 3 shown, the CPU architectures of different computing chips vary greatly, which is represented by CPU_* in the figure. The factors affecting the computing power are obtained through the analysis of the data flow direction and processing logic. On the premise that the AI computing unit of the computing chip is maximally squeezed and considering both the contributing factors and the constraint factors, the overall computing power is obtained according to the following expression:

[0098] T ij = f ij × M ; (1)

[0099] where, T ij is the overall computing power of the chip corresponding to the i-th chip computing power influencing factor in the j-th state, f is the processing frame rate corresponding to the i-th chip computing power influencing factor in the j-th state, and M is the model computing complexity of the overall computing power algorithm model;

[0100] Considering the influence of various factors on computing power, calculate the influence value of a single factor on computing power. The calculation formula is as follows:

[0101]

[0102] where τ ij is the influence value of the i-th chip computing power influence factor on the comprehensive computing power of the chip in the j-th state. e is a constant, α is the theoretical comprehensive computing power of the test chip, and T ij is the comprehensive computing power of the chip corresponding to the i-th chip computing power influence factor in the j-th state.

[0103] 2. Contribution factor influence test: The contribution factors mainly include CPU frequency, number of cores, DDR bandwidth, and on-chip storage. These contribution factors will have a greater impact on the comprehensive computing power of the computing chip. On the premise that other factors remain unchanged, the test data set is back-injected into the AI acceleration unit of the chip through the data backfilling system to make its occupancy rate reach the limit, and the influence degree of a single factor on computing power is tested.

[0104] (1) Test of the influence of CPU frequency on computing power

[0105] There are various forms of the CPU architecture of the computing chip, and there are also various values of the frequency. Test the influence of multiple CPU frequencies of the same chip on the computing power value. For the case where other influencing factors remain unchanged, use the same data set and algorithm model to ensure that the occupancy rate of the AI acceleration unit of the chip reaches the limit, and test the computing power at P 1 , P 2 , P 3 , P 4 , P 5 frequencies. According to formula (1), obtain the comprehensive computing power corresponding to different CPU frequencies, and according to formula (2), obtain the influence value of different CPU frequencies on computing power.

[0106] (2) Test of the influence of DDR bandwidth on computing power

[0107] For the external DDR of the computing chip, test the influence on the computing power value when the DDR bandwidth of the same chip is D 1 MT / s, D 2 MT / s, D 3 MT / s, D 4 MT / s, etc. For the case where other influencing factors remain unchanged, use the same data set and algorithm model to ensure that the occupancy rate of the AI acceleration unit of the chip reaches the limit. Calculate the computing power values corresponding to different DDR bandwidths according to formula (1), and obtain the influence scores of different DDR bandwidths on computing power according to formula (2).

[0108] (3) Test of the influence of on-chip storage on computing power

[0109] For a computing chip with on-chip storage, when testing the storage capacities of M 1 kB, M 2 kB, M 3 kB, M 4 kB, with other influencing factors remaining unchanged, using the same dataset and algorithm model, ensuring that the occupancy rate of the AI acceleration unit of the chip reaches the limit, calculate the computing power values corresponding to different storage capacities according to Expression (1), and obtain the influence scores of different on-chip storage capacities on the computing power according to Expression (2).

[0110] (4) Test on the influence of interface form on computing power

[0111] Currently, the interface forms of in-vehicle cameras mainly include Fakra and USB. Test the influence of the two camera interface forms of the same chip on the computing power value. With other influencing factors remaining unchanged, use the same dataset and algorithm model, ensure that the occupancy rate of the AI acceleration unit of the chip reaches the limit, calculate the computing power under the two interface forms, calculate the computing power values corresponding to different interface forms according to Expression (1), and obtain the influence scores of different interface forms on the computing power according to Expression (2).

[0112] (6) Test on the influence of input resolution on computing power

[0113] The current mainstream camera resolutions for autonomous driving are H 1 ×W 1 、H 2 ×W 2 、H 3 ×W 3 、H 4 ×W 4 , respectively test the single influence of different input resolutions on the computing power of the chip with other influencing factors remaining unchanged, use the same dataset and algorithm model, ensure that the occupancy rate of the AI acceleration unit of the chip reaches the limit, calculate the computing power values corresponding to different input resolutions according to Expression (1), and obtain the influence scores of different interface forms on the computing power according to Expression (2).

[0114] (7) Test on the influence of the number of cores on computing power

[0115] There are various numbers of cores in the computing chip. Test the number of cores of N 1 、N 2 、N 3 、N 4Regarding the impact of the same chip on the computing power value, use the same dataset and algorithm model, ensure that the occupancy rate of the AI acceleration unit of the chip reaches the limit, calculate the computing power corresponding to different numbers of cores according to Expression (1), and obtain the impact score of different numbers of cores on the computing power according to Expression (2).

[0116] (8) Test on the impact of input form on computing power

[0117] The input forms of data include direct input from the camera, hard disk reading method, and data backfilling method. Test the three data input methods respectively, use the same dataset and algorithm model, ensure that the occupancy rate of the AI acceleration unit of the chip reaches the limit, calculate the computing power corresponding to different input forms according to Expression (1), and obtain the impact score of different input forms on the computing power according to Expression (2).

[0118] 3. Test on the impact of constraint factors: including power consumption / temperature test, accuracy test, latency test, and frame rate test. Constraint factors are generally the requirements of typical scenario applications for automotive-grade chips. On the premise that other factors remain unchanged, inject the test dataset into the AI acceleration unit of the chip through the data backfilling system to make its occupancy rate reach the limit. When the constraint factor requirements are met, test the impact degree of a single factor on the computing power.

[0119] (1) Test on the impact of power consumption / temperature on computing power

[0120] High chip power consumption easily reaches the junction temperature, affecting the normal operation of the system. Use a power analyzer to measure and record the power consumption of the system, and analyze the power consumption of the AI acceleration engine during operation according to the data graph. At the same time, analyze the actual computing power of the chip corresponding to different temperatures T1, T2, T3, T4, T5 respectively, and obtain the impact scores of power consumption and temperature on the computing power according to Expression (2).

[0121] (2) Test on the impact of accuracy on computing power

[0122] For different scenarios, the accuracy requirements are different. If the accuracy requirement is high, the model will be more complex and the number of parameters after quantization will be larger; if the accuracy requirement is not high, the number of parameters of the model after quantization will be relatively small. The evaluation expression of accuracy is as follows:

[0123]

[0124] In the formula, TP is the true positive example, FP is the false positive example, and FN is the false negative example.

[0125] For the same model, when different accuracies are achieved, calculate the computing power corresponding to different accuracies according to Expression (1), and obtain the impact scores of different accuracies on the computing power according to Expression (2).

[0126] (3) Test on the impact of latency on computing power

[0127] The communication delay of the image data is represented by the reception time difference ΔT between two adjacent frames of images. Through the data feedback system, the data of the same scene is fed back with time differences of ΔT 1 , ΔT 2 , ΔT 3 , ΔT 4 , ΔT 5 , and the computing power corresponding to different time differences is calculated according to Expression (1). The influence score of the computing power by different time differences is obtained according to Expression (2).

[0128] (4) Test on the influence of frame rate on computing power

[0129] The image processing frame rate reflects the data processing ability of the AI acceleration unit. Through the data feedback system, data is backfilled for a specified scene, and the algorithm model is designed to make the processing frame rate of the computing chip reach H 1 , H 2 , H 3 , H 4 , H 5 , respectively. The computing power corresponding to different processing frame rates is calculated according to Expression (1), and the influence score of the computing power by different processing frame rates is obtained according to Expression (2).

[0130] 4. Test on the influence of algorithm model:

[0131] The algorithms include classification algorithms, detection algorithms, and segmentation algorithms. The factors affecting the computing power mainly include the algorithm structure composed of convolution kernels and the number of channels. Study the influence of the convolution kernel size and the number of channels on the model's computational complexity, and then obtain the influence on the chip's computing power according to the following expressions.

[0132] M = H × W × (C in × K 2 + 1) × C out ; (4)

[0133] where H is the height value of the output feature map, W is the width value of the output feature map, C in and C out are the number of input channels and the number of output channels respectively, and K is the convolution kernel size.

[0134] (1) Test on the influence of convolution kernel size

[0135] When the output feature map remains unchanged, a convolutional network with a fixed number of channels is designed, and the size of each layer's convolution kernel is set to K 1 , K 2 , K 3 , K 4 , K 5Calculate the computational complexity of the model according to expression (4), calculate the computing power corresponding to different convolutional kernel sizes according to expression (1), and obtain the influence score of different convolutional kernel sizes on the computing power according to expression (2).

[0136] (2) Influence test of the number of channels

[0137] When the output feature map remains unchanged, design a convolutional network with a fixed convolutional kernel size, and set the number of input and output channels of each layer to C 1 , C 2 , C 3 , C 4 , C 5 Calculate the computational complexity of the model according to expression (4), calculate the computing power corresponding to different input and output channel numbers according to expression (1), and at the same time obtain the influence score of different input and output channel numbers on the computing power according to expression (2).

[0138] Develop algorithms with different computational complexities through convolutional kernels and channel numbers of different sizes, obtain models with different computational complexities through training with different application scenario datasets, and establish an algorithm model and a dataset test library to meet the test requirements of chips with different computing powers.

[0139] 5. Comprehensive computing power rapid evaluation

[0140] Based on the influence degree of the comprehensive influence factor and the model test results, obtain the final result of the comprehensive computing power, as shown in Figure 4 the data evaluation matrix.

[0141] When it is necessary to evaluate the actual comprehensive computing power of a chip, when the hardware configuration and application scenario requirements of the chip are known, quickly estimate the actual comprehensive computing power of the computing chip through the data evaluation matrix. The calculation expression is as follows

[0142] T gi = T l × τ ij ; (5) Among them, T gi is the actual comprehensive computing power of the chip to be estimated corresponding to the i-th chip computing power influence factor, and T l is the theoretical comprehensive computing power formula of the chip to be estimated. In the formula, T g is the estimated actual comprehensive computing power, T l is the theoretical computing power of the computing chip, and τ is the influence degree of the influence factor.

[0143] Example 2

[0144] This embodiment provides a chip comprehensive computing power test device, including:

[0145] A data interface between the sensor and the chip, which is used to transmit the road test scenario data of the database / vehicle sensor to the chip through the data interface, and perform chip comprehensive computing power testing based on the comprehensive computing power algorithm model;

[0146] A test module, which is used to perform chip comprehensive computing power testing based on the comprehensive computing power algorithm model;

[0147] An analysis module, which analyzes the chip computing power influencing factors that affect the chip comprehensive computing power when the occupancy rate of the AI acceleration unit of the chip reaches the limit based on the data flow direction and processing logic of the chip during the test process;

[0148] A data backfilling module, which is used to re-import the road test scenario data into the chip based on the data backfilling method;

[0149] A first calculation module, which is used to calculate the corresponding chip comprehensive computing power when each chip computing power influencing factor is in different states under the condition that other chip computing power influencing factors remain unchanged;

[0150] A second calculation module, which is used to calculate the influence value of each chip computing power influencing factor in different states on the comprehensive computing power based on the chip comprehensive computing power and the theoretical comprehensive computing power of the chip;

[0151] A building module, which is used to establish a chip comprehensive computing power estimation model based on the influence value, chip computing power influencing factor and chip comprehensive computing power;

[0152] A determination and estimation module, which is used to determine the states of each chip computing power influencing factor based on the hardware configuration and application scenario requirements of the chip to be estimated, and then calculate the actual chip comprehensive computing power of the chip to be estimated corresponding to each chip computing power influencing factor based on the chip comprehensive computing power estimation model.

[0153] Embodiment 3

[0154] As Figure 5 shown, this embodiment provides a chip comprehensive computing power testing device, including:

[0155] This device consists of an algorithm model, a data set, a data back-injection system, a mother-daughter board carrying the chip, etc. Among them, the data back-injection system simulates the working principle of a real sensor, and injects real road test scenario data and VTD simulated road test scenario data back to the board end through the interfaces of the sensor and the mother board, so as to complete the simulation test of the real road test data set in the laboratory.

[0156] Embodiment 4

[0157] This embodiment provides an electronic device, which includes:

[0158] At least one processor; and,

[0159] A memory communicatively connected to the at least one processor; wherein,

[0160] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the chip comprehensive computing power test method in Embodiment 1.

[0161] The electronic device according to an embodiment of the present disclosure includes a memory and a processor, and the memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0162] The processor may be a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions. In an embodiment of the present disclosure, the processor is used to run the computer-readable instructions stored in the memory.

[0163] Those skilled in the art should understand that, in order to solve the technical problem of how to obtain good user experience effects, this embodiment may also include well-known structures such as communication buses, interfaces, etc., and these well-known structures should also be included in the protection scope of the present disclosure.

[0164] For the detailed description of this embodiment, reference may be made to the corresponding descriptions in the foregoing embodiments, and details will not be repeated here.

[0165] Embodiment 5

[0166] This embodiment provides a non-transitory computer-readable storage medium, and the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute the chip comprehensive computing power test method in Embodiment 1.

[0167] The computer-readable storage medium according to an embodiment of the present disclosure stores non-transitory computer-readable instructions thereon. When the non-transitory computer-readable instructions are run by a processor, all or part of the steps of the methods of the foregoing embodiments of the present disclosure are executed.

[0168] The above computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or removable hard disk), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0169] The embodiments of the present invention have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for testing the comprehensive computing power of a chip, characterized in that, it includes: Transmitting the road test scenario data of the database / vehicle sensor to the chip based on the data interface between the sensor and the chip, and performing a comprehensive computing power test on the chip based on the comprehensive computing power algorithm model; Based on the data flow direction and processing logic of the chip during the test, analyzing the chip computing power impact factors that affect the comprehensive computing power of the chip when the occupancy rate of the AI acceleration unit of the chip reaches the limit; Based on the data backfilling method, re-importing the road test scenario data into the chip, and calculating the corresponding comprehensive computing power of the chip when each chip computing power impact factor is in different states while other chip computing power impact factors remain unchanged; Calculating the influence value of each chip computing power impact factor on the comprehensive computing power when it is in different states based on the comprehensive computing power of the chip and the theoretical comprehensive computing power of the chip; Establishing a comprehensive computing power estimation model of the chip based on the influence value, the chip computing power impact factor, and the comprehensive computing power of the chip; Determining the states of each chip computing power impact factor based on the hardware configuration and application scenario requirements of the chip to be estimated, and then calculating the actual comprehensive computing power of the chip to be estimated corresponding to each chip computing power impact factor based on the comprehensive computing power estimation model of the chip.

2. The method for testing the comprehensive computing power of a chip according to claim 1, characterized in that, The specific process of calculating the corresponding comprehensive computing power of the chip when each chip computing power impact factor is in different states includes: S1. Setting multiple states of a single chip computing power impact factor; S2. Re-importing the road test scenario data into the chip based on the data backfilling method; S3. Calculating the comprehensive computing power of the chip when the chip computing power impact factor is in one state while the states of other chip computing power impact factors remain unchanged; S4. Changing the state of the chip computing power impact factor, repeating S2 - S3, and respectively obtaining the corresponding comprehensive computing power of the chip when the chip computing power impact factor is in different states; S5. Replacing the chip computing power impact factor, repeating S1 - S4 until obtaining the corresponding comprehensive computing power of the chip when each chip computing power impact factor is in different states.

3. The method for testing the comprehensive computing power of a chip according to claim 1, characterized in that, The chip computing power impact factors include: Contribution factors and constraint factors; The contribution factors include: CPU frequency, number of cores, DDR bandwidth, on-chip storage, form of in-vehicle camera interface, resolution of in-vehicle camera, number of chip cores, and data input form; The constraint factors include: power consumption / temperature, accuracy of the comprehensive computing power algorithm model, image data communication delay, and image processing frame rate.

4. The method for testing the comprehensive computing power of a chip according to claim 1, characterized in that, The calculation expression of the comprehensive computing power of the chip is: T ij = f ij × M; Among them, T ij is the comprehensive computing power of the chip corresponding to the i-th chip computing power influence factor in the j-th state, f ij is the processing frame rate corresponding to the i-th chip computing power influence factor in the j-th state, and M is the model calculation amount of the comprehensive computing power algorithm model.

5. The method for testing the comprehensive computing power of a chip according to claim 1, characterized in that, The calculation expression of the influence value is: Among them, T ij is the comprehensive chip computing power corresponding to the i-th chip computing power influence factor in the j-th state, and τ ij is the influence value of the i-th chip computing power influence factor on the comprehensive chip computing power in the j-th state. e is a constant, and α is the theoretical comprehensive computing power of the test chip.

6. The method for testing the comprehensive computing power of a chip according to claim 1, characterized in that, The calculation expression of the actual comprehensive computing power is: T gi = T l × τ ij ; Among them, τ ij is the influence value of the i-th chip computing power influence factor on the comprehensive computing power of the chip in the j-th state, T gi is the actual comprehensive computing power of the chip to be estimated corresponding to the i-th chip computing power influence factor, T l is the theoretical comprehensive computing power of the chip to be estimated.

7. The chip comprehensive computing power testing method according to claim 4, wherein, the calculation expression of the model calculation amount is: M = H × W × (C in × K 2 + 1) × C out ; Among them, H is the height value of the output feature map, W is the width value of the output feature map, C in and C out are the number of input channels and the number of output channels respectively, and K is the convolution kernel size.

8. An electronic device, wherein, the electronic device includes: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the chip comprehensive computing power testing method according to any one of claims 1-7.

9. A non-transitory computer-readable storage medium, wherein, the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute the chip comprehensive computing power testing method according to any one of claims 1-7.

10. A chip comprehensive computing power testing device, wherein, it includes: a data interface between a sensor and a chip, configured to transmit the road test scenario data of a database / vehicle sensor to the chip through the data interface, and perform chip comprehensive computing power testing based on a comprehensive computing power algorithm model; a testing module, configured to perform chip comprehensive computing power testing based on the comprehensive computing power algorithm model; an analysis module, based on the data flow direction and processing logic of the chip during the testing process, analyzes the chip computing power impact factors that affect the chip comprehensive computing power when the occupancy rate of the AI acceleration unit of the chip reaches the limit; a data backfilling module, configured to re-import the road test scenario data into the chip based on a data backfilling method; a first calculation module, configured to calculate the corresponding chip comprehensive computing power when each of the chip computing power impact factors is in a different state while other chip computing power impact factors remain unchanged; a second calculation module, configured to calculate the influence value of each chip computing power impact factor on the comprehensive computing power when in a different state based on the chip comprehensive computing power and the theoretical comprehensive computing power of the chip; a building module, configured to build a chip comprehensive computing power estimation model based on the influence value, the chip computing power impact factor, and the chip comprehensive computing power; a determining and estimating module, configured to determine the states of the chip computing power impact factors based on the hardware configuration and application scenario requirements of the chip to be estimated, and then calculate the actual chip comprehensive computing power of the chip to be estimated corresponding to each of the chip computing power impact factors based on the chip comprehensive computing power estimation model.

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