Memory comprehensive testing method and device

Abstract

The present invention discloses a memory comprehensive test method and device, and relates to the field of memory test technology. The method can achieve the purpose of comprehensive and complete testing of the target memory by sequentially performing basic tests, system index tests, and reliability tests on the target memory, thereby ensuring the accuracy of the test results and avoiding the phenomenon that the target memory is misjudged as a defective product. In addition, non-defective products can also be accurately graded to further ensure the accuracy of the test results, which is beneficial to product grading and pricing, and is convenient for practical application and promotion.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory testing, and in particular relates to a memory comprehensive testing method and device. Background Art

[0002] End users have become accustomed to quality issues of electronic products such as mobile phone freezes and computer blue screens, which have become a "collective experience" for the public. With the rise of intelligent computing industries such as artificial intelligence, online finance, driverless driving, and medical intelligence, "computing power" is the core driving force, and the underlying infrastructure of computing power has extremely high requirements for "reliability", so the performance and quality of memory are crucial to the computer.

[0003] Although the existing memory testing scheme adopts a step-by-step testing method to test the memory quality, the memory test is not comprehensive. Therefore, a more comprehensive technical scheme for memory testing is urgently needed. Summary of the invention

[0004] The purpose of the present invention is to provide a memory comprehensive testing method and device to solve the problem that the existing memory testing scheme is not comprehensive for memory testing, thereby affecting the accuracy of the test results.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] In a first aspect, a memory comprehensive testing method is provided, comprising:

[0007] Performing a basic test on the target memory using a preset basic test template, and determining whether the target memory is a non-defective product based on the obtained basic test results;

[0008] When it is determined that the target memory is not a defective product according to the basic test result, the target memory is firstly tested for system indicators under a preset first working environment to obtain operating parameters, and then data analysis is performed on the operating parameters to obtain a first test result, and finally, it is determined whether the target memory is not a defective product according to a first comparison result between the first test result and a first preset standard;

[0009] When it is determined that the target memory is not a defective product based on the first comparison result, the target memory is first subjected to a reliability test under a preset second working environment to obtain a second test result, and then it is determined whether the target memory is not a defective product based on a second comparison result of the second test result and a second preset standard.

[0010] Based on the above invention content, a new solution for comprehensive testing of target memory is provided, that is, by performing basic test, system indicator test and reliability test on the target memory in sequence, the purpose of comprehensive and complete testing of the target memory can be achieved, thereby ensuring the accuracy of the test results, avoiding the phenomenon of target memory being misjudged as a defective product, and facilitating practical application and promotion.

[0011] In one possible design, the basic test includes appearance inspection, DC parameter test and / or AC parameter test, wherein the DC parameter test includes open circuit test, short circuit test, current power consumption test and / or voltage parameter test under a certain DC voltage range, and the certain DC voltage range at least covers the maximum / minimum voltage values ​​defined by the JEDEC standard, and the AC parameter test includes a test for measuring time-related electrical parameters, and the electrical parameters include frequency, access delay time, refresh time and / or data retention time.

[0012] In one possible design, the first working environment includes a first high temperature environment and a first low temperature environment, the system indicator test includes a core parameter test and / or a signal integrity test, wherein the core parameter test includes a test for measuring any parameter in the JEDEC standard, the original design specification and / or the customer's stringent test standard, the signal integrity test includes an RMT test, a second RMT test under the condition of applying environmental fluctuation factors and / or a third RMT test under the condition of applying environmental fluctuation factors and self-fluctuation factors at the same time, the environmental fluctuation factors include temperature and voltage, and the self-fluctuation factors include the internal data topology complexity of the chip.

[0013] In one possible design, the second working environment includes a second high temperature environment and a second low temperature environment, and the reliability test includes repeated power on and off test, aging test and / or factory customized aging test, wherein the repeated power on and off test refers to a test in which the memory to be tested is repeatedly powered on and off to obtain a number of consecutive successful power-on startups, the aging test refers to a test in which the memory to be tested is refined to achieve a state in which parameters do not drift and is stable and reliable, the factory customized aging test refers to an aging test performed according to factory customized aging test conditions, test time and judgment criteria, the aging refers to the phenomenon of parameter drift generated by the memory to be tested during the online process, and the refining refers to the use of detection means to make the memory to be tested go through a parameter turbulence stage.

[0014] In a possible design, when the system indicator test includes a signal integrity test and the signal integrity test includes a second RMT test under the condition of applying environmental fluctuation factors or a third RMT test under the condition of simultaneously applying environmental fluctuation factors and self-fluctuation factors, the test includes: taking random addresses and random data to perform input and output I / O training of data and addresses, and doubling the training timing after each data line eye diagram is obtained, and then performing the input and output I / O training again until the two data line eye diagrams obtained from two consecutive trainings converge to be completely consistent.

[0015] In a possible design, performing data analysis on the operating parameters to obtain a first test result includes:

[0016] The operating parameters are continuously monitored, and the fluctuation amplitude of each parameter in the operating parameters is comprehensively superimposed to obtain a chip internal fluctuation index used as a first test result and used to characterize chip stability.

[0017] In a possible design, determining whether the target memory is a non-defective product according to the obtained basic test result includes:

[0018] According to the basic test results obtained, it is determined whether the target memory has passed the basic system test. If so, it is determined that the target memory is not a defective product. Otherwise, it is further determined whether the target memory can be repaired after chip packaging. If not, it is determined that the target memory is a defective product.

[0019] In a possible design, determining whether the target memory is a non-defective product according to a first comparison result between the first test result and a first preset standard includes:

[0020] According to the first comparison result between the first test result and the first preset standard, it is determined whether the core parameter test result of the target memory complies with the JEDEC standard and whether the target memory passes the RMT test. If so, it is determined that the target memory is not a defective product. Otherwise, it is further determined whether the target memory can be repaired after chip packaging. If not, it is determined that the target memory is a defective product.

[0021] In a possible design, determining whether the target memory is a non-defective product according to a second comparison result between the second test result and a second preset standard includes:

[0022] According to the second comparison result between the second test result and the second preset standard, determine whether the number of consecutive successful power-on and power-off startups of the target memory in the repeated power-on and power-off test results reaches a preset first number threshold. If so, determine that the target memory is not a defective product; otherwise, directly determine that the quality level of the target memory is an original product.

[0023] In one possible design, the method further includes:

[0024] Each time the target memory is determined to be a defective product, a repair test is performed on the target memory based on customer feedback and / or the repair conditions of the target memory. If the repair test is passed, the target memory is finally determined to be a non-defective product. Otherwise, the target memory is finally determined to be a defective product.

[0025] In a possible design, after finally determining that the target memory is a non-defective product, the method further includes:

[0026] A factory zero-error test is performed on the target memory, and a quality grade of the target memory is determined according to the factory zero-error test result.

[0027] In a possible design, determining the quality level of the target memory according to the factory zero error test result includes the following steps S501 to S514:

[0028] S501. According to the factory zero error test result, determine whether the error count of the target memory under the On-die ECC mechanism is equal to 0, if so, execute step S503, otherwise execute step S502;

[0029] S502. Determine whether the target memory can be repaired after chip packaging, if not, determine the quality level of the target memory is original;

[0030] S503. Determine whether the number of times the target memory has been tested for superior products is greater than or equal to a preset second number threshold. If so, determine that the quality level of the target memory is a standard product, otherwise execute step S504;

[0031] S504. Determine whether there is a record of failed detection of aged products in the target memory. If so, execute step S511; otherwise, execute step S505;

[0032] S505. Determine whether to perform an aging test on the target memory. If so, execute step S506; otherwise, execute step S511;

[0033] S506. Start to perform aging detection on the target memory, and then execute step S507;

[0034] S507. Determine whether the target memory meets the first half of the product normal distribution and passes the third RMT test. If so, execute step S508; otherwise, execute step S511;

[0035] S508. Determine whether the target memory passes the customer-defined strict test. If so, execute step S509; otherwise, execute step S513;

[0036] S509. Determine whether the number of consecutive successful power-on and power-off test results in the target memory reaches a preset third number threshold. If so, execute step S510, otherwise execute step S514;

[0037] S510. Determine whether the target memory is completely aged, and if so, determine that the quality level of the target memory is a high-quality refined product;

[0038] S511. Start to detect the target memory as a high-quality product, and then execute step S512;

[0039] S512. Determine whether the target memory conforms to the product normal distribution @-2 standard deviations and passes the second RMT test. If so, execute step S513;

[0040] S513. Determine whether the target memory passes the tightened system test, if so, execute step S514;

[0041] S514. Determine whether the number of consecutive successful power-on and power-off test results of the target memory reaches a preset fourth number threshold. If so, determine that the quality level of the target memory is superior; otherwise, determine that the quality level of the target memory is standard, wherein the fourth number threshold is lower than the third number threshold.

[0042] In a second aspect, a memory comprehensive test device is provided, including a basic test module, a system index test module and a reliability test module which are sequentially communicatively connected;

[0043] The basic test module is used to perform a basic test on the target memory using a preset basic test template, and determine whether the target memory is a non-defective product based on the obtained basic test result;

[0044] The system index test module is used for, when it is determined that the target memory is not a defective product according to the basic test result, firstly performing a system index test on the target memory under a preset first working environment to obtain operating parameters, then performing data analysis on the operating parameters to obtain a first test result, and finally determining whether the target memory is a non-defective product according to a first comparison result between the first test result and a first preset standard;

[0045] The reliability testing module is used to first perform a reliability test on the target memory under a preset second working environment to obtain a second test result when it is determined that the target memory is not a defective product based on the first comparison result, and then determine whether the target memory is a non-defective product based on a second comparison result of the second test result and a second preset standard.

[0046] Beneficial effects of the above scheme:

[0047] (1) The present invention creatively provides a new scheme for performing comprehensive testing on a target memory, that is, by sequentially performing basic tests, system index tests, and reliability tests on the target memory, the purpose of performing comprehensive and complete testing on the target memory can be achieved, thereby ensuring the accuracy of the test results and avoiding the phenomenon that the target memory is misjudged as a defective product, which is convenient for practical application and promotion;

[0048] (2) It can also accurately classify non-defective products into quality grades, further ensuring the accuracy of the test results and facilitating product grading and pricing. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 A flowchart of a comprehensive memory testing method provided in an embodiment of the present application.

[0051] Figure 2 A schematic diagram of the memory quality level classification process provided in an embodiment of the present application.

[0052] Figure 3 A schematic diagram of the structure of a comprehensive memory testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structures of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these embodiments without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0054] It should be understood that although the terms first and second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another object. For example, a first object can be referred to as a second object, and similarly, a second object can be referred to as a first object without departing from the scope of the exemplary embodiments of the present invention.

[0055] It should be understood that the term "and / or" that may appear in this document is merely a description of the association relationship between associated objects, indicating that there may be three relationships. For example, A and / or B can represent three situations: the existence of A alone, the existence of B alone, or the existence of A and B at the same time; for another example, A, B and / or C can represent the existence of any one of A, B and C or any combination of them; in addition, the character " / " that may appear in this document generally indicates that the associated objects before and after are in an "or" relationship.

[0056] Example:

[0057] like Figure 1 As shown, the memory comprehensive testing method provided in the first aspect of this embodiment may include but is not limited to the following steps S1 to S3.

[0058] S1. Perform a basic test on the target memory using a preset basic test template, and determine whether the target memory is a non-defective product based on the obtained basic test results.

[0059] In step S1, the target memory is a specific memory to be tested. Specifically, the basic test includes but is not limited to appearance inspection, DC (Direct Current) parameter test and / or AC (Alternating Current) parameter test, etc., wherein the DC parameter test includes but is not limited to open circuit test, short circuit test, current power consumption test and / or voltage parameter test under a certain DC voltage range, and the certain DC voltage range at least covers the maximum / minimum voltage value defined by the JEDEC (Joint Electron Device Engineering Council, which is a broad standardization organization that has established a series of standards for the design, manufacture, testing and packaging of electronic equipment) standard, and the AC parameter test includes but is not limited to tests for measuring time-related electrical parameters, and the electrical parameters include but are not limited to frequency, access delay time, refresh time and / or data retention time, etc. The specific test means of the basic test are existing technical means. In addition, more specifically, determining whether the target memory is a non-defective product based on the obtained basic test results includes but is not limited to: judging whether the target memory passes the basic system test based on the obtained basic test results, if so, determining that the target memory is a non-defective product, otherwise further judging whether the target memory can be repaired after chip packaging, if not, determining that the target memory is a defective product. In addition, if it is determined that the target memory can be repaired after chip packaging, the target memory is repaired after chip packaging, and then the execution of step S1 is returned to the memory obtained after the repair.

[0060] S2. When it is determined that the target memory is not a defective product based on the basic test result, the target memory is first subjected to a system index test under a preset first working environment to obtain operating parameters, and then data analysis is performed on the operating parameters to obtain a first test result. Finally, it is determined whether the target memory is not a defective product based on a first comparison result between the first test result and a first preset standard.

[0061] In the step S2, specifically, the first working environment includes but is not limited to a first high temperature environment and a first low temperature environment, the system index test includes but is not limited to a core parameter test and / or a signal integrity test, wherein the core parameter test includes a test for measuring any parameter in the JEDEC standard, the original design specification and / or the customer's stringent test standard, etc., the signal integrity test includes but is not limited to an RMT (Rank Margining Tool) test, a second RMT test under the condition of applying environmental fluctuation factors, and / or a third RMT test under the condition of applying environmental fluctuation factors and self-fluctuation factors at the same time, the environmental fluctuation factors include but are not limited to temperature and voltage, etc., and the self-fluctuation factors include the complexity of the internal data topology of the chip. The JEDEC standard is an existing standard. The original design specification is used to implement the current national laws and regulations in the original chip design to meet the chip production requirements; it is mainly designed around core parameters, standardizing the core parameters of the chip such as tRCD, tCL, tRP, tRASmin, tRFC, tDataRetention, tREFI, tWR, tRTP, tCWL, tRRD_S, tRRD_L, tWTR_S, tFAW, CmdRate and tCCD_L (the specific meanings of these core parameters are existing common knowledge, for example, tRCD represents the delay time for the memory row address to be transmitted to the column address, tCL represents the delay time for the column address access, tRP represents the pre-charge effective period, etc.); in addition, the parameters in the original design specification may also include a detection setting as the median of a normal distribution, wherein the role of the median is to serve as a standard reference value (specifically defined according to the characteristics of the memory product to be tested) so that the test level can be determined based on the comparison result between the test data and the standard reference value. The customer's tightened test standard refers to the standard for tightening system testing for a certain parameter under the test requirements specified by the customer, wherein the tightened system test refers to running different test programs to perform long-term (generally 8 to 24 hours) system stress testing on the memory under high temperature environment, pressure and core parameter deviation, so that in the actual application end, a certain parameter test (i.e., custom data standard) can be focused on according to the use environment to screen out higher-level products. Signal integrity is an important concept in electronic and electrical engineering, especially in high-speed digital and analog circuit design; signal integrity is mainly concerned with whether the eye diagram and timing characteristics can be accurately and reliably maintained when the signal is transmitted in the circuit; the specific process of the RMT test is the existing technology, for example, including: starting from the memory initialization training timing (Timing Training), first grabbing the data valid access window of each I / O pin, then center alignment, and then superimposing the eye diagrams of all I / Os to obtain a common valid access window (Solution Window).The second RMT test refers to superimposing and quantifying its common effective access window (Solution Window) under the condition of applying environmental fluctuation factors; the third RMT test refers to superimposing and quantifying its common effective access window (Solution Window) under the condition of applying environmental fluctuation factors and self-fluctuation factors at the same time. Considering that the second RMT test and the third RMT test jump from one data combination to another data combination, there are infinite possibilities, and it is impossible to achieve a truly perfect final RMT test. Therefore, in order to achieve a stable RMT test, preferably, when the system index test includes a signal integrity test and the signal integrity test includes a second RMT test under the condition of applying environmental fluctuation factors or a third RMT test under the condition of applying environmental fluctuation factors and self-fluctuation factors at the same time, the test includes but is not limited to: taking random addresses and random data to perform input and output I / O training of data and addresses, and after each data line eye diagram is obtained, the training timing is doubled, and then the input and output I / O training is performed again until the two data line eye diagrams obtained from two consecutive trainings converge to be completely consistent. In addition, among the environmental fluctuation factors, the voltage specifically affects the environment through voltage pull-bias stress (which can be set through a test software program); and the complexity of the internal data topology of the chip is an inherent property of the chip. Because of the complex topology, the impact is relatively large (for example, different individual physiques have different adaptability to severe cold and other harsh weather environments).

[0062] In the step S2, specifically, the operating parameters include but are not limited to core parameters such as tRCD, tCL, tRP, tRASmin, tRFC, tDataRetention, tREFI, tWR, tRTP, tCWL, tRRD_S, tRRD_L, tWTR_S, tFAW, CmdRate, tCCD_L and / or RMT test results. In addition, more specifically, data analysis is performed on the operating parameters to obtain a first test result, including but not limited to: continuously monitoring the operating parameters, and comprehensively superimposing the fluctuation amplitude of each parameter in the operating parameters to obtain a chip internal fluctuation index used as the first test result and for characterizing chip stability. In addition, when the chip internal fluctuation index reaches a stable value of 0 or close to 0, it can also be used to indicate that the chip is fully aged.

[0063] In step S2, specifically, determining whether the target memory is a non-defective product is based on the first comparison result between the first test result and the first preset standard, including but not limited to: judging whether the core parameter test result of the target memory complies with the JEDEC standard and whether the target memory passes the RMT test based on the first comparison result between the first test result and the first preset standard, if so, determining that the target memory is a non-defective product, otherwise further judging whether the target memory can be repaired after chip packaging, if not, determining that the target memory is a defective product. Similarly, if it is determined that the target memory can be repaired after chip packaging, the target memory is repaired after chip packaging, and then the memory obtained after the repair is returned to step S1.

[0064] S3. When it is determined that the target memory is not a defective product based on the first comparison result, the target memory is first subjected to a reliability test under a preset second working environment to obtain a second test result, and then it is determined whether the target memory is not a defective product based on a second comparison result of the second test result and a second preset standard.

[0065] In the step S3, specifically, the second working environment includes but is not limited to a second high temperature environment and a second low temperature environment, etc., and the reliability test includes but is not limited to repeated power-on and power-off test, aging test and / or original factory custom aging test, etc., wherein the repeated power-on and aging test refers to a test in which the memory to be tested is repeatedly powered on and off to obtain the number of consecutive successful power-on startups, the aging test refers to a test in which the memory to be tested is refined to achieve a state in which the parameters do not drift and are stable and reliable, the original factory custom aging test refers to an aging test according to the original factory custom aging test conditions, test time and judgment criteria, the aging refers to the phenomenon of parameter drift generated by the memory to be tested during the online process, and the refining refers to making the memory to be tested pass the parameter turbulence stage through detection means. The functions of the repeated power-on and aging test, the aging test and the original factory custom aging test are all used to obtain index parameters reflecting the stability and reliability of the memory product to be tested, so as to judge whether the memory product to be tested passes the reliability test based on the comparison result of the index parameters with the preset standard. Due to the existence of "residual stress" in the chip manufacturing process and the electromagnetic "force field pull" during the operation of the chip, the internal structure of the memory product does not enter a stable state after leaving the factory, which is mainly reflected in "parameter drift" and "parameter turbulence", etc., so it is necessary to perform the aging test and / or the original factory customized aging test. In addition, more specifically, determining whether the target memory is a non-defective product based on the second comparison result of the second test result and the second preset standard, including but not limited to: judging whether the number of consecutive successful power-on and power-off startups of the target memory in the repeated power-on and power-off test results reaches a preset first number threshold (for example, 10 times) based on the second comparison result of the second test result and the second preset standard. If so, the target memory is determined to be a non-defective product, otherwise the quality level of the target memory is directly determined to be an original product.

[0066] Therefore, based on the memory comprehensive testing method described in the aforementioned steps S1 to S3, a new scheme for comprehensive testing of the target memory is provided, that is, by performing basic tests, system indicator tests and reliability tests on the target memory in sequence, the purpose of comprehensive and complete testing of the target memory can be achieved, thereby ensuring the accuracy of the test results and avoiding the phenomenon of the target memory being misjudged as a defective product, which is convenient for practical application and promotion.

[0067] Based on the technical solution of the first aspect, this embodiment further provides a possible design for repairing defective products other than high-quality refined products, that is, the method further includes but is not limited to the following step S4.

[0068] S4. Each time the target memory is determined to be a defective product, a repair test is performed on the target memory according to customer opinions and / or the repair conditions of the target memory. If the repair test is passed, the target memory is finally determined to be a non-defective product. Otherwise, the target memory is finally determined to be a defective product.

[0069] In step S4, the specific process of the repair test includes but is not limited to: firstly judging whether the hardware of the memory product to be tested has the repair conditions and / or judging whether there is any customer opinion, and then performing chip post-package repair (i.e., post-package repair) if the aforementioned conditions permit. Figure 2 Specifically, except for the test step for determining whether the memory product to be tested is of high-quality grade, after each step of the test fails, the repair test is required, and then the test of the previous step is repeated again to finally determine the product grade.

[0070] Therefore, based on the above-mentioned possible design one, defective products can also be remedied and repaired, further achieving the purpose of comprehensive and complete testing of the target memory and avoiding the phenomenon that the target memory is misjudged as a defective product.

[0071] Based on the technical solution of the aforementioned possible design one, this embodiment further provides a possible design two for classifying the quality grades of non-defective products, that is, after finally determining that the target memory is a non-defective product, the method further includes the following step S5.

[0072] S5. Perform a factory zero-error test on the target memory, and determine the quality level of the target memory according to the factory zero-error test result.

[0073] In the step S5, the factory zero error test refers to a test for factory zero error detection of the tested memory, which is the core concept of post-factory quality control, that is, the product must meet the zero error requirement before entering the application end, including On-die ECC (Error Checking and Correcting, error checking and correction, developed from parity check, mainly used in memory and processor cache, ECC can realize the discovery and correction of errors in data, thereby improving the operation stability of the entire computer system; On-die ECC is a prior art concept, which adds 8 bits of ECC check bits for every 128 bits of data of a single DRAM particle, and the check bits are stored in the DRAM array together with the data) mechanism, DIMM ECC (DIMM means "dual in-line memory module", ECC is a technology that can realize "error checking and correction") mechanism and system RAS (referring to three indicators such as reliability, availability and serviceability, which are important indicators for evaluating the performance of computer operating system system) mechanism, all error counts are 0. The quality grades are divided into defective products, original products, standard products, superior products and aged products, and their classification rules can be specifically as follows: if any one or more of the core parameter JEDEC standard test, standard signal integrity test (i.e. the RMT test) and basic system test of the product fails, it is judged as a defective product; although the product meets the JEDEC standard, standard signal integrity test (i.e. the RMT test) and basic SLT (System Level test) test requirements, it does not meet the standard product requirements and is judged as an original product; if the product simultaneously meets the JEDEC standard, standard signal integrity test (i.e. the RMT test), repeated power on and off and restart successfully for 10 consecutive times, basic system test, and zero factory errors, it is judged as a standard product, and its expected return rate reaches the original factory guarantee value; if the core parameters of the product meet the JEDEC standard and two sets of standards that are better than the original design specifications by negative two standard deviations, and the signal integrity meets the RMT margin control test (i.e. the second RMT test) standard , and at the same time meets the requirements of repeated power on and off and restart for 100 times, stricter system testing, and zero factory errors, it is judged as a superior product, and its expected return rate is reduced to 50% of the original factory guarantee value; if the core parameters of the product simultaneously meet the three sets of standards of JEDEC standards, the first half of the original design specifications and customer-specified requirements, and the signal integrity meets the stable RMT margin control test (that is, the third RMT test) standard, and at the same time meets the requirements of repeated power on and off and restart for 1000 times, complete aging, and zero factory errors, it is judged as a superior product, and its expected return rate is reduced to 10% of the original factory guarantee value.Specifically, determining the quality level of the target memory according to the factory zero-error test result includes but is not limited to the following steps S501 to S514.

[0074] S501. According to the factory zero error test result, determine whether the error count of the target memory under the On-die ECC mechanism is equal to 0. If so, execute step S503; otherwise, execute step S502.

[0075] S502. Determine whether the target memory can be repaired after chip packaging. If not, determine that the quality level of the target memory is original.

[0076] In the step S502, if it is determined that the target memory can be repaired after chip packaging, the target memory is repaired after chip packaging, and then the process returns to step S1 for the repaired memory.

[0077] S503. Determine whether the number of times the target memory has been tested for superior products is greater than or equal to a preset second number threshold (for example, 3). If so, determine that the quality level of the target memory is a standard product. Otherwise, execute step S504.

[0078] In the step S503, the number of times the target memory has been tested for high-quality products is specifically equal to the number of times the subsequent step S511 is performed on the target memory.

[0079] S504. Determine whether there is a record of failed detection of aged products in the target memory. If so, execute step S511; otherwise, execute step S505.

[0080] In the step S504, the aged product detection refers to the aged test.

[0081] S505. Determine whether to perform an aging test on the target memory. If so, execute step S506; otherwise, execute step S511.

[0082] In step S505, if the target memory has been tested for high-quality products for less than 3 times and there is no record of failed testing for aged products, then the target memory will continue to be tested for aged products by default. Figure 2 Part of the standard process (Bin2) is shown.

[0083] S506. Start to perform aged product detection on the target memory, and then execute step S507.

[0084] S507. Determine whether the target memory conforms to the first half of the product normal distribution and passes the third RMT test. If so, execute step S508; otherwise, execute step S511.

[0085] In step S507, the first half of the product normal distribution is an existing mathematical concept and is used to select optimal data.

[0086] S508. Determine whether the target memory passes the customer-defined strict test. If so, execute step S509; otherwise, execute step S513.

[0087] S509. Determine whether the number of consecutive successful power-on and power-off test results in the target memory reaches a preset third number threshold (for example, 1000 times of repeated power-on and power-off). If so, execute step S510, otherwise execute step S514.

[0088] S510. Determine whether the target memory is completely aged. If so, determine that the quality level of the target memory is high-quality.

[0089] In step S510, it can be specifically determined whether the target memory is completely aged based on the internal fluctuation index of the chip, that is, when the internal fluctuation index of the chip reaches a stable value of 0 or close to 0, it is determined that the target memory is completely aged. In addition, if it is determined that the target memory is not completely aged, the target memory can be repaired after chip packaging, and then the repaired memory can be returned to execute step S1. The process of the above steps S506 to S510 can be seen in Figure 2 The Best Ingredients Flow (BIC) is shown.

[0090] S511. Start to perform high-quality detection on the target memory, and then execute step S512.

[0091] S512. Determine whether the target memory conforms to the product normal distribution @-2 standard deviations and passes the second RMT test. If so, execute step S513.

[0092] In step S512, the product normal distribution @-2 standard deviations is an existing mathematical concept. In addition, if it is determined that the target memory does not conform to the product normal distribution @-2 standard deviations and / or fails the second RMT test, the target memory may be repaired after chip packaging, and then the repaired memory may be returned to step S1.

[0093] S513. Determine whether the target memory passes the tightened system test. If so, execute step S514.

[0094] In step S513, if it is determined that the target memory fails the tightened system test, the target memory may be repaired after chip packaging, and then the process returns to step S1 for the repaired memory.

[0095] S514. Determine whether the number of consecutive successful power-on and power-off startup times in the repeated power-on and power-off test results of the target memory reaches a preset fourth number threshold (for example, 100 repeated power-on and power-off times). If so, determine that the quality level of the target memory is superior; otherwise, determine that the quality level of the target memory is standard, wherein the fourth number threshold is lower than the third number threshold.

[0096] The process flow of the above steps S511 to S514 can be found in Figure 2 The superior product process (Bin1) is shown.

[0097] Therefore, based on the aforementioned possible design 2, non-defective products can also be accurately classified into quality grades, further ensuring the accuracy of the test results, which is beneficial to product grading and pricing.

[0098] like Figure 3 As shown, the second aspect of this embodiment provides a virtual device for implementing the memory comprehensive test method described in the first aspect or any possible design in the first aspect, including a basic test module, a system index test module and a reliability test module that are sequentially connected in communication;

[0099] The basic test module is used to perform a basic test on the target memory using a preset basic test template, and determine whether the target memory is a non-defective product based on the obtained basic test result;

[0100] The system index test module is used for, when it is determined that the target memory is not a defective product according to the basic test result, firstly performing a system index test on the target memory under a preset first working environment to obtain operating parameters, then performing data analysis on the operating parameters to obtain a first test result, and finally determining whether the target memory is a non-defective product according to a first comparison result between the first test result and a first preset standard;

[0101] The reliability testing module is used to first perform a reliability test on the target memory under a preset second working environment to obtain a second test result when it is determined that the target memory is not a defective product based on the first comparison result, and then determine whether the target memory is a non-defective product based on a second comparison result of the second test result and a second preset standard.

[0102] The working process, working details and technical effects of the aforementioned device provided in the second aspect of this embodiment can be referred to the first aspect or any possible design of the memory comprehensive testing method described in the first aspect, and will not be repeated here.

[0103] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory comprehensive testing method, characterized in that: include: Performing a basic test on the target memory using a preset basic test template, and determining whether the target memory is a non-defective product based on the obtained basic test results; When it is determined that the target memory is not a defective product according to the basic test result, the target memory is first subjected to a system indicator test under a preset first working environment to obtain operating parameters, and then data analysis is performed on the operating parameters to obtain a first test result, and finally, it is determined whether the target memory is not a defective product according to a first comparison result between the first test result and a first preset standard, wherein, when the system indicator test includes a signal integrity test and the signal integrity test includes a second RMT test under the condition of applying environmental fluctuation factors or a third RMT test under the condition of applying environmental fluctuation factors and self-fluctuation factors at the same time, the test includes: taking random addresses and random data to perform input and output I / O training of data and addresses, and after each data line eye diagram is obtained, doubling the training timing, and then performing the input and output I / O training again, until the two data line eye diagrams obtained from two consecutive trainings converge to be completely consistent; When it is determined that the target memory is not a defective product based on the first comparison result, the target memory is first subjected to a reliability test under a preset second working environment to obtain a second test result, and then it is determined whether the target memory is not a defective product based on a second comparison result of the second test result and a second preset standard.

2. The memory comprehensive testing method according to claim 1, characterized in that: The basic test includes appearance inspection, DC parameter test and / or AC parameter test, wherein the DC parameter test includes an open circuit test, a short circuit test, a current power consumption test and / or a voltage parameter test under a certain DC voltage range, and the certain DC voltage range at least covers the maximum / minimum voltage value defined by the JEDEC standard, and the AC parameter test includes a test for measuring time-related electrical parameters, and the electrical parameters include frequency, access delay time, refresh time and / or data retention time; And / or, the first working environment includes a first high temperature environment and a first low temperature environment, the system index test also includes a core parameter test, wherein the core parameter test includes a test for measuring any parameter in the JEDEC standard, the original design specification and / or the customer's stringent test standard, the signal integrity test also includes an RMT test, the environmental fluctuation factor includes temperature and voltage, and the self-fluctuation factor includes the complexity of the chip's internal data topology; And / or, the second working environment includes a second high temperature environment and a second low temperature environment, the reliability test includes repeated power on and off test, aging test and / or factory customized aging test, wherein the repeated power on and off test refers to a test in which the memory to be tested is repeatedly powered on and off so as to obtain a continuous number of successful power-on and startup times, the aging test refers to a test in which the memory to be tested is refined so as to achieve a state in which parameters do not drift and is stable and reliable, the factory customized aging test refers to an aging test in accordance with the factory customized aging test conditions, test time and judgment criteria, the aging refers to the phenomenon of parameter drift generated by the memory to be tested during the online process, and the refining refers to the use of detection means to make the memory to be tested pass through the parameter turbulence stage.

3. The memory comprehensive testing method according to claim 1, characterized in that: Performing data analysis on the operating parameters to obtain a first test result includes: The operating parameters are continuously monitored, and the fluctuation amplitude of each parameter in the operating parameters is comprehensively superimposed to obtain a chip internal fluctuation index used as a first test result and used to characterize chip stability.

4. The memory comprehensive testing method according to claim 1, characterized in that: Determining whether the target memory is a non-defective product according to the obtained basic test results includes: According to the basic test results obtained, it is determined whether the target memory has passed the basic system test. If so, it is determined that the target memory is not a defective product. Otherwise, it is further determined whether the target memory can be repaired after chip packaging. If not, it is determined that the target memory is a defective product.

5. The memory comprehensive testing method according to claim 1, characterized in that: Determining whether the target memory is a non-defective product according to a first comparison result between the first test result and a first preset standard, including: judging whether a core parameter test result of the target memory complies with a JEDEC standard and whether the target memory passes an RMT test according to a first comparison result between the first test result and the first preset standard, and if so, determining that the target memory is a non-defective product; otherwise, further judging whether the target memory can be repaired after chip packaging, and if not, determining that the target memory is a defective product; And / or, determining whether the target memory is a non-defective product based on a second comparison result between the second test result and a second preset standard, including: judging whether the number of consecutive successful power-on and power-off startups of the target memory in the repeated power-on and power-off test results reaches a preset first number threshold based on the second comparison result between the second test result and the second preset standard; if so, determining that the target memory is a non-defective product; otherwise directly determining that the quality level of the target memory is an original product.

6. The memory comprehensive testing method according to claim 1, characterized in that: The method further comprises: Each time the target memory is determined to be a defective product, a repair test is performed on the target memory based on customer feedback and / or the repair conditions of the target memory. If the repair test is passed, the target memory is finally determined to be a non-defective product. Otherwise, the target memory is finally determined to be a defective product.

7. The memory comprehensive testing method according to claim 6, characterized in that: After finally determining that the target memory is a non-defective product, the method further includes: A factory zero-error test is performed on the target memory, and a quality grade of the target memory is determined according to the factory zero-error test result.

8. The memory comprehensive testing method according to claim 7, characterized in that: Determining the quality level of the target memory according to the factory zero error test result includes the following steps S501 to S514: S501. According to the factory zero error test result, determine whether the error count of the target memory under the On-die ECC mechanism is equal to 0, if so, execute step S503, otherwise execute step S502; S502. Determine whether the target memory can be repaired after chip packaging, if not, determine the quality level of the target memory is original; S503. Determine whether the number of times the target memory has been tested for superior products is greater than or equal to a preset second number threshold. If so, determine that the quality level of the target memory is a standard product, otherwise execute step S504; S504. Determine whether there is a record of failed detection of aged products in the target memory. If so, execute step S511; otherwise, execute step S505; S505. Determine whether to perform an aging test on the target memory. If so, execute step S506; otherwise, execute step S511; S506. Start to perform aging detection on the target memory, and then execute step S507; S507. Determine whether the target memory meets the first half of the product normal distribution and passes the third RMT test. If so, execute step S508, otherwise execute step S511; S508. Determine whether the target memory passes the customer-defined strict test. If so, execute step S509; otherwise, execute step S513; S509. Determine whether the number of consecutive successful power-on and power-off test results in the target memory reaches a preset third number threshold. If so, execute step S510, otherwise execute step S514; S510. Determine whether the target memory is completely aged, and if so, determine that the quality level of the target memory is a high-quality refined product; S511. Start to detect the target memory as a high-quality product, and then execute step S512; S512. Determine whether the target memory conforms to the product normal distribution @-2 standard deviations and passes the second RMT test. If so, execute step S513; S513. Determine whether the target memory passes the tightened system test, if so, execute step S514; S514. Determine whether the number of consecutive successful power-on and power-off test results of the target memory reaches a preset fourth number threshold. If so, determine that the quality level of the target memory is superior; otherwise, determine that the quality level of the target memory is standard, wherein the fourth number threshold is lower than the third number threshold.

9. A memory comprehensive testing device, characterized in that: It includes a basic test module for sequential communication connection, a system index test module and a reliability test module; The basic test module is used to perform a basic test on the target memory using a preset basic test template, and determine whether the target memory is a non-defective product based on the obtained basic test result; The system indicator test module is used for, when it is determined that the target memory is not defective according to the basic test result, firstly performing a system indicator test on the target memory under a preset first working environment to obtain operating parameters, then performing data analysis on the operating parameters to obtain a first test result, and finally determining whether the target memory is not defective according to a first comparison result between the first test result and a first preset standard, wherein, when the system indicator test includes a signal integrity test and the signal integrity test includes a second RMT test under the condition of applying environmental fluctuation factors or a third RMT test under the condition of applying environmental fluctuation factors and self-fluctuation factors at the same time, the test includes: taking random addresses and random data to perform input and output I / O training of data and addresses, and doubling the training timing after each data line eye diagram is obtained, and then performing the input and output I / O training again until the two data line eye diagrams obtained from two consecutive trainings converge to be completely consistent; The reliability testing module is used to first perform a reliability test on the target memory under a preset second working environment to obtain a second test result when it is determined that the target memory is not a defective product based on the first comparison result, and then determine whether the target memory is a non-defective product based on a second comparison result of the second test result and a second preset standard.

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