A bandgap reference voltage source circuit with temperature compensation circuit

Abstract

This invention discloses a bandgap reference voltage source circuit with a temperature compensation circuit, relating to the field of analog integrated circuit design technology. The circuit includes a startup and bias circuit, a bandgap reference core circuit, and a temperature compensation circuit. The input terminal of the startup and bias circuit is connected to a reference voltage VREF; the output terminal of the startup and bias circuit outputs a bias voltage; the output terminal of the startup and bias circuit is connected to the input terminal of the bandgap reference core circuit; the output terminal of the bandgap reference core circuit is used to generate PTAT voltage, CTAT voltage, and the reference voltage VREF; the output terminal of the bandgap reference core circuit is connected to the input terminal of the temperature compensation circuit; the temperature compensation circuit is used to compensate for the temperature of the bandgap reference voltage source circuit, effectively improving the power supply rejection ratio, reducing the temperature drift coefficient, and providing an adjustable output reference voltage.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design technology, and in particular to a bandgap reference voltage source circuit with temperature compensation circuitry. Background Technology

[0002] In recent years, with the rapid development of microelectronics technology and the semiconductor industry, bandgap reference voltage sources (Bandgap) have become extremely important as the most basic unit circuit in the field of power management systems. A precise reference voltage is typically required for a power management system to output an accurate voltage. Bandgap reference voltage sources can provide a stable reference voltage for low dropout regulators (LDOs) and DC-DC switching power supplies. As the pursuit of greater stability and accuracy in power management systems increases, the reference voltage must become less dependent on process technology, temperature, and power supply voltage, remaining unchanged regardless of variations in these factors. In other words, it is desirable for bandgap reference voltage sources to reduce temperature drift and improve power supply rejection ratio (PSRR). However, traditional bandgap reference circuits suffer from disadvantages such as low loop gain, high temperature drift, low PSRR, and a fixed output reference voltage of approximately 1.2V, which are detrimental to the high stability and high accuracy of the power management system's output voltage. Summary of the Invention

[0003] The purpose of this invention is to provide a bandgap reference voltage source circuit with a temperature compensation circuit, which can effectively improve the power supply rejection ratio, reduce the temperature drift coefficient, and has the feature of adjustable output reference voltage.

[0004] To achieve the above objectives, the present invention provides the following solution:

[0005] A bandgap reference voltage source circuit with temperature compensation circuit includes: a startup and bias circuit, a bandgap reference core circuit, and a temperature compensation circuit.

[0006] The input terminal of the startup and bias circuit is connected to the reference voltage VREF; the output terminal of the startup and bias circuit outputs the bias voltage; the output terminal of the startup and bias circuit is connected to the input terminal of the bandgap reference core circuit; the output terminal of the bandgap reference core circuit is used to generate PTAT voltage, CTAT voltage, and the reference voltage VREF; the output terminal of the bandgap reference core circuit is connected to the input terminal of the temperature compensation circuit; the temperature compensation circuit is used to perform temperature compensation on the bandgap reference voltage source circuit.

[0007] Optionally, the startup and bias circuit specifically includes: PMOS transistors PM5, PM6, NMOS transistors NM1, NMOS transistors NM2, PM7, PM8, NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, NMOS transistors NM6 and resistor R5;

[0008] The sources of PMOS transistors PM5, PM7, and PM8 are all connected to the power supply voltage VDD. The gate and drain of PMOS transistor PM5 are shorted and connected to the source of PMOS transistor PM6. The gates of PMOS transistor PM6 and NMOS transistor NM1 serve as the input terminals of the startup and bias circuit, connected to the reference voltage VREF. The drains of PMOS transistor PM6 and NMOS transistor NM1 are both connected to the gate of NMOS transistor NM2. The drain of NMOS transistor NM2 is connected to the gates of PMOS transistors PM7 and PM8, respectively. The drain of NMOS transistor NM2 is also connected to the drain of PMOS transistor PM8, and this connection serves as the output terminal of the startup and bias circuit. A bias voltage VB1 is applied; the gate and drain of the NMOS transistor NM3 are shorted and connected to the drain of the PMOS transistor PM7; the gate of the NMOS transistor NM3 is also connected to the gate of the NMOS transistor NM4; the gate and drain of the NMOS transistor NM5 are shorted and connected to the source of the NMOS transistor NM3; the gate of the NMOS transistor NM5 is also connected to the gate of the NMOS transistor NM6; the drain of the NMOS transistor NM4 is connected to the drain of the PMOS transistor PM8; the source of the NMOS transistor NM4 is connected to the drain of the NMOS transistor NM6; the source of the NMOS transistor NM6 is connected to one end of the resistor R5; the sources of the NMOS transistors NM1, NM2, and NM5, as well as the other end of the resistor R5, are all grounded.

[0009] Optionally, the bandgap reference core circuit specifically includes: an operational amplifier, a PSRR enhancement circuit, BJT transistors Q1 and Q2, PMOS transistors PM1 and PM2, a resistor R1, and an output stage circuit;

[0010] The sources of PMOS transistors PM1 and PM2 are both connected to the power supply voltage VDD; the gates of PMOS transistors PM1 and PM2 are both connected to the output terminal OUT of the PSRR enhancement circuit; the output terminal OUT of the PSRR enhancement circuit is also connected to the output stage circuit; the output stage circuit serves as the output terminal of the bandgap reference core circuit, generating PTAT voltage, CTAT voltage, and reference voltage VREF; the drain of PMOS transistor PM1 is connected to one end of resistor R1 and the non-inverting input terminal of the operational amplifier; the other end of resistor R1 is connected to the emitter of BJT transistor Q1; the drain of PMOS transistor PM2 is connected to the emitter of BJT transistor Q2 and the inverting input terminal of the operational amplifier; the output terminal of the operational amplifier is connected to the input terminal of the PSRR enhancement circuit; the power supply terminal of the operational amplifier is connected to the output terminal of the bias circuit; the base and collector of BJT transistor Q1 and the base and collector of BJT transistor Q2 are both grounded.

[0011] Optionally, the PSRR enhancement circuit specifically includes: a PMOS transistor PM9 and an NMOS transistor NM7;

[0012] The source of the PMOS transistor PM9 is connected to the power supply voltage VDD; the gate and drain of the PMOS transistor PM9 are shorted and connected to the drain of the NMOS transistor NM7, and the connection point serves as the output terminal OUT of the PSRR enhancement circuit; the gate of the NMOS transistor NM7 serves as the input terminal of the PSRR enhancement circuit and is connected to the output terminal of the operational amplifier.

[0013] Optionally, the output stage circuit specifically includes: PMOS transistor PM3, PMOS transistor PM4, BJT transistor Q3, resistor R2, resistor R3, and resistor R4;

[0014] The sources of PMOS transistors PM3 and PM4 are both connected to the power supply voltage VDD; the gates of PMOS transistors PM3 and PM4, serving as the input terminals of the output stage circuit, are both connected to the output terminal OUT of the PSRR enhancement circuit; the drain of PMOS transistor PM3 is connected to one end of resistor R4 and the emitter of BJT transistor Q3, generating a CTAT voltage at the connection point; the other end of resistor R4 is connected to one end of resistor R3, generating a reference voltage VREF at the connection point; the other end of resistor R3 is connected to the drain of PMOS transistor PM4 and one end of resistor R2, generating a PTAT voltage at the connection point; the collector and base of BJT transistor Q3 and the other end of resistor R2 are all grounded.

[0015] Optionally, the temperature compensation circuit specifically includes: PMOS transistors PM10, PM11, PM12, PM13, PM14, PM15, NMOS transistors NM8, NMOS transistors NM9, NMOS transistors NM10, and resistor R6.

[0016] The sources of PMOS transistors PM10, PM11, PM12, PM13, PM14, and PM15 are all connected to the power supply voltage VDD. The gates of PMOS transistors PM10 and PM11 serve as the input terminals of the temperature compensation circuit and are connected to the output terminal OUT of the PSRR enhancement circuit. The drain of PMOS transistor PM10 is connected to the drain of NMOS transistor NM8 and the gate of NMOS transistor NM10, respectively. The gate and drain of NMOS transistor NM8 are shorted. The drain of PMOS transistor PM11 is connected to the gate of NMOS transistor NM9 and the resistor R6, respectively. One end is connected; the gate and drain of the PMOS transistor PM12 are shorted and connected to the drain of the NMOS transistor NM9; the gate of the PMOS transistor PM12 is connected to the gate of the PMOS transistor PM13; the drain of the PMOS transistor PM13 is connected to the PTAT voltage input terminal as the PTAT voltage; the gate and drain of the PMOS transistor PM14 are shorted and connected to the drain of the NMOS transistor NM10; the gate of the PMOS transistor PM14 is connected to the gate of the PMOS transistor PM15; the drain of the PMOS transistor PM15 is connected to the CTAT voltage input terminal as the CTAT voltage; the source of the NMOS transistor NM8, the other end of the resistor R6, the source of the NMOS transistor NM9, and the source of the NMOS transistor NM10 are all grounded.

[0017] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0018] This invention provides a bandgap reference voltage source circuit with temperature compensation, designed based on a voltage-mode architecture for voltage regulation. Compared to traditional bandgap reference voltage source circuits, it adds a temperature compensation circuit. This bandgap reference voltage source circuit consists of a start-up and bias circuit, a bandgap core circuit, and a temperature compensation circuit, making it a simple and effective way to reduce the temperature drift coefficient. Therefore, the bandgap reference voltage source circuit with temperature compensation provided by this invention can effectively improve the power supply rejection ratio, reduce the temperature drift coefficient, and has the characteristic of adjustable output reference voltage. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a bandgap reference voltage source circuit with temperature compensation provided by the present invention;

[0021] Figure 2 A schematic diagram of the startup and bias circuit provided by the present invention;

[0022] Figure 3 A schematic diagram of the core circuit of the bandgap reference provided by the present invention;

[0023] Figure 4 A schematic diagram of the PSRR enhancement circuit provided by the present invention;

[0024] Figure 5 This is a schematic diagram of the temperature compensation circuit for compensating the output stage circuit provided by the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] The purpose of this invention is to provide a bandgap reference voltage source circuit with a temperature compensation circuit, which can effectively improve the power supply rejection ratio, reduce the temperature drift coefficient, and has the feature of adjustable output reference voltage.

[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] like Figure 1 As shown, this invention discloses a bandgap reference voltage source circuit with a temperature compensation circuit, comprising a startup and bias circuit, a bandgap reference core circuit, and a temperature compensation circuit. The startup and bias circuit includes a startup circuit and a bias circuit. The input terminal of the startup circuit serves as the input terminal of the startup and bias circuit, connected to the reference voltage VREF (i.e., the reference voltage), used to eliminate degeneracy points in the reference voltage VREF. The output terminal of the startup circuit is connected to the input terminal of the bias circuit. The bias circuit outputs a bias voltage. The output terminal of the bias circuit serves as the output terminal of the startup and bias circuit, connected to the input terminal of the bandgap reference core circuit. The bandgap reference core circuit includes an output stage circuit. The output stage circuit serves as the output terminal of the bandgap reference core circuit, generating PTAT voltage, CTAT voltage, and the reference voltage (VREF). The input terminal of the temperature compensation circuit is connected to the output terminal of the bandgap reference core circuit, the PTAT voltage, and the CTAT voltage, respectively, used to perform temperature compensation on the bandgap reference voltage source circuit.

[0029] Specifically, such as Figure 2 As shown, the startup and bias circuit specifically includes: PMOS transistors PM5, PM6, NMOS transistors NM1, NMOS transistors NM2, PM7, PM8, NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, NMOS transistors NM6, and resistor R5.

[0030] The sources of PMOS transistors PM5, PM7, and PM8 are all connected to the power supply voltage VDD. The gate and drain of PMOS transistor PM5 are shorted and connected to the source of PMOS transistor PM6. The gate of PMOS transistor PM6 and the gate of NMOS transistor NM1 serve as the input terminals of the startup and bias circuit, connected to the reference voltage VREF. The drains of PMOS transistor PM6 and NMOS transistor NM1 are both connected to the gate of NMOS transistor NM2. The drain of NMOS transistor NM2 is connected to the gates of PMOS transistors PM7 and PM8, respectively. The drain of NMOS transistor NM2 is also connected to the drain of PMOS transistor PM8, and this connection serves as the output terminal of the startup and bias circuit, outputting the bias voltage VB1. The gate and drain of NMOS transistor NM3 are shorted and connected to the drain of PMOS transistor PM7. The gate of NMOS transistor NM3 is also connected to the gate of NMOS transistor NM4. The gate and drain of NMOS transistor NM5 are shorted and connected to the source of NMOS transistor NM3. The gate of NMOS transistor NM5 is also connected to the gate of NMOS transistor NM6. The drain of NMOS transistor NM4 is connected to the drain of PMOS transistor PM8. The source of NMOS transistor NM4 is connected to the drain of NMOS transistor NM6. The source of NMOS transistor NM6 is connected to one end of resistor R5. The sources of NMOS transistors NM1, NM2, and NM5, as well as the other end of resistor R5, are all grounded.

[0031] like Figure 3 As shown, the core circuit of the bandgap reference specifically includes: an operational amplifier, a PSRR enhancement circuit, BJT transistors Q1 and Q2, PMOS transistors PM1 and PM2, a resistor R1, and an output stage circuit.

[0032] The sources of PMOS transistors PM1 and PM2 are both connected to the power supply voltage VDD. The gates of both PMOS transistors PM1 and PM2 are connected to the output terminal OUT of the PSRR enhancement circuit. The output terminal OUT of the PSRR enhancement circuit is also connected to the output stage circuit. The output stage circuit, as the output terminal of the bandgap reference core circuit, generates PTAT, CTAT, and the reference voltage VREF. The drain of PMOS transistor PM1 is connected to one end of resistor R1 and the non-inverting input terminal of the operational amplifier. The other end of resistor R1 is connected to the emitter of BJT transistor Q1. The drain of PMOS transistor PM2 is connected to the emitter of BJT transistor Q2 and the inverting input terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the input terminal of the PSRR enhancement circuit. The power supply terminal of the operational amplifier is connected to the output terminal of the bias circuit. The base and collector of BJT transistor Q1 and the base and collector of BJT transistor Q2 are both grounded.

[0033] The output stage circuit specifically includes: PMOS transistor PM3, PMOS transistor PM4, BJT transistor Q3, resistor R2, resistor R3, and resistor R4.

[0034] The sources of PMOS transistors PM3 and PM4 are both connected to the power supply voltage VDD. The gates of PMOS transistors PM3 and PM4, serving as inputs to the output stage circuit, are connected to the output terminal OUT of the PSRR enhancement circuit. The drain of PMOS transistor PM3 is connected to one end of resistor R4 and the emitter of BJT transistor Q3, generating a CTAT voltage at the connection. The other end of resistor R4 is connected to one end of resistor R3, generating a reference voltage VREF at the connection. The other end of resistor R3 is connected to the drain of PMOS transistor PM4 and one end of resistor R2, generating a PTAT voltage at the connection. The collector and base of BJT transistor Q3 and the other end of resistor R2 are all grounded.

[0035] Specifically, the gates of PMOS transistors PM3 and PM4, serving as input terminals of the output stage circuit, are both connected to the output terminal OUT of the PSRR enhancement circuit. The gates of PMOS transistors PM1, PM2, PM3, and PM4 are connected to form a current mirror. The drain of PMOS transistor PM3 is connected to one end of resistor R4 and the emitter of BJT transistor Q3, respectively. Figure 3 At point N in the circuit, a CTAT voltage is generated. The other end of resistor R3 is connected to the drain of PMOS transistor PM4 and one end of resistor R2, respectively. The PTAT current flows through resistor R2 at the connection point ( Figure 3 A PTAT voltage is generated at point P in the circuit. The voltages generated at point P and point N are connected and complement each other through resistors R3 and R4, and a reference voltage VREF is generated at the connection point. Furthermore, the number of BJT transistors Q1 and Q2 connected in parallel is not limited to one; the number of BJT transistors Q1 connected in parallel is n times the number of BJT transistors Q2 connected in parallel.

[0036] like Figure 4 As shown, the PSRR enhancement circuit specifically includes a PMOS transistor PM9 and an NMOS transistor NM7.

[0037] The source of PMOS transistor PM9 is connected to the power supply voltage VDD. The gate and drain of PMOS transistor PM9 are shorted and connected to the drain of NMOS transistor NM7. This connection point serves as the output terminal OUT of the PSRR enhancement circuit and is also connected to the output stage of the bandgap reference core circuit. The gate of NMOS transistor NM7 serves as the input terminal of the PSRR enhancement circuit and is connected to the output terminal of the operational amplifier.

[0038] Specifically, such as Figure 3 and Figure 4As shown, the core circuit of the bandgap reference generates PTAT current through BJT transistors Q1 and Q2, resistor R1, and OPA. This current flows through the output stage circuit to generate PTAT and CTAT voltages. The PSRR enhancement circuit can be considered as the third stage of the OPA to increase the gain of the OPA, thereby increasing the PSRR of the bandgap circuit. The PSRR enhancement circuit introduces a 180° phase shift.

[0039] In summary, the core circuit of the bandgap reference operates as follows: a virtual loop is formed through the BJT, resistors, and OPA. The clamping effect of the positive and negative input terminals of the input pair transistors in the OPA generates the PTAT current. The addition of a PSRR enhancement circuit can be considered as a third stage of the OPA to increase gain, thereby enhancing the power supply rejection capability of the bandgap circuit and reducing its dependence on the power supply voltage. The PTAT current is replicated through a current mirror, flowing through the resistor to generate the PTAT voltage. The negative temperature coefficient of the BJT generates the CTAT voltage. The PTAT and CTAT voltages are connected through two resistors to complement each other, outputting the reference voltage VREF at the resistor connection point. Kirchhoff's laws deduce that the reference voltage VREF is adjustable and can achieve a reference voltage less than 1.2V.

[0040] The temperature compensation circuit reduces the temperature coefficient of the bandgap circuit by compensating for the PTAT and CTAT voltages. This part provides a bandgap circuit that is unaffected by process technology, temperature, and power supply voltage, and can provide a stable reference voltage for LDOs, DC-DC switching power supplies, etc.

[0041] like Figure 5 As shown, the temperature compensation circuit specifically includes: PMOS transistors PM10, PM11, PM12, PM13, PM14, PM15, NMOS transistors NM8, NMOS transistors NM9, NMOS transistors NM10, and resistor R6.

[0042] The sources of PMOS transistors PM10, PM11, PM12, PM13, PM14, and PM15 are all connected to the power supply voltage VDD. The gates of PMOS transistors PM10 and PM11 serve as the inputs to the temperature compensation circuit and are connected to the output OUT of the PSRR enhancement circuit. The drain of PMOS transistor PM10 is connected to the drain of NMOS transistor NM8 and the gate of NMOS transistor NM10. The gate and drain of NMOS transistor NM8 are shorted. The drain of PMOS transistor PM11 is connected to the gate of NMOS transistor NM9 and one end of resistor R6. The gate and drain of PMOS transistor PM12 are shorted and connected to the drain of NMOS transistor NM9. The gate of PMOS transistor PM12 is connected to the gate of PMOS transistor PM13. The drain of PMOS transistor PM13 serves as the PTAT voltage input and is connected to the PTAT voltage. The gate and drain of PMOS transistor PM14 are shorted and connected to the drain of NMOS transistor NM10. The gate of PMOS transistor PM14 is connected to the gate of PMOS transistor PM15; the drain of PMOS transistor PM15 serves as the CTAT voltage input terminal, connected to the CTAT voltage. The source of NMOS transistor NM8, the other end of resistor R6, the source of NMOS transistor NM9, and the source of NMOS transistor NM10 are all grounded.

[0043] Specifically, such as Figure 5 As shown, the gates of PMOS transistors PM10 and PM11 are connected to the output terminal OUT of the PSRR enhancement circuit. The gate of PMOS transistor PM13 is connected to the gate of PMOS transistor PM12, and its drain is connected to the PTAT voltage in the output stage circuit. The gate of PMOS transistor PM15 is connected to the gate of PMOS transistor PM14, and its drain is connected to the CTAT voltage in the output stage circuit. This part can compensate for the PTAT and CTAT voltages by adjusting the width-to-length ratio of the diode-connected NMOS transistors NM8, NM9, and NM10, and by adjusting the value of the resistor according to the process voltage temperature (PVT) characteristics of the resistor, thereby reducing the temperature dependence of the reference voltage VREF and reducing the temperature drift coefficient of the bandgap circuit.

[0044] In summary, the temperature compensation circuit operates as follows: by adjusting the width-to-length ratio of the NMOS transistor and adjusting the resistance based on the PVT characteristics of the resistor, the PTAT and CTAT voltages are compensated using the current mirror's current replication feature, thereby reducing the temperature dependence of the reference voltage VREF and lowering the temperature drift coefficient of the bandgap circuit.

[0045] This invention provides a bandgap reference voltage source circuit with temperature compensation, which can ensure the output stability of electrical parameters, thereby solving the problem that the reference voltage VREF is highly dependent on temperature and power supply voltage.

[0046] Traditional bandgap reference circuits, due to their simple structure and low loop gain, result in a fixed output reference voltage that varies significantly with temperature or power supply voltage. This is detrimental to the high stability and accuracy of the output voltage required by the power management system. Compared to traditional bandgap reference circuits, the bandgap reference voltage source circuit with temperature compensation circuitry provided by this invention has the following advantages.

[0047] (1) The bandgap reference voltage source circuit with temperature compensation circuit provided by the present invention is not affected by the power supply voltage. By increasing the gain of the loop through the PSRR enhancement circuit, the PSRR of the bandgap reference voltage source circuit is improved, thereby reducing the change of the output reference voltage with the power supply voltage.

[0048] (2) The bandgap reference voltage source circuit with temperature compensation circuit provided by the present invention is not affected by CMOS process and temperature. By adjusting the temperature compensation circuit, the temperature drift coefficient of the bandgap reference voltage source circuit can be effectively reduced, and the change of the output reference voltage with process angle and temperature can be reduced.

[0049] (3) The reference voltage output by the output stage circuit of the bandgap reference voltage source circuit with temperature compensation circuit provided by the present invention can be derived from Kirchhoff's law. The output reference voltage is adjustable and a reference voltage of less than 1.2V can be obtained.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A bandgap reference voltage source circuit with temperature compensation circuit, characterized by, The application relates to a bandgap reference circuit, which comprises: a start-up and bias circuit, a bandgap reference core circuit and a temperature compensation circuit; an input end of the start-up and bias circuit is connected with a reference voltage VREF; an output end of the start-up and bias circuit outputs a bias voltage; an output end of the start-up and bias circuit is connected with an input end of the bandgap reference core circuit; an output end of the bandgap reference core circuit is used for generating a PTAT voltage, a CTAT voltage and a reference voltage VREF; an output end of the bandgap reference core circuit is connected with an input end of the temperature compensation circuit; the temperature compensation circuit is used for temperature compensation of the bandgap reference voltage source circuit; the output stage circuit specifically comprises a PMOS tube PM3, a PMOS tube PM4, a BJT tube Q3, a resistor R2, a resistor R3 and a resistor R4; a source of the PMOS tube PM3 and a source of the PMOS tube PM4 are both connected with a power supply voltage VDD; a gate of the PMOS tube PM3 and a gate of the PMOS tube PM4 are both connected with an output end OUT of the PSRR enhancement circuit as input ends of the output stage circuit; a drain of the PMOS tube PM3 is connected with one end of the resistor R4 and an emitter of the BJT tube Q3 respectively, and a CTAT voltage is generated at the connection position; the other end of the resistor R4 is connected with one end of the resistor R3, and a reference voltage VREF is generated at the connection position; the other end of the resistor R3 is connected with a drain of the PMOS tube PM4 and one end of the resistor R2 respectively, and a PTAT voltage is generated at the connection position; a collector and a base of the BJT tube Q3 and the other end of the resistor R2 are both grounded; the temperature compensation circuit specifically comprises a PMOS tube PM10, a PMOS tube PM11, a PMOS tube PM12, a PMOS tube PM13, a PMOS tube PM14, a PMOS tube PM15, an NMOS tube NM8, an NMOS tube NM9, an NMOS tube NM10 and a resistor R6; The source of the PMOS tube PM10, the source of the PMOS tube PM11, the source of the PMOS tube PM12, the source of the PMOS tube PM13, the source of the PMOS tube PM14 and the source of the PMOS tube PM15 are all connected to a power supply voltage VDD; the gate of the PMOS tube PM10 and the gate of the PMOS tube PM11 are connected to the output end OUT of the PSRR enhancement circuit as the input end of the temperature compensation circuit; the drain of the PMOS tube PM10 is connected to the drain of the NMOS tube NM8 and the gate of the NMOS tube NM10 respectively; the gate and the drain of the NMOS tube NM8 are short-circuited; the drain of the PMOS tube PM11 is connected to the gate of the NMOS tube NM9 and one end of the resistor R6 respectively; the gate and the drain of the PMOS tube PM12 are short-circuited and connected to the drain of the NMOS tube NM9; the gate of the PMOS tube PM12 is connected to the gate of the PMOS tube PM13; the drain of the PMOS tube PM13 is connected to the PTAT voltage as the PTAT voltage input end; the gate and the drain of the PMOS tube PM14 are short-circuited and connected to the drain of the NMOS tube NM10; the gate of the PMOS tube PM14 is connected to the gate of the PMOS tube PM15; the drain of the PMOS tube PM15 is connected to the CTAT voltage as the CTAT voltage input end; the source of the NMOS tube NM8, the other end of the resistor R6, the source of the NMOS tube NM9 and the source of the NMOS tube NM10 are all grounded.

2. The bandgap reference voltage source circuit with temperature compensation circuit according to claim 1, characterized in that, The starting and biasing circuit specifically comprises a PMOS tube PM5, a PMOS tube PM6, an NMOS tube NM1, an NMOS tube NM2, a PMOS tube PM7, a PMOS tube PM8, an NMOS tube NM3, an NMOS tube NM4, an NMOS tube NM5, an NMOS tube NM6 and a resistor R5. The source of the PMOS tube PM5, the source of the PMOS tube PM7 and the source of the PMOS tube PM8 are all connected with a power supply voltage VDD; the gate and the drain of the PMOS tube PM5 are short-circuited and connected with the source of the PMOS tube PM6; the gate of the PMOS tube PM6 and the gate of the NMOS tube NM1 are connected with a reference voltage VREF as the input end of the starting and biasing circuit; the drain of the PMOS tube PM6 and the drain of the NMOS tube NM1 are both connected with the gate of the NMOS tube NM2; the drain of the NMOS tube NM2 is connected with the gate of the PMOS tube PM7 and the gate of the PMOS tube PM8 respectively; the drain of the NMOS tube NM2 is also connected with the drain of the PMOS tube PM8, and the connection place is the output end of the starting and biasing circuit, outputting a bias voltage VB1; the gate and the drain of the NMOS tube NM3 are short-circuited and connected with the drain of the PMOS tube PM7; the gate of the NMOS tube NM3 is also connected with the gate of the NMOS tube NM4; the gate and the drain of the NMOS tube NM5 are short-circuited and connected with the source of the NMOS tube NM3; the gate of the NMOS tube NM5 is also connected with the gate of the NMOS tube NM6; the drain of the NMOS tube NM4 is connected with the drain of the PMOS tube PM8; the source of the NMOS tube NM4 is connected with the drain of the NMOS tube NM6; the source of the NMOS tube NM6 is connected with one end of the resistor R5; the source of the NMOS tube NM1, the source of the NMOS tube NM2, the source of the NMOS tube NM5 and the other end of the resistor R5 are all grounded.

3. The bandgap reference voltage source circuit with temperature compensation circuit according to claim 2, characterized in that, The band gap reference core circuit specifically comprises: an operational amplifier, a PSRR enhancement circuit, a BJT tube Q1, a BJT tube Q2, a PMOS tube PM1, a PMOS tube PM2, a resistor R1 and an output stage circuit; The source of the PMOS tube PM1 and the source of the PMOS tube PM2 are connected to a power supply voltage VDD; the gate of the PMOS tube PM1 and the gate of the PMOS tube PM2 are connected to the output end OUT of the PSRR enhancement circuit; the output end OUT of the PSRR enhancement circuit is also connected to the output stage circuit; the output stage circuit serves as the output end of the band gap reference core circuit, and generates a PTAT voltage, a CTAT voltage and a reference voltage VREF; the drain of the PMOS tube PM1 is connected to one end of the resistor R1 and the non-inverting input end of the operational amplifier, respectively; the other end of the resistor R1 is connected to the emitter of the BJT tube Q1; the drain of the PMOS tube PM2 is connected to the emitter of the BJT tube Q2 and the inverting input end of the operational amplifier, respectively; the output end of the operational amplifier is connected to the input end of the PSRR enhancement circuit; the power supply end of the operational amplifier is connected to the output end of the bias circuit; the base and collector of the BJT tube Q1 and the base and collector of the BJT tube Q2 are grounded.

4. The bandgap reference voltage source circuit with temperature compensation circuit according to claim 3, characterized in that, The PSRR enhancement circuit specifically comprises a PMOS tube PM9 and an NMOS tube NM7. The source of the PMOS tube PM9 is connected to a power supply voltage VDD; the gate and the drain of the PMOS tube PM9 are short-circuited and connected to the drain of the NMOS tube NM7, and the connection point serves as the output end OUT of the PSRR enhancement circuit; the gate of the NMOS tube NM7 serves as the input end of the PSRR enhancement circuit and is connected to the output end of the operational amplifier, and the source of the NMOS tube NM7 is grounded.

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