Comparator simulation verification method and device, storage medium and computer equipment

Abstract

The embodiment of the application discloses a comparator simulation verification method and device, a storage medium and computer equipment, and relates to the field of device simulation verification. The application creates a test system by using a simulation verification platform, inputs a staircase signal into the comparator in the test system, counts the rising segment flip count value in the rising segment of the staircase signal and the falling segment flip count value in the falling segment of the staircase signal by sampling the output signal of the comparator, then calculates the rising segment offset voltage value according to the rising segment flip count value, calculates the falling segment offset voltage value according to the falling segment flip count value, finally averages the two offset voltage values to obtain the final offset voltage value of the comparator, and the offset voltage value is calculated in a gradually approximating manner, so that the precision and efficiency of offset voltage value measurement can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of device simulation verification, and particularly relates to a simulation verification method and device of a comparator, a storage medium and a computer device. BACKGROUND

[0002] High-precision dynamic comparators are widely used in analog-to-digital converters, data acquisition systems and the like, and have the advantages of high precision and fast response speed. A voltage comparator is configured to rapidly compare the voltage values at the positive and negative input terminals by using the amplification factor of the operational amplifier close to "infinity", so as to realize the output flip of the comparator. However, due to the random errors of the manufacturing process, the threshold voltage and W / L size of the CMOS components are mismatched, so that the input offset voltage exists in the input common-mode voltage range of the operational amplifier. The size of the offset voltage value determines the resolution of the comparator. Therefore, it is particularly important to simulate and verify the offset voltage value of the high-precision comparator, and how to quickly and accurately measure the offset voltage value of the comparator is a problem to be solved. SUMMARY

[0003] The simulation verification method and device of the comparator, the storage medium and the computer device provided by the embodiments of the present application can solve the problems of low precision and low efficiency in measuring the offset voltage value of the comparator in the prior art. The technical solutions are as follows.

[0004] In a first aspect, the embodiments of the present application provide a simulation verification method of a comparator, and the method comprises the following steps.

[0005] Based on the triggering of a first clock signal, a staircase signal is generated, and the staircase signal is input to the positive input terminal of the comparator.

[0006] Based on the triggering of a second clock signal, the output signal of the comparator is sampled in the rising segment of the staircase signal. If the voltage value of the output voltage is greater than a voltage threshold value, the current rising segment flip count value is increased by a preset step value 1 / (2n). If the voltage value of the output voltage is less than or equal to the voltage threshold value, the current rising segment flip count value is cleared. At the end of the rising segment, the current rising segment flip count value is rounded to obtain q1. The frequency of the second clock signal is 2n times the frequency of the first clock signal, and n is an integer greater than 1.

[0007] Based on the triggering of the second clock signal, the output signal of the comparator is sampled in the falling segment of the staircase signal. If the voltage value of the output voltage is greater than the voltage threshold value, the current falling segment flip count value is increased by the preset step value 1 / (2n). If the voltage value of the output voltage is less than or equal to the voltage threshold value, the current falling segment flip count value is kept unchanged and the current falling segment flip count value is stopped updating. At the end of the falling segment, the current falling segment flip count value is rounded to obtain q2.

[0008] The up-ramp offset voltage value and the down-ramp offset voltage value of the comparator are calculated, and a final offset voltage value is obtained by averaging the up-ramp offset voltage value and the down-ramp offset voltage value; wherein VLH=(up_times-q1)×LSB, VHL=(up_times-q2)×LSB, VLH represents the up-ramp offset voltage value, VHL represents the down-ramp offset voltage value, up_times represents half of the number of steps of the staircase signal, and LSB represents the step value of the staircase signal.

[0009] In a second aspect, an embodiment of the present application provides a simulation verification device of a comparator, and the device comprises:

[0010] An input excitation control logic unit is configured to generate a staircase signal based on triggering of a first clock signal, and input the staircase signal to a positive input end of the comparator.

[0011] A resolution counting logic unit is configured to sample an output signal of the comparator in an up-ramp segment of the staircase signal based on triggering of a second clock signal, increase a current up-ramp flip count value by a preset step value 1 / (2n) if a voltage value of an output voltage is greater than a voltage threshold value, clear the current up-ramp flip count value if the voltage value of the output voltage is less than or equal to the voltage threshold value, and obtain q1 by rounding the current up-ramp flip count value at the end of the up-ramp segment; a frequency of the second clock signal is 2n times of a frequency of the first clock signal, and n is an integer greater than 1.

[0012] The resolution counting logic unit is further configured to sample the output signal of the comparator in a down-ramp segment of the staircase signal based on triggering of the second clock signal, increase a current down-ramp flip count value by the preset step value 1 / (2n) if the voltage value of the output voltage is greater than the voltage threshold value, keep the current down-ramp flip count value unchanged and stop updating the current down-ramp flip count value if the voltage value of the output voltage is less than or equal to the voltage threshold value, and obtain q2 by rounding the current down-ramp flip count value at the end of the down-ramp segment.

[0013] The resolution counting logic unit is further configured to calculate an up-ramp offset voltage value and a down-ramp offset voltage value of the comparator, and obtain a final offset voltage value by averaging the up-ramp offset voltage value and the down-ramp offset voltage value; wherein VLH=(up_times-q1)×LSB, VHL=(up_times-q2)×LSB, VLH represents the up-ramp offset voltage value, VHL represents the down-ramp offset voltage value, up_times represents half of the number of steps of the staircase signal, and LSB represents the step value of the staircase signal.

[0014] In a third aspect, an embodiment of the present application provides a computer storage medium, which stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and performing the method steps described above.

[0015] In a fourth aspect, an embodiment of the present application provides a computer device, which can include a processor and a memory, wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and performing the method steps described above.

[0016] The technical scheme provided by some embodiments of the present application has at least the following beneficial effects:

[0017] The staircase signal is input to the comparator, the rising segment flip count value is counted in the rising segment of the staircase signal through sampling of the output signal of the comparator, the falling segment flip count value is counted in the falling segment of the staircase signal, then the rising segment offset voltage value is calculated according to the rising segment flip count value, the falling segment offset voltage value is calculated according to the falling segment flip count value, finally the final offset voltage value of the comparator is obtained by averaging the two offset voltage values, and the offset voltage value is calculated in a gradually approaching manner, so that the precision and efficiency of the offset voltage value measurement can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical schemes in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0019] Figure 1 is a network architecture schematic diagram provided by an embodiment of the present application;

[0020] Figure 2 is a flowchart of a comparator simulation verification method provided by an embodiment of the present application;

[0021] Figure 3 is a prediction principle schematic diagram provided by an embodiment of the present application;

[0022] Figure 4 is a structure schematic diagram of a comparator simulation verification device provided by the present application;

[0023] Figure 5 is a structure schematic diagram of a computer device provided by the present application. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

[0025] It should be noted that the simulation verification method of the comparator provided in the present application is generally executed by a computer device, and accordingly, the simulation verification device of the comparator is generally set in the computer device.

[0026] Figure 1 An exemplary system architecture that can be applied to the simulation verification method of a comparator or the simulation verification device of a comparator of the present application is shown.

[0027] like Figure 1 As shown, the test system includes: an input excitation control logic unit 20, a comparator 21, a constant voltage source 22, a resolution counting logic unit 23 and a clock circuit ( Figure 1 not shown).

[0028] In the present application, during the design phase of the comparator 21, that is, before the comparator 21 is manufactured, a computer device uses a Verilog-A platform to create a test system, and then uses the test system to simulate and verify the offset voltage of the comparator 21. The Verilog-A platform can be Cadence Virtuoso, which provides powerful circuit design and simulation tools that support designers in creating various types of analog circuits, digital circuits, and mixed-signal circuits. The computer device is provided with an analog simulator that can be used to verify the performance, stability, and functionality of the circuit.

[0029] The clock circuit is connected with the clock end of the input excitation control logic unit 20 and the resolution counting logic unit 23 respectively, the clock circuit inputs the first clock signal CLK to the input excitation logic control unit 20, and inputs the second clock signal CLK_2 to the resolution counting logic unit 23. The output end of the input recording control logic unit 20 is connected with the positive input end of the comparator 21, the negative input end of the comparator 21 is connected with the constant voltage source 22, and the output end of the comparator 21 is connected with the input end of the resolution counting logic unit 23. The frequency of the first clock signal is f1, the frequency of the second clock signal is f2, f2=2*n*f1, n is an integer greater than 1. The input excitation control logic unit 20 is used for inputting the excitation signal to the positive input end of the comparator, the excitation signal of the application is a staircase signal, the time period of the staircase signal is divided into a rising section and a falling section, the time of the rising section and the falling section is the same, in the rising section, under the trigger (for example: rising edge trigger or falling edge trigger) of the first clock signal, the amplitude starts from 0 and increases to the maximum value according to a certain step value LSB; in the falling section, under the trigger of the first clock signal, the amplitude starts from the maximum value and decreases to 0 according to the step value LSB, the step value can be determined according to actual needs, for example: the step value can be 1uV or 1mV. The constant voltage source 22 is used for inputting the reference voltage signal to the comparator 21, the voltage value of the reference voltage signal is close to the maximum value of the staircase signal, for example: the amplitude of the staircase signal is equal to 8mV, the voltage value of the reference voltage signal is equal to 8.192mV. The resolution counting logic unit 23 samples and counts the output signal of the comparator 21, and calculates the offset voltage value of the comparator 21 according to the counting result.

[0030] In some embodiments of the application, the input excitation control logic unit includes a signal generator, an analog-to-digital converter ADC and a digital-to-analog converter DAC, the signal generator generates a triangular wave signal, the analog-to-digital converter converts the triangular wave signal into a digital signal, and then the digital-to-analog converter converts the digital signal into an analog form of a staircase signal.

[0031] In some embodiments of the application, the performance parameters of the analog-to-digital converter and the digital converter can be adjusted according to actual needs.

[0032] For example, assuming that the precision of the comparator is about 100uV under typical value, and the precision of the estimated mismatch of the Monte Carlo simulation process is about 8mV, the performance parameters of the input excitation, the ADC and the DAC written by Verilog_A are adjusted to make the step value of the output staircase signal 1uV and the full scale 8mV. Under the above conditions, a 13-bit ADC and a 13-bit DAC can be selected, and the voltage value of the reference voltage signal is set to 8.192mV to realize the 1uV step value. The frequency of the first clock signal CLK input to the ADC is in the frequency range of the comparator, and the frequency of the staircase signal is consistent with the frequency of the first clock signal CLK. The frequency and amplitude of the corresponding triangular wave input excitation are given according to the frequency of the first clock signal CLK and the amplitude of the staircase signal to be climbed.

[0033] The method for measuring the offset voltage value in the application has the following advantages.

[0034] Brief and efficient: ①No need to manually set the input of the staircase signal, only need to set the amplitude and frequency of the input triangular wave signal according to the precision range, and extend the excitation time of the triangular wave signal, so that multiple groups of data can be automatically measured and the average value can be selected, without the need for manual multiple repeated measurements. ②Since the comparator output flip is used as the basis for judgment, and when the comparator input difference is close to the offset voltage value, the comparator is in a metastable state, and the output will flip back and forth, which cannot be calculated and output by the comparator resolution result through simple capture syntax or measurement statements. When the simulation task amount increases, such as PVT and Monte Carlo simulation, it is too time-consuming and laborious to manually check the simulation waveform one by one, calculate and record the comparator resolution data. The application can automatically sample, judge, count and output the results according to the output waveform, and the output data can be directly observed during the multi-task simulation such as Monte Carlo simulation, so that the influence of process mismatch on the comparator offset voltage can be clearly and intuitively observed.

[0035] Flexible and adjustable precision: the precision, reference voltage value and resolution of the ADC and DAC can be selected according to the precision range; for example, the resolution of the output staircase wave is set to 1uV, 1mV, etc.

[0036] It should be understood that Figure 1 The number of components or units in the application is only illustrative. Any number of components or units can be used according to the implementation needs.

[0037] The application will be described in detail below with reference to the accompanying drawings. Figure 2 The simulation verification method of the comparator provided by the embodiment of the application will be described in detail. The simulation verification device of the comparator in the embodiment of the application can be the computer device shown in Figure 1 .

[0038] Please refer to Figure 2A flowchart of a simulation verification method of a comparator is provided for the embodiments of the present application. As shown in Figure 2 the method of the embodiments of the present application can include the following steps:

[0039] S201, based on the trigger of the first clock signal, a staircase signal is generated, and the staircase signal is input to the positive input terminal of the comparator.

[0040] The staircase signal can be triggered by the falling edge of the first clock signal. Each time a falling edge of the first clock signal is detected, the input excitation control logic unit generates a step of the staircase signal. The staircase signal here represents a signal within a period, and the staircase signal is composed of a rising segment and a falling segment. The duration of the rising segment and the falling segment is the same. The number of steps of the staircase signal in a period is represented as times. Then the number of steps of the rising segment and the falling segment is represented as up_times = times / 2.

[0041] S202, based on the trigger of the second clock signal, the resolution counting logic unit samples the voltage value of the output signal of the comparator within the rising segment of the staircase signal. If the voltage value of the output voltage is greater than the voltage threshold value, the current rising segment flip count value is increased by a preset step value 1 / (2n). If the voltage value of the output voltage is less than or equal to the voltage threshold value, the current rising segment flip count value is cleared. At the end of the rising segment, the current rising segment flip count value is obtained after rounding to obtain q1.

[0042] The resolution counting logic unit can be triggered by the falling edge of the second clock signal, that is, each time a falling edge of the second clock signal is detected, the resolution counting logic unit performs a sampling action on the output terminal of the comparator. The frequency f2 of the second clock signal = 2n x f1, n is an integer greater than 1, that is, the frequency of the second clock signal can be 2 times, 4 times or 8 times the frequency of the first clock signal, etc. Within a period of the staircase signal, the rising segment is experienced first, and then the falling segment is experienced. In the rising segment, the voltage difference between the two input terminals (the positive input terminal and the negative input terminal) of the comparator gradually approaches the offset voltage value. When approaching the offset voltage value, the comparator is in a metastable state, and the output signal of the comparator flips between 0 and 1. If the steps of the staircase signal continue to increase, the voltage difference between the two input terminals of the comparator is greater than the offset voltage value, and the output signal of the comparator will be stable as a high level signal.

[0043] Referring to Figure 3The timing diagram shows that the second clock signal is represented as CLK_2, and the frequency of the second clock signal is twice the frequency of the first clock signal, i.e., n = 2. The output signal of the comparator is represented as CAMOUT, and the staircase signal is represented as CMPVINN. The counting method of the resolution counting logic unit is as follows: in the rising segment, when the voltage value of the output signal is greater than the voltage threshold value, the current rising segment flip count value count_vlh1 is increased by a preset step value 0.5; when the voltage value of the output signal is less than or equal to the voltage threshold value, the current rising segment flip count value count_vlh1 is cleared. When the end of the rising segment is detected, the current rising segment flip count value is rounded to obtain q1, and the rounding can be upward rounding or downward rounding.

[0044] S203, based on the triggering of the second clock signal, sampling the output signal of the comparator in the falling segment of the staircase signal, if the voltage value of the output voltage is greater than the voltage threshold value, the current falling segment flip count value is increased by a preset step value 1 / (2n); if the voltage value of the output voltage is less than or equal to the voltage threshold value, the current falling segment flip count value is kept unchanged and the updating of the current falling segment flip count value is stopped; at the end of the falling segment, the current falling segment flip count value is rounded to obtain q2.

[0045] In the falling segment, the voltage difference between the two input terminals of the comparator is greater than the offset voltage value at the beginning, and the output voltage starts to stabilize at a high level. As the number of steps increases, the voltage difference between the two input terminals of the comparator gradually approaches the offset voltage value, the comparator enters a metastable state, and the output voltage flips between 0 and 1.

[0046] Referring to Figure 3 The timing diagram shows that according to the example of S202, the counting method of the resolution counting logic unit is as follows: in the falling segment, if the voltage value of the output voltage is greater than the voltage threshold value, the current falling segment flip count value count_vlh1 is increased by a preset step value 0.5; if the voltage value of the output voltage is less than or equal to the voltage threshold value, the current falling segment flip count value count_vlh1 is kept unchanged, and the updating of the current falling segment flip count value is stopped. When the end of the falling segment is detected, the current falling segment flip count value is rounded to obtain q2, and the rounding can be upward rounding or downward rounding.

[0047] S204, calculating the rising segment offset voltage value and the falling segment offset voltage value of the comparator, and averaging the rising segment offset voltage value and the falling segment offset voltage value to obtain the final offset voltage value.

[0048] Wherein, the uplink segment offset voltage value VLH=(up_times-q1)×LSB is calculated according to the formula, and the downlink segment offset voltage value VHL=(up_times-q2)×LSB is calculated according to the formula, wherein up_times represents half of the number of steps of the staircase wave signal, and LSB represents the step value of the staircase wave signal. Then, the final offset voltage value is obtained by averaging the uplink segment offset voltage value and the downlink segment offset voltage value.

[0049] In some embodiments of the present application, in order to improve the calculation accuracy of the offset voltage value, a plurality of offset voltage values can be calculated by using a plurality of periods of the staircase wave signal according to the method of the present application, and then the final offset voltage value is obtained by averaging the plurality of offset voltage values.

[0050] The comparator resolution can be simply and quickly simulated, verified and compared by the present application, and the automatic verification under the multi-task simulation scenarios such as PVT and Monte Carlo is met. The result after calculation is presented in the form of data. The influence of different corner conditions on the comparator resolution under PVT can be directly and intuitively known. Through Monte Carlo simulation, the data result is presented in the form of a histogram, and the distribution of the comparator resolution result size corresponding to the number under the process mismatch condition can be directly and intuitively known, such as the normal distribution.

[0051] In addition, the method of the present application can effectively simulate and verify the equivalent input offset voltage of the high-precision dynamic comparator under high-speed working conditions. The simulation circuit of the present application includes an input excitation control logic unit and a resolution counting logic unit, both of which are written by Verilog_A and are ideal models. The configuration parameters of the input excitation control logic can be quickly and conveniently modified according to the actual situation, the requirements for the simulation system are relatively low, the simulation time is greatly reduced, and the hardware such as servers will not bring excessive load. The simulation circuit of the present application can be widely applied to various integrated circuit design platforms such as Cadence, Hspice and Pspice. The result data of the comparator resolution size can be automatically obtained efficiently and simply, which is suitable for multi-task simulation scenarios including PVT and Monte Carlo, and the distribution of the result can be directly and intuitively known.

[0052] The following is an apparatus embodiment of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the apparatus embodiments of the present application, please refer to the method embodiments of the present application.

[0053] Please refer to Figure 4Fig. 4 shows a schematic diagram of a simulation verification device of a comparator according to an example embodiment of the present application, hereinafter referred to as device 4. The device 4 can be implemented in software, hardware, or a combination thereof, as all or part of a computer device. The device 4 comprises a clock terminal of an input stimulus control logic unit 401 and a resolution counting logic unit 402.

[0054] The input stimulus control logic unit 401 is configured to generate a staircase signal based on a trigger of a first clock signal, and input the staircase signal to a positive input terminal of the comparator.

[0055] The resolution counting logic unit 402 is configured to sample an output signal of the comparator in a rising segment of the staircase signal based on a trigger of a second clock signal, and increase a current rising segment flip count value by a preset step value 1 / (2n) if a voltage value of the output voltage is greater than a voltage threshold value, or clear the current rising segment flip count value if the voltage value of the output voltage is less than or equal to the voltage threshold value. The current rising segment flip count value is rounded to obtain q1 at the end of the rising segment. The frequency of the second clock signal is 2n times the frequency of the first clock signal, and n is an integer greater than 1.

[0056] The resolution counting logic unit 402 is further configured to sample the output signal of the comparator in a falling segment of the staircase signal based on the trigger of the second clock signal, and increase a current falling segment flip count value by the preset step value 1 / (2n) if the voltage value of the output voltage is greater than the voltage threshold value, or keep the current falling segment flip count value unchanged and stop updating the current falling segment flip count value if the voltage value of the output voltage is less than or equal to the voltage threshold value. The current falling segment flip count value is rounded to obtain q2 at the end of the falling segment.

[0057] The resolution counting logic unit 402 is further configured to calculate an up segment offset voltage value and a down segment offset voltage value of the comparator, and average the up segment offset voltage value and the down segment offset voltage value to obtain a final offset voltage value. Wherein, VLH=(up_times-q1)×LSB, VHL=(up_times-q2)×LSB, VLH represents the up segment offset voltage value, VHL represents the down segment offset voltage value, up_times represents half of the number of steps of the staircase signal, and LSB represents the step value of the staircase signal.

[0058] In one or more possible embodiments, the frequency of the second clock signal is equal to twice the frequency of the first clock signal.

[0059] In one or more possible embodiments, the plurality of offset voltage values are calculated according to a plurality of staircase signals of a plurality of periods, and the final offset voltage value of the comparator is obtained by averaging the plurality of offset voltage values.

[0060] In one or more possible embodiments, the generating the staircase signal comprises:

[0061] The input triangular wave signal is converted into a digital signal by an analog-to-digital conversion, and the digital signal is converted into the staircase signal by a digital-to-analog conversion.

[0062] In one or more possible embodiments, the voltage threshold is equal to half of the high-level signal voltage value.

[0063] It should be noted that the apparatus 4 provided in the above embodiments is only used for illustrating the division of the functional modules in the simulation verification method of the comparator, and in actual applications, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above functions. In addition, the simulation verification apparatus of the comparator and the simulation verification method of the comparator provided in the above embodiments belong to the same concept, and the implementation process is detailed in the method embodiments, which will not be repeated here.

[0064] The serial numbers of the above embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0065] The embodiments of the present application also provide a computer storage medium, which can store a plurality of instructions, the instructions being suitable for being loaded and executed by a processor to implement the method steps of the method of the embodiments as shown above. The specific implementation process can be referred to the specific description of the embodiments as shown above, which will not be repeated here. Figure 2 Figure 2 The embodiments of the present application also provide a computer storage medium, which can store a plurality of instructions, the instructions being suitable for being loaded and executed by a processor to implement the method steps of the method of the embodiments as shown above. The specific implementation process can be referred to the specific description of the embodiments as shown above, which will not be repeated here.

[0066] The present application also provides a computer program product, which stores at least one instruction, the at least one instruction being loaded and executed by the processor to implement the simulation verification method of the comparator as described in each of the above embodiments.

[0067] Please refer to Figure 5 , which provides a structural schematic diagram of a computer device for the embodiments of the present application. As shown in Figure 5 , the computer device 500 can include at least one processor 501, at least one output interface 504, an input interface 503, a memory 505, and at least one communication bus 502.

[0068] The communication bus 502 is used to realize the connection and communication between the components.

[0069] ​The input interface 503 can include a display, a camera, and can further include a standard wired interface and a wireless interface.

[0070] The output interface 504 can include a standard wired interface and a wireless interface (e.g., a WI-FI interface).

[0071] The processor 501 can include one or more processing cores. The processor 501 connects various parts of the computer device 500 through various interfaces and lines, and performs various functions and processes data of the computer device 500 by running or executing instructions, programs, code sets or instruction sets stored in the memory 505, and calling data stored in the memory 505. Optionally, the processor 501 can be implemented in at least one of a digital signal processing (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 501 can be integrated with a combination of one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU is mainly used to process an operating system, a user interface, and an application program. The GPU is used to render and draw content to be displayed on the display. The modem is used to process wireless communication. It can be understood that the modem can also not be integrated into the processor 501, but can be implemented by a separate chip.

[0072] The memory 505 can include a random access memory (RAM) and a read-only memory (ROM). Optionally, the memory 505 includes a non-transitory computer-readable storage medium. The memory 505 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 505 can include a program storage area and a data storage area. The program storage area can store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-mentioned various method embodiments, etc. The data storage area can store data related to the above-mentioned various method embodiments, etc. The memory 505 can further include at least one storage device located away from the processor 501. For example, the memory 505 can include a hard disk (HD).Figure 5 As shown, the memory 505 as a computer storage medium may include an operating system, a network communication module, a user interface module, and an application program.

[0073] exist Figure 5 In the computer device 500 shown in FIG. 1 , the input interface 503 is mainly used to provide an input interface for the user and obtain the data input by the user; and the processor 501 can be used to call the application stored in the memory 505 and specifically execute the following operations: Figure 2 The specific process can be referred to the method shown in Figure 2 As shown, no further details are given here.

[0074] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory, or a random access memory.

[0075] The above disclosure is only a preferred embodiment of the present application, and certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A simulation verification method for a comparator, characterized in that: include: Based on the triggering of the first clock signal, a step wave signal is generated, and the step wave signal is input to the positive input terminal of the comparator; Based on the triggering of the second clock signal, the output signal of the comparator is sampled in the rising segment of the step wave signal. If the voltage value of the output voltage is greater than the voltage threshold, the current rising segment flip count value is increased by a preset step value 1 / (2n); if the voltage value of the output voltage is less than or equal to the voltage threshold, the current rising segment flip count value is cleared; at the end of the rising segment, the current rising segment flip count value is rounded to obtain q1; The frequency of the second clock signal is 2n times the frequency of the first clock signal, where n is an integer greater than or equal to 1; Based on the triggering of the second clock signal, the output signal of the comparator is sampled in the falling segment of the step wave signal. If the voltage value of the output voltage is greater than the voltage threshold, the current falling segment flip count value is increased by a preset step value 1 / (2n); if the voltage value of the output voltage is less than or equal to the voltage threshold, the current falling segment flip count value is maintained unchanged and the updating of the current falling segment flip count value is stopped; at the end of the falling segment, the current falling segment flip count value is rounded to obtain q2; Calculate the rising and falling offset voltage values ​​of the comparator, and average the rising and falling offset voltage values ​​to obtain the final offset voltage value; where VLH = (up_times - q1) × LSB, VHL = (up_times - q2) × LSB, VLH represents the rising offset voltage value, VHL represents the falling offset voltage value, up_times represents half the number of steps of the step wave signal, and LSB represents the step value of the step wave signal.

2. The method according to claim 1, characterized in that A plurality of offset voltage values ​​are calculated based on the step wave signals of a plurality of cycles, and a final offset voltage value of the comparator is obtained by averaging the plurality of offset voltage values.

3. The method according to claim 1, characterized in that Generating a step wave signal includes: The input triangle wave signal is converted into a digital signal by analog-to-digital conversion, and the digital signal is converted into a step wave signal by digital-to-analog conversion.

4. The method according to claim 1, wherein The voltage threshold is equal to half of the voltage value of the high-level signal.

5. A simulation verification device for a comparator, characterized in that: include: An input excitation control logic unit, configured to generate a step wave signal based on the triggering of the first clock signal, and input the step wave signal to the positive input terminal of the comparator; a resolution counting logic unit, configured to sample the output signal of the comparator during a rising segment of the step wave signal based on a trigger of a second clock signal; if the voltage value of the output voltage is greater than a voltage threshold, increase the current rising segment flip count value by a preset step value 1 / (2n); if the voltage value of the output voltage is less than or equal to the voltage threshold, clear the current rising segment flip count value; and at the end of the rising segment, round the current rising segment flip count value to obtain q1; the frequency of the second clock signal is 2n times the frequency of the first clock signal, where n is an integer greater than or equal to 1; The resolution counting logic unit is further configured to sample the output signal of the comparator during a falling segment of the step wave signal based on a trigger of the second clock signal; if the voltage value of the output voltage is greater than a voltage threshold, increase the current falling segment flip count value by a preset step value 1 / (2n); if the voltage value of the output voltage is less than or equal to the voltage threshold, maintain the current falling segment flip count value unchanged and stop updating the current falling segment flip count value; and at the end of the falling segment, round the current falling segment flip count value to obtain q2; The resolution counting logic unit is further used to calculate the rising segment offset voltage value and the falling segment offset voltage value of the comparator, and to average the rising segment offset voltage value and the falling segment offset voltage value to obtain a final offset voltage value; wherein, VLH=(up_times-q1)×LSB, VHL=(up_times-q2)×LSB, VLH represents the rising segment offset voltage value, VHL represents the falling segment offset voltage value, up_times represents half the number of steps of the step wave signal, and LSB represents the step value of the step wave signal.

6. A computer storage medium, characterized in that The computer storage medium stores a plurality of instructions, which are suitable for being loaded by a processor and executing the method steps according to any one of claims 1 to 4.

7. A computer device, characterized in that: include: A processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the method steps according to any one of claims 1 to 4.

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