Active clamp flyback circuit control device, control method and clamp flyback circuit

Abstract

This invention provides an active clamp flyback circuit control device, control method, and clamp flyback circuit. The device, applied to an active clamp flyback circuit, includes: a transformer, a flyback switch, a clamping switch, and a clamping capacitor; the primary side of the transformer is connected in series with the flyback switch between the positive and negative terminals of a power supply; the clamping switch and clamping capacitor are connected in series and then in parallel with the flyback switch; the device includes: a drive signal generation module and a main control module; the input terminal of the drive signal generation module receives a control signal sent by the main control module, the first output terminal outputs a first duty cycle signal controlling the flyback switch, and the second output terminal outputs a second duty cycle signal controlling the clamping switch; the clamping switch and the flyback switch do not conduct simultaneously and are not complementary in conduction. In this invention, the clamping switch and the flyback switch do not conduct complementaryly, reducing the conduction time of the clamping switch, significantly reducing the clamping switch loss, and correspondingly reducing the current stress on the secondary side.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and more particularly to an active clamp flyback circuit control device, control method, and clamp flyback circuit. Background Technology

[0002] Active clamp flyback circuits are widely used in small and medium power switching power supplies due to their low cost and simple topology. They typically consist of a main power transistor, a clamping switch transistor, a transformer, and a clamping capacitor.

[0003] In existing technology, the flyback switch and the clamping switch conduct in a complementary manner. When the flyback switch is turned off, the clamping switch is turned on, and the leakage inductance energy charges the clamping capacitor through the clamping switch, then participates in resonance, transferring energy to the secondary side. However, in this process, the operating current of the clamping switch is relatively large, resulting in high losses and correspondingly high current stress on the transformer secondary side. Summary of the Invention

[0004] This invention provides an active clamp flyback circuit control device, control method, and clamp flyback circuit to solve the problems of high operating current and high loss of clamping switching transistors and high stress on the secondary current of transformers in the prior art.

[0005] In a first aspect, embodiments of the present invention provide an active clamp flyback circuit control device, applied to an active clamp flyback circuit; the active clamp flyback circuit includes: a transformer, a flyback switch, a clamping switch, and a clamping capacitor; the primary side of the transformer and the flyback switch are connected in series between the positive and negative terminals of the power supply, and the clamping switch and the clamping capacitor are connected in series and then in parallel with the flyback switch.

[0006] The aforementioned device includes: a drive signal generation module and a main control module;

[0007] The input terminal of the drive signal generation module is used to receive control signals sent by the main control module; the first output terminal of the drive signal generation module outputs a first duty cycle signal for controlling the flyback switch, and the second output terminal of the drive signal generation module outputs a second duty cycle signal for controlling the clamping switch.

[0008] In this configuration, the clamping switch and the flyback switch do not conduct simultaneously and are not complementary.

[0009] Secondly, embodiments of the present invention provide an active clamp flyback circuit control method, applied to an active clamp flyback circuit; the active clamp flyback circuit includes: a transformer, a flyback switch, a clamping switch, and a clamping capacitor; the primary side of the transformer and the flyback switch are connected in series between the positive and negative terminals of the power supply, and the clamping switch and the clamping capacitor are connected in series and then in parallel with the flyback switch.

[0010] The above methods include:

[0011] The control clamping switch transistor is turned on according to the first preset duty cycle;

[0012] The flyback switch is controlled to conduct according to the second preset duty cycle;

[0013] In this configuration, the clamping switch and the flyback switch do not conduct simultaneously and are not complementary.

[0014] Thirdly, embodiments of the present invention provide an active clamp flyback circuit, including: a transformer, a flyback switch, a clamping switch, a clamping capacitor, and a control terminal; the primary side of the transformer and the flyback switch are connected in series between the positive and negative terminals of the power supply, and the clamping switch and the clamping capacitor are connected in series and then in parallel with the flyback switch; the control terminal is connected to the control terminal of the clamping switch and the control terminal of the flyback switch respectively.

[0015] The control terminal executes the steps of the active clamp flyback circuit control method provided in the second aspect of the present invention to control the flyback switch and the clamp switch.

[0016] This invention provides an active clamp flyback circuit control device, control method, and clamp flyback circuit. The active clamp flyback circuit control device is applied to an active clamp flyback circuit. The active clamp flyback circuit includes: a transformer, a flyback switch, a clamping switch, and a clamping capacitor. The primary winding of the transformer is connected in series with the flyback switch between the positive and negative terminals of the power supply. The clamping switch and clamping capacitor are connected in series and then in parallel with the flyback switch. The device includes: a drive signal generation module and a main control module.

[0017] The input terminal of the drive signal generation module is used to receive control signals sent by the main control module; the first output terminal of the drive signal generation module outputs a first duty cycle signal for controlling the flyback switch, and the second output terminal of the drive signal generation module outputs a second duty cycle signal for controlling the clamping switch; wherein, the clamping switch and the flyback switch do not conduct simultaneously and are not complementary in conduction. In this embodiment of the invention, the clamping switch and the flyback switch do not conduct complementaryly, that is, during the time the flyback switch is turned off in each cycle, the clamping switch is only turned on for a short period of time, shortening the conduction time of the clamping switch in each cycle. Without affecting the normal power transfer of the clamping flyback circuit, the conduction current of the clamping switch is reduced, the circuit loss is reduced, and the current stress on the secondary side of the transformer is further reduced. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a circuit schematic diagram of an active clamp flyback circuit in the prior art;

[0020] Figure 2 These are waveform diagrams of various points in an active clamp flyback circuit in the prior art;

[0021] Figure 3 The waveform diagrams are shown at various points in the active clamp flyback circuit after being controlled by the active clamp flyback circuit control device in the embodiment of the present invention.

[0022] Figure 4 This is a schematic diagram of the waveform of capacitor-inductor resonance;

[0023] Figure 5 This is a schematic diagram of the structure of a drive signal generation module provided in an embodiment of the present invention;

[0024] Figure 6 This is a circuit schematic diagram of a drive signal generation module provided in an embodiment of the present invention;

[0025] Figure 7 yes Figure 6 The diagram shows the waveforms at various points in the drive signal generation module.

[0026] Figure 8 This is a circuit schematic diagram of another driving signal generation module provided in an embodiment of the present invention;

[0027] Figure 9 yes Figure 8 The diagram shows the waveforms at various points in the drive signal generation module.

[0028] Figure 10 This is a flowchart illustrating the implementation of an active clamp flyback circuit control according to an embodiment of the present invention.

[0029] Figure 11 This is a schematic diagram of the structure of an active clamp flyback circuit control system provided in an embodiment of the present invention;

[0030] Figure 12 This is a schematic diagram of the control terminal provided in an embodiment of the present invention;

[0031] Figure 13 This is a schematic diagram of an active clamp flyback circuit provided in an embodiment of the present invention. Detailed Implementation

[0032] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0034] Figure 1 A circuit diagram of an active clamp flyback circuit is shown. The circuit includes: a transformer T, a flyback switch Q1, a clamping switch Q2, and a clamping capacitor C1. The primary winding of the transformer T is connected in series with the flyback switch Q1 between the positive and negative terminals of the power supply. The clamping switch Q2 and the clamping capacitor C1 are connected in series and then in parallel with the flyback switch Q1. The active clamp flyback circuit may also include other components, which will not be detailed here; please refer to relevant documentation for details. Figure 1 Its working principle is based on existing technology and will not be elaborated here.

[0035] In the prior art, the flyback switch Q1 and the clamping switch Q2 conduct complementaryly. When the clamping switch Q2 is on, the clamping capacitor C1 resonates with the leakage inductance of the transformer T. For ease of control, the conduction time of the clamping switch Q2 should be less than the resonant period of the clamping capacitor C1 and the leakage inductance of the transformer T.

[0036] If the conduction time of clamping switch Q2 is greater than the resonant period, multiple resonances may occur when clamping switch Q2 is turned on, making the timing of clamping switch Q2's turn-off uncontrollable. Therefore, if the conduction time of clamping switch Q2 is less than the resonant period, only one resonance will occur when clamping switch Q2 is turned on, resulting in a smaller turn-off current. (See reference [link to relevant documentation] for details.) Figure 2 .

[0037] Depend on Figure 2 It can be seen that during the time that clamping switch Q2 is turned on, the current Icc flowing through clamping switch Q2 is relatively large, and the current ISR1 of the MOSFET on the secondary side of transformer T is also relatively large. Meanwhile, due to... Figure 2 It can also be seen that when the flyback switch Q1 is turned on, the current flowing through the flyback switch Q1 is greater than 0, so ZVS cannot be achieved.

[0038] To address the aforementioned problems, embodiments of the present invention provide an active clamp flyback circuit control device, applied to... Figure 1The active clamp flyback circuit shown includes: transformer T, flyback switch Q1, clamp switch Q2 and clamp capacitor C1; the primary side of transformer T is connected in series with flyback switch Q1 between the positive and negative terminals of the power supply, and clamp switch Q2 and clamp capacitor C1 are connected in series and then in parallel with flyback switch Q1.

[0039] The aforementioned device includes: a drive signal generation module and a main control module;

[0040] The input terminal of the drive signal generation module is used to receive the control signal PWM_0 sent by the main control module; the first output terminal of the drive signal generation module outputs the first duty cycle signal PWM_Q1 used to control the flyback switch Q1, and the second output terminal of the drive signal generation module outputs the second duty cycle signal PWM_Q2 used to control the clamping switch Q2.

[0041] Among them, the clamping switch Q2 and the flyback switch Q1 are not turned on at the same time, and their conduction is not complementary.

[0042] In this embodiment of the invention, the clamping switch Q2 and the flyback switch Q1 are not complementary in conduction; that is, when the flyback switch Q1 is turned off within a switching cycle, the clamping switch Q2 is only turned on for a portion of the time. For example, refer to... Figure 3 The clamping switch Q2 is only turned on for a short time. Without affecting the normal operation of the active clamping flyback circuit, the operating current and turn-off current of the clamping switch Q2 are greatly reduced, the operating loss of the clamping switch Q2 is reduced, and the current stress on the secondary side of the transformer T is further reduced.

[0043] Furthermore, since the conduction time of the clamping switch Q2 is reduced, the resonant period can also be smaller accordingly. With the leakage inductance of transformer T remaining unchanged, the clamping capacitor C1 can be selected with a smaller capacitance, reducing the size and cost of the circuit.

[0044] It should be noted that the control signal PWM_0 is calculated by the main control module based on the output parameters of the active clamp flyback circuit and the control loop. These output parameters include output current, output voltage, and output power.

[0045] In one possible implementation, the clamping switch Q2 is turned on for a first preset time after the flyback switch Q1 is turned off.

[0046] The first preset duration is not less than And the conduction time of clamping switch Q2 is less than

[0047] Where D is the duty cycle of the first duty cycle signal PWM_Q1, and T1 is the period of the first duty cycle signal PWM_Q1.

[0048] refer to Figure 3 After the flyback switch Q1 is turned off, Ip equals Icc + Ilm. When the clamping switch Q2 is turned on, the clamping capacitor C1 discharges to form Icc, and Ilm, combined with Icc, creates a small spike. Therefore, when the conduction time of the clamping switch Q2 remains constant, as Ilm gradually decreases, the later the clamping switch Q2 is turned on after the flyback switch Q1 is turned off, the smaller the superimposed Ilm becomes, and the smaller Ip and ISR1 become.

[0049] In this embodiment of the invention, by Figure 3 It can be seen that in the latter half of the turn-off time of the flyback switch Q1, Ip and ISR1 are smaller, and the peak current formed by the discharge of the clamping capacitor C1 is smaller than that in the first half. The current stress of the MOSFET on the secondary side of the transformer T is smaller, and the requirements for the device are lower.

[0050] More specifically, clamping switch Q2 can be turned on before flyback switch Q1 is turned on, with a dead time interval between them. That is, after clamping switch Q2 is turned off and a dead time delay occurs, flyback switch Q1 is turned on. See [link / reference] for details. Figure 3 .

[0051] In one possible implementation, the on-time of the clamping switch Q2 is less than... T2 is the period of resonance between the clamping capacitor C1 and the leakage inductance of the transformer T.

[0052] refer to Figure 3 After the flyback switch Q1 is turned off, the clamping switch Q2 is also turned off. The leakage inductance energy of the transformer T charges the clamping capacitor C1 through the clamping switch Q2. At this time, the energy transfer method is the same as that of a traditional active clamp flyback circuit. The current Icc flowing through the clamping switch Q2 shows a small spike pulse, and the duration is very short. When the energy transfer is about to end, before the flyback switch Q1 turns on, the clamping switch Q2 turns on, and the clamping capacitor C1 discharges through the clamping switch Q2. The clamping capacitor C1 feeds back the absorbed energy to the load. The clamping capacitor C1 participates in resonance. At this time, the resonant current is large, and Icc is less than the sum of Ilm and Ip. Therefore, the flyback switch Q1 needs to freewheel through the body diode. At this time, the voltage of the flyback switch Q1 is 0, which can achieve ZVS.

[0053] Based on the above analysis, the conduction time of the clamping switch Q2 should be less than T2 to avoid multiple uncontrollable resonances occurring during the conduction time of the clamping switch Q2. Simultaneously, the resonant current exhibits a sinusoidal wave pattern, for example, referring to... Figure 4 The conduction time of clamping switch Q2 is less than During the negative half-cycle, the clamping capacitor C1 discharges, achieving zero-voltage switching (ZVS); if it exceeds the conduction time of the clamping switch Q2... Clamping capacitor C1 begins charging and enters the positive half-cycle, making ZVS impossible.

[0054] In one possible implementation, the on-time of the clamping switch Q2 can be equal to...

[0055] To achieve ZVS, in this embodiment of the invention, the on-time of the clamping switch Q2 is set to... refer to Figure 4 When the resonant current is at its maximum, the flyback switch Q1 is more likely to freewheel through the body diode, thus making it easier to achieve ZVS.

[0056] Specifically, the on-time of the clamping switch Q2 can be 100ns, 200ns, or 400ns. The specific time can be set according to the actual application requirements.

[0057] In one possible implementation, refer to Figure 5 The control signal PWM_0 is a PWM signal; the drive signal generation module includes: a first signal generation unit 11 and a second signal generation unit 12;

[0058] The first signal generation unit 11 is used to delay the control signal PWM_0 for a second preset time to obtain the first duty cycle signal PWM_Q1. The input terminal is the control signal PWM_0, and the output terminal is the first duty cycle signal PWM_Q1.

[0059] The second signal generation unit 12 is used to perform logical operations on the first duty cycle signal PWM_Q1 and the control signal PWM_0 to obtain the second duty cycle signal PWM_Q2. The first input terminal receives the first duty cycle signal PWM_Q1, the second input terminal receives the control signal PWM_0, and the output terminal outputs the second duty cycle signal PWM_Q2.

[0060] In this embodiment of the invention, a first duty cycle signal PWM_Q1 and a second duty cycle signal PWM_Q2 are generated using the control signal PWM_0 as a reference signal to ensure the stability of the timing of the first duty cycle signal PWM_Q1 and the second duty cycle signal PWM_Q2.

[0061] In one possible implementation, refer to Figure 6 The second signal generation unit 12 may include: a first OR gate OR1, a second OR gate OR2, and a NOT gate NOT1;

[0062] The first input terminal of the first OR gate OR1 receives the first duty cycle signal PWM_Q1, the second input terminal of the first OR gate OR1 receives the control signal PWM_0, and the output terminal of the first OR gate OR1 is connected to the input terminal of the NOT gate NOT1.

[0063] The first input of the second OR gate OR2 is connected to the output of the NOT gate NOT1. The second input of the second OR gate OR2 receives the first duty cycle signal PWM_Q1, and the output of the second OR gate OR2 outputs the second duty cycle signal PWM_Q2.

[0064] In this embodiment of the invention, the second duty cycle signal PWM_Q2 is generated using only three logic devices. See the waveform diagram below. Figure 7 This allows the clamping switch Q2 to conduct briefly for t1 before the flyback switch Q1, resulting in a simple circuit structure, fewer components, lower cost, and better stability.

[0065] In one possible implementation, refer to Figure 8 The second signal generation unit 12 may further include: a third OR gate OR3;

[0066] The first input terminal of the third OR gate OR3 receives the first duty cycle signal PWM_Q1, the second input terminal of the third OR gate OR3 receives the delay signal, and the output terminal of the third OR gate OR3 is connected to the second input terminal of the second OR gate OR2.

[0067] The first duty cycle signal PWM_Q1 has the same duty cycle as the delay signal, and the first duty cycle signal PWM_Q1 lags behind the delay signal by a third preset time; the third preset time is the dead time between the clamping switch Q2 and the flyback switch Q1.

[0068] In this embodiment of the invention, a third OR gate (OR3) is also provided to introduce a delay signal. The first duty cycle signal PWM_Q1 lags behind the delay signal by a third preset time, i.e., the dead time. The dead time can be set through the third OR gate (OR3), which simplifies the circuit and improves its safety. Refer to the specific waveform diagram. Figure 9 The clamping switch Q2 has an on-time of t1 and a dead time of t2. For example, the dead time can be 100ns.

[0069] In one possible implementation, refer to Figure 8 The first signal generation unit 11 may include: a first delay unit U1 and a second delay unit U2;

[0070] The input terminal of the first delay U1 receives the control signal PWM_0, and the output terminal of the first delay U1 is connected to the input terminal of the second delay U2; the output terminal of the second delay U2 outputs the first duty cycle signal PWM_Q1.

[0071] The second input of the third OR gate OR3 is connected to the output of the first delay U1;

[0072] The delay time of the first delay unit U1 is equal to the conduction time of the clamping switch Q2; the delay time of the second delay unit U2 is equal to the third preset duration.

[0073] Since the first duty cycle signal PWM_Q1 lags behind the delay signal by a third preset duration, in this embodiment of the invention, the delay of the first signal generation unit 11 can be divided into two parts, including a first delay unit U1 and a second delay unit U2. Simultaneously, the delay time of the second delay unit U2 is equal to the third preset duration, and the waveform reference... Figure 9 That is, the first duty cycle signal PWM_Q1 is exactly after the dead time relative to the input of the second delay U2. No additional delay time is needed. Simply connect the second input of the third OR gate OR3 to the output of the first delay U1 to simplify the circuit.

[0074] refer to Figure 10 This invention also provides an active clamp flyback circuit control method, applied to an active clamp flyback circuit; see reference. Figure 1 The active clamp flyback circuit includes: transformer T, flyback switch Q1, clamping switch Q2 and clamping capacitor C1; the primary side of transformer T is connected in series with flyback switch Q1 between the positive and negative terminals of the power supply, and clamping switch Q2 and clamping capacitor C1 are connected in series and then in parallel with flyback switch Q1.

[0075] The above methods include:

[0076] S101: Control clamping switch Q2 to conduct according to the first preset duty cycle;

[0077] S102: Control the flyback switch Q1 to conduct according to the second preset duty cycle;

[0078] Among them, the clamping switch Q2 and the flyback switch Q1 are not turned on at the same time, and their conduction is not complementary.

[0079] Similar to the above embodiments, in this embodiment of the invention, the clamping switch Q2 and the flyback switch Q1 are controlled by software to achieve non-complementary conduction, thereby reducing the turn-off current and turn-off loss of the clamping switch Q2, reducing the current stress on the secondary MOS of the transformer T, and making it easier to achieve ZVS. The specific principle is the same as in the above embodiments.

[0080] In one possible implementation, the clamping switch Q2 is turned on for a first preset time after the flyback switch Q1 is turned off.

[0081] The first preset duration is not less than And the conduction time of clamping switch Q2 is less than

[0082] Where D is the duty cycle of the first duty cycle signal PWM_Q1, and T1 is the period of the first duty cycle signal PWM_Q1.

[0083] In one possible implementation, the on-time of the clamping switch Q2 can be less than [a certain value]. T2 is the period of resonance between the clamping capacitor C1 and the leakage inductance of the transformer T.

[0084] In one possible implementation, the on-time of the clamping switch Q2 can be equal to...

[0085] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0086] refer to Figure 11 This invention also provides an active clamp flyback circuit control system, applied to an active clamp flyback circuit; the active clamp flyback circuit includes: a transformer T, a flyback switch Q1, a clamping switch Q2, and a clamping capacitor C1; the primary side of the transformer T is connected in series with the flyback switch Q1 between the positive and negative terminals of the power supply, and the clamping switch Q2 and the clamping capacitor C1 are connected in series and then in parallel with the flyback switch Q1;

[0087] The above system includes:

[0088] The first control module 21 is used to control the clamping switch Q2 to conduct according to the first preset duty cycle;

[0089] The second control module 22 is used to control the flyback switch Q1 to conduct according to the second preset duty cycle;

[0090] Among them, the clamping switch Q2 and the flyback switch Q1 are not turned on at the same time, and their conduction is not complementary.

[0091] Similar to the above embodiments, in this embodiment of the invention, the clamping switch Q2 and the flyback switch Q1 are controlled by software to achieve non-complementary conduction, thereby reducing the turn-off current and turn-off loss of the clamping switch Q2, reducing the current stress on the secondary MOS of the transformer T, and making it easier to achieve ZVS. The specific principle is the same as in the above embodiments.

[0092] In one possible implementation, the clamping switch Q2 is turned on for a first preset time after the flyback switch Q1 is turned off.

[0093] The first preset duration is not less than And the conduction time of clamping switch Q2 is less than

[0094] Where D is the duty cycle of the first duty cycle signal PWM_Q1, and T1 is the period of the first duty cycle signal PWM_Q1.

[0095] In one possible implementation, the on-time of the clamping switch Q2 can be less than [a certain value]. T2 is the period of resonance between the clamping capacitor C1 and the leakage inductance of the transformer T.

[0096] In one possible implementation, the on-time of the clamping switch Q2 can be equal to...

[0097] Figure 12 This is a schematic diagram of the control terminal 3 provided in an embodiment of the present invention. Figure 12 As shown, the control terminal 3 in this embodiment includes a processor 30 and a memory 31. The memory 31 stores a computer program 32, and the processor 30 calls and runs the computer program 32 stored in the memory 31 to execute the steps in the control method embodiments of the various active clamp flyback circuits described above, for example... Figure 10 The steps S101 to S102 are shown. Alternatively, the processor 30 is used to call and run the computer program 32 stored in the memory 31 to implement the functions of each module / unit in the above-described device embodiments, for example... Figure 11 The functions of modules 21 and 22 shown.

[0098] For example, computer program 32 can be divided into one or more modules / units, one or more of which are stored in memory 31 and executed by processor 30 to complete the present invention. One or more modules / units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 32 in control terminal 3. For example, computer program 32 can be divided into... Figure 11 Modules / units 21 to 22 are shown.

[0099] The control terminal 3 can be a desktop computer, laptop, handheld computer, or cloud server, etc. The control terminal 3 may include, but is not limited to, a processor 30 and a memory 31. Those skilled in the art will understand that... Figure 12 This is merely an example of control terminal 3 and does not constitute a limitation on control terminal 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, the terminal may also include input / output devices, network access devices, buses, etc.

[0100] The processor 30 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0101] The memory 31 can be an internal storage unit of the control terminal 3, such as a hard disk or RAM of the control terminal 3. The memory 31 can also be an external storage device of the control terminal 3, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the control terminal 3. Furthermore, the memory 31 can include both internal and external storage units of the control terminal 3. The memory 31 is used to store computer programs and other programs and data required by the terminal. The memory 31 can also be used to temporarily store data that has been output or will be output.

[0102] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0103] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0104] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0105] In the embodiments provided by this invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0106] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0108] If an integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0109] Corresponding to the above embodiments, refer to Figure 13 This invention also provides an active clamp flyback circuit, including: a transformer T, a flyback switch Q1, a clamping switch Q2, a clamping capacitor C1, and a control terminal 3; the primary side of the transformer T is connected in series with the flyback switch Q1 between the positive and negative terminals of the power supply, and the clamping switch Q2 and the clamping capacitor C1 are connected in series and then in parallel with the flyback switch Q1; the control terminal 3 is connected to the control terminal of the clamping switch Q2 and the control terminal of the flyback switch Q1 respectively.

[0110] The control terminal 3 executes the steps of the active clamp flyback circuit control method provided in the above embodiment to control the flyback switch Q1 and the clamp switch Q2.

[0111] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An active clamp flyback circuit control device, characterized in that, It is applied to an active clamp flyback circuit; the active clamp flyback circuit includes: a transformer, a flyback switch, a clamping switch, and a clamping capacitor; the primary side of the transformer is connected in series with the flyback switch between the positive and negative terminals of the power supply, and the clamping switch and the clamping capacitor are connected in series and then in parallel with the flyback switch; The aforementioned device includes: a drive signal generation module and a main control module; The input terminal of the drive signal generation module is used to receive the control signal sent by the main control module; the first output terminal of the drive signal generation module outputs a first duty cycle signal for controlling the flyback switch, and the second output terminal of the drive signal generation module outputs a second duty cycle signal for controlling the clamping switch. The clamping switch and the flyback switch are not turned on simultaneously and are not complementary in conduction. The clamping switch is turned on after the flyback switch is turned off for a first preset time period; The first preset duration is not less than And the conduction time of the clamping switch transistor is less than ; in, The duty cycle of the first duty cycle signal. The period of the first duty cycle signal is denoted as .

2. The active clamp flyback circuit control device according to claim 1, characterized in that, The conduction time of the clamping switch transistor is less than ; The period of resonance between the clamping capacitor and the leakage inductance of the transformer.

3. The active clamp flyback circuit control device according to claim 2, characterized in that, The conduction time of the clamping switch is equal to .

4. The active clamp flyback circuit control device according to claim 1, characterized in that, The control signal is a PWM signal; the drive signal generation module includes: a first signal generation unit and a second signal generation unit; The first signal generation unit is used to delay the control signal for a second preset time to obtain the first duty cycle signal, with the control signal input at the input terminal and the first duty cycle signal output at the output terminal; The second signal generation unit is used to perform logical operations on the first duty cycle signal and the control signal to obtain the second duty cycle signal. The first input terminal receives the first duty cycle signal, the second input terminal receives the control signal, and the output terminal outputs the second duty cycle signal.

5. The active clamp flyback circuit control device according to claim 4, characterized in that, The second signal generation unit includes: a first OR gate, a second OR gate, and a NOT gate; The first input terminal of the first OR gate receives the first duty cycle signal, the second input terminal of the first OR gate receives the control signal, and the output terminal of the first OR gate is connected to the input terminal of the NOT gate. The first input terminal of the second OR gate is connected to the output terminal of the NOT gate, the second input terminal of the second OR gate receives the first duty cycle signal, and the output terminal of the second OR gate outputs the second duty cycle signal.

6. The active clamp flyback circuit control device according to claim 5, characterized in that, The second signal generation unit further includes: a third OR gate; The first input terminal of the third OR gate receives the first duty cycle signal, the second input terminal of the third OR gate receives the delay signal, and the output terminal of the third OR gate is connected to the second input terminal of the second OR gate; Wherein, the first duty cycle signal has the same duty cycle as the delay signal, and the first duty cycle signal lags behind the delay signal by a third preset duration; the third preset duration is the dead time between the clamping switch and the flyback switch.

7. The active clamp flyback circuit control device according to claim 6, characterized in that, The first signal generation unit includes: a first delay unit and a second delay unit; The control signal is input to the input terminal of the first delay unit, and the output terminal of the first delay unit is connected to the input terminal of the second delay unit; the output terminal of the second delay unit outputs the first duty cycle signal. The second input terminal of the third OR gate is connected to the output terminal of the first delay unit; Wherein, the delay time of the first delay unit is equal to the conduction time of the clamping switch; the delay time of the second delay unit is equal to the third preset duration.

8. A control method for an active clamp flyback circuit, characterized in that, It is applied to an active clamp flyback circuit; the active clamp flyback circuit includes: a transformer, a flyback switch, a clamping switch, and a clamping capacitor; the primary side of the transformer is connected in series with the flyback switch between the positive and negative terminals of the power supply, and the clamping switch and the clamping capacitor are connected in series and then in parallel with the flyback switch; The above methods include: The clamping switch is controlled to be turned on according to the second duty cycle signal; The flyback switch is controlled to turn on according to the first duty cycle signal; The clamping switch and the flyback switch are not turned on simultaneously and are not complementary in conduction. The clamping switch is turned on after the flyback switch is turned off for a first preset time period; The first preset duration is not less than And the conduction time of the clamping switch transistor is less than ; in, The duty cycle of the first duty cycle signal. The period of the first duty cycle signal is denoted as .

9. An active clamp flyback circuit, characterized in that, include: The transformer comprises a flyback switch, a clamping switch, a clamping capacitor, and a control terminal; the primary winding of the transformer is connected in series with the flyback switch between the positive and negative terminals of the power supply; the clamping switch and the clamping capacitor are connected in series and then in parallel with the flyback switch; the control terminal is connected to the control terminals of the clamping switch and the flyback switch respectively. The control terminal executes the steps of the active clamp flyback circuit control method as described in claim 8, and controls the flyback switch and the clamping switch.

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