Method for performing system and power management over a serial data communication interface

Abstract

The present disclosure relates to methods for performing system and power management over a serial data communication interface. The invention provides a system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as pulse counts as serial data, and delivers the serial data to a peripheral device. The peripheral device decodes the received serial data to determine the parallel data, which is sent to processing logic. The device sends encoded pulses on a bidirectional line, so the pulses can be sent in both directions. The device sends encoded pulses on the bidirectional line using a non-zero base voltage level. The device can use voltage headroom when delivering encoded pulses between each other. Thus, a full voltage swing between a ground reference voltage level and a power supply voltage level is not used when delivering encoded pulses, which reduces power consumption.

Description

[0001] This application is a divisional application of PCT International Application No. 202180040009.3, filed on May 26, 2021, in the name of China, with the title of “Method for Performing System and Power Management over Serial Data Communication Interface”, which entered the Chinese national phase on May 26, 2021. BACKGROUND TECHNICAL FIELD

[0003] Embodiments described herein relate to the field of computing systems, and more specifically to efficiently transferring data between devices.

[0004] DESCRIPTION OF RELATED ART

[0005] Users connect various peripheral devices to host computing devices for business and entertainment purposes. Examples of such peripheral devices include portable data storage devices, multimedia devices, printers, scanners, cameras, and the like. Some examples of host devices include desktop computers, laptop or tablet computers, smartphones, and multimedia systems in vehicles. In many applications, interfaces have supported the connection and later reconnection of peripheral devices. In many designs, interfaces use bidirectional signal buses for data transfer between the host computing device and the peripheral device.

[0006] Generally, a communication protocol determines the format of control signals, the voltage levels used, and the timing of signals transferred across the signal bus. Logic within the interface on each of the host computing device and the peripheral device supports a selected one of a variety of communication protocols. As data is transferred across the signal bus, the peripheral device consumes power. As each generation of communication protocol generally supports a larger bandwidth, power consumption also increases.

[0007] In view of the foregoing, there is a need for methods and mechanisms for efficiently transferring data between devices. SUMMARY

[0008] Systems and methods are contemplated for efficiently transferring data between devices. In various embodiments, a transmitter and a receiver have one or more data lines between each other. The transmitter receives multi-bit data to be delivered to the receiver. Control logic in the transmitter encodes the received multi-bit data into a series of pulses. The encoded pulses represent the received data. The transmitter sends the encoded pulses to the receiver. In some embodiments, the transmitter sends the encoded pulses over a single data line. Thus, the transmitter receives parallel multi-bit data and the pulses encode the received data into serial data. In various embodiments, the receiver receives the serial pulse-encoded data and control logic in the receiver decodes the received data. By decoding the received serial data, the control logic of the receiver recreates the parallel multi-bit data that was earlier received by the transmitter. The decoded multi-bit data is sent by the control logic in the receiver to processing logic.

[0009] In some embodiments, a power management unit determines when the transmitter and receiver are deactivated or otherwise power down one or more data lines. In one embodiment, the transmitter and receiver power down one of the two data lines between each other, which reduces power consumption. In some embodiments, the transmitter and receiver transition between a data transfer mode and another, smaller idle mode during data transfer. Instead of transferring data as it is received until all received data is transferred, the transmitter stores the received data in one or more buffers. When an idle time interval ends, data is read from one of the buffers and transferred to the receiver for another time interval. The process is repeated until all data is transferred.

[0010] In some embodiments, the transmitter and receiver use a voltage margin when the transmitter and receiver transfer the encoded pulses between each other. The voltage margin provides further power consumption reduction. In one embodiment, the idle voltage level is greater than the power supply voltage level by the voltage margin. In one embodiment, the data transfer voltage level is greater than the idle voltage level by the voltage margin. Thus, the full voltage swing between the ground reference voltage level and the power supply voltage level is not used when transferring the encoded pulses. In some embodiments, the interface supports a master / slave architecture, such as the Universal Serial Bus (USB) standard serial bus protocol for connecting devices. In other embodiments, another communication protocol is used.

[0011] These and other embodiments will be further understood by reference to the following description and attached drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and further advantages of the methods and mechanisms can be better understood by referring to the following description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of one embodiment of a data transfer.

[0014] Figure 2 is a block diagram of one embodiment of a symbol generation table.

[0015] Figure 3 is a block diagram of one embodiment of a data transfer.

[0016] Figure 4 is a flow diagram of one embodiment of a method for efficiently transferring data between devices.

[0017] Figure 5 is a flow diagram of one embodiment of a method for efficiently transferring data between devices.

[0018] Figure 6 is a block diagram of one embodiment of a computing system.

[0019] Figure 7 is a flow diagram of one embodiment of a method for efficiently transferring data between devices.

[0020] Figure 8 is a block diagram of one embodiment of a signal waveform on a data line between devices.

[0021] Figure 9 is a block diagram of one embodiment of an interface for transferring data between devices.

[0022] Figure 10 is a block diagram of one embodiment of an interface for transferring data between devices.

[0023] Figure 11 is a flow diagram of one embodiment of a method for efficiently transferring data between devices.

[0024] Figure 12 is a flow diagram of one embodiment of a method for efficiently transferring data between devices.

[0025] Figure 13 is a block diagram of one embodiment of an interface for transferring data between devices.

[0026] Figure 14 is a block diagram of one embodiment of a symbol mapping used by a symbol generation table.

[0027] Figure 15 is a block diagram of one embodiment of a symbol mapping used by a symbol generation table.

[0028] While the embodiments described in this disclosure can be susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the claims. As used throughout this patent application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words "include," "including," and "includes" mean including, but not limited to.

[0029] Various units, circuits, or other components can be described as being "configured to" perform a task or tasks. In such contexts, "configured to" is a broad recitation of structure generally meaning "having circuitry that" performs the task or tasks during operation. As such, the unit / circuit / component can be configured to perform the task even when the unit / circuit / component is not currently on. In general, the circuitry that forms the structure corresponding to "configured to" can include hardware circuits. Similarly, various units / circuits / components can be described as "performing" a task or tasks, in DETAILED DESCRIPTION

[0030] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments described in the present disclosure. However, one having ordinary skill in the art will recognize that the embodiments can be practiced without the specific details. In some instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the description of the embodiments.

[0031] Reference Figure 1FIG. 1 shows a generalized block diagram of one embodiment of a data transfer 100. In various embodiments, a transmitter 110 receives parallel multi-bit data 102 and delivers serial data 118 as encoded pulses to a receiver 120. The encoded pulses of serial data 118 represent the parallel multi-bit data 102 received on multiple pins of the transmitter 110. In some embodiments, the receiver 120 generates parallel multi-bit data 128 from the received serial data 118 and delivers the data 128 to external processing logic (not shown). In one embodiment, each of the transmitter 110 and the receiver 120 includes pulse encoding logic 112 and pulse encoding logic 122, respectively. Each of the pulse encoding logic 112 and the pulse encoding logic 122 is implemented by hardware such as circuitry, or by software such as firmware, or a combination of hardware and software.

[0032] The pulse encoding logic 112 includes an encoder 114 to generate serial data 118 as encoded pulses from the received parallel data 102. In one embodiment, the encoded pulses in the serial data 118 include symbols, where each symbol represents a portion of the parallel multi-bit data 102. Each symbol uses a particular number of pulses to represent the parallel data. In one embodiment, a symbol with three pulses indicates a particular 2-bit state, while another symbol with two pulses indicates a different 2-bit state, and so on. In other embodiments, other numbers of pulses and parallel bits are possible and can be contemplated. In some embodiments, the transmitter 110 sends the symbols as data 118 to the receiver 120 on a single data line.

[0033] In various embodiments, the decoder 126 of the pulse encoding logic 122 receives symbols of the serial data 118 and converts each symbol into a portion of the parallel multi-bit data 128. By decoding the received symbols of the serial data 118, the decoder 126 recreates the parallel multi-bit 102 as the parallel multi-bit data 128. In one embodiment, the decoder 126 distinguishes the symbols from one another, counts the number of pulses in a particular symbol, and maps the number of pulses to a particular number of parallel bits. In one embodiment, the decoder 126 counts one pulse in a particular symbol and maps the count of one pulse to a particular 2-bit state. The data transmission between the transmitter 110 and the receiver 120 uses symbols to represent the parallel data, where there is no one-to-one relationship between the pulses and the data bits. Instead, different numbers of pulses are used to represent the same number of parallel bits. In one embodiment, 2 bits in parallel are capable of representing 4 states. Rather than sending 4 serial bits, the transmitter 110 sends a number of pulses in the range of 0 to 3 pulses to represent one of the 4 states of 2 parallel bits. In other embodiments, other numbers of parallel bits and pulses are used to represent the parallel bits.

[0034] In some embodiments, one or more of the data lines between the transmitter 110 and the receiver 120 are bidirectional data lines. To support bidirectional transmission of data, the pulse encoding logic 112 uses a decoder 116 with equivalent functionality of the decoder 126. Similarly, the pulse encoding logic 122 uses an encoder 124 with equivalent functionality of the encoder 114. In some embodiments, the transmitter 110 and the receiver 120 support a master / slave architecture, such as the Universal Serial Bus (USB) standard serial bus protocol for connecting devices. In other embodiments, another communication protocol is used.

[0035] While the above describes a previous pin state to current pin state mapping using a pulse of voltage levels to indicate the data being transmitted, in other embodiments, the logic of the I / O interface uses other events. For example, instead of using a pulse of voltage levels, in other embodiments, the logic uses one of a fixed frequency voltage carrier signal on a physical wire to indicate on / off switching and amplitude shift keying, magnetic or inductive coupling, electrostatic or capacitive coupling, optical coupling, and wireless rate interfaces capable of transmitting events.

[0036] Turning now to Figure 2FIG. 2 shows a generalized block diagram illustrating one embodiment of a symbol generation table 150 (or table 150). In the illustrated embodiment, the symbol generation table 150 maps 2-bit previous pin states to 2-bit current pin states. In various embodiments, the table 150 performs the mapping based on a number of pulses received on a single data signal line during a time interval. In other embodiments, however, another number of parallel bits are used for pin states. While a particular mapping is shown in table 150, another mapping is possible and can be envisioned in other embodiments.

[0037] The transmitter and receiver use table 150 and symbol mapping 160 to support transmission of parallel multi-bit data as serial data on a single data line. In various embodiments, each of the transmitter and receiver uses a copy of table 150 and symbol mapping 160. The transmitter determines when it is time to send data based on various conditions. When the transmitter has parallel multi-bit data to send to the receiver, the transmitter divides the parallel multi-bit data into successive portions or segments. Each segment has a current pin state. In one embodiment, each segment has 2 bits. In other embodiments, each segment has another number of parallel multi-bit.

[0038] The transmitter maintains a previous pin state, which is the current pin state during a previous data transmission. Using table 150, control logic of the transmitter identifies a row of table 150 based on the previous pin state and identifies a column based on the current pin state. For the initial 2 bits to be sent, the previous pin state is the state used during an earlier data transmission or is a default pin state known to each of the transmitter and receiver. The logic uses the resulting symbol and symbol mapping 160 to determine a number of pulses to send in a time interval, and the number of pulses represents the current pin state.

[0039] The symbol "2'b" represents a 2-bit binary value, and as shown, when the previous pin state is 2'b01 and the current pin state to be sent is 2'b10, control logic of the transmitter selects the second row from the top of table 150 based on the previous pin state. The control logic selects the third column from the left of table 150 based on the current pin state and identifies the symbol "D". The control logic uses symbol mapping 160 to determine that the symbol "D" represents a count of 3 pulses to be sent on the serial data line to the receiver. In some embodiments, the transmitter sends 3 pulses in a time interval to indicate the symbol "D".

[0040] In one embodiment, when the transmitter does not send a pulse during the time interval, the current pin state is equal to the previous pin state. This mapping is represented by the top row of the symbol mapping 160 and the symbol "A" in the table 150. The symbol mapping 160 maps no pulse or a zero pulse to the symbol "A". When the transmitter sends one pulse during the time interval, only a particular bit of the current pin state changes. In some embodiments, the particular bit is the least significant bit indicated as "bl" in the table 150. In other embodiments, the particular bit is the most significant bit indicated as "bO" in the table 150.

[0041] The control logic of the receiver counts the number of received pulses within the time interval and uses the symbol mapping 160 to determine the symbol. The control logic of the receiver selects a row of the table 150 based on the previous pin state and selects a column based on the symbol read from the mapping 160. The selected column provides the current pin state. The control logic sends the current pin state to one or more of the data storage and processing logic.

[0042] Reference Figure 3 A generalized block diagram illustrating one embodiment of a data transfer 200 is shown. In various embodiments, a transmitter 210 and a receiver 230 have one or more data lines between each other. While the communication protocol uses multiple data lines between the transmitter 210 and the receiver 230, in some embodiments, a single data line is used while the other one or more data lines are deactivated or otherwise powered down. In one embodiment, the transmitter 210 and the receiver 230 use a single active (powered up) data line between each other to transfer data 220. The transmitter 210 receives data 202 and data 204 from external processing logic (not shown) and sends data 220 as a representation of the received data 202 and data 204. The receiver 230 receives data 220 and decodes or maps the received data 220 to data 202 and data 204. The receiver sends the decoded data as data 240 and data 242 to the external processing logic (not shown).

[0043] The transmitter 210 includes control logic (or logic 214), a buffer 216 for storing received data 202 and 204, and an interface 212 for transmitting data 220 with the receiver 230. Similarly, the receiver 230 includes control logic (or logic 234), a buffer 236 for storing received data 240 and 242, and an interface 232 for transmitting data 220 with the transmitter 210. Each of the logic 214 and the logic 234 is implemented by one or more of hardware such as control circuitry and software such as firmware and software applications. Each of the buffer 216 and the buffer 236 is implemented with flip-flops, one of various types of random access memory (RAM), content addressable memory (CAM), or other components. In some embodiments, the transmitter 210 and the receiver 230 use an active bidirectional data line between each other, so at times the transmitter 210 sends data to the receiver 230, and at other times the receiver 230 sends data to the transmitter 210. When the receiver 230 sends data to the transmitter 210, in one embodiment the receiver 230 receives data 240 and data 242 on the bidirectional data line, and similarly the transmitter sends data 202 and data 204 on the bidirectional data line. In other embodiments, each of the transmitter 210 and the receiver 230 transmits data on other data lines (not shown).

[0044] The logic 214 and the logic 234 determine the mode of operation of the transmitter 210 and the receiver 230, respectively. When the logic 214 and the logic 234 determine the mode of operation to be a data transmission mode, the logic 214 and the logic 234 determine the source of data to be transmitted. One source for the transmitter 210 is the received data 202 and data 204. Another source is data stored in the buffer 216. The logic 214 selects between the two sources based on the mode of operation, such as the data transmission mode and the power efficient data transmission mode. Similarly, one source for the receiver 230 is the received data 240 and data 204. Another source is data stored in the buffer 236.

[0045] When the transmitter 210 is operating in a data transmission mode, the logic 214 determines a current state of data to be transmitted over a time interval. One example of a time interval is the time interval 250. Three voltage-time graphs are shown, each for the input data 202 and the input data 204, and one for the data 220 between the transmitter 210 and the receiver 230. In some embodiments, the time interval 250 is a duration of time determined to be sufficient to transmit data and have the data correctly interpreted for storage or use at the receiver 230. For example, the data to be sent in the time interval 250 is a subset or a portion of the total data to be transmitted over multiple time intervals. In one embodiment, the transmitter 210 can transmit 1 gigabyte (GB) of total data, but 2 bits (binary digits) for each time interval 250. When each of the transmitter 210 and the receiver 230 are capable of transmitting 2-bit states between each other during a 90 nanosecond (ns) time interval, the time interval 250 is 90 ns. In such an embodiment, the logic 214 determines a current state. In one embodiment, the source of the data is the received data 202 and 204 having a value of 2’b10, where “2’b” indicates a 2-bit binary value.

[0046] In addition to the current state, the logic 214 also determines a previous state. The previous state is the current state of a previous time interval immediately preceding the current time interval. When the current time interval is an initial time interval, the previous state is a default initial state. In one example, the default initial state is 2b’00. Other data sizes, time interval durations, and initial states are possible and can be contemplated in other embodiments. To send the received data 202 and 204 on a single data line, the logic 214 uses each of the current state and the previous state to determine a number of pulses to send as the data 220 to the receiver 230. In one embodiment, the logic 214 uses a state table that maps the previous state to the current state based on a number of pulses received as the data 220 over the time interval 250. In various embodiments, the logic 234 of the receiver 230 uses the same state table in order to decode the received pulses. In various embodiments, each of the logic 214 and the logic 234 also stores a copy of the previous state.

[0047] In one embodiment, each of the logic 214 and the logic 234 stores a previous state of 2’b00, and the logic 214 determines a current state of the received data 202 and 204 to be 2’bll. For example, at a time tl, the data 202 transitions to a Boolean value of “1” or a logical high, and at a later time t3, the data 204 transitions to a Boolean value of “1” as well, which is also a logical low. Using the previous state 2’b00, the current state 2’bll, and the fact that the data 202 and 204 are both high, the logic 214 determines that the data 220 to be sent to the receiver 230 is a pulse of a logical low.Figure 2 The logic 214 determines that 3 pulses should be sent as data 220 to the receiver 230 before the time interval 250 elapses, using a state table such as the previous table 150. In one embodiment, each unique number of pulses corresponds to a symbol that is mapped or decoded to a 2-bit current state. In one embodiment, 3 pulses indicate the symbol D, 2 pulses indicate the symbol C, and one pulse indicates the symbol B. However, in other embodiments, another combination of mapping and number of pulses is used in addition to another size of state.

[0048] In one embodiment, in response to the first data transition of the data 202 at time tl, the first pulse of the symbol D is generated at time t2. Thus, the logic 214 does not wait a fixed delay to determine each possible data transition of the data 202 and 204 before beginning to generate pulses. In one embodiment, in response to the second data transition of the data 204 at time t3, the third pulse of the symbol D is generated at time t4. The amount of time of the last data transition on the data 202 and 204, the pulse width, and the delay between pulses varies depending on the design and each is used to determine the time interval 250. In various embodiments, the logic 234 uses the previous state of 2'bOO, the received 3 pulses, and the state table to determine that the current state is 2'bll. The logic 234 either sends the current state of 2'bll as data 242 and data 144 or stores the current state in the buffer 236.

[0049] In the next time interval 250, each of the logic 214 and 234 stores the previous state of 2'11 and the logic 214 determines the current state of the received data 202 and 204. At time t5, the data 204 transitions, which causes the first pulse to be generated at time t6. The transition of the data 202 at time t7 determines the symbol to be sent, such as the symbol C, which also determines the final number of pulses to be generated and sent to the receiver 230. In a similar manner, in the third time interval 250, the logic 214 determines that the current state is represented by the symbol B or a single pulse, which is decoded or remapped by the logic 234 of the receiver 230.

[0050] Referring now to Figure 4 , a generalized flow diagram of one embodiment of a method 300 for efficiently transferring data between devices is shown. For purposes of discussion, the steps in this embodiment (as well as in Figure 5 , Figure 7 and Figure 11 to Figure 12 ) are shown in sequential order. However, in other embodiments, some steps can occur in a different order than shown, some steps can be performed concurrently, some steps can be combined, and some steps can be absent.

[0051] The logic of the I / O interface of the transmitter and receiver transitions the transmitter and receiver to a data transfer mode (block 302). In various embodiments, the transmitter is one of the I / O interfaces of the host computing device and the peripheral device, and similarly, the receiver is the other of the host computing device and the peripheral device. In some embodiments, the transmitter and receiver communicate with each other using a serial data communication protocol. In various embodiments, the communication protocol determines which device is the transmitter at a particular time. The logic of the I / O interface determines that it is time to transition from the idle mode to the data transfer mode based on one or more of: determining that a time interval has passed; determining that an amount of data for transmission exceeds a threshold; and receiving a control signal from the processing logic of one or more of the transmitter and receiver indicating the transition.

[0052] The logic of the I / O interface determines a default state of the pulsed encoded data of the transmitter and receiver (block 304). The default state is also referred to as the initial state. In the following description, the transmitter and receiver transmit data in 2-bit states, but using a single data signal line. In other embodiments, another number of bits and another number of data lines are used. Additionally, in other embodiments, the logic and number of data signal lines are replicated to provide a bus between the transmitter and receiver. In various embodiments, the transmitter and receiver store an initial state of the data, which is a predetermined default state. The initial state is used as the previous state of the first state to be transmitted from the transmitter to the receiver.

[0053] After determining the initial state of the data, the transmitter logic starts a timer to measure a time interval (block 306). The amount of time that occurs between the last data transition on the received data, the pulse width, and the delay between pulses varies by design, and each is used to determine the duration of the time interval. In one embodiment, the receiver logic does not start a timer to measure the same time interval until a data transition is received from the transmitter. During the time interval, the transmitter encodes the parallel multi-bit data into serial data as a series of pulses (block 308). In one embodiment, the transmitter determines the number of pulses (or count) based on the received current state and the stored previous state. In one embodiment, the transmitter uses a symbol generation table equivalent to table 150 of (FIG. 15). The transmitter sends the serial data, such as the number of pulses, to the receiver (block 310). Figure 2

[0054] ​During the time interval measured at the receiver, the receiver logic counts the number of pulses in the pulse encoded data received from the transmitter (block 312). In some embodiments, the pulses begin with a rising edge, while in other embodiments, the pulses begin with a falling edge. When a rising edge is used to indicate the beginning of a pulse, it should be noted that the last pulse can begin with a rising edge, but a falling edge can occur outside of the time interval. However, in some embodiments, the receiver logic still counts the last pulse. Similarly, when a falling edge is used to indicate the beginning of a pulse, the receiver logic still counts the last pulse when the corresponding rising edge of the last pulse occurs after the completion of the second time interval.

[0055] If the logic of the receiver I / O interface determines that the time interval has not yet passed (the "No" branch of conditional block 314), control flow of the method 300 returns to block 312, where the logic continues to count any received pulses. If the logic of the receiver I / O interface determines that the second time interval has passed (the "Yes" branch of conditional block 314), the logic decodes the serial data representing the parallel data (block 316). In one embodiment, the logic determines the current state of the data based on the pulse count and the previous state. For example, the logic uses the number of pulses to map the previous state to the current state. In various embodiments, the logic determines the mapping by using a table equivalent to table 150: Figure 2

[0056] In one embodiment, a count of no pulses indicates that the current state is equal to the previous state. Similarly, the logic determines that a count of one pulse indicates only a change in a particular one of the 2-bit data states, while the logic determines that a count of two pulses indicates a change in only another of the 2-bit data states. For example, if the previous state is 2'b01, where "2'b" indicates a two-bit binary value, the logic determines that a count of one pulse indicates that the current state is 2'b00, where only the least significant bit has changed. In a similar manner, the logic determines that a count of two pulses indicates that the current state is 2'b11, where only the most significant bit has changed. In this example, the logic determines that a count of zero indicates no change, so the current state is 2'b01, and a count of three pulses indicates that both bits have changed, so the current state is 2'b10.

[0057] ​The receiver logic sends the current state to processing logic and / or data storage at the receiver (block 318). If the I / O interface determines that the data transfer mode has not ended (the "No" branch of conditional block 320), control flow of the method 300 returns to block 306, where the timer is restarted to measure the time interval. Otherwise, if the I / O interface determines that the data transfer mode has ended (the "Yes" branch of conditional block 320), the I / O interface transitions each of the transmitter and receiver to another mode of operation, such as an idle mode (block 322).

[0058] Referring now to Figure 5 , a generalized flow diagram illustrating one embodiment of a method 400 for efficiently transferring data between devices is shown. Logic of an interface of a device operates a bidirectional signal line between a host computing device and a peripheral device (block 402). Data transfer occurs based on a data transfer mode, an idle mode, or other mode. The data line is equivalent to a physical wire, whose contact connects with other contacts or pads to form an electrical short between the host computing device and the peripheral device. The interface logic is implemented in hardware, such as circuitry, software, or a combination of hardware and software. In various embodiments, the interface logic supports a serial data communication protocol.

[0059] If the logic of one or more of the transmitter and receiver does not receive an indication to operate in a power efficient mode (the "No" branch of conditional block 404), control flow of the method 400 returns to block 402, where the interface remains in the current mode of operation. In some embodiments, the interface determines that it is time to transition to a power efficient mode based on a time interval, an indication received from a power management unit, or other item. If the logic of one or more of the transmitter and receiver receives an indication to operate in a power efficient mode (the "Yes" branch of conditional block 404), the interface operates the bidirectional data signal line in an idle mode while storing data (block 406). While the bidirectional data line is held at a constant voltage level, the interface stores received data in a corresponding buffer, rather than sending data on the bidirectional data line as it is received.

[0060] If the interface does not determine that it is time to end the idle mode (the "No" branch of conditional block 408), control flow of the method 400 returns to block 406, where the interface remains in the idle mode while storing received data. Conditions for transitioning from the idle mode to a data transfer mode include one or more of: determining that a time interval has elapsed; determining that an amount of data stored during the idle mode exceeds a threshold; and receiving a control signal from processing logic of the device indicating a transition. If the interface determines that it is time to end the idle mode (the "Yes" branch of conditional block 408), the interface operates the bidirectional data signal line in a data transfer mode by sending stored data between the devices (block 410).

[0061] Conditions for transitioning from the data transfer mode include one or more of: determining that a time interval has passed; determining that an amount of data transmitted during the data transfer mode exceeds a threshold; and receiving a control signal indicating a transition from processing logic of the device. In various embodiments, the interface generates a series of pulses, as previously described. The receiving logic converts the pulses on the single data signal line into two or more data signals. When the communication protocol is the USB serial data communication protocol, the receiving logic converts the pulses into two data signals.

[0062] If the interface does not determine that it is time to end the data transfer mode (the "No" branch of conditional block 412), control flow of the method 400 returns to block 410, in which the interface maintains the data transfer mode. If the interface determines that it is time to end the data transfer mode (the "Yes" branch of conditional block 412), but the power efficient mode has not ended (the "No" branch of conditional block 414), control flow of the method 400 returns to block 406, in which the interface operates the bidirectional data signal line in the idle mode while storing data. If the interface determines that it is time to end the data transfer mode (the "Yes" branch of conditional block 412), and the power efficient mode has ended (the "Yes" branch of conditional block 414), control flow of the method 400 returns to block 402, in which the interface operates the bidirectional signal line based on the current mode of operation, rather than the power efficient mode.

[0063] Referring to Figure 6 , a generalized block diagram of one embodiment of a computing system 500 is shown. In various embodiments, the computing system 500 includes a processor complex 510 having interfaces for connecting to peripheral devices 540A-B and a memory interface 560 for communicating with a memory 562. For example, in some embodiments, the processor complex 510 includes input / output (I / O) interfaces 530A-B for communicating with I / O interfaces 542A-B of the peripheral devices 540A-B. For ease of illustration, not all components of the computing system 500 are shown in Figure 5 Clock sources, such as phase-locked loops (PLLs), interrupt controllers, power managers, etc., are not shown in FIG. 5. It should also be noted that the number of components of the computing system 500 (and the Figure 5The number of sub-components of computing systems such as those illustrated in FIG. 5 can vary in different embodiments, such as within processor complex 510. For example, in some embodiments, computing system 500 uses a communication structure 550 (or multiple structures 550) to route data between additional input / output (I / O) interfaces 530C and additional peripheral devices 540C having corresponding I / O interfaces 542C. In such embodiments, processor complex 510 includes a fabric interface unit 512 for communicating with structure 550. In other embodiments, computing system 500 does not include structure 550 and I / O interfaces 530C.

[0064] In various embodiments, computing system 500 is included within one of a variety of host computing devices. Examples of host computing devices are desktop computers, laptop or notebook computers or tablet computers, smartphones, multimedia systems in vehicles, etc. The term “processor complex” is used to denote a configuration of one or more processor cores that use local storage such as shared cache memory subsystems and are capable of processing workloads together. As shown, processor complex 510 is in communication with one or more peripheral devices such as peripheral devices 540A through 540C. Examples of peripheral devices 540A through 540C are portable data storage devices, multimedia devices, printers, scanners, cameras and video cameras, keyboards, joysticks, etc.

[0065] For many applications, there is no need to access and install device drivers for processor complex 510 to communicate with peripheral devices 540A through 540C. I / O interfaces 530A through 530C and 542A through 542C already support connection and subsequent reconnection of peripheral devices 540A through 540C. In various embodiments, I / O interfaces 530A through 530C and 542A through 542C support a serial data communication protocol such as the Universal Serial Bus (USB) standard serial bus protocol for connecting devices with distributed real-time control and safety. While the USB protocol uses two data lines, in some embodiments, one or more of I / O interfaces 530A through 530C and 542A through 542C use a single data signal line, while one of the data lines is deactivated or otherwise powered down. As shown in one example, I / O interfaces 530B and 542B communicate via a single data signal line 576, while data line 578 is deactivated. In various embodiments, when an interface has multiple bits of data in parallel to transmit over a single data line, the interface encodes the parallel data into serial data such as a series of pulses.

[0066] During a data transfer mode, either of the I / O interfaces 530B and 542B is the transmitter 570 at this time, sending a series of one or more pulses on the single data signal line 576 to the receiver 580. As shown, in one embodiment, the transmitter 570 receives two data signals as shown by Data 1 572 and Data 2 574 on two separate data signal lines. However, the transmitter 570 sends a series of one or more pulses on the single data signal line 576 to the receiver 580. The receiver 580 detects the pulses on the single data signal line 576 and converts them into two digital signals on two separate data lines, such as Data 1 582 and Data 2 584. It should be noted that while data transfer is shown from left to right in the illustrated embodiment, in other embodiments, data transfer transmits data from right to left as the I / O interfaces 530A-C and 542A-C support bidirectional data communication.

[0067] In one embodiment, the I / O interfaces 530A-C and 542A-C support multiple operating modes, such as a data transfer mode, an idle mode, and a lower power idle mode. For each of the idle mode and the lower power idle mode, the I / O interfaces 530A-C and 542A-C maintain a constant voltage level on the corresponding single data signal line. For example, each of the transmitter 570 and the receiver 580 maintains a constant voltage level on the single data line 576. The lower power idle mode uses a first voltage level that is less than a second voltage level of the idle mode. In one embodiment, the power supply voltage of each of the transmitter 570 and the receiver 580 is 4.0 volts, and the first voltage level is greater than or equal to 4.0 volts and less than 4.15 volts. Here, in this embodiment, a voltage margin of 0.15 volts is used. The second voltage level is equal to the sum of the power supply voltage and the voltage margin, or 4.15 volts. Thus, when the lower power idle mode is used, power consumption is further reduced.

[0068] The data transfer mode uses each of the second voltage level and a third voltage level that is greater than the second voltage level. For example, the data transfer mode uses a second voltage level of 4.15 volts and a third voltage level that is equal to the sum of the power supply voltage and twice the voltage margin, or 4.30 volts. The one or more pulses sent from the transmitter 570 to the receiver 580 on the single data line 576 have voltage levels that transition between 4.15 volts and 4.30 volts. Thus, before transitioning to the data transfer mode, the interfaces 530A-C and the peripheral devices 540A-C first transition from the lower power idle mode to the idle mode, and then from the idle mode to the data transfer mode.

[0069] In some embodiments, memory interface 560 uses at least one memory controller and at least one cache for off-chip memory 562, such as synchronous DRAM (SDRAM). Memory interface 560 stores memory requests in a request queue, uses any number of memory ports, and uses circuitry capable of interfacing with memory 562 using one or more of a variety of protocols for interfacing with memory channels for interfacing with memory devices (not shown). Memory 562 stores one or more application programs, a base operating system (OS), and sometimes a virtual (guest) OS. Copies of portions of the base OS are executed by one or more of processors 520A-B. In addition to result data and intermediate data generated during execution of application programs, memory 562 stores source data for the application programs.

[0070] In some embodiments, processors 520A-B use a homogeneous architecture. For example, each of processors 520A-B is a general-purpose processor, such as a central processing unit (CPU), that utilizes circuitry to execute instructions according to a predefined general-purpose instruction set. Any of a variety of instruction set architectures (ISAs) are selected. In some embodiments, each core within processors 520A-B supports out-of-order execution of one or more threads of a software process and includes a multi-stage pipeline. In other embodiments, one or more of processors 520A-B support in-order execution of instructions. In some embodiments, processors 520A-B include units for fetching instructions, decoding instructions, performing dependency checks, register renaming of operand identifiers, and executing instructions. Processors 520A-B can support execution of a variety of operating systems.

[0071] In other embodiments, processors 520A-B use a heterogeneous architecture. In such embodiments, one or more of processors 520A-B are highly parallel data-parallel processors rather than CPUs. In some embodiments, these other processors of processors 520A-B use single-instruction-multiple-data (SIMD) cores. Examples of SIMD cores are graphics processing units (GPUs), digital signal processing (DSP) cores, or others. In various embodiments, each of processors 520A-B uses one or more cores and one or more levels of cache memory subsystems.

[0072] In various embodiments, different types of traffic flow independently through fabric 550. Independent flow is achieved by allowing a single physical fabric bus to include multiple overlapping virtual channels or dedicated source and destination buffers, each virtual channel carrying a different type of traffic. Each channel independently flow controls without relying on transactions in different channels. Fabric 5110 can also be packet-based and can be hierarchical with bridges, crossbars, point-to-point, or other interconnectors.

[0073] Referring now to Figure 7 , a generalized flow diagram illustrating one embodiment of a method 600 for efficiently transferring data between devices is shown. Logic of an interface of a device operates a bidirectional signal line between a host computing device and a peripheral device in a lower power idle mode at a first voltage level on a data line of the interface (block 602). As previously described, the data line is equivalent to a physical line whose contacts are connected with other contacts or pads to form an electrical short between the host computing device and the peripheral device. The interface logic is implemented in hardware such as circuitry, software, or a combination of hardware and software. In various embodiments, the interface logic supports a serial data communication protocol.

[0074] While the communication protocol uses more than one data signal line, in some embodiments, the interface logic uses a single data signal line at a voltage level higher than a power supply voltage level used by the interface logic of the host computing device and the interface logic of the peripheral. In various embodiments, each of the higher voltage levels is greater than the power supply voltage level by an integer multiple of a voltage margin. The higher voltage level on the single data signal line produces pulses that are converted by the receiving logic into separate data signals. In some embodiments, the first voltage level of the lower power idle mode is equal to the power supply voltage level. In other embodiments, the first voltage level of the lower power idle mode is equal to a sum of the power supply voltage level and a voltage level less than the voltage margin. In one example, the power supply voltage level is 4.0 volts and the voltage margin is 0.15 volts. Thus, in the lower power idle mode, the interface logic maintains a voltage level on the single data signal line between the devices that is greater than or equal to 4.0 volts and less than 4.15 volts.

[0075] If the interface does not determine that it is time to transition to the data transfer mode (the "No" branch of conditional block 604), control flow of the method 600 returns to block 602 in which the interface remains in the lower power idle mode. In some embodiments, the interface determines that it is time to transition to another mode based on a time interval. In other embodiments, the interface determines that it is time to transition to another mode based on a stored amount of data for transfer exceeding a threshold. In other embodiments, the interface determines that it is time to transition to another mode based on receiving a control signal from processing logic of the device indicating the transition.

[0076] If the interface determines that it is time to transition to the data transfer mode (the "Yes" branch of conditional block 604), the interface operates the bidirectional data signal line in the idle mode at a second voltage level that is greater than the first voltage level (block 606). As previously described, the first voltage level of the lower power idle mode is equal to the sum of the power supply voltage level and a voltage level that is less than the voltage margin. In one example, the power supply voltage level is 4.0 volts and the voltage margin is 0.15 volts. Thus, in the lower power idle mode, the interface logic maintains a voltage level on the single data signal line between the devices that is greater than or equal to 4.0 volts and less than 4.15 volts. In one embodiment, the second voltage level is equal to the sum of the power supply voltage level and the voltage margin. Using the previous example of values, the second voltage level is the sum of 4.0 volts and 0.15 volts, or 4.15 volts.

[0077] If the interface does not determine that it is time to end the idle mode (the "No" branch of conditional block 608), control flow of the method 600 returns to block 606, in which the interface maintains the idle mode. As previously described, conditions for transitioning to another mode include one or more of determining that a time interval has passed, determining that an amount of data stored for transmission exceeds a threshold, and receiving a control signal from the processing logic of the device indicating a transition. If the interface determines that it is time to end the idle mode (the "Yes" branch of conditional block 608), the interface operates the bidirectional data signal line in the data transfer mode at a series of pulses between the second voltage level and the sum of the second voltage level and the voltage margin (block 610). Using the previous example of values, the interface generates a series of pulses between 4.15 volts and 4.30 volts. The receiving logic converts the pulses on the single data signal line into two or more data signals to be stored in a buffer. When the communication protocol is the USB serial data communication protocol, the receiving logic converts the pulses into two data signals.

[0078] If the interface does not determine that it is time to end the data transfer mode (the "No" branch of conditional block 612), control flow of the method 600 returns to block 610, in which the interface maintains the data transfer mode. Conditions for transitioning from the data transfer mode include one or more of determining that a time interval has passed, determining that an amount of data transferred exceeds a threshold, and receiving a control signal from the processing logic of the device indicating a transition. If the interface determines that it is time to end the data transfer mode (the "Yes" branch of conditional block 612), control flow of the method 600 returns to block 602, in which the interface operates in the lower power idle mode.

[0079] Turning now to Figure 8, a generalized block diagram of the signal waveform 700 is shown. In one embodiment, the time interval 710 represents the duration of the idle mode, while the time interval 720 represents the duration of data transmission on the bidirectional data line. The voltage level of the signal on the bidirectional data line is shown. During the idle mode, such as during each time interval 710, the bidirectional data line is held at a constant voltage level. During a first data transmission period, such as the first time interval 720, data is transmitted as a series of pulses. Instead of using a ground reference voltage level to measure the pulses, the same constant voltage level used during the previous idle mode is used. A voltage margin 730 is added to the voltage level of the idle mode to indicate the pulses. Conversely, during a second data transmission period, such as the second time interval 720, data is again transmitted as a series of pulses. Instead of using a ground reference voltage level to measure the pulses, the same constant voltage level used during the previous idle mode is used. The voltage margin 730 is removed from the voltage level of the idle mode to indicate the pulses.

[0080] Turning now to Figure 9 , a generalized block diagram of the I / O interface 800 of the host computing device (or interface 800) is shown. During the data transmission mode, the codec 874 receives data from the processing logic of the host computing device, such as the data on the data line 870 and the data line 872. When the communication protocol is the USB serial data communication protocol, the interface 800 receives two data signals. In other embodiments, another communication protocol and another number of data signal lines are used. In some embodiments, the data received on the data signal line 870 and the data signal line 872 is a differential signal, and the codec 874 converts these signals to digital signals, which are stored in the buffer 878 for later use in scheduling data transmission. As shown, the interface 800 receives a supply voltage 802, which is increased by a voltage boost 804, such as a buck-boost converter, to provide a voltage level 806. In some embodiments, the supply voltage 802 is 4.0 volts, and the voltage level 806 is two times the voltage margin greater than the supply voltage 802. When the voltage margin is 0.15 volts, the voltage level 806 is 4.30 volts. In some embodiments, the increase of the supply voltage level 802 to produce the voltage level 806 is programmable.

[0081] In one embodiment, the capacitor 808 is selected to have a large value to remove voltage variations on the voltage level 806. For example, in some embodiments, the capacitor 808 has a capacitance of 5 to 60 microfarads. In one embodiment, the interface 800 includes a circuit element that includes the switch 810 and has an input node connected to the input node 807, and has an output node connected to the output node 809. The circuit element receives the voltage level 806 on the input node 807 and provides a voltage level 840 on the output node 809. In one embodiment, the series of switches 810 includes a plurality of series connected switches to generate pulses on the output node 809 based on the voltage level 806 on the input node 807. In addition, the switches 810 generate pulses on the output node 809 based on inputs from a delay pulse modulator (DPM) 876 to a control circuit. In the illustrated embodiment, the control circuit for the switches 812-816 includes a switch 818 and a switch 820. However, in other embodiments, various other types of control circuits are used. In one embodiment, the plurality of series connected switches of the switch 810 are implemented by field effect transistors (FETs). While three transistors 812, 814, and 816 are shown, in other embodiments, other numbers of transistors are used. In one embodiment, the n-type transistor 812 (or nfet 812) is always enabled or always turned on, and includes one of a plurality of circuits for over current protection (OCP). In the illustrated embodiment, the nfet 814 is enabled and disabled by the switch 818, and the pfet 816 is enabled and disabled by the switch 820. In various embodiments, the switch 818 and the switch 820 are also implemented by transistors. The switch 818 and the switch 820 receive input values from the delay pulse modulator 876.

[0082] In various embodiments, the output node 809 of the switch 810 is connected to an external peripheral device via an external single data signal line. In various embodiments, the replication interface 800 is replicated and the data signal line is one of a plurality of data signal lines of an external bidirectional bus between the host computing device and the peripheral device. For ease of illustration, protection circuitry and noise reduction circuitry, such as passive devices like diodes, resistors, and capacitors, are not shown. The input node 807 of the switch 810, such as a terminal of the switch 812, receives a voltage level 806. Using the values of the previous example, the switch 812 receives 4.30 volts. When the interface 800 is operating in an idle mode, the switch 818 disables the nfet 814, which disconnects the switch 814, and causes the voltage level 806 to drive current through the series connected inductors 832-836 of the inductor 830. While three inductors are shown, in other embodiments, the inductor 830 includes another number of inductors. The inductor 830 reduces current ripple and increases the effective output impedance. The inductor 830 increases its voltage in response to any rapid changes (rate of change of time) in the current flowing through the inductor 830, and reduces the effective gate-source voltage of the pfet 816. The increase in the voltage of the inductor 830 also limits the change in current flowing from the voltage level 806 on the input node 807 to the voltage level 840 on the output node 809 when a pulse appears on the single data signal line connected to the external peripheral device.

[0083] Further, when the interface 800 is operating in the idle mode, the switch 820 selects the output of the operational amplifier 852 as the control input of the pfet 816. The control input of the pfet 816 is the gate terminal of the pfet 816. The operational amplifier 852 compares the voltage level 840 to the voltage level 806, which is less than the value of the variable voltage source 850. When the interface 800 is operating in the idle mode, the voltage source 850 is set to a voltage margin or 0.15 volts. Thus, the input to the operational amplifier is 4.30 volts, which is the value of the voltage level 806, less 0.15 volts, or 4.15 volts. When the voltage level 840 on the output node 809 is equal to the value of the other input of the operational amplifier 852 or 4.15 volts, the operational amplifier 852 does not amplify the difference. When the interface 800 is operating in a lower power idle mode, in one embodiment, the logic sets the programmable voltage source 850 to 0.25 volts, instead of 0.15 volts, which causes the operational amplifier 852 to control the switch 816 in a manner that provides a voltage level 840 of 4.05 volts. Thus, the interface 800 consumes less power during the lower power idle mode than during the idle mode. In other embodiments, the logic sets the programmable voltage source 850 to various other voltage levels.

[0084] When the interface 800 is operating in the data transmission mode, the switch 818 enables (closes) the switch 816, which causes the signal to bypass the inductor 830 and generate a series of pulses on the output node 809 having a value between the voltage level 806 (or 4.30 volts in one example) and the sum of the supply voltage and voltage margin (or 4.15 volts in one example). The pulses are sent from the output node 809 to the external peripheral device on a single data signal line. When the interface 800 is operating in the receive mode, pulses are received on the output node 809 at the switch 810 and are received by the operational amplifier 860. In various embodiments, the operational amplifier 860 has a faster response than the inductor 830. Thus, the operational amplifier 860 processes the received pulses on the output node 809 faster than the inductor 830.

[0085] In the receive mode, the switch 818 disables (opens) the switch 814 and connects the gate terminal of the pfet 816 to the control output of the delayed pulse modulator 876, rather than the output of the operational amplifier 852. The operational amplifier 860 compares the received pulses to the voltage level 806 (or 4.30 volts in one example). One or more of the delayed pulse modulator 876 and the codec 874 convert the pulses to a digital data signal, such as using the mappings previously described for the state table 150 Figure 2 ) and the state table 152. The converted data is stored in the buffer 878 for later transmission to the processing logic of the host computing device.

[0086] Turning now to Figure 10 , a generalized block diagram of the I / O interface 900 of a peripheral device (or interface 900) is shown. In various embodiments, the interface 900 includes the interface 800 previously described Figure 9Many of the components of interface 900 are similar to those of interface 800. However, in one embodiment, interface 900 does not use a booster, the polarity of programmable voltage source 950 is opposite to that of voltage source 850, and the order of switches 912, 914, and 916 is opposite to that of switches 812, 814, and 816. Switch 912 includes a reverse current protection (RCP) circuit instead of the over current protection (OCP) circuit used by switch 812. Using the earlier example values for the supply voltage and voltage margin, interface 900 generates pulses for data transmission between 4.0 volts and 4.15 volts, instead of between 4.15 volts and 4.30 volts as generated by interface 800. Operational amplifier 960 compares the pulses received from the external host computing device on a single data signal line to the supply voltage 902 (or 4.0 volts in one example). This comparison by operational amplifier 960 is in contrast to the comparison performed by operational amplifier 860 of interface 800, which compares the received pulses to the sum of the supply voltage and twice the voltage margin (or 4.3 volts in one example).

[0087] In some embodiments, the data received on data signal line 970 and data signal line 972 are differential signals, and codec 974 converts these signals to digital signals, which are stored in buffer 978 for later use in scheduling data transmissions. As shown, interface 900 receives supply voltage 902. In some embodiments, supply voltage 902 is 4.0 volts, and during an idle mode of operation, voltage level 906 is greater than supply voltage 902 by a voltage margin, which is also used by the external host computing device. When the voltage margin is 0.15 volts, voltage level 906 on switch output node 909 (or output node 909) is 4.15 volts when interface 900 is operating in idle mode. In one embodiment, capacitor 908 is selected to have a large value to remove voltage variations on supply voltage 902. For example, in some embodiments, capacitor 908 has a capacitance of 5 to 90 microfarads.

[0088] In one embodiment, interface 900 includes a circuit element that includes switches 910 and has an input node connected to input node 907 and has an output node connected to output node 909. The circuit element receives supply voltage 902 on input node 907 and provides voltage level 906 on output node 909. In one embodiment, the series of switches 910 includes a plurality of series-connected switches for generating pulses based on inputs from delay pulse modulator 976 to the control circuit. Similar to interface 500, the switches in interface 900 are implemented by transistors. While three transistors 912, 914, and 916 are shown, in other embodiments, other numbers of transistors are used. In the illustrated embodiment, the control circuit for switches 912-916 includes switch 918 and switch 920. However, in other embodiments, various other types of control circuits are used.

[0089] In one embodiment, n-type transistor 912 (or nfet 912) is always enabled or always on. In the illustrated embodiment, nfet 914 is individually enabled and disabled by switch 918, and pfet 916 is individually enabled and disabled by switch 920. In various embodiments, switches 918 and 920 are also implemented by transistors. Switches 918 and 920 receive input values from delay pulse modulator 976. In various embodiments, output node 909 of switches 910 is connected to an external host computing device via an external single data signal line. In various embodiments, interface 900 is replicated, and the data signal line is one of a plurality of data signal lines of an external bidirectional bus between the host computing device and the peripheral device. For ease of illustration, protection circuitry and noise reduction circuitry, such as passive devices like diodes, resistors, and capacitors, are not shown. Switch input node 907 (or input node 907) of switches 910, such as the terminal of switch 912, receives supply voltage 902. Using the values of the previous example, when interface 900 is operating in idle mode, switch 912 receives 4.0 volts on input node 907, and switch 916 provides 4.15 volts on output node 909.

[0090] When the interface 900 is operating in the idle mode, the switch 918 disables the nfet 914, which disconnects the switch 914, and causes the input voltage level 906 to drive current through the series-connected inductors 932 to 936 of the inductor 930. Although three inductors are shown, in other embodiments, the inductor 930 includes another number of inductors. The inductor 930 reduces current ripple and improves the effective output impedance. The inductor 930 increases its voltage in response to any rapid changes (rate of change of time) in the current flowing through the inductor 930, and reduces the effective gate-source voltage of the pfet 916. The increase in the voltage of the inductor 930 also limits the change in current flowing from the voltage level 906 to the supply voltage 902 when a pulse appears on the single data signal line connected to the external host computing device.

[0091] Furthermore, when the interface 900 is operating in the idle mode, the switch 920 selects the output of the operational amplifier 952 as the control input to the pfet 916. The control input to the pfet 916 is the gate terminal of the pfet 916. The operational amplifier 952 compares the voltage level 906 to the sum of the supply voltage 902 and the variable voltage source 950. In one embodiment, when the interface 900 is operating in the idle mode, the voltage source 950 is set to a voltage margin or 0.15 volts. Thus, when using the values of the previous example, the input to the operational amplifier 952 is the sum of 4.0 volts and 0.15 volts, or 4.15 volts. When the voltage level 906 is equal to this sum or 4.15 volts, the operational amplifier 952 does not amplify the difference. As previously described for the interface 500, when the interface 900 is operating in the lower power idle mode, in one embodiment, the logic sets the programmable voltage source 950 to 0.05 volts instead of 0.15 volts, which causes the operational amplifier 952 to control the switch 916 in a manner that provides a voltage level 906 of 4.05 volts. Thus, the interface 900 consumes less power during the lower power idle mode than during the idle mode. In other embodiments, the logic sets the programmable voltage source 950 to various other voltage levels.

[0092] When interface 900 is operating in data transmission mode, switch 918 enables (closes) switch 916, which causes the signal to bypass inductor 930 and generate a series of pulses on output node 909 having a value between the supply voltage (or 4.0 volts in one example) and the sum of the supply voltage and the voltage margin (or 4.15 volts in one example). The pulses are sent from output node 909 on a single data signal line to an external host computing device. When interface 900 is operating in receive mode, the pulses are received by operational amplifier 960. In various embodiments, operational amplifier 960 has a faster response than inductor 930. Thus, operational amplifier 960 processes the received pulses on output node 909 faster than inductor 930.

[0093] In receive mode, switch 918 disables (opens) switch 914 and connects the gate terminal of pfet 916 to the control output of delay pulse modulator 976, instead of the output of operational amplifier 952. Operational amplifier 960 compares the received pulses to supply voltage 902 (or 4.0 volts in one example). One or more of delay pulse modulator 976 and codec 974 convert the pulses to a digital data signal, such as using the mappings previously described for state table 150 Figure 2 ) and interface 800. The converted data is stored in buffer 978 for later transmission to the peripheral device's processing logic.

[0094] Methods 1000 and 1100 each describe an interface of a host computing device and a peripheral device when the interfaces are in any one of a plurality of idle modes or are transmitting data. When receiving data, the steps previously described for interfaces 800 and 900 are used. Referring now to Figure 11 , a generalized flow diagram of one embodiment of a method 1000 for efficiently transmitting data between devices is shown. Interface logic of a host computing device for a bidirectional signal line receives a supply voltage level (block 1002). A boost converter generates a first voltage level that is two times a voltage margin greater than the supply level (block 1004). In one embodiment, the boost converter is a direct current (DC) to DC buck-boost converter.

[0095] A series of switches of the interface logic receives a first voltage level at an input node (block 1006). In one embodiment, the series of switches is two or more transistors, such as field effect transistors (FETs), connected in series. One of the switches is connected in electrical parallel configuration with one or more inductors connected in series. When the switch is closed, an electrical signal flows through the switch, rather than through the inductors connected in series. If the operating mode of the host computing device is the lower power idle mode (the "lower power idle mode" branch of conditional block 1008), the interface of the host computing device generates a second voltage level that is between the power supply voltage level and the sum of the power supply voltage and a voltage margin (block 1010). As previously described, using the previous example of values, the interface generates the second voltage level as a voltage level that is greater than or equal to 4.0 volts and less than 4.15 volts. The interface maintains the second voltage level at an output of the interface (block 1012).

[0096] If the operating mode of the host computing device is the idle mode (the "idle mode" branch of conditional block 1008), the interface generates a third voltage level that is greater than the power supply voltage level by the voltage margin (block 1014). As previously described, using the previous example of values, the interface generates the third voltage level as the sum of 4.0 volts and 0.15 volts, or 4.15 volts. The interface maintains the third voltage level at an output of the interface (block 1016).

[0097] If the operating mode of the host computing device is the data transfer mode (the "data transfer mode" branch of conditional block 1008), the interface generates a first series of pulses based on the power supply voltage level and data to be transferred (block 1018). In one embodiment, a delay pulse modulator retrieves the data from a buffer. The data was previously converted by a codec from two separate analog differential signals into a single digital signal, and a representation of the single digital signal or pulses is stored in the buffer. The delay pulse modulator sends the pulses to a control circuit of the series of switches.

[0098] In one embodiment, one switch in the series is connected in parallel configuration with one or more series-connected inductors. During either idle mode, the switch is open, which causes the signal to be routed through the one or more series-connected inductors. During the data transfer mode, the switch is closed, which causes the signal to bypass the one or more series-connected inductors. The series of switches generates a second series of pulses between the second voltage level and the third voltage level based on the data to be transferred (block 1020). The second series of pulses also depends on the control circuit. Using the previous example of values, the interface generates a series of pulses between 4.15 volts and 4.30 volts. The receive logic converts the pulses on the single data signal line into two or more data signals to be stored in the buffer. When the communication protocol is the USB serial data communication protocol, the receive logic converts the pulses into two data signals.

[0099] Referring now to Figure 12 , a generalized flow diagram of one embodiment of a method 1100 for efficiently transferring data between devices is shown. The interface logic of a peripheral device for a bidirectional signal line receives a power supply voltage level (block 1102). A series of switches of the interface logic receives a first voltage level at an input node (block 1104). In various embodiments, the series of switches has a mirrored configuration of a series of switches in a host computing device. If the operating mode of the peripheral device is a lower power idle mode (the "lower power idle mode" branch of conditional block 1106), the interface generates a first voltage level between the power supply voltage level and the sum of the power supply voltage and a voltage level less than a voltage margin (block 1108). As previously described, using the previous example of values, the interface of the peripheral device generates the first voltage level as a voltage level greater than or equal to 4.0 volts and less than 4.15 volts. The interface maintains the first voltage level at an output of the interface (block 1110).

[0100] If the operating mode of the host computing device is an idle mode (the "idle mode" branch of conditional block 1108), the interface generates a second voltage level that is greater than the power supply voltage level by the voltage margin (block 1112). As previously described, using the previous example of values, the interface generates the third voltage level as the sum of 4.0 volts and 0.15 volts or 4.15 volts. The interface maintains the second voltage level at an output of the interface (block 1114).

[0101] If the operating mode of the host computing device is the data transfer mode (the "data transfer mode" branch of conditional block 1108), the interface generates a first series of pulses based on the power supply voltage level and the data to be transferred (block 1116). The series of switches generates a second series of pulses between the power supply voltage level and a second voltage level based on the data to be transferred (block 1118). The second series of pulses also depends on the control circuit. Using the previous example of values, the interface of the peripheral device generates a series of pulses between 4.0 volts and 4.15 volts. The receive logic converts the pulses on the single data signal line into two or more data signals to be stored in the buffer. When the communication protocol is the USB serial data communication protocol, the receive logic converts the pulses into two data signals.

[0102] Turning now to Figure 13 , a generalized block diagram of an I / O interface 1200 between a host computing device and a peripheral device is shown. The I / O interface 1200 can also be referred to as the interface 1200. In the illustrated embodiment, the host computing device is shown on the left and the peripheral device is shown on the right. However, in other embodiments, this placement is reversed and the components are switched. As shown, the host computing device and the peripheral device communicate across a signal line between pin 1210 and pin 1240 and between pin 1212 and pin 1242. In one embodiment, the signal line between pin 1210 and pin 1240 transmits data in the form of pulses, while the signal line between pin 1212 and pin 1242 transmits a ground reference voltage level. In various embodiments, the interface 1200 includes many of the components of the previously described interfaces 800 and 900 Figure 9 and Figure 10 ).

[0103] In some embodiments, the power supply voltage 1202 is 4.0 volts and no voltage booster is used. Similar to the inductor 830 described earlier with respect to the interface 800, the inductor 1204 reduces current ripple and boosts the effective output impedance. The inductor 1204 increases its voltage in response to any rapid changes (rate of change of time) in the current flowing through the inductor 1204. The voltage increase of the inductor 1204 also limits the current change from the power supply voltage 1202 to the voltage level on the node 1206 when a pulse appears on the single data signal line between pin 1210 and pin 1240. The inductor 1234 has similar behavior to the inductor 1204. The capacitor 1208 is an alternating current (AC) coupling capacitor. The capacitor 1208 couples the node 1206 from the AC signals between the delay pulse modulator 1220 and the delay pulse modulator 1222. The capacitor 1208 prevents direct current (DC) signals from passing through, while only allowing AC signals to pass through. The capacitor 1238 has similar behavior to the capacitor 1208.

[0104] The host computing device includes a transmit delay pulse modulator (DPM) 1220 and a receive DPM 1222. During a data transfer mode, a codec (not shown) receives data from the processing logic of the host computing device. As previously described, in some embodiments, a USB serial data communication protocol is used. In one embodiment, the processing logic of the host computing device provides a differential signal to the codec, which converts the signal to a digital signal. The transmit DPM 1220 delivers the digital signal as pulses on node 1206.

[0105] Briefly referring to data transfer 100 and data transfer 200 (of Figure 1 and Figure 3 In one embodiment, the transmitter continues to send pulses, but in some embodiments, the transmitter sends both positive and negative pulses, rather than just positive pulses. Examples of these pulses are provided in Figure 14 to Figure 15 In one embodiment, the transmit DPM 1220 of interface 1200 receives data, such as data 202 and data 204 (of Figure 3 and delivers both positive and negative pulses. Control logic in the peripheral device interprets the series of positive and negative pulses from the transmit DPM 1220 as symbols. In one embodiment, the control logic in the peripheral device uses a symbol generation table 150 (of Figure 2 ) to map 2-bit previous pin states to 2-bit current pin states. Table 150 performs the mapping based on the number and order of positive and negative pulses received on a single data signal line during a time interval. The transmit DPM 1250 in the peripheral device has similar behavior as the transmit DPM 1220.

[0106] When the host computing device is operating in a receive mode, pulses are received on node 1206 and by receive DPM 1222. In various embodiments, the receive DPM 1222 and any input circuitry (not shown), such as one or more buffers, operational amplifiers, or other input circuitry, has a faster response than inductor 1204. Thus, the receive DPM 1222 processes received pulses on node 1206 faster than inductor 1204. One or more of the receive DPM 1222 and any codec (not shown) converts the pulses to a digital data signal, such as using the mapping as previously described for symbol table 150 (of Figure 2 In one embodiment, the converted data is stored in a buffer for later transmission to the processing logic of the host computing device. In various embodiments, the receive DPM 1252 in the peripheral device has similar behavior as the receive DPM 1222.

[0107] Turning now to Figure 14, shows a generalized block diagram of one embodiment of symbol mapping 1300. In various embodiments, symbol mapping 1300 is associated with ( Figure 2 The same table 150 is used with the symbol map 1300, but the symbol map 1300 is used with the ( Figure 2 Unlike symbol mapping 160, symbol mapping 1300 uses both positive and negative pulses instead of only positive pulses. In one embodiment, using ( Figure 12 The transmitter and receiver of interface 1200 also use table 150 and symbol map 1300 to support transmission of parallel multi-bit data as serial data on a single data line. In various embodiments, each of the transmitter and receiver uses a copy of table 150 and symbol map 1300. The transmitter determines when it is time to send data based on various conditions. When the transmitter has parallel multi-bit data to send to the receiver, the transmitter divides the parallel multi-bit data into consecutive parts or segments. Each segment has the current pin state. In one embodiment, each segment has 2 bits. In other embodiments, each segment has another number of parallel multiple bits.

[0108] The transmitter maintains the previous pin state, which was the current pin state during the previous data transmission. Using table 150, the transmitter's control logic identifies the rows of table 150 based on the previous pin state and the columns based on the current pin state. The transmitter's logic uses the resulting symbol and symbol map 1300 to determine the number and order of positive and negative pulses to be sent within the time interval to represent the current pin state. For example, when the previous pin state was 2'b01 and the current pin state to be sent is 2'b10, the transmitter's control logic uses table 150 to identify the symbol "D." The control logic uses symbol map 1300 to determine the symbol "D," which represents three iterations of a positive pulse followed by a negative pulse, to be sent to the receiver on the serial data line. Alternatively, the symbol "D" represents three iterations of a negative pulse followed by a positive pulse, to be sent to the receiver on the serial data line. The receiver includes one of a variety of detection circuits for interpreting the received symbol "D." In some embodiments, an alternative representation of the symbol "D" is used to allow additional sideband data to be sent simultaneously with the data transmission on the serial data line. Similarly, the symbols "B" and "C" have alternative representations that will be used for sideband data transmission.

[0109] In one embodiment, when the transmitter does not send a pulse during the time interval, the current pin state is equal to the previous pin state. This mapping is represented by the top row of symbol map 1300 and the symbol "A" in table 150. Symbol map 1300 maps no pulse or zero pulse to symbol "A". When the transmitter sends a pulse mapped to symbol "B" during the time interval, only a specific bit of the current pin state changes. In some embodiments, the specific bit is the least significant bit indicated as "b1" in table 150. In other embodiments, the specific bit is the most significant bit indicated as "b0" in table 150. In some embodiments, ( Figure 4 Method 300 uses symbol map 1300 instead of symbol map 160 to convert data transmitted on the serial data line. In addition, in one embodiment, computing system 500 uses symbol map 1300 to perform data transmission on the serial data line.

[0110] Now turn Figure 15 , shows a generalized block diagram of one embodiment of symbol mapping 1400. In various embodiments, symbol mapping 1400 is associated with ( Figure 2 Similar to symbol map 1300, symbol map 1400 uses both positive and negative pulses instead of only positive pulses. In one embodiment, using ( Figure 12 The transmitter and receiver of the interface 1200 also use table 150 and symbol mapping 1400 to support parallel multi-bit data transmitted as serial data on a single data line. In one embodiment, at least the symbol "D" of symbol mapping 1400 is different from the corresponding symbol "D" of symbol mapping 1300. For example, an example of symbol "D" of symbol mapping 1400 uses two positive pulses, such as symbol "C", but the two positive pulses are separated by two consecutive negative pulses. In other embodiments, one or more other symbols of symbol mapping 1400 are different from the corresponding symbols of symbol mapping 1300. Similar to symbol mapping 1300, symbol mapping 1400 uses an alternative representation of symbols. In one embodiment, the alternative symbol representation allows additional sideband data to be sent simultaneously with the data transmission on the serial data line. In some embodiments, ( Figure 4 Method 300 uses symbol map 1400 to convert data transmitted on a serial data line instead of symbol map 160 or symbol map 1300. Additionally, in one embodiment, computing system 500 uses symbol map 1400 to perform data transmission on a serial data line.

[0111] In various embodiments, program instructions of a software application can be used to implement the previously described methods and / or mechanisms. The program instructions can describe the behavior of hardware in a high-level programming language, such as C. Alternatively, a hardware design language (HDL) such as Verilog can be used. The program instructions can be stored on a non-transitory computer-readable storage medium. Many types of storage media are available. The storage medium can be accessed by a computer during use to provide the program instructions and accompanying data to the computer for program execution. In some embodiments, a synthesis tool reads the program instructions in order to generate a netlist including a gate list from a synthesis library.

[0112] It should be emphasized that the above-described embodiments are only non-limiting examples of specific implementations, and that many variations and modifications will become apparent to those skilled in the art once informed of the above disclosure. The disclosure is intended to be interpreted broadly within the terms of the attached claims, including all such variations and modifications.

Claims

1. A device, comprising: an interface configured to transmit data over one or more bidirectional lines; and control circuit; and The control circuit is configured as follows: maintaining a first voltage level greater than a power supply voltage level on the one or more bidirectional lines via the interface in response to detecting a first idle pattern; and In response to detecting a data transmission mode, a first number of encoded pulses are generated on the one or more bidirectional lines via the interface, each encoded pulse having a first voltage swing that is less than a second voltage swing between a ground reference voltage level and the power supply voltage level.

2. The apparatus of claim 1 , wherein the control circuit is further configured to, in response to detecting that the data transmission mode is a first data transmission mode in which the apparatus is used as a transmitter, generate the first number of pulses, each pulse being between the first voltage level and a second voltage level greater than the first voltage level.

3. The apparatus of claim 2 , wherein the control circuit is further configured to, in response to detecting that the data transmission mode is a second data transmission mode in which the apparatus is used as a receiver, receive a second number of coded pulses on the one or more bidirectional lines via the interface, each coded pulse being between the first voltage level and the supply voltage level.

4. The apparatus of claim 1 , wherein the control circuit is further configured to maintain a third voltage level on the one or more bidirectional lines via the interface that is greater than a power supply voltage level and less than the first voltage level in response to detecting a second idle mode that consumes less power than the first idle mode. The apparatus of claim 2 , wherein the first voltage level is greater than the power supply voltage level by a voltage margin. The apparatus of claim 5 , wherein the second voltage level is greater than the first voltage level by the voltage margin.

7. The apparatus of claim 1, wherein the control circuit is further configured to store received data for transmission in response to detecting that the data transmission mode does not utilize the apparatus as a transmitter.

8. A method comprising: The host computing device transmits data to the peripheral device on a bidirectional line; maintaining, by the host computing device, a first voltage level on the bidirectional line that is greater than a power supply voltage level in response to detecting a first idle pattern; as well as In response to detecting a data transmission mode, a first number of encoded pulses are generated by the host computing device on the bidirectional line, each encoded pulse having a first voltage swing that is less than a second voltage swing between a ground reference voltage level and the power supply voltage level.

9. The method according to claim 8, further comprising: In response to detecting that the data transmission mode is a first data transmission mode using the host computing device as a transmitter, the host computing device generates the first number of pulses on the bidirectional line, each pulse being between the first voltage level and a second voltage level greater than the first voltage level.

10. The method according to claim 9, further comprising: In response to detecting that the data transmission mode is a second data transmission mode using the host computing device as a receiver, a second number of encoded pulses are received by the host computing device on the bidirectional line, each encoded pulse being between the first voltage level and the supply voltage level.

11. The method according to claim 8, further comprising: In response to detecting a second idle mode that consumes less power than the first idle mode, a third voltage level greater than a power supply voltage level and less than the first voltage level is maintained on the bidirectional line by the host computing device. 12 . The method of claim 9 , wherein the first voltage level is greater than the power supply voltage level by a voltage margin. The method of claim 12 , wherein the second voltage level is greater than the first voltage level by the voltage margin.

14. The method according to claim 8, further comprising: In response to detecting that the data transmission mode does not utilize the host computing device as a receiver, the received data is stored by the peripheral device for transmission.

15. A bidirectional signal interface, comprising: host computing device; peripheral devices; and a bidirectional data line between the host computing device and the peripheral device; and Wherein, the host computing device is configured to: In response to detecting a first idle pattern, maintaining a first voltage level greater than a power supply voltage level on the bidirectional data line; and In response to detecting a data transmission mode, a first number of encoded pulses are generated on the bidirectional data line, each encoded pulse having a first voltage swing that is less than a second voltage swing between a ground reference voltage level and the power supply voltage level.

16. The bidirectional signal interface of claim 15 , wherein the host computing device is further configured to generate the first number of pulses, each pulse being between the first voltage level and a second voltage level greater than the first voltage level, in response to detecting that the data transmission mode is a first data transmission mode in which the host computing device is used as a transmitter.

17. The bidirectional signal interface of claim 16 , wherein the host computing device is further configured to receive a second number of encoded pulses on the bidirectional data line, each encoded pulse being between the first voltage level and the power supply voltage level, in response to detecting that the data transmission mode is a second data transmission mode in which the host computing device functions as a receiver.

18. The bidirectional signal interface of claim 15 , wherein the host computing device is further configured to maintain a third voltage level on the bidirectional data line that is greater than a power supply voltage level and less than the first voltage level in response to detecting a second idle mode that consumes less power than the first idle mode.

19. The bidirectional signal interface according to claim 16, wherein the first voltage level is greater than the power supply voltage level by a voltage margin.

20. The bidirectional signal interface of claim 19, wherein the second voltage level is greater than the first voltage level by the voltage margin.

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