Crosspoint array architecture for multiple levels of layers

Abstract

This application relates to cross-point array architectures for multiple tiers. A memory array can include multiple tiers, such as six or eight tiers. The memory array can also include slots for coupling access lines with associated decoders. The slots can be included in sub-blocks of the array. A sub-block can be configured to include slots for multiple access lines. The slots can intersect the access lines in the middle of the access lines or at the ends of the access lines. Sub-blocks containing slots for access lines can be separated by cycles based on the access lines.

Description

[0001] Cross-reference

[0002] This patent application is a national stage application of International Patent Application No. PCT / US2022 / 077576, filed October 5, 2022, entitled CROSS POINT ARRAY ARCHITECTURE FOR MULTIPLE DECKS, by Pirovano et al., which claims priority to U.S. Patent Application No. 17 / 499,707, filed October 12, 2021, entitled CROSS POINT ARRAY ARCHITECTURE FOR MULTIPLE DECKS, by Pirovano et al., which is assigned to the assignee hereof and is expressly incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The technical field relates to cross point array architecture for multiple decks. BACKGROUND

[0004] Memory devices are widely used to store information in electronic devices such as computers, user devices, wireless communications devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, an individual memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selecting memory, chalcogenide memory technology, and the like. Memory cells can be volatile or non-volatile. SUMMARY

[0006] A device is described. The device can include a memory array having a plurality of tiers and a plurality of bit lines, each of the plurality of bit lines coupled with one or more tiers of the plurality of tiers, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line; a plurality of bit line decoders positioned beneath the memory array; and a plurality of bit line vias comprising: a first subset of bit line vias arranged according to a first periodicity and coupling respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders; a second subset of bit line vias arranged according to a second periodicity and coupling respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders; and a third subset of bit line vias arranged according to the second periodicity and coupling respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders.

[0007] A device is described. The device can include a plurality of tiles of a memory array, each tile of the plurality of tiles comprising a plurality of sub-blocks and a plurality of tiers, wherein each sub-block of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, each of the plurality of bit lines coupled with one or more tiers of the plurality of tiers, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line; and a plurality of bit line decoders positioned beneath the memory array, wherein a first bit line decoder of the plurality of bit line decoders is coupled with the first bit line using a first configuration of vias within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with the second bit line using a second configuration of vias within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with the third bit line using a third configuration of vias within a third subset of the plurality of sub-blocks.

[0008] A method is described. The method can include identifying at least one cell of a memory array having a plurality of levels, a plurality of word lines, a plurality of word line decoders, a plurality of bit lines, and a plurality of bit line decoders positioned below the memory array, each of the plurality of bit lines coupled with a respective one or more of the plurality of levels, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line; and accessing the at least one cell of the memory array using one of the plurality of word line decoders and one of the plurality of bit line decoders, wherein the each of the plurality of bit lines is coupled with a respective bit line decoder using a plurality of bit line vias, wherein the plurality of bit line vias comprises: a first subset of bit line vias arranged according to a first periodicity and coupling respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders; a second subset of bit line vias arranged according to a second periodicity and coupling respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders; and a third subset of bit line vias arranged according to the second periodicity and coupling respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders.

[0009] A method is described. The method can include identifying at least one cell of a memory array comprising a plurality of tiles, each tile of the plurality of tiles comprising a plurality of sub-blocks and a plurality of levels, wherein each sub-block of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, the plurality of bit lines comprising: a first bit line coupled with a first level and a second level of the plurality of levels; a second bit line coupled with a third level and a fourth level of the plurality of levels; and a third bit line coupled with a fifth level and a sixth level of the plurality of levels; and accessing the at least one cell of the memory array using a plurality of bit line decoders positioned below the memory array, wherein a first bit line decoder of the plurality of bit line decoders is coupled with the first bit line using a first configuration of vias within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with the second bit line using a second configuration of vias within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with the third bit line using a third configuration of vias within a third subset of the plurality of sub-blocks. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 Examples of systems supporting cross-point array architectures for multiple levels are described in accordance with examples as disclosed herein.

[0011] Figure 2 Examples of memory dies supporting cross-point array architectures for multiple levels are described in accordance with examples as disclosed herein.

[0012] Figure 3 An example of a memory cell supporting a cross-point array architecture for multiple levels of memory is illustrated in accordance with examples as disclosed herein.

[0013] Figure 4 An example of a set of levels supporting a cross-point array architecture for multiple levels of memory is illustrated in accordance with examples as disclosed herein.

[0014] Figure 5 An example of a top view of a memory array supporting a cross-point array architecture for multiple levels of memory is illustrated in accordance with examples as disclosed herein.

[0015] Figure 6 An example of a top view of a memory array supporting a cross-point array architecture for multiple levels of memory is illustrated in accordance with examples as disclosed herein.

[0016] Figure 7 An example of a top view of a memory array supporting a cross-point array architecture for multiple levels of memory is illustrated in accordance with examples as disclosed herein.

[0017] Figure 8 An example of a top view of a memory array supporting a cross-point array architecture for multiple levels of memory is illustrated in accordance with examples as disclosed herein.

[0018] Figure 9 An example of a top view of a memory array supporting a cross-point array architecture for multiple levels of memory is illustrated in accordance with examples as disclosed herein.

[0019] Figure 10 A block diagram illustrating a periodic access operation manager supporting a cross-point array architecture for multiple levels of memory is shown in accordance with examples as disclosed herein.

[0020] Figure 11 A block diagram illustrating a configuration access operation manager supporting a cross-point array architecture for multiple levels of memory is shown in accordance with examples as disclosed herein.

[0021] Figure 12 and 13 A flow diagram illustrating one or more methods supporting a cross-point array architecture for multiple levels of memory is shown in accordance with examples as disclosed herein. DETAILED DESCRIPTION

[0022] Some memory systems, such as cross-point memory systems, can include more than four levels, such as a cross-point memory system using six or eight levels. However, the commercial viability of increasing the number of levels is impacted by yield. As yield improves and substrate costs increase, the additional cost of including more than four levels can prove to be justified by the increase in memory cell density. Memory systems including more than four levels can use an increased number of decoders to access and decode additional access lines, such as bit lines. Including additional access lines can be challenging because the arrangement of vias coupling the access lines to respective decoders can become complex. The vias can include one or more vias that extend vertically through the levels to couple the access lines to decoders positioned below the memory array. Techniques to highly couple access lines to decoders in cross-point systems including more than four levels are desired.

[0023] The present disclosure describes cross-point memory systems supporting more than four levels using novel via configurations. For example, a memory array of a memory system can be divided into a grid of sub-blocks. Each sub-block can contain a via for one or more access lines in a plurality of levels of the memory array (e.g., a sub-block can contain a single via for a first bit line, or a sub-block can contain vias for a first bit line and a second bit line). Additionally or alternatively, a sub-block can not contain any vias. The sub-blocks can be arranged according to one or more periodicities. For example, sub-blocks containing a via for a first access line can be arranged according to a first periodicity, while sub-blocks containing a via for a second access line can be arranged according to a second periodicity.

[0024] Additionally or alternatively, a via coupling an access line to an associated driver can intersect the access line at a middle of the access line or at an end of the access line. As used herein, a via located at an end of an access line segment can not mean that the via is located at the physical end of the segment, but rather that no memory device is coupled to the segment on the other side of the via. Similarly, a via located at a middle of an access line segment can not mean that the via is located at the center of the segment, but rather that at least one memory device is coupled to the segment on both sides of the via.

[0025] Features of the present disclosure are initially described in the context of a memory system, die, and array as described with reference to Figures 1 to 3 Features of the present disclosure are described in the context of a set of levels and a top view of a memory array as described with reference to Figures 4 to 9 Features of the present disclosure are described in the context of a set of levels and a top view of a memory array as described with reference to Figures 10 to 13 These and other features of the present disclosure are further illustrated by and described with reference to apparatus diagrams and flowcharts relating to cross-point array architectures for multiple levels as described with reference to

[0026] Figure 1Examples are described in accordance with which a system 100 supporting a crosspoint array architecture for multiple levels is implemented as disclosed herein. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. The system 100 can include one or more memory devices, but aspects of the one or more memory devices 110 can be described in the context of a single memory device, such as the memory device 110.

[0027] The system 100 can include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular telephone, a wearable device, an internet-connected device, a vehicle controller, or the like. The memory device 110 can be a component of the system that is operable to store data for one or more other components of the system 100.

[0028] At least portions of the system 100 can be an example of the host device 105. The host device 105 can be an example of a processor or other circuitry within a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular telephone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, the host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 can be referred to as a host or host device 105.

[0029] The memory device 110 can be a standalone device or component that is operable to provide physical memory addresses / space that can be used or referenced by the system 100. In some examples, the memory device 110 can be configurable to work with one or more different types of host devices 105. Signaling between the host device 105 and the memory device 110 can be operable to support one or more of: a modulation scheme used to modulate signals; various pin configurations used to communicate signals; various form factors of physical packaging of the host device 105 and the memory device 110; clock signaling and synchronization between the host device 105 and the memory device 110; timing conventions; or other factors.

[0030] Memory device 110 can be operable to store data for components of host device 105. In some examples, memory device 110 can act as a secondary or slave device (e.g., responsive to and executing commands provided by host device 105 through external memory controller 120) of host device 105. Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0031] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). Components of host device 105 can be coupled with each other using bus 135.

[0032] Processor 125 can be operable to provide control or other functionality for at least part of system 100 or at least part of host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 can be implemented by or be part of processor 125.

[0033] BIOS component 130 can be a software component that includes a BIOS operating as firmware that can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and the various components of system 100 or host device 105. BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile storage.

[0034] Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 can be a set of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections), where each memory cell is operable to store at least one data bit. A memory device 110 including two or more memory dies 160 can be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0035] Memory die 160 can be an instance of a two-dimensional (2D) memory cell array or can be an instance of a three-dimensional (3D) memory cell array. A 2D memory die 160 can include a single memory array 170. A 3D memory die 160 can include two or more memory arrays 170 that can be stacked on top of each other or positioned next to each other (e.g., relative to a substrate). In some examples, a memory array 170 in a 3D memory die 160 can be referred to as a tier, level, layer, or die. A 3D memory die 160 can include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory dies 160, different tiers can share at least one common access line such that some tiers can share one or more of row lines or column lines.

[0036] Device memory controller 155 can include circuitry, logic, or components operable to control operations of memory device 110. Device memory controller 155 can include hardware, firmware, or instructions that enable memory device 110 to perform various operations, and can be operable to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 can be operable to communicate with external memory controller 120, one or more memory dies 160, or one or more of processor 125. In some examples, device memory controller 155 can control operations of memory device 110 described herein in connection with local memory controllers 165 of memory dies 160.

[0037] In some examples, the memory device 110 can receive data or commands, or both, from the host device 105. For example, the memory device 110 can receive a write command instructing the memory device 110 to store data of the host device 105 or a read command instructing the memory device 110 to provide data stored in the memory die 160 to the host device.

[0038] The local memory controller 165 (e.g., local to the memory die 160) can include circuitry, logic, or components operable to control operations of the memory die 160. In some examples, the local memory controller 165 can be operable to communicate (e.g., receive or transmit data or commands, or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155 and the local memory controller 165, or the external memory controller 120 can perform various functions described herein. As such, the local memory controller 165 can be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165, or both, can include a receiver to receive signals (e.g., from the external memory controller 120), a transmitter to transmit signals (e.g., to the external memory controller 120), a decoder to decode or demodulate received signals, an encoder to encode or modulate signals to be transmitted, or various other circuitry or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0039] The external memory controller 120 can be operable to enable communication of one or more of information, data, or commands between components of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 can convert or translate communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 described herein, or other components of the system 100 or the host device 105, or functions thereof, can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 described herein, or functions thereof, can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0040] The components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. A signal path can be an example of an electrically conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of an electrically conductive input or output point of a device of the system 100, and a pin can be operable to act as part of a channel.

[0041] The channels 115 (and associated signal paths and terminals) can be dedicated to communicating one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be communicated via the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0042] In some cases, the memory device 110 can support the memory array 170 by adjusting a slot configuration of the memory array 170 having more than four levels. For example, the memory array 170 can be divided into a grid of sub-blocks. Each sub-block can contain a slot for one or more access lines in the multiple levels of the memory array (e.g., a sub-block can contain a single slot for a first bit line, or a sub-block can contain slots for a first bit line and a second bit line). Additionally or alternatively, a sub-block can not contain any slots. The sub-blocks can be arranged according to one or more periods. For example, sub-blocks containing slots for a first access line can be arranged according to a first period, while sub-blocks containing slots for a second access line can be arranged according to a second period.

[0043] Additionally or alternatively, the slots that couple an access line to the associated drivers can intersect the access line in the middle of the access line or at an end of the access line. It should be noted that although the slots are shown as being located at the ends of the access lines, the slots can be located at any suitable location along the access lines. Figure 1Storage using chalcogenide materials is described, but the techniques described herein can be applicable to any memory type using self-selecting memory materials or cross-point type architectures.

[0044] Figure 2 Examples of a memory die 200 supporting cross-point array architectures for multiple levels are described in accordance with examples as disclosed herein. The memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus, with reference to Figure 1 Examples of a memory die 160 are described. In some examples, the memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 can include one or more memory cells 205 that can each be programmable to store different logic states (e.g., a programmed one of a set of two or more possible states). For example, the memory cells 205 can be operable to store one bit of information (e.g., a logic 0 or a logic 1) at a time. In some examples, the memory cells 205 (e.g., multi-level memory cells 205) can be operable to store more than one bit of information (e.g., logic 00, logic 01, logic 10, logic 11) at a time. In some examples, the memory cells 205 can be arranged in an array, such as with reference to Figure 1 A memory array 170 is described.

[0045] The memory cells 205 can store logic states using configurable materials (which can be referred to as memory elements, memory storage elements, material elements, material memory elements, material portions, or polarity- written material portions, among others). The configurable materials of the memory cells 205 can refer to chalcogenide-based storage components, such as with reference to Figure 3 are described in greater detail. For example, chalcogenide storage elements can be used in phase change memory (PCM) cells, thresholding memory cells, or self-selecting memory cells.

[0046] The memory die 200 can include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern (e.g., a grid-like pattern). The access lines can be formed of one or more conductive materials. In some examples, the row lines 210 can be referred to as word lines. In some examples, the column lines 215 can be referred to as digit lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or their analogs, are interchangeable without loss of understanding or operation. The memory cells 205 can be positioned at intersections of the row lines 210 and the column lines 215.

[0047] Operations such as reads and writes can be performed on the memory cells 205 by activating or selecting an access line, such as one or more of the row lines 210 or the column lines 215. A single memory cell 205 can be accessed at the intersection of a row line 210 and a column line 215 by biasing them, such as applying a voltage to the row line 210 or the column line 215. The intersection of a row line 210 and a column line 215, whether in two dimensions or three dimensions, can be referred to as an address of a memory cell 205. An access line can be an electrically conductive line coupled with a memory cell 205 and can be used to perform an access operation on the memory cell 205.

[0048] Accessing the memory cells 205 can be controlled by the row decoder 220 or the column decoder 225. For example, the row decoder 220 can receive a row address from the local memory controller 245 and activate a row line 210 based on the received row address. The column decoder 225 can receive a column address from the local memory controller 245 and can activate a column line 215 based on the received column address.

[0049] The sense component 230 can be operable to detect a state of the memory cell 205 (e.g., material state, resistance, threshold state) and determine a logic state of the memory cell 205 based on the stored state. The sense component 230 can include one or more sense amplifiers to amplify or otherwise convert signals resulting from accessing the memory cell 205. The sense component 230 can compare a signal detected from the memory cell 205 to a reference 235 (e.g., a reference voltage). The detected logic state of the memory cell 205 can be provided as an output of the sense component 230 (e.g., to the input / output 240) and can be indicated to another component of a memory device including the memory die 200.

[0050] The local memory controller 245 can control access of the memory cells 205 through various components, such as the row decoder 220, the column decoder 225, the sense component 230. The local memory controller 245 can be a reference Figure 1An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, the column decoder 225, and the sense component 230 can be co-located with the local memory controller 245. The local memory controller 245 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., the external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 245 can generate row signals and column address signals to activate a target row line 210 and a target column line 215. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein can vary and can differ for the various operations discussed in operating the memory die 200.

[0051] The local memory controller 245 can be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations can include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, the access operations can be performed or otherwise coordinated by the local memory controller 245 in response to various access commands (e.g., from the host device 105). The local memory controller 245 can be operable to perform other access operations not listed here or other operations related to the operation of the memory die 200 but not directly related to accessing the memory cells 205.

[0052] In some cases, the memory die 200 can support more than four levels by adjusting the slot configuration of the memory die 200. For example, the memory die 200 can be divided into a grid of sub-blocks. Each sub-block can contain a slot (e.g., a sub-block can contain a single slot for a first bit line, or a sub-block can contain slots for a first bit line and a second bit line) for one or more access lines (e.g., row lines 210 or column lines 215) in a multi-level of a decoder (e.g., the row decoder 220, the column decoder 225, or both). Additionally or alternatively, a sub-block can not contain any slots. The sub-blocks can be arranged according to one or more periods. For example, sub-blocks containing slots for a first access line can be arranged according to a first period, while sub-blocks containing slots for a second access line can be arranged according to a second period.

[0053] Additionally or alternatively, the slot holes coupling the access lines to the associated drivers can intersect the access lines in the middle of the access lines or at the ends of the access lines. It should be noted that although Figure 2 Storage using chalcogenide materials is described, but the techniques described herein can be applicable to any memory type using self-selecting memory materials or cross-point type architecture.

[0054] Figure 3 An example of a memory array 300 according to examples as disclosed herein is described. The memory array 300 can be a reference Figure 1 and 2 An example of a portion of a memory array or memory die is described. The memory array 300 can include a first level 305 of memory cells positioned above a substrate (not shown) and a second level 310 of memory cells on top of the first array or level 305. Although the example of the memory array 300 includes two levels 305, 310, the memory array 300 can include any number of levels (e.g., one or more than two).

[0055] The memory array 300 can also include row lines 210-a, 210-b, 210-c, 210-d, column lines 215-a, and 215-b, which can be examples of row lines 210 and column lines 215 as described with reference to Figure 2 The first level 305 and the second level 310 of one or more memory cells can include one or more chalcogenide materials in the pillars between the access lines. For example, a single stack between the access lines can include one or more of a first electrode, a first chalcogenide material (e.g., a selector component), a second electrode, a second chalcogenide material (e.g., a storage element), or a third electrode. Although some elements included in Figure 3 Although some elements included in

[0056] The one or more memory cells of the first level 305 can include one or more of the electrode 325-a, the storage element 320-a, or the electrode 325-b. The one or more memory cells of the second level 310 can include the electrode 325-c, the storage element 320-b, and the electrode 325-d. The storage element 320 can be an example of a chalcogenide material, such as a phase change storage element, a thresholding storage element, or a self-selecting storage element. In some examples, the memory cells of the first level 305 and the second level 310 can have a common conductive line such that corresponding memory cells of the one or more levels 305 and the one or more levels 310 can share a column line 215 or a row line 210. For example, the first electrode 325-c of the second level 310 and the second electrode 325-b of the first level 305 can be coupled with the column line 215-a such that the column line 215-a can be shared by vertically adjacent memory cells.

[0057] In some examples, the material of the storage element 320 can include a chalcogenide material or other alloy, including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG alloy. In some examples, a SAG alloy can also include silicon (Si) and such a chalcogenide material can be referred to as a SiSAG alloy. In some examples, a SAG alloy can include silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials can be referred to as a SiSAG alloy or an InSAG alloy, respectively, or combinations thereof. In some examples, a chalcogenide glass can include additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0058] In some examples, the storage element 320 can be an example of a phase change memory cell. In such examples, the material used in the storage element 320 can be based on an alloy (such as the alloys listed above) and can be operated so as to undergo a phase change or become a different physical state during normal operation of the memory cell. For example, a phase change memory cell can have an amorphous state (e.g., a relatively disordered atomic configuration) and a crystalline state (e.g., a relatively ordered atomic configuration).

[0059] A phase change memory cell can exhibit a significant difference in resistance between the crystalline state and the amorphous state of the phase change material, which can be a chalcogenide material. Material in the crystalline state can have atoms arranged in a periodic structure, which can result in a relatively low resistance. In contrast, material in the amorphous state can not have a periodic atomic structure or have a relatively small periodic atomic structure, which can have a relatively high resistance.

[0060] The difference in resistance values between the amorphous state and the crystalline state of a material can be substantial. For example, a material in an amorphous state can have a resistance that is one or more orders of magnitude greater than the resistance of the material in a crystalline state. In some examples, a material can be partially amorphous and partially crystalline, and the resistance can have a value between the resistance of a material in a fully crystalline or fully amorphous state. In such examples, the material can be used to store more than two logic states (e.g., three or more logic states).

[0061] During a program (write) operation of a phase change memory cell (e.g., electrode 325-a, storage element 320-a, electrode 325-b), various parameters of a program pulse can influence (e.g., determine, set, program) a particular behavior or characteristic of the material of the storage element 320, such as a threshold voltage of the material or a resistance of the material. To program a low resistance state (e.g., a relatively crystalline state) in a phase change memory cell, a program pulse that heats or melts the material of the storage element 320 can be applied, which can be associated with at least temporarily forming a relatively disordered (e.g., amorphous) atomic arrangement. The amplitude of the program pulse can be decreased over a duration of time (e.g., relatively slowly) to allow the material to form a crystalline structure as it cools, thereby forming a stable crystalline material state. To program a high resistance state (e.g., a relatively amorphous state) in a phase change memory cell, a program pulse that heats and / or melts the material of the storage element 320 can be applied. The amplitude of the program pulse can be decreased more rapidly than for a program pulse for a low resistance state. In such scenarios, the material can cool with atoms in a more disordered atomic arrangement, as the atoms are unable to form a crystalline structure before the material reaches a stable state, thereby forming a stable amorphous material state. The difference in threshold voltage or resistance of the material of the storage element 320 depending on the logic state stored by the material of the storage element 320 can correspond to a read window for the storage element 320. In some cases, a portion of the storage element can undergo a material change associated with a logic state.

[0062] In some examples, such as for thresholding memory cells or self-selecting memory cells, some or all of a set of logic states supported by the memory cells can be associated with an amorphous state of a chalcogenide material (e.g., the material in a single state can be operable to store different logic states). In some examples, the storage element 320 can be an example of a self-selecting memory cell. In such examples, the material used in the storage element 320 can be based on an alloy (e.g., the alloys listed above) and can be operated so as to undergo a change to a different physical state during normal operation of the memory cell. For example, a self-selecting memory cell can have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state can correspond to a first logic state (e.g., a RESET state) and the low threshold voltage state can correspond to a second logic state (e.g., a SET state).

[0063] During a program (write) operation of a self-selecting memory cell (e.g., including electrode 325-a, storage element 320-a, and electrode 325-b), a polarity for a write operation can affect (determine, set, program) a particular behavior or characteristic of the material of storage element 320, such as a threshold voltage of the material. A difference in the threshold voltage of the material of storage element 320 depending on a logical state stored by the material of storage element 320 (e.g., a difference between a threshold voltage when the material stores a logical state '0' and a threshold voltage when the material stores a logical state '1') can correspond to a read window of storage element 320.

[0064] In some examples, the architecture of memory array 300 can be referred to as a cross-point architecture, in which memory cells are formed at topological cross-points between row lines 210 and column lines 215. This cross-point architecture can provide relatively high density of data storage at lower production cost compared to other memory architectures. For example, the cross-point architecture can have memory cells with reduced area and thus increased memory cell density compared to other architectures. For example, DRAM can use transistors (which are three-terminal devices) as selector elements for each memory cell and can have a larger memory cell area compared to the cross-point architecture. For example, a DRAM can use a transistor as a selector element for each memory cell and can have a larger memory cell area compared to the cross-point architecture.

[0065] While Figure 3 Examples of memory array 300 show two memory levels, but other configurations are possible. In some examples, a single memory level of memory cells (which can be referred to as two-dimensional memory) can be constructed over a substrate. In some examples, two or more levels of memory cells can be configured in a three-dimensional cross-point architecture in a similar manner. Further, in some cases, Figure 3 Elements described in Figure 3 Elements described can be electrically coupled to one another as shown or described but physically rearranged (e.g., storage elements 320 and possibly selector elements or electrodes 325 can be electrically in series between row lines 210 and column lines 215 but need not be in a pillar or stack configuration).

[0066] In some cases, memory array 300 can support more than four tiers (e.g., in addition to tiers 305 and 310) by adjusting the slot configuration of memory array 300. For example, memory array 300 can be divided into a grid of sub-blocks. Each sub-block can contain a slot (e.g., a sub-block can contain a single slot for a first bit line, or a sub-block can contain slots for a first bit line and a second bit line) for one or more access lines (e.g., row lines 210 or column lines 215) of a multi-tier coupling a decoder to a memory array. Additionally or alternatively, a sub-block can not contain any slots. Sub-blocks can be arranged according to one or more periods. For example, sub-blocks containing slots for a first access line can be arranged according to a first period, while sub-blocks containing slots for a second access line can be arranged according to a second period.

[0067] Additionally or alternatively, slots coupling an access line to an associated driver can intersect the access line at a middle of the access line or at an end of the access line. Note that although Figure 3 While chalcogenide materials are described for storage elements 320, the techniques described herein can be applicable to any memory type using self-selecting memory materials or a cross-point type architecture.

[0068] Figure 4 An example of a set of tiers 400 supporting a cross-point array architecture for multiple tiers is illustrated in accordance with examples as disclosed herein. In some cases, a set of tiers 400 can include up to six tiers of memory cells. In such cases, a set of tiers 400 can include memory cell tiers 405-a through 405-f. In other cases, a set of tiers 400 can include up to eight tiers of memory cells. In such cases, a set of tiers 400 can additionally include tiers 405-g and 405-h (e.g., in addition to including tiers 405-a through 405-f).

[0069] A set of tiers 400 can include one or more access lines for accessing memory cells of tiers 405. Memory cells can include a storage material (e.g., a chalcogenide material) arranged between an upper electrode coupled to a first access line and a lower electrode coupled to a second access line. For example, memory cells in a first tier 405-a can be accessed using a first word line 410-a and a first bit line 415-a, while memory cells in a second tier 405-b can be accessed using the first bit line 415-a and a second word line 410-b. Similarly, memory cells in a third tier 405-c can be accessed using the second word line 410-b and a second bit line 415-b, memory cells in a fourth tier 405-d can be accessed using a third word line 410-c and the second bit line 415-b, and so on, such that memory cells in any tier can be accessed using word lines and bit lines directly above and below the tier, as illustrated in Figure 4 A set of tiers 400 can include one or more access lines for accessing memory cells of tiers 405. Memory cells can include a storage material (e.g., a chalcogenide material) arranged between an upper electrode coupled to a first access line and a lower electrode coupled to a second access line. For example, memory cells in a first tier 405-a can be accessed using a first word line 410-a and a first bit line 415-a, while memory cells in a second tier 405-b can be accessed using the first bit line 415-a and a second word line 410-b. Similarly, memory cells in a third tier 405-c can be accessed using the second word line 410-b and a second bit line 415-b, memory cells in a fourth tier 405-d can be accessed using a third word line 410-c and the second bit line 415-b, and so on, such that memory cells in any tier can be accessed using word lines and bit lines directly above and below the tier, as illustrated in

[0070] The access lines can be coupled to decoders (not shown) disposed below the set of levels 400 using one of the word line vias 420 or one of the bit line vias 425. For example, the word lines 410-a, 410-c, and 410-e (e.g., “even” word lines) can be coupled with a first word line decoder using the word line vias 420-a, while the word lines 410-b and 410-d (e.g., “odd” word lines) can be coupled with a second word line decoder using the word line vias 420-b.

[0071] In some cases, each bit line can be coupled to a respective bit line decoder (e.g., rather than sharing a decoder as with the word lines). For example, the first bit line 415-a can be coupled with a first decoder using the bit line via 425-a, the second bit line 415-b can be coupled with a second decoder using the bit line via 425-b, the third bit line 415-c can be coupled with a third decoder using the bit line via 425-c, and the fourth bit line 415-d can be coupled with a fourth decoder using the bit line via 425-d.

[0072] In some examples, each access line (e.g., each of the word lines 410 and each of the bit lines 415) can be divided into one or more segments. Each segment of an access line can be separate (e.g., physically separate) from segments of the same access line and can be coupled with a respective decoder for the access line. The via for a segment can be located in the middle of the segment (e.g., positioned such that memory cells are located on either side of the via) or at either end of the segment (e.g., positioned such that memory cells are located on one side of the via but not the other). In some cases, the via coupling the segment of an access line to a decoder can extend vertically through the set of levels 400, while the access line can extend horizontally through the set of levels 400.

[0073] It should be noted that while examples as disclosed herein describe bit lines and word lines, one of skill in the art will appreciate that both bit lines and word lines can be examples of access lines, and the definitions of word lines and bit lines can be interchanged.

[0074] Figure 5 An example of a top view of a memory array 500 supporting a cross-point array architecture for multiple levels of memory is illustrated in accordance with examples as disclosed herein. The memory array 500 can include a stack of levels 400 as described with reference to Figure 4 The memory array 500 can include a number of levels (e.g., six levels) in which the access lines are divided into segments of access lines. Each segment of an access line can be coupled with a decoder for that access line located below the memory array 500 using a via.

[0075] The memory array 500 can be divided into a number of tiles, which can be further divided into a number of sub-tiles arranged in a grid structure overlying the tiles. A tile can refer to a finite number of memory cells with a corresponding set of memory cell addresses, where each memory cell of the set can be individually addressed.

[0076] In some cases, the tiles of the memory array 500 can not be square (e.g., the tiles can not correspond to an nxn arrangement of sub-tiles). Instead, the tiles can be a more general arrangement of sub-tiles, which can be repeated to form the memory array 500. In some cases, the tiles can terminate on an edge of the memory array. In such cases, the tiles can include driver banks (e.g., bit line decoders or word line decoders) with slot connections outside the footprint of the tile.

[0077] A sub-tile of a tile can indicate where a slot will couple an access line segment (e.g., a bit line and a word line segment) with a respective access line decoder, which in some cases is located below the memory array 500. For example, the sub-tile 505 of a tile can contain one or more slots for coupling a bit line segment with a respective bit line decoder. The slots of the sub-tile 505 can extend vertically through the memory array 500 (e.g., the slots can be examples of vias), while the access lines can extend horizontally through the memory array (e.g., the bit lines can extend in a first horizontal direction, while the word lines can extend in a second horizontal direction that is orthogonal to the first horizontal direction).

[0078] For example, the memory array 500 can include a first word line divided into word line segments 510-a through 510-c and a second word line divided into word line segments 515-a and 515-b. A tile of the memory array 500 can include sub-tiles for coupling the word line segments 510 and 515 with respective word line decoders, which are arranged as described in Figure 5 In some cases, the word line segments 510 can be coupled with a first set of levels (e.g., the first word line can be an "even" word line) and the word line segments 515 can be coupled with a second set of levels (e.g., the second word line can be an "odd" word line). In some cases, the slots coupling the word line segments 510 and 515 with respective word line decoders can be located in the middle (e.g., substantially centered) of the word line segments.

[0079] In some cases, the memory array 500 can include a first bit line divided into bit line segments 520-a through 520-c, a second bit line divided into bit line segments 525-a through 525-c, and a third bit line divided into bit line segments 530-a through 530-c. A tile of the memory array 500 can include sub-tiles for coupling the bit line segments 520, 525, and 530 with respective bit line decoders, which are arranged as described in Figure 5Sub-blocks arranged as described in the summary will couple bit line segments 520, 525, and 530 with respective word line decoders. That is, a via containing the first bit line segment 520, the second bit line segment 525, and the third bit line segment 530 can be located in a sub-block 505. In some cases, sub-blocks containing the first bit line segment 520, the second bit line segment 525, and the third bit line segment 530 can be arranged according to a periodicity 535. For example, the period separating sub-blocks containing a particular bit line segment can indicate a number of sub-blocks (e.g., in a horizontal direction) between a repeating arrangement of vias.

[0080] In some cases, vias coupling bit line segments 520, 525, and 530 with respective bit line decoders can be located at an end of the respective bit line segment. In a cross-sectional view of the memory array 500, word line segments 510 and 515 and bit line segments 520, 525, and 530 can be schematically depicted at the right and bottom, respectively, of the memory array 500, with respective vias extending vertically (e.g., in the z-direction).

[0081] In some cases, bit line segments 520, 525, and 530 can each be substantially the same length. While vias coupling bit line segments with respective drivers can differ in length, this difference can be small compared to the relative lengths of the access line segments. In some cases, the size of a tile of the memory array 500 can depend on the lengths and configurations of bit line segments 520, 525, and 530 and word line segments 510 and 515. For example, in the configuration described in the summary, a tile can include a 4x4 arrangement of sub-blocks including a via for each of the bit lines and each of the word lines (e.g., a total of 16 sub-blocks). However, it should be appreciated that other tile sizes, tile configurations (e.g., a more general arrangement that can be uniformly repeated), or both are possible. Figure 5 In the configuration described in the summary, a tile can include a 4x4 arrangement of sub-blocks including a via for each of the bit lines and each of the word lines (e.g., a total of 16 sub-blocks). However, it should be appreciated that other tile sizes, tile configurations (e.g., a more general arrangement that can be uniformly repeated), or both are possible.

[0082] Figure 6 An example of a top view of a memory array 600 supporting a cross-point array architecture for multiple levels is described in accordance with examples as disclosed herein. The memory array 600 can include a stack of levels as described with reference to Figure 4 The memory array 600 can include a number of levels (e.g., six levels) in which access lines are divided into access line segments. Each segment of an access line can be coupled with a decoder for that access line located below the memory array 600 using a via.

[0083] The memory array 600 can be divided into a number of tiles, which can be further divided into a number of sub-blocks arranged in a grid structure overlying the tiles. A tile can refer to a finite number of memory cells with a set of corresponding memory cell addresses, where each memory cell of the set can be individually addressable.

[0084] In some cases, tiles of memory array 600 can not be square (e.g., the tiles can not correspond to an nxn arrangement of sub-tiles). Instead, the tiles can be a more general arrangement of sub-tiles that can be repeated to form memory array 600. In some cases, tiles can terminate on an edge of the memory array. In such cases, a tile can include a driver bank (e.g., a bit line decoder or a word line decoder) that has a slot connection outside the footprint of the tile.

[0085] For example, memory array 600 can include a first word line divided into word line segments 610-a through 610-c and a second word line divided into word line segments 615-a and 615-b. Tiles of memory array 600 can include sub-tiles for coupling word line segments 610 and 615 with respective word line decoders, arranged as described in Figure 6 In some cases, word line segments 610 can be coupled with a first set of levels (e.g., the first word line can be an "even" word line) and word line segments 615 can be coupled with a second set of levels (e.g., the second word line can be an "odd" word line). In some cases, slots for coupling word line segments 610 and 615 with respective word line decoders can be located in the middle (e.g., substantially in the center) of the word line segments.

[0086] In some cases, memory array 600 can include a first bit line divided into bit line segments 620-a through 620-c, a second bit line divided into bit line segments 625-a and 625-b, and a third bit line divided into bit line segments 630-a through 630-b. Tiles of memory array 600 can include sub-tiles for coupling bit line segments 620, 625, and 630 with respective bit line decoders, arranged as described in Figure 6 For example, memory array 600 can include a first sub-tile 605-a that includes a configuration of slots including slots for first bit line segment 620 and second bit line segment 625, and a second sub-tile 605-b that includes a configuration of slots including slots for first bit line segment 620 and third bit line segment 630. For example, compared to the configuration described in Figure 5 This configuration of slots and sub-tiles can reduce complexity of the slots by allowing the slot regions to be less crowded, compared to the configuration described in

[0087] In some cases, sub-tiles that include first bit line segment 620 can be separated by a first period, while sub-tiles that include second bit line segment 625 or third bit line segment 630 can be separated by a second period. For example, the period that separates sub-tiles that include a particular bit line segment can indicate a number of sub-tiles (e.g., in the horizontal direction) between a repeating arrangement of slots. In some cases, the second period can be greater than the first period (e.g., the second period can be twice the first period).

[0088] In some cases, the via coupling the first bit line segment 620 with the respective bit line decoder can be located at an end of the respective bit line segment. Additionally or alternatively, the vias coupling the second bit line segment 625 and the third bit line segment 630 can be located in the middle of the respective bit line segments. In a cross-sectional view of the memory array 600, the word line segments 610 and 615 and the bit line segments 620, 625, and 630 can be schematically depicted on the right and bottom, respectively, of the memory array 600, with the respective vias extending vertically (e.g., in the z-direction).

[0089] In some cases, the second bit line segment 625 and the third bit line segment 630 can each be substantially the same length (e.g., a first length), while the first bit line segment 620 can be shorter than the first length. Thus, a certain number of decoders for the bit line segments can be equivalent to a set of tiers containing four tiers. However, a corresponding tile size of the memory array 600 can be larger. For example, in the configuration described in Figure 6 a tile can include an 8x8 arrangement of sub-tiles (e.g., a total of 64 sub-tiles) including a via for each of the bit lines and for each of the word lines. However, it should be appreciated that other tile sizes, tile configurations (e.g., a more general arrangement that can be uniformly repeated), or both are possible.

[0090] Figure 7 An example of a top view of a memory array 700 supporting a cross-point array architecture for a number of tiers is described in accordance with examples as disclosed herein is described. The memory array 700 can include a stack of tiers 400 as described with reference to Figure 4 The memory array 700 can include a number of tiers (e.g., six tiers) in which the access lines are divided into access line segments. Each segment of an access line can be coupled with a decoder for that access line located below the memory array 700 using a via.

[0091] The memory array 700 can be divided into a number of tiles, which can be further divided into a number of sub-tiles arranged in a grid structure overlying the tiles. A tile can refer to a finite number of memory cells with a corresponding set of memory cell addresses, where each memory cell of the set can be individually addressable.

[0092] In some cases, the tiles of the memory array 700 can not be square (e.g., the tiles can not correspond to an nxn arrangement of sub-tiles). Instead, the tiles can be a more general arrangement of sub-tiles, which can be repeated to form the memory array 700. In some cases, the tiles can terminate on an edge of the memory array. In such cases, the tiles can include a driver bank (e.g., a bit line decoder or a word line decoder) with a via connection outside the footprint of the tile.

[0093] For example, memory array 700 can include first word lines divided into word line segments 710-a through 710-c and second word lines divided into word line segments 715-a and 715-b. Tiles of memory array 700 can include sub-tiles for coupling word line segments 710 and 715 with respective word line decoders, which are arranged as described in Figure 7 In some cases, word line segments 710 can be coupled with a first set of tiers (e.g., first word lines can be "even" word lines) and word line segments 715 can be coupled with a second set of tiers (e.g., second word lines can be "odd" word lines). In some cases, the slots coupling word line segments 710 and 715 with respective word line decoders can be located in the middle (e.g., substantially in the center) of the word line segments.

[0094] In some cases, memory array 700 can include first bit lines divided into bit line segments 720-a through 720-c, second bit lines divided into bit line segments 725-a and 725-b, and third bit lines divided into bit line segments 730-a through 730-b. Tiles of memory array 700 can include sub-tiles for coupling bit line segments 720, 725, and 730 with respective bit line decoders using sub-tiles arranged as described in Figure 7 For example, memory array 700 can include a first sub-tile 705-a containing slots for first bit line segment 720, a second sub-tile 705-b containing slots for second bit line segment 725, and a third sub-tile 705-c containing slots for first bit line segment 720 and third bit line segment 730.

[0095] In some cases, sub-tiles containing first bit line segment 720 can be separated by a first periodicity, while sub-tiles containing second bit line segment 725 or third bit line segment 730 can be separated by a second periodicity. For example, the period separating sub-tiles containing a particular bit line segment can indicate a number of sub-tiles (e.g., in a horizontal direction) between a repeating arrangement of slots. The second periodicity can be greater than the first periodicity (e.g., the second periodicity can be twice the first periodicity). In some cases, the slots coupling first bit line segment 720, second bit line segment 725, and third bit line segment 730 can be located in the middle of the respective bit line segments.

[0096] In some cases, second bit line segment 725 and third bit line segment 730 can each be substantially the same length (e.g., a first length), while first bit line segment 720 can be shorter than the first length. Thus, a number of decoders for bit line segments can be equivalent to a set of tiers containing four tiers. However, a corresponding tile size of memory array 700 can be larger. In a cross-sectional view of memory array 700, word line segments 710 and 715 and bit line segments 720, 725, and 730 can be schematically depicted in the right and bottom, respectively, of memory array 700, with respective slots extending vertically (e.g., in the z-direction).

[0097] In some examples, the resistance of the second bit line segment 725 and the third bit line segment 730 can be greater than the resistance of the first bit line segment 720 (e.g., due to differences in length). To compensate for the increased resistance, the thickness of the second bit line segment 725 and the third bit line segment 730 can be increased (e.g., to reduce the resistance). Additionally or alternatively, leakage due to the adjusted length and thickness of the second bit line segment 725 and the third bit line segment 730 can be mitigated by adjusting the word line select voltage, the bit line select voltage, or both.

[0098] Figure 8 An example of a top view of a memory array 800 supporting a cross-point array architecture for multiple levels is illustrated in accordance with examples as disclosed herein. The memory array 800 can include a stack of levels 400 as described with reference to Figure 4 The memory array 800 can include a number of levels (e.g., eight levels), where the access lines are divided into access line segments. Each segment of an access line can be coupled with a slot to a decoder for that access line located below the memory array 800.

[0099] The memory array 800 can be divided into a number of tiles, which can be further divided into a number of sub-tiles arranged in a grid structure overlying the tiles. A tile can refer to a finite number of memory cells with a corresponding set of memory cell addresses, where each memory cell of the set can be individually addressable.

[0100] In some cases, the tiles of the memory array 800 can not be square (e.g., the tiles can not correspond to an nxn arrangement of sub-tiles). Instead, the tiles can be a more general arrangement of sub-tiles, which can be repeated to form the memory array 800. In some cases, the tiles can terminate on an edge of the memory array. In such cases, the tiles can include driver banks (e.g., bit line decoders or word line decoders) with slot connections outside the footprint of the tile.

[0101] For example, the memory array 800 can include a first word line divided into word line segments 810-a through 810-c and a second word line divided into word line segments 815-a and 815-b. A tile of the memory array 800 can include sub-tiles for coupling the word line segments 810 and 815 with respective word line decoders, which are arranged as illustrated in Figure 8 In some cases, the word line segments 810 can be coupled with a first set of levels (e.g., the first word line can be an "even" word line) and the word line segments 815 can be coupled with a second set of levels (e.g., the second word line can be an "odd" word line). In some cases, the slots coupling the word line segments 810 and 815 with respective word line decoders can be located in the middle (e.g., substantially in the center) of the word line segments.

[0102] In some cases, memory array 800 can include a first bit line divided into bit line segments 820-a through 820-c, a second bit line divided into bit line segments 825-a through 825-c, a third bit line divided into bit line segments 830-a and 830-b, and a fourth bit line divided into bit line segments 835-a and 835-b. A tile of memory array 800 can include sub-tiles that couple the bit line segments 820, 825, 830, and 835 with respective bit line decoders arranged as described in Figure 8 In some cases, memory array 800 can include a first bit line divided into bit line segments 820-a through 820-c, a second bit line divided into bit line segments 825-a through 825-c, a third bit line divided into bit line segments 830-a and 830-b, and a fourth bit line divided into bit line segments 835-a and 835-b. A tile of memory array 800 can include sub-tiles that couple the bit line segments 820, 825, 830, and 835 with respective bit line decoders arranged as described in

[0103] In some cases, sub-tiles containing first bit line segments 820 and second bit line segments 825 can be separated by a first periodicity, while sub-tiles containing third bit line segments 830 or fourth bit line segments 835 can be separated by a second periodicity. For example, the periodicity at which sub-tiles containing a particular bit line segment are separated can indicate a number of sub-tiles (e.g., in a horizontal direction) between repeated arrangements of slots. The second periodicity can be greater than the first periodicity (e.g., the second periodicity can be twice the first periodicity). In some cases, slots that couple third bit line segments 830 and fourth bit line segments 835 can be located at a middle of the respective bit line segments, while slots that couple first bit line segments 820 and second bit line segments 825 can be located at an end of the respective bit line segments.

[0104] In some cases, third bit line segments 830 and fourth bit line segments 835 can each be substantially the same length (e.g., a first length), while first bit line segments 820 and second bit line segments 825 can be shorter than the first length. In some cases, the size of a tile of memory array 800 can depend on the lengths and configurations of bit line segments 820, 825, 830, and 835, as well as word line segments 810 and 815. For example, in the configuration described in Figure 8 In the configuration described in, a tile can include an 8x8 arrangement of sub-tiles that include slots for each of the bit lines and each of the word lines (e.g., a total of 64 sub-tiles). However, it should be appreciated that other tile sizes, tile configurations (e.g., a more general arrangement that can be consistently repeated), or both are possible. In a cross-sectional view of memory array 800, word line segments 810 and 815, as well as bit line segments 820, 825, 830, and 835, can be schematically depicted at the right and bottom, respectively, of memory array 800, with respective slots extending vertically (e.g., in the z-direction).

[0105] Figure 9 An example of a top view of a memory array 900 supporting a cross-point array architecture for multiple levels is illustrated in accordance with examples as disclosed herein. The memory array 900 can include a stack of levels 400 as described with reference to Figure 4 The memory array 900 can include a number of levels (e.g., eight levels) in which the access lines are divided into access line segments. Each segment of an access line can be coupled with a slot to a decoder for that access line located below the memory array 900.

[0106] The memory array 900 can be divided into a number of tiles, which can be further divided into a number of sub-tiles arranged in a grid structure overlying the tiles. A tile can refer to a finite number of memory cells with a set of corresponding memory cell addresses, where each memory cell of the set can be individually addressed.

[0107] In some cases, the tiles of the memory array 900 can not be square (e.g., the tiles can not correspond to an nxn arrangement of sub-tiles). Instead, the tiles can be a more general arrangement of sub-tiles, which can be repeated to form the memory array 900. In some cases, the tiles can terminate on an edge of the memory array. In such cases, the tiles can include a driver bank (e.g., a bit line decoder or a word line decoder) with a slot connection outside the footprint of the tile.

[0108] For example, the memory array 900 can include a first word line divided into word line segments 910-a through 910-c and a second word line divided into word line segments 915-a and 915-b. A tile of the memory array 900 can include sub-tiles for coupling the word line segments 910 and 915 with respective word line decoders, which are arranged as illustrated in Figure 9 In some cases, the word line segments 910 can be coupled with a first set of levels (e.g., the first word line can be an “even” word line) and the word line segments 915 can be coupled with a second set of levels (e.g., the second word line can be an “odd” word line). In some cases, the slots coupling the word line segments 910 and 915 with respective word line decoders can be located in the middle (e.g., substantially in the center) of the word line segments.

[0109] In some cases, the memory array 900 can include a first bit line divided into bit line segments 920-a through 920-c, a second bit line divided into bit line segments 925-a through 925-c, a third bit line divided into bit line segments 930-a and 930-b, and a fourth bit line divided into bit line segments 935-a and 935-b. A tile of the memory array 900 can include sub-tiles for coupling the bit line segments 920, 925, 930, and 935 with respective bit line decoders, which are arranged as illustrated in Figure 9Sub-blocks arranged as described in the summary will couple bit line segments 920, 925, 930, and 935 with respective bit line decoders. For example, memory array 900 can include a first sub-block 905-a that includes slots for first bit line segment 920. Memory array 900 can also include a second sub-block 905-b that includes a configuration of slots that includes slots for second bit line segment 925 and fourth bit line segment 935. Memory array 900 can also include a third sub-block 905-c that includes a configuration of slots that includes slots for second bit line segment 925 and third bit line segment 930.

[0110] In some cases, sub-blocks containing first bit line segment 920 and second bit line segment 925 can be separated by a first periodicity, while sub-blocks containing third bit line segment 930 or fourth bit line segment 935 can be separated by a second periodicity. For example, the periodicity at which sub-blocks containing a particular bit line segment are separated can indicate a number of sub-blocks (e.g., in a horizontal direction) between a repeating arrangement of slots. The second periodicity can be greater than the first periodicity (e.g., the second periodicity can be twice the first periodicity). In some cases, slots that couple third bit line segment 930 and fourth bit line segment 935 can be located in the middle of the respective bit line segments, while slots that couple first bit line segment 920 and second bit line segment 925 can be located at the ends of the respective bit line segments.

[0111] In some cases, second bit line segment 925, third bit line segment 930, and fourth bit line segment 935 can each be substantially the same length (e.g., a first length), while first bit line segment 920 can be shorter than the first length. In some cases, the size of a tile of memory array 900 can depend on the lengths and configurations of bit line segments 920, 925, 930, and 935 as well as word line segments 910 and 915. For example, in the configuration described in the summary, a tile can include an 8x8 arrangement of sub-blocks that include slots for each of the bit lines and each of the word lines (e.g., a total of 64 sub-blocks). However, it should be appreciated that other tile sizes, tile configurations, or both are possible. In a cross-sectional view of memory array 900, word line segments 910 and 915 as well as bit line segments 920, 925, 930, and 935 can be depicted schematically at the right and bottom, respectively, of memory array 900, with respective slots extending vertically (e.g., in the z-direction). Figure 9 In the configuration described in the summary, a tile can include an 8x8 arrangement of sub-blocks that include slots for each of the bit lines and each of the word lines (e.g., a total of 64 sub-blocks). However, it should be appreciated that other tile sizes, tile configurations, or both are possible. In a cross-sectional view of memory array 900, word line segments 910 and 915 as well as bit line segments 920, 925, 930, and 935 can be depicted schematically at the right and bottom, respectively, of memory array 900, with respective slots extending vertically (e.g., in the z-direction).

[0112] Figure 10 A block diagram 1000 showing a periodic access operation manager 1020 that supports a cross-point array architecture for multiple levels of memory in accordance with examples as disclosed herein is shown. Periodic access operation manager 1020 can be as described with reference to Figures 1 to 9Examples of aspects of the periodic access operation manager are described. The periodic access operation manager 1020, or various components thereof, can be examples of means for performing various aspects of a cross-point array architecture for multiple levels as described herein. For example, the periodic access operation manager 1020 can include a memory cell manager 1025, a decoder manager 1030, or any combination thereof. Each of these components can be in communication, directly or indirectly, with one another (e.g., via one or more buses).

[0113] The memory cell manager 1025 can be configured as, or otherwise support, means for identifying at least one cell of a memory array having a plurality of levels, a plurality of word lines, a plurality of word line decoders, a plurality of bit lines, and a plurality of bit line decoders positioned below the memory array, each of the plurality of bit lines coupled with a respective one or more levels of the plurality of levels, the plurality of bit lines including a first bit line, a second bit line, and a third bit line. The decoder manager 1030 can be configured as, or otherwise support, means for accessing the at least one cell of the memory array using one of the plurality of word line decoders and one of the plurality of bit line decoders, where each of the plurality of bit lines is coupled with a respective bit line decoder using a plurality of bit line vias, where the plurality of bit line vias includes: a first subset of bit line vias arranged according to a first periodicity and coupling respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders; a second subset of bit line vias arranged according to a second periodicity and coupling respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders; and a third subset of bit line vias arranged according to the second periodicity and coupling respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders.

[0114] In some examples, the second periodicity is greater than the first periodicity.

[0115] In some examples, each bit line via of the second subset of bit line vias intersects a respective segment of the second bit line between ends of the segment and each bit line via of the third subset of bit line vias intersects a respective segment of the third bit line between ends of the segment.

[0116] In some examples, each bit line via of the first subset of bit line vias divides each segment of the first bit line into a first sub-segment and a second sub-segment.

[0117] Figure 11 A block diagram 1100 showing a configuration access operation manager 1120 supporting a cross-point array architecture for multiple levels is shown, in accordance with examples as disclosed herein. The configuration access operation manager 1120 can be an example of the configuration access operation manager 1120 as described with reference to FIG. 1, or various components thereof. For example, the configuration access operation manager 1120 can include a memory cell manager 1125, a decoder manager 1130, or any combination thereof. Each of these components can be in communication, directly or indirectly, with one another (e.g., via one or more buses). Figures 1 to 9Examples of aspects of a configuration access operation manager are described. Configuration access operation manager 1120, or various components thereof, can be examples of means for performing various aspects of a cross-point array architecture for multiple levels as described herein. For example, configuration access operation manager 1120 can include memory cell manager 1125, decoder manager 1130, or any combination thereof. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0118] Memory cell manager 1125 can be configured as, or otherwise support, means for identifying at least one cell of a memory array, the memory array including a plurality of tiles, each tile of the plurality of tiles including a plurality of sub-blocks and a plurality of levels, wherein each sub-block of the plurality of sub-blocks includes a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, the plurality of bit lines including: a first bit line coupled with a first level and a second level of the plurality of levels; a second bit line coupled with a third level and a fourth level of the plurality of levels; and a third bit line coupled with a fifth level and a sixth level of the plurality of levels. Decoder manager 1130 can be configured as, or otherwise support, means for accessing at least one cell of a memory array using a plurality of bit line decoders positioned underneath the memory array, wherein a first bit line decoder of the plurality of bit line decoders is coupled with a first bit line using a first configuration of slots within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with a second bit line using a second configuration of slots within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with a third bit line using a third configuration of slots within a third subset of the plurality of sub-blocks.

[0119] In some examples, at least one sub-block of the plurality of sub-blocks includes slots coupling more than one bit line with a respective bit line decoder of the plurality of bit line decoders.

[0120] In some examples, the plurality of bit lines further includes a fourth bit line coupled with a seventh level and an eighth level of the plurality of levels. In some examples, a fourth bit line decoder of the plurality of bit line decoders is coupled with the fourth bit line using a fourth configuration of slots.

[0121] In some examples, a first sub-block of the plurality of sub-blocks includes the first configuration of slots, the second configuration of slots, and a fourth configuration of slots, and a second sub-block of the plurality of sub-blocks includes the first configuration of slots, the second configuration of slots, and the third configuration of slots.

[0122] In some examples, a first pair of sub-blocks including the first configuration of slots is separated by a first sub-block including the second configuration of slots and the fourth configuration of slots, and a second pair of sub-blocks including the first configuration of slots is separated by a second sub-block including the second configuration of slots and the third configuration of slots.

[0123] In some examples, a first sub-block of the plurality of sub-blocks includes the first configuration of slots and the second configuration of slots, and a second sub-block of the plurality of sub-blocks includes the first configuration of slots and the third configuration of slots.

[0124] Figure 12 A flow diagram illustrating a method 1200 to support for a cross-point array architecture for multiple levels in accordance with examples as disclosed herein is shown. The operations of method 1200 can be implemented by a periodic access operation manager or its components as described herein. For example, the operations of method 1200 can be performed by a periodic access operation manager as described with reference to Figures 1 to 10 The periodic access operation manager can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the periodic access operation manager can use special-purpose hardware to perform aspects of the described functions.

[0125] At 1205, the method can include identifying at least one cell of a memory array having a plurality of levels, a plurality of word lines, a plurality of word line decoders, a plurality of bit lines, and a plurality of bit line decoders positioned below the memory array, each of the plurality of bit lines coupled with a respective one or more levels of the plurality of levels, the plurality of bit lines including a first bit line, a second bit line, and a third bit line. The operations of 1205 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 1205 can be performed by a memory cell manager 1025 as described with reference to Figure 10 The operations of 1210 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 1210 can be performed by a memory cell manager 1025 as described with reference to

[0126] At 1210, the method can include accessing the at least one cell of the memory array using one of the plurality of word line decoders and one of the plurality of bit line decoders, where each of the plurality of bit lines is coupled with a respective bit line decoder using a plurality of bit line slots, where the plurality of bit line slots includes: a first subset of bit line slots according to a first periodic arrangement and coupling respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders; a second subset of bit line slots according to a second periodic arrangement and coupling respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders; and a third subset of bit line slots according to the second periodic arrangement and coupling respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders. The operations of 1210 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 1210 can be performed by a memory cell manager 1025 as described with reference to Figure 10The described decoder manager 1030 to perform.

[0127] In some examples, an apparatus as described herein can perform one or several methods, such as method 1200. The apparatus can include features, circuitry, logic, means, or instructions for performing aspects of the disclosure below (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof:

[0128] Aspect 1 : An apparatus comprising features, circuitry, logic, means, or instructions for, or any combination thereof: identifying at least one cell of a memory array, the memory array having a plurality of levels, a plurality of word lines, a plurality of word line decoders, a plurality of bit lines, and a plurality of bit line decoders positioned below the memory array, each of the plurality of bit lines coupled with a respective one or more levels of the plurality of levels, the plurality of bit lines including a first bit line, a second bit line, and a third bit line and accessing the at least one cell of the memory array using one of the plurality of word line decoders and one of the plurality of bit line decoders, wherein each of the plurality of bit lines is coupled with a respective bit line decoder using a plurality of bit line vias, wherein the plurality of bit line vias includes: a first subset of bit line vias arranged according to a first periodicity and coupling a respective segment of the first bit line with a respective bit line decoder of the plurality of bit line decoders; a second subset of bit line vias arranged according to a second periodicity and coupling a respective segment of the second bit line with a respective bit line decoder of the plurality of bit line decoders; and a third subset of bit line vias arranged according to the second periodicity and coupling a respective segment of the third bit line with a respective bit line decoder of the plurality of bit line decoders.

[0129] Aspect 2: The apparatus of Aspect 1, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: the second periodicity is greater than the first periodicity.

[0130] Aspect 3: The apparatus of Aspect 2, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: each bit line via of the second subset of bit line vias intersects the respective segment of the second bit line between ends of each segment of the second bit line and each bit line via of the third subset of bit line vias intersects the respective segment of the third bit line between ends of each segment of the third bit line.

[0131] Aspect 4: The apparatus of Aspect 3, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: each bit line via of the first subset of bit line vias divides each segment of the first bit line into a first sub-segment and a second sub-segment.

[0132] Figure 13 A diagram illustrates a method 1300 that supports techniques for cross-point array architecture for multiple levels in accordance with examples as disclosed herein. The operations of method 1300 can be implemented by a configuration access operation manager or its components as described herein. For example, the operations of method 1300 can be performed by a configuration access operation manager as described with reference to Figures 1 to 9 FIGS. 11 through 13, and 17. In some examples, a configuration access operation manager can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the configuration access operation manager can perform aspects of the described functions using special-purpose hardware.

[0133] At 1305, the method can include identifying at least one cell of a memory array, the memory array including a plurality of tiles, each tile of the plurality of tiles including a plurality of sub-blocks and a plurality of levels, wherein each sub-block of the plurality of sub-blocks includes a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, the plurality of bit lines including: a first bit line coupled with a first level and a second level of the plurality of levels; a second bit line coupled with a third level and a fourth level of the plurality of levels; and a third bit line coupled with a fifth level and a sixth level of the plurality of levels. The operations of 1305 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 1305 can be performed by a memory cell manager 1125 as described with reference to Figure 11 FIGS. 11 through 13, and 17. In some examples, a configuration access operation manager can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the configuration access operation manager can perform aspects of the described functions using special-purpose hardware.

[0134] At 1310, the method can include accessing the at least one cell of the memory array using a plurality of bit line decoders positioned below the memory array, wherein a first bit line decoder of the plurality of bit line decoders is coupled with the first bit line using a first configuration of slots within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with the second bit line using a second configuration of slots within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with the third bit line using a third configuration of slots within a third subset of the plurality of sub-blocks. The operations of 1310 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 1310 can be performed by a decoder manager 1130 as described with reference to Figure 11 FIGS. 11 through 13, and 17. In some examples, a configuration access operation manager can execute a set of instructions to control the functional elements of a device to perform the described functions. Additionally or alternatively, the configuration access operation manager can perform aspects of the described functions using special-purpose hardware.

[0135] In some examples, an apparatus as described herein can perform one or more methods, such as method 1300. The apparatus can include, or can operate in association with, a configuration access operation manager, a memory cell manager, a decoder manager, or any combination thereof.

[0136] Aspect 5: An apparatus comprising features, circuitry, logic, means, or instructions for, or any combination of the following: identifying at least one cell of a memory array, the memory array comprising a plurality of tiles, each tile of the plurality of tiles comprising a plurality of sub-blocks and a plurality of levels, wherein each sub-block of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, the plurality of bit lines comprising: a first bit line coupled with a first level and a second level of the plurality of levels; a second bit line coupled with a third level and a fourth level of the plurality of levels; and a third bit line coupled with a fifth level and a sixth level of the plurality of levels and accessing the at least one cell of the memory array using a plurality of bit line decoders positioned below the memory array, wherein a first bit line decoder of the plurality of bit line decoders is coupled with the first bit line using a first configuration of vias within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled with the second bit line using a second configuration of vias within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled with the third bit line using a third configuration of vias within a third subset of the plurality of sub-blocks.

[0137] Aspect 6: The apparatus of Aspect 5, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the following: at least one sub-block of the plurality of sub-blocks comprises vias coupling more than one bit line with a respective bit line decoder of the plurality of bit line decoders.

[0138] Aspect 7: The apparatus of Aspect 6, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the following: the plurality of bit lines further comprises a fourth bit line coupled with a seventh level and an eighth level of the plurality of levels, and a fourth bit line decoder of the plurality of bit line decoders is coupled with the fourth bit line using a fourth configuration of vias.

[0139] Aspect 8: The apparatus of Aspect 7, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination of the following: a first sub-block of the plurality of sub-blocks comprises the first configuration of vias, the second configuration of vias, and the fourth configuration of vias, and a second sub-block of the plurality of sub-blocks comprises the first configuration of vias, the second configuration of vias, and the third configuration of vias.

[0140] Aspect 9: The apparatus of any of aspects 7 through 8, further including operations, features, circuitry, logic, means, or instructions for, or any combination of the same, the first pair of sub-blocks of the first configuration including slots are separated by a first sub-block of the second configuration including slots and the fourth configuration of slots, and the second pair of sub-blocks of the first configuration including slots are separated by a second sub-block of the second configuration including slots and the third configuration of slots.

[0141] Aspect 10: The apparatus of any of aspects 5 through 9, further including operations, features, circuitry, logic, means, or instructions for, or any combination of the same, a first sub-block of the plurality of sub-blocks includes the first configuration of slots and the second configuration of slots, and a second sub-block of the plurality of sub-blocks includes the first configuration of slots and the third configuration of slots.

[0142] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more methods can be combined.

[0143] An apparatus is described. An overview of aspects of an apparatus as described herein is provided below:

[0144] Aspect 11 : An apparatus comprising: a memory array having a plurality of levels and a plurality of bit lines, each of the plurality of bit lines coupled with one or more levels of the plurality of levels, the plurality of bit lines including a first bit line, a second bit line, and a third bit line; a plurality of bit line decoders positioned beneath the memory array; and a plurality of bit line slots including: a first subset of bit line slots arranged according to a first periodicity and coupling respective segments of the first bit line with respective bit line decoders of the plurality of bit line decoders; a second subset of bit line slots arranged according to a second periodicity and coupling respective segments of the second bit line with respective bit line decoders of the plurality of bit line decoders; and a third subset of bit line slots arranged according to the second periodicity and coupling respective segments of the third bit line with respective bit line decoders of the plurality of bit line decoders.

[0145] Aspect 12: The apparatus of aspect 11, wherein the second periodicity is greater than the first periodicity.

[0146] Aspect 13: The apparatus of aspect 12, wherein each bit line slot of the second subset of bit line slots intersects each segment of the second bit line between ends of the each segment and each bit line slot of the third subset of bit line slots intersects each segment of the third bit line between ends of the each segment.

[0147] Aspect 14: The device according to aspect 13, wherein each bit slot of the first subset of bit slots intersects with each segment between the ends of each segment of the first bit line.

[0148] Aspect 15: The device according to any one of aspects 11 to 14, wherein the plurality of bit lines further comprises a fourth bit line coupled to a seventh and an eighth layer of the plurality of layers.

[0149] Aspect 16: The device according to aspect 15, wherein the plurality of bit line slots further comprises a fourth subset of bit line slots that couple a corresponding segment of the fourth bit line to a corresponding bit line decoder among the plurality of bit line decoders according to the second periodic arrangement.

[0150] Aspect 17: The device according to aspect 16, wherein each bit slot of the third subset of bit slots intersects the segment between the ends of each segment of the third bit line, and each bit slot of the fourth subset of bit slots intersects the segment between the ends of each segment of the fourth bit line.

[0151] Aspect 18: The device according to aspect 17, wherein each bit slot of the first subset of bit slots intersects with each segment between the ends of each segment of the first bit line.

[0152] Aspect 19: The device according to any one of aspects 11 to 18 further comprises: a plurality of word lines, each of the plurality of word lines being coupled to one or more of the plurality of layers; a plurality of word line decoders positioned below the memory array; and a plurality of word line slots coupling each of the plurality of word lines to a corresponding word line decoder among the plurality of word line decoders.

[0153] Aspect 20: The device according to aspect 19, wherein the plurality of word line slots comprises: a first subset of word line slots arranged according to a third periodicity to couple a corresponding segment of a first word line to a corresponding word line decoder among the plurality of word line decoders; and a second subset of word line slots arranged according to the third periodicity for coupling a second word line to the plurality of word line decoders.

[0154] Aspect 21: The device according to any one of aspects 11 to 20, wherein the first bit line is coupled to a first and a second layer of the plurality of layers, the second bit line is coupled to a third and a fourth layer of the plurality of layers, and the third bit line is coupled to a fifth and a sixth layer of the plurality of layers.

[0155] Describe a device. The following provides an overview of aspects of the device as described herein:

[0156] Aspect 22: An apparatus comprising: a plurality of slabs of a memory array, each of the plurality of slabs comprising a plurality of sub-blocks and a plurality of layers, wherein each of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, each of the plurality of bit lines being coupled to one or more of the plurality of layers, the plurality of bit lines comprising a first bit line, a second bit line, and a third bit line; a plurality of bit line decoders positioned below the memory array, wherein a first bit line decoder of the plurality of bit line decoders is coupled to the first bit line using a first configuration of slots within a first subset of the plurality of sub-blocks, a second bit line decoder of the plurality of bit line decoders is coupled to the second bit line using a second configuration of slots within a second subset of the plurality of sub-blocks, and a third bit line decoder of the plurality of bit line decoders is coupled to the third bit line using a third configuration of slots within a third subset of the plurality of sub-blocks.

[0157] Aspect 23: The device according to aspect 22, wherein at least one of the plurality of sub-blocks includes a slot that couples more than one bit line to a corresponding bit line decoder among the plurality of bit line decoders.

[0158] Aspect 24: The device according to aspect 23, wherein a first sub-block of the plurality of sub-blocks includes the first configuration of the slot and the second configuration of the slot, and a second sub-block of the plurality of sub-blocks includes the first configuration of the slot and the third configuration of the slot.

[0159] Aspect 25: The device according to any one of aspects 22 to 24 further comprises: a plurality of word line decoders positioned below the memory array, wherein each of the plurality of word lines is coupled to a corresponding word line decoder among the plurality of word line decoders using a fourth configuration of the plurality of sub-blocks.

[0160] Aspect 26: The device according to any one of aspects 22 to 25, wherein the first bit line is coupled to a first and a second layer of the plurality of layers, the second bit line is coupled to a third and a fourth layer of the plurality of layers, and the third bit line is coupled to a fifth and a sixth layer of the plurality of layers.

[0161] Aspect 27: The device according to any one of aspects 22 to 26, wherein the first pair of sub-blocks of the first configuration including slots are separated by the first sub-block of the second configuration including slots, and the second pair of sub-blocks of the first configuration including slots are separated by the second sub-block of the third configuration including slots.

[0162] Aspect 28: The apparatus according to any one of aspects 22 to 27, wherein the plurality of bit lines further comprises a fourth bit line coupled to a seventh and an eighth layer of the plurality of layers, and the fourth bit line decoder of the plurality of bit line decoders is coupled to the fourth bit line using a fourth configuration of slots within a fourth subset of the plurality of sub-blocks.

[0163] Aspect 29: The device according to aspect 28, wherein a first sub-block of the plurality of sub-blocks includes a first configuration of slots, a second configuration of slots, and a fourth configuration of slots, and a second sub-block of the plurality of sub-blocks includes a first configuration of slots, a second configuration of slots, and a third configuration of slots.

[0164] Aspect 30: The device according to any one of aspects 28 to 29, wherein a first pair of sub-blocks of the first configuration including slots are separated by a first sub-block of the second configuration including slots and the fourth configuration including slots, and a second pair of sub-blocks of the first configuration including slots are separated by a second sub-block of the second configuration including slots and the third configuration including slots.

[0165] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced herein can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, wherein the bus may have various bit widths.

[0166] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to relationships between components that support signal flow between them. Components are considered electronically connected (or conductively contacted, connected, or coupled) to each other if any conductive path exists between them that can readily support signal flow between them. At any given time, the conductive path between electronically connected (or conductively contacted, connected, or coupled) components may be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between the components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0167] The term "coupling" refers to a condition that moves from an open-circuit relationship between components in which signals cannot currently be transmitted between components via conductive paths to a closed-circuit relationship in which signals can be transmitted between components via conductive paths. When a component (such as a controller) couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0168] The term "isolation" refers to the relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, two components separated by a switch positioned between them are isolated from each other when that switch is open. When a controller isolates two components, the controller affects the change to prevent signals from flowing between the components using previously permissible conductive paths.

[0169] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. Layers or levels may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0170] As used herein, the term “substantially” means that the modified characteristic (e.g., a verb or adjective modified by the term “substantially”) need not be absolute, but close enough to achieve the advantage of the described characteristic.

[0171] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to other components of a memory cell or memory array. Electrodes can be included as traces, wires, conductive lines, conductive layers, or the like that provide a conductive path between elements or components of the memory array.

[0172] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0173] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0174] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "example" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to other examples." The detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0175] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0176] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0177] For example, various illustrative blocks and modules described herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0178] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, an instance step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0179] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. For example, and not limitingly, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is suitably referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave), then the definition of media includes coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave). As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0180] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: A memory array having multiple layers and multiple bit lines, each of the multiple bit lines being coupled to one or more of the multiple layers, the multiple bit lines including a first bit line, a second bit line and a third bit line; Multiple bitline decoders are located below the memory array; and A plurality of bitline slots, comprising: a first subset of bitline slots arranged according to a first periodicity and coupling corresponding segments of the first bitline to corresponding bitline decoders among the plurality of bitline decoders; a second subset of bitline slots arranged according to a second periodicity and coupling corresponding segments of the second bitline to corresponding bitline decoders among the plurality of bitline decoders; and a third subset of bitline slots arranged according to the second periodicity and coupling corresponding segments of the third bitline to corresponding bitline decoders among the plurality of bitline decoders.

2. The memory device of claim 1, wherein the second periodicity is greater than the first periodicity.

3. The memory device of claim 2, wherein each bit slot of the second subset of bit line slots intersects with each segment of the second bit line between the ends of each segment, and each bit slot of the third subset of bit line slots intersects with each segment of the third bit line between the ends of each segment.

4. The memory device of claim 3, wherein each bit line slot of the first subset intersects with each segment between the ends of each segment of the first bit line.

5. The memory device of claim 1, wherein the plurality of bit lines further includes a fourth bit line, the fourth bit line being coupled to a seventh layer and an eighth layer of the plurality of layers.

6. The memory device of claim 5, wherein the plurality of bit line slots further comprises a fourth subset of bit line slots that, according to the second periodic arrangement, couple a corresponding segment of the fourth bit line to a corresponding bit line decoder among the plurality of bit line decoders.

7. The memory device of claim 6, wherein each bit line slot of the third subset of bit line slots intersects the segment between the ends of each segment of the third bit line, and each bit line slot of the fourth subset of bit line slots intersects the segment between the ends of each segment of the fourth bit line.

8. The memory device of claim 7, wherein each bit line slot of the first subset intersects with each segment between the ends of each segment of the first bit line.

9. The memory device of claim 1, further comprising: Multiple word lines, each of which is coupled to one or more of the multiple layers; Multiple word line decoders are located below the memory array; and Multiple word line slots couple each of the multiple word lines to a corresponding word line decoder among the multiple word line decoders.

10. The memory device of claim 9, wherein the plurality of word line slots comprises: The first subset of word line slots, which, according to the third periodic arrangement, couples the corresponding segments of the first word line with the corresponding word line decoders among the plurality of word line decoders; and a second subset of word line slots, which are arranged according to the third periodicity for coupling the second word line to the plurality of word line decoders.

11. The memory device of claim 1, wherein the first bit line is coupled to a first layer and a second layer of the plurality of layers, the second bit line is coupled to a third layer and a fourth layer of the plurality of layers, and the third bit line is coupled to a fifth layer and a sixth layer of the plurality of layers.

12. A memory device comprising: A memory array comprising multiple slabs, each of the multiple slabs including multiple sub-blocks and multiple layers, wherein each of the multiple sub-blocks includes multiple memory cells of the memory array addressable via multiple word lines and multiple bit lines, each of the multiple bit lines being coupled to one or more of the multiple layers, the multiple bit lines including a first bit line, a second bit line, and a third bit line; and A plurality of bitline decoders are positioned below the memory array, wherein a first bitline decoder of the plurality of bitline decoders is coupled to the first bitline using a first configuration of slots within a first subset of the plurality of sub-blocks, a second bitline decoder of the plurality of bitline decoders is coupled to the second bitline using a second configuration of slots within a second subset of the plurality of sub-blocks, and a third bitline decoder of the plurality of bitline decoders is coupled to the third bitline using a third configuration of slots within a third subset of the plurality of sub-blocks.

13. The memory device of claim 12, wherein at least one of the plurality of sub-blocks includes a slot that couples more than one bit line to a corresponding bit line decoder among the plurality of bit line decoders.

14. The memory device of claim 13, wherein the first sub-block of the plurality of sub-blocks includes the first configuration of the slot and the second configuration of the slot, and the second sub-block of the plurality of sub-blocks includes the first configuration of the slot and the third configuration of the slot.

15. The memory device of claim 12, further comprising: Multiple word line decoders are positioned below the memory array, wherein each of the multiple word lines is coupled to a corresponding word line decoder among the multiple word line decoders using a fourth configuration of the multiple sub-blocks.

16. The memory device of claim 12, wherein the first bit line is coupled to a first and a second layer of the plurality of layers, the second bit line is coupled to a third and a fourth layer of the plurality of layers, and the third bit line is coupled to a fifth and a sixth layer of the plurality of layers.

17. The memory device of claim 12, wherein the first pair of sub-blocks of the first configuration including a slot is separated by a first sub-block of the second configuration including a slot, and the second pair of sub-blocks of the first configuration including a slot is separated by a second sub-block of the third configuration including a slot.

18. The memory device according to claim 12, wherein: The plurality of bit lines further includes a fourth bit line, which is coupled to the seventh and eighth layers of the plurality of layers; and The fourth bitline decoder of the plurality of bitline decoders is coupled to the fourth bitline using a fourth configuration of slots within a fourth subset of the plurality of sub-blocks.

19. The memory device of claim 18, wherein the first sub-block of the plurality of sub-blocks includes the first configuration of the slot, the second configuration of the slot, and the fourth configuration of the slot, and the second sub-block of the plurality of sub-blocks includes the first configuration of the slot, the second configuration of the slot, and the third configuration of the slot.

20. The memory device of claim 18, wherein the first pair of sub-blocks of the first configuration including the slot is separated by a first sub-block of the second configuration including the slot and the fourth configuration including the slot, and the second pair of sub-blocks of the first configuration including the slot is separated by a second sub-block of the second configuration including the slot and the third configuration including the slot.

21. A method for operating a memory device, comprising: Identify at least one cell of a memory array having multiple layers, multiple word lines, multiple word line decoders, multiple bit lines, and multiple bit line decoders positioned below the memory array, each of the multiple bit lines being coupled to one or more corresponding layers of the multiple layers, the multiple bit lines including a first bit line, a second bit line, and a third bit line; and At least one cell of the memory array is accessed using one of the plurality of word line decoders and one of the plurality of bit line decoders, wherein each of the plurality of bit lines is coupled to a corresponding bit line decoder using a plurality of bit line slots, wherein the plurality of bit line slots includes: a first subset of bit line slots arranged according to a first periodicity and coupling a corresponding segment of the first bit line to a corresponding bit line decoder among the plurality of bit line decoders; a second subset of bit line slots arranged according to a second periodicity and coupling a corresponding segment of the second bit line to a corresponding bit line decoder among the plurality of bit line decoders; and a third subset of bit line slots arranged according to the second periodicity and coupling a corresponding segment of the third bit line to a corresponding bit line decoder among the plurality of bit line decoders.

22. The method of claim 21, wherein the second periodicity is greater than the first periodicity.

23. The method of claim 22, wherein each bit slot of the second subset of bit slots intersects the segment between the ends of each segment of the second bit line, and each bit slot of the third subset of bit slots intersects the segment between the ends of each segment of the third bit line.

24. The method of claim 23, wherein each bit slot of the first subset of bit line slots divides each segment of the first bit line into a first sub-segment and a second sub-segment.

25. A method for operating a memory device, comprising: Identify at least one cell of a memory array, the memory array comprising a plurality of slabs, each of the plurality of slabs comprising a plurality of sub-blocks and a plurality of layers, wherein each of the plurality of sub-blocks comprises a plurality of memory cells of the memory array addressable via a plurality of word lines and a plurality of bit lines, the plurality of bit lines comprising: a first bit line coupled to a first layer and a second layer of the plurality of layers; a second bit line coupled to a third layer and a fourth layer of the plurality of layers; and a third bit line coupled to a fifth layer and a sixth layer of the plurality of layers; and At least one cell of the memory array is accessed using a plurality of bitline decoders positioned below the memory array, wherein a first bitline decoder of the plurality of bitline decoders is coupled to the first bitline using a first configuration of slots within a first subset of the plurality of sub-blocks, a second bitline decoder of the plurality of bitline decoders is coupled to the second bitline using a second configuration of slots within a second subset of the plurality of sub-blocks, and a third bitline decoder of the plurality of bitline decoders is coupled to the third bitline using a third configuration of slots within a third subset of the plurality of sub-blocks.

26. The method of claim 25, wherein at least one of the plurality of sub-blocks includes a slot that couples more than one bit line to a corresponding bit line decoder among the plurality of bit line decoders.

27. The method according to claim 26, wherein: The plurality of bit lines further includes a fourth bit line, which is coupled to the seventh and eighth layers of the plurality of layers; and The fourth bitline decoder of the plurality of bitline decoders is coupled to the fourth bitline using a fourth configuration of slots.

28. The method of claim 27, wherein the first sub-block of the plurality of sub-blocks includes the first configuration of the slot, the second configuration of the slot, and the fourth configuration of the slot, and the second sub-block of the plurality of sub-blocks includes the first configuration of the slot, the second configuration of the slot, and the third configuration of the slot.

29. The method of claim 27, wherein a first pair of sub-blocks of the first configuration of the slot is separated by a first sub-block comprising a second configuration of the slot and a fourth configuration of the slot, and a second pair of sub-blocks of the first configuration of the slot is separated by a second sub-block comprising a second configuration of the slot and a third configuration of the slot.

30. The method of claim 25, wherein the first sub-block of the plurality of sub-blocks includes the first configuration of the slot and the second configuration of the slot, and the second sub-block of the plurality of sub-blocks includes the first configuration of the slot and the third configuration of the slot.

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