A low voltage differential signal self-training transmission device, platform and application method

Abstract

The present invention discloses a low voltage differential signal self-training transmission device, platform and application method. The device of the present invention comprises a low voltage differential signal module LVDS respectively arranged in a pair of FPGAs, and the LVDS comprises: a data sending module, which is used to send out a training data packet, and changes the format of the training data packet by detecting the feedback signal of the data receiving module inside the FPGA, and at the same time confirms whether the training of another FPGA is completed; a data receiving module, which is used to receive the training data packet for parsing, adjusting the phase and recovering the parallel data; the data sending module and the data receiving module are connected to each other and respectively connected to the device under test DUT, the data sending module is connected to the data receiving module in another FPGA, and the data receiving module is connected to the data sending module in another FPGA. The present invention aims to improve the transmission bandwidth between FPGAs and ensure that the data between the two FPGAs can be sent and received synchronously.

Description

Technical Field

[0001] The present invention relates to the communication field of FPGA chips, and in particular to a low-voltage differential signal self-training transmission device, platform and application method. Background Art

[0002] In a multi-FPGA simulation verification platform, adjacent FPGA chips need to frequently exchange data. LVDS (Low Voltage Differential Signaling) is a transmission technology with low latency, low power consumption and high anti-interference ability, which can solve the problem of efficient interconnection between multiple FPGA chips. During data transmission, due to the delay caused by the internal routing of the FPGA and the external connection between the FPGAs, there is a timing difference between the clock and the data. It is necessary to first perform self-training and adjust the channel delay at the receiving end to achieve alignment of the data channel and the clock channel before user data transmission. In data transmission, how to broadcast the user layer of each FPGA after the training is completed to realize the switching between the training mode and the data transmission mode has become an urgent problem to be solved. In order to solve the above problem, one of the main means is to add a feedback signal channel between the two FPGAs, and the receiving FPGA feeds back the training completion signal to the sending FPGA. However, due to the delay of the feedback signal connection between the FPGAs, the user layer data between the FPGAs cannot be sent and received synchronously. Summary of the invention

[0003] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a low-voltage differential signal self-training transmission device, platform and application method are provided. The present invention aims to improve the transmission bandwidth between FPGAs and ensure that data between two FPGAs can be sent and received synchronously.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A low voltage differential signal self-training transmission device includes a low voltage differential signal module LVDS respectively arranged in a pair of FPGAs, wherein the low voltage differential signal module LVDS includes:

[0006] The data sending module is used to send out the training data packet, change the format of the training data packet by detecting the feedback signal of the data receiving module inside the FPGA, and confirm whether the training of another FPGA is completed;

[0007] A data receiving module, used for receiving training data packets, analyzing and adjusting phases, and recovering parallel data;

[0008] The data sending module and the data receiving module are connected to each other and are respectively connected to the device under test DUT in the local FPGA, the data sending module is connected to the data receiving module in another FPGA, and the data receiving module is connected to the data sending module in another FPGA.

[0009] Optionally, the data sending module includes:

[0010] A link training sending module, used for sending link training data;

[0011] A command code generation module is used to detect whether the local training completion signal my_rx_rdy of the data receiving module in the local FPGA is pulled high. If the local training completion signal my_rx_rdy is pulled high, the link training data sent by the link training sending module is adjusted to notify another FPGA to inform the local FPGA that the training is completed;

[0012] The sending identification module is used to detect whether the training completion signal training_done of the data receiving module in the local FPGA is pulled high. If it is pulled high, it is determined that the training of another FPGA is completed;

[0013] The transmission channel adjustment module is used to adjust the differential data signal channel parameters of the data transmission module after determining that another FPGA training is completed.

[0014] Optionally, the link training data includes a training code pattern, a test code PRBS7 and a command code CMD, wherein the command code CMD is used to indicate a completion status of local FPGA training.

[0015] Optionally, the data receiving module includes:

[0016] The link training receiving module is used to receive link training data and enter the phase adjustment stage after receiving the training code pattern sent by another FPGA. The steps performed in the phase adjustment stage include: firstly, using the IDELAY3 primitive to increase the delay of each low voltage differential signal channel for phase compensation so that it can sample stable serial data, then using the ISERDES3 primitive to convert the serial data into parallel data, and finally restoring the training code pattern from the parallel data through a shift operation. If the training code pattern fails to be restored, the phase is readjusted;

[0017] The test code check module is used to detect the link quality through the test code PRBS7 after the training code pattern is successfully recovered to confirm whether there is a bit error. If there is a bit error, the link training receiving module is controlled to readjust the phase;

[0018] The command code check module is used to pull up the local training completion signal my_rx_rdy signal to indicate that the phase adjustment is completed when the test code check module detects the link quality and finds that there is no bit error;

[0019] The identification checking module is used to send a training completion signal training_done to the data sending module in the local FPGA after the command code checking module sends a local training completion signal my_rx_rdy to the data sending module in the local FPGA;

[0020] The receiving channel adjustment module is used to adjust the channel parameters of the differential data signal of the data receiving module after sending the training completion signal training_done.

[0021] Optionally, the signals transmitted by the physical signal transmission link between the data sending modules and the data receiving modules of different FPGAs include one pair of differential clock signals and multiple pairs of differential data signals.

[0022] In addition, the present invention also provides a multi-FPGA simulation verification platform, including two FPGAs connected to each other, both of which are provided with the low-voltage differential signal self-training transmission device, and the two FPGAs are bidirectionally connected through the low-voltage differential signal self-training transmission device.

[0023] Optionally, the two FPGAs are both provided with a designed DUT under test, the designed DUT under test is a chip under test or a functional module in the chip under test, and the designed DUT under test is connected to a low voltage differential signal self-training transmission device.

[0024] In addition, the present invention also provides an application method of the low voltage differential signal self-training transmission device, including selecting two FPGAs in a multi-FPGA simulation verification platform to write the design under test DUT, and using the data sending module and the data receiving module in the low voltage differential signal module LVDS of the two FPGAs to realize self-training of the low voltage differential signal module LVDS.

[0025] Optionally, when the data sending module and the data receiving module in the low voltage differential signal module LVDS of the two FPGAs are used to implement the self-training of the low voltage differential signal module LVDS, the working steps of the data sending module include:

[0026] S101, cyclically sending link training data to a data receiving module of another FPGA through a link training sending module, wherein the link training data includes a training code pattern, a test code PRBS7 and a command code CMD;

[0027] S102, detecting, by a command code generating module, whether a local training completion signal my_rx_rdy of a data receiving module in a local FPGA is pulled high, and if the local training completion signal my_rx_rdy is pulled high, adjusting a command code CMD in the link training data sent by a link training sending module to notify another FPGA to inform the local FPGA that training is completed;

[0028] S103, detecting whether a training completion signal training_done of a data receiving module in a local FPGA is pulled high by a sending identification module, and if so, determining that the training of another FPGA is completed;

[0029] S104, adjusting the differential data signal channel parameters of the data sending module through the sending channel adjustment module after determining that another FPGA training is completed.

[0030] Optionally, when the data sending module and the data receiving module in the low voltage differential signal module LVDS of the two FPGAs are used to implement the self-training of the low voltage differential signal module LVDS, the working steps of the data receiving module include:

[0031] S201, receiving link training data through a link training receiving module, and entering a phase adjustment phase after receiving a training code pattern sent by another FPGA. The steps performed in the phase adjustment phase include: firstly adding a delay to each differential data signal channel to perform phase compensation so that it samples stable serial data, then converting the serial data into parallel data, and finally restoring the training code pattern through a shift operation of the parallel data. If the training code pattern fails to be restored, the phase is readjusted;

[0032] S202, after the training code pattern is successfully recovered, the test code check module detects the link quality through the test code PRBS7 to confirm whether there is a bit error. If there is a bit error, the link training receiving module is controlled to readjust the phase;

[0033] S203, when the command code check module detects the link quality and finds that there is no bit error in the test code check module, the local training completion signal my_rx_rdy signal is pulled high to indicate that the phase adjustment is completed;

[0034] S204, after the command code checking module sends the local training completion signal my_rx_rdy to the data sending module in the local FPGA, the identification checking module sends the training completion signal training_done to the data sending module in the local FPGA;

[0035] S205 , adjusting the channel parameters of the differential data signal of the data receiving module through the receiving channel adjustment module after sending the training completion signal training_done.

[0036] Compared with the prior art, the present invention mainly has the following advantages: the present invention includes a low voltage differential signal module LVDS respectively arranged in a pair of FPGAs, the low voltage differential signal module LVDS includes: a data sending module, used to send out a training data packet, change the format of the training data packet by detecting the feedback signal of the data receiving module inside the FPGA, and confirm whether the training of another FPGA is completed; a data receiving module, used to receive the training data packet for parsing, adjusting the phase and recovering parallel data; the data sending module and the data receiving module are connected to each other and respectively connected to the device under test DUT in the local FPGA, the data sending module is connected to the data receiving module in another FPGA, and the data receiving module is connected to the data sending module in another FPGA. Through the above structure, a bidirectional data transmission method can be adopted between the two FPGAs, and it includes a sending end and a receiving end at the same time. During the training process, training is performed using a data packet with a feedback signal, and signal feedback is performed through a data channel, thereby increasing the transmission bandwidth between FPGAs and achieving synchronous transmission and reception of user layer data between multiple FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of the communication principle structure between two FPGAs, FPGA0 and FPGA1, in an embodiment of the present invention.

[0038] Figure 2 A schematic diagram of the module structure of a data sending module and a data receiving module in an embodiment of the present invention.

[0039] Figure 3 Schematic diagram of the sending / receiving state machine of the data sending module and the data receiving module in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below by taking the low voltage differential signal transmission between two FPGAs, FPGA0 and FPGA1, as an example.

[0041] like Figure 1 As shown, this embodiment provides a low voltage differential signal self-training transmission device, including low voltage differential signal modules LVDS respectively arranged in a pair of FPGAs, and the low voltage differential signal module LVDS includes:

[0042] The data sending module is used to send out the training data packet, change the format of the training data packet by detecting the feedback signal of the data receiving module inside the FPGA, and confirm whether the training of another FPGA is completed;

[0043] A data receiving module, used for receiving training data packets, analyzing and adjusting phases, and recovering parallel data;

[0044] The data sending module and the data receiving module are connected to each other and are respectively connected to the device under test DUT in the local FPGA, the data sending module is connected to the data receiving module in another FPGA, and the data receiving module is connected to the data sending module in another FPGA.

[0045] like Figure 2 As shown, the data sending module in this embodiment includes:

[0046] A link training sending module, used for sending link training data;

[0047] A command code generation module is used to detect whether the local training completion signal my_rx_rdy of the data receiving module in the local FPGA is pulled high. If the local training completion signal my_rx_rdy is pulled high, the link training data sent by the link training sending module is adjusted to notify another FPGA to inform the local FPGA that the training is completed;

[0048] The sending identification module is used to detect whether the training completion signal training_done of the data receiving module in the local FPGA is pulled high. If it is pulled high, it is determined that the training of another FPGA is completed;

[0049] The transmission channel adjustment module is used to adjust the differential data signal channel parameters of the data transmission module after determining that another FPGA training is completed.

[0050] In this embodiment, the link training data includes a training code pattern, a test code PRBS7 and a command code CMD, wherein the command code CMD is used to indicate the completion status of the local FPGA training. The test code PRBS7 is a code generated according to a specified format, and is used to determine the number of error bits to detect the link quality. As an optional implementation, the data format definition of the training code pattern, the test code PRBS7 and the command code CMD in this embodiment is shown in Table 1.

[0051] Table 1: Data format definition of training code pattern, test code PRBS7 and command code CMD.

[0052]

[0053] The test code PRBS7 is a pseudo-random binary sequence pattern, which is usually used to test the bit error rate of high-speed serial channel transmission. Its spectrum characteristics are very close to white noise. It is the most commonly used test pattern in serial buses below 10Gbps. It consists of a linear feedback shift register (LFSR) and an XOR circuit. The test code check module contains a PRBS7 generator model, whose seed SEED is consistent with the sending module. The polynomial is X7+X6+1, where X7 and X6 refer to the 7th and 6th bits of the randomly generated 8-bit data respectively. After recovering the training code pattern, the seed SEED is searched. After finding the seed SEED, the received test code PRBS7 is compared with the data of the generator model to see if there is a bit error. If there is a bit error, the link training receiving module is controlled to readjust the phase.

[0054] like Figure 2 As shown, the data receiving module in this embodiment includes:

[0055] The link training receiving module is used to receive link training data and enter the phase adjustment stage after receiving the training code pattern sent by another FPGA. The steps performed in the phase adjustment stage include: firstly, using the IDELAY3 primitive to increase the delay of each low voltage differential signal channel for phase compensation so that it can sample stable serial data, then using the ISERDES3 primitive to convert the serial data into parallel data, and finally restoring the training code pattern from the parallel data through a shift operation. If the training code pattern fails to be restored, the phase is readjusted;

[0056] The test code check module is used to detect the link quality through the test code PRBS7 after the training code pattern is successfully recovered to confirm whether there is a bit error. If there is a bit error, the link training receiving module is controlled to readjust the phase;

[0057] The command code check module is used to pull up the local training completion signal my_rx_rdy signal to indicate that the phase adjustment is completed when the test code check module detects the link quality and finds that there is no bit error;

[0058] The identification checking module is used to send a training completion signal training_done to the data sending module in the local FPGA after the command code checking module sends a local training completion signal my_rx_rdy to the data sending module in the local FPGA;

[0059] The receiving channel adjustment module is used to adjust the channel parameters of the differential data signal of the data receiving module after sending the training completion signal training_done.

[0060] In this embodiment, the signals transmitted by the physical signal transmission link between the data sending modules and the data receiving modules of different FPGAs include one pair of differential clock signals and multiple pairs of differential data signals.

[0061] In summary, in data transmission, in order to solve the problem of how to broadcast to the user layer of each FPGA after training is completed to realize the switching between the training mode and the data transmission mode, the low voltage differential signal self-training transmission device of this embodiment adopts a bidirectional data transmission method between two FPGAs. The FPGAs are composed of a pair of differential clock signals and multiple pairs of differential data signals. The LVDS module of each FPGA has a data sending module (TX) and a data receiving module (RX) for data transmission. The link training sending module of TX sends out the training data packet, changes the format of the training data packet by detecting the feedback signal of RX inside the FPGA, and confirms whether the training of another FPGA is completed. The link training receiving module of RX receives the training data packet for parsing, adjusts the phase and recovers the parallel data. The bidirectional data transmission method is adopted between the two FPGAs, and it includes a transmitting end and a receiving end at the same time. During the training process, the data packet with the feedback signal is used for training, and the signal feedback is performed through the data channel, which increases the transmission bandwidth between the FPGAs and achieves the synchronous transmission and reception of user layer data between multiple FPGAs.

[0062] In addition, this embodiment also provides a multi-FPGA simulation verification platform, including two FPGAs connected to each other, the two FPGAs are both provided with the aforementioned low voltage differential signal self-training transmission device, and the two FPGAs are bidirectionally connected via the low voltage differential signal self-training transmission device. In this embodiment, both FPGAs are provided with a design under test DUT, the design under test DUT is a chip under test or a functional module in the chip under test, and the design under test DUT is connected to the low voltage differential signal self-training transmission device.

[0063] In addition, this embodiment also provides an application method of the aforementioned low voltage differential signal self-training transmission device, including selecting two FPGAs in a multi-FPGA simulation verification platform to write the design under test DUT, and using the data sending module and data receiving module in the low voltage differential signal module LVDS of the two FPGAs to realize self-training of the low voltage differential signal module LVDS.

[0064] See also Figure 2 and Figure 3 In this embodiment, when the data sending module and the data receiving module in the low voltage differential signal module LVDS of two FPGAs are used to implement the self-training of the low voltage differential signal module LVDS, the working steps of the data sending module include:

[0065] S101, cyclically sending link training data to a data receiving module of another FPGA through a link training sending module, wherein the link training data includes a training code pattern, a test code PRBS7 and a command code CMD;

[0066] S102, detecting, by a command code generating module, whether a local training completion signal my_rx_rdy of a data receiving module in a local FPGA is pulled high, and if the local training completion signal my_rx_rdy is pulled high, adjusting a command code CMD in the link training data sent by a link training sending module to notify another FPGA to inform the local FPGA that training is completed;

[0067] S103, detecting whether a training completion signal training_done of a data receiving module in a local FPGA is pulled high by a sending identification module, and if so, determining that the training of another FPGA is completed;

[0068] S104, adjusting the differential data signal channel parameters of the data sending module through the sending channel adjustment module after determining that another FPGA training is completed.

[0069] Figure 1 and Figure 3 TX_Train_FSM in the figure indicates the transmission state machine used by the data transmission module. After initialization, the transmission state machine TX_Train_FSM is in the idle stage IDLE, and then enters the link training stage. In the link training stage, the link training transmission module is called to cyclically send the training code pattern, the test code PRBS7 and the command code CMD. Figure 3 In the transmission channel adjustment stage (Channel_change), the differential data signal channel parameters of the data transmission module are adjusted after the training of the other FPGA is completed.

[0070] See also Figure 2 and Figure 3In this embodiment, when the data sending module and the data receiving module in the low voltage differential signal module LVDS of two FPGAs are used to implement the self-training of the low voltage differential signal module LVDS, the working steps of the data receiving module include:

[0071] S201, receiving link training data through a link training receiving module, and entering a phase adjustment phase after receiving a training code pattern sent by another FPGA. The steps performed in the phase adjustment phase include: firstly adding a delay to each differential data signal channel to perform phase compensation so that it samples stable serial data, then converting the serial data into parallel data, and finally restoring the training code pattern through a shift operation of the parallel data. If the training code pattern fails to be restored, the phase is readjusted;

[0072] S202, after the training code pattern is successfully recovered, the test code check module detects the link quality through the test code PRBS7 to confirm whether there is a bit error. If there is a bit error, the link training receiving module is controlled to readjust the phase;

[0073] S203, when the command code check module detects the link quality and finds that there is no bit error in the test code check module, the local training completion signal my_rx_rdy signal is pulled high to indicate that the phase adjustment is completed;

[0074] S204, after the command code checking module sends the local training completion signal my_rx_rdy to the data sending module in the local FPGA, the identification checking module sends the training completion signal training_done to the data sending module in the local FPGA;

[0075] S205 , adjusting the channel parameters of the differential data signal of the data receiving module through the receiving channel adjustment module after sending the training completion signal training_done.

[0076] Figure 1 and Figure 3RX_Train_FSM in the figure represents the receiving state machine used by the data receiving module. After initialization, the receiving state machine RX_Train_FSM is in the idle state, and then enters the phase adjustment stage (Phase_Adjust and Slip). In the phase adjustment stage (Phase_Adjust and Slip), delay is first added to each differential data signal channel for phase compensation so that it can sample stable serial data, and then the serial data is converted into parallel data. Finally, the parallel data is shifted to restore the training code pattern. If the training code pattern fails to be restored, the phase is readjusted; if the training code pattern is successfully restored, the test code check stage (Prbs7_check) is entered. In the test code check stage (Prbs7_check), after the training code pattern is successfully restored, the test code check module uses the test code PRBS7 to detect the link quality and confirm whether there is a bit error. If there is a bit error, the link training receiving module is controlled to readjust the phase and return to the phase adjustment stage (Phase_Adjust and Slip), otherwise it enters the command code check stage (CMD_check). In the command code check phase (CMD_check), when the test code check module detects the link quality and finds no bit errors, the command code check module pulls up the local training completion signal my_rx_rdy to indicate that the phase adjustment is complete, and enters the flag check phase (flag_check). In the flag check phase (flag_check), after the command code check module sends the local training completion signal my_rx_rdy to the data sending module in the local FPGA, the flag check module sends the training completion signal training_done to the data sending module in the local FPGA; enters the receiving channel adjustment state (Channel_change). In the receiving channel adjustment state (Channel_change), after sending the training completion signal training_done, the receiving channel adjustment module adjusts the channel parameters of the differential data signal of the data receiving module, and ends and exits.

[0077] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A low voltage differential signal self-training transmission device, characterized in that: The invention comprises a low voltage differential signal module LVDS respectively arranged in a pair of FPGAs, wherein the low voltage differential signal module LVDS comprises: The data sending module is used to send out the training data packet, change the format of the training data packet by detecting the feedback signal of the data receiving module inside the FPGA, and confirm whether the training of another FPGA is completed; A data receiving module, used for receiving training data packets, analyzing and adjusting phases, and recovering parallel data; The data sending module and the data receiving module are connected to each other and are respectively connected to the device under test DUT in the local FPGA, the data sending module is connected to the data receiving module in another FPGA, and the data receiving module is connected to the data sending module in another FPGA; The data receiving module comprises: The link training receiving module is used to receive link training data and enter the phase adjustment stage after receiving the training code pattern sent by another FPGA. The steps performed in the phase adjustment stage include: firstly, using the IDELAY3 primitive to increase the delay of each low voltage differential signal channel for phase compensation so that it can sample stable serial data, then using the ISERDES3 primitive to convert the serial data into parallel data, and finally restoring the training code pattern from the parallel data through a shift operation. If the training code pattern fails to be restored, the phase is readjusted; The test code check module is used to detect the link quality through the test code PRBS7 after the training code pattern is successfully recovered to confirm whether there is a bit error. If there is a bit error, the link training receiving module is controlled to readjust the phase; The command code check module is used to pull up the local training completion signal my_rx_rdy signal to indicate that the phase adjustment is completed when the test code check module detects the link quality and finds that there is no bit error; The identification checking module is used to send a training completion signal training_done to the data sending module in the local FPGA after the command code checking module sends a local training completion signal my_rx_rdy to the data sending module in the local FPGA; The receiving channel adjustment module is used to adjust the channel parameters of the differential data signal of the data receiving module after sending the training completion signal training_done.

2. The low voltage differential signal self-training transmission device according to claim 1, characterized in that: The data sending module comprises: A link training sending module, used for sending link training data; A command code generation module is used to detect whether the local training completion signal my_rx_rdy of the data receiving module in the local FPGA is pulled high. If the local training completion signal my_rx_rdy is pulled high, the link training data sent by the link training sending module is adjusted to notify another FPGA to inform the local FPGA that the training is completed; The sending identification module is used to detect whether the training completion signal training_done of the data receiving module in the local FPGA is pulled high. If it is pulled high, it is determined that the training of another FPGA is completed; The transmission channel adjustment module is used to adjust the differential data signal channel parameters of the data transmission module after determining that another FPGA training is completed.

3. The low voltage differential signal self-training transmission device according to claim 2, characterized in that: The link training data includes a training code pattern, a test code PRBS7 and a command code CMD, wherein the command code CMD is used to indicate the completion status of the local FPGA training.

4. The low voltage differential signal self-training transmission device according to claim 3, characterized in that: The signals transmitted by the physical signal transmission link between the data sending modules and the data receiving modules of different FPGAs include one pair of differential clock signals and multiple pairs of differential data signals.

5. A multi-FPGA simulation verification platform, comprising two FPGAs connected to each other, characterized in that: The two FPGAs are both provided with the low voltage differential signal self-training transmission device according to any one of claims 1 to 4, and the two FPGAs are bidirectionally connected via the low voltage differential signal self-training transmission device.

6. The multi-FPGA simulation verification platform according to claim 5, characterized in that: The two FPGAs are both provided with a design under test (DUT), which is a chip under test or a functional module in the chip under test, and is connected to a low voltage differential signal self-training transmission device.

7. An application method of the low voltage differential signal self-training transmission device according to any one of claims 1 to 4, characterized in that: The method includes selecting two FPGAs in a multi-FPGA simulation verification platform to write the design under test DUT, and utilizing the data sending module and the data receiving module in the low voltage differential signal module LVDS of the two FPGAs to realize the self-training of the low voltage differential signal module LVDS.

8. The application method of the low voltage differential signal self-training transmission device according to claim 7, characterized in that: When the data sending module and the data receiving module in the low voltage differential signal module LVDS of the two FPGAs are used to implement the self-training of the low voltage differential signal module LVDS, the working steps of the data sending module include: S101, cyclically sending link training data to a data receiving module of another FPGA through a link training sending module, wherein the link training data includes a training code pattern, a test code PRBS7 and a command code CMD; S102, detecting, by a command code generating module, whether a local training completion signal my_rx_rdy of a data receiving module in a local FPGA is pulled high, and if the local training completion signal my_rx_rdy is pulled high, adjusting a command code CMD in the link training data sent by a link training sending module to notify another FPGA to inform the local FPGA that training is completed; S103, detecting whether a training completion signal training_done of a data receiving module in a local FPGA is pulled high by a sending identification module, and if so, determining that the training of another FPGA is completed; S104, adjusting the differential data signal channel parameters of the data sending module through the sending channel adjustment module after determining that another FPGA training is completed.

9. The application method of the low voltage differential signal self-training transmission device according to claim 8, characterized in that: When the data sending module and the data receiving module in the low voltage differential signal module LVDS of the two FPGAs are used to implement the self-training of the low voltage differential signal module LVDS, the working steps of the data receiving module include: S201, receiving link training data through a link training receiving module, and entering a phase adjustment phase after receiving a training code pattern sent by another FPGA. The steps performed in the phase adjustment phase include: firstly adding a delay to each differential data signal channel to perform phase compensation so that it samples stable serial data, then converting the serial data into parallel data, and finally restoring the training code pattern through a shift operation of the parallel data. If the training code pattern fails to be restored, the phase is readjusted; S202, after the training code pattern is successfully recovered, the test code check module detects the link quality through the test code PRBS7 to confirm whether there is a bit error. If there is a bit error, the link training receiving module is controlled to readjust the phase; S203, when the command code check module detects the link quality and finds that there is no bit error in the test code check module, the local training completion signal my_rx_rdy signal is pulled high to indicate that the phase adjustment is completed; S204, after the command code checking module sends the local training completion signal my_rx_rdy to the data sending module in the local FPGA, the identification checking module sends the training completion signal training_done to the data sending module in the local FPGA; S205 , adjusting the channel parameters of the differential data signal of the data receiving module through the receiving channel adjustment module after sending the training completion signal training_done.

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