Three-dimensional spiral inductor, manufacturing method thereof and electronic device

Abstract

A three-dimensional spiral inductor, its fabrication method, and an electronic device are disclosed. The three-dimensional spiral inductor, from bottom to top, comprises: a substrate; a first nitride dielectric layer, in which a first conductive layer is formed; a first oxide dielectric layer, in which a second conductive layer is formed; a second nitride dielectric layer, in which a third conductive layer is formed; and further comprises a first metal passivation layer and / or a second metal passivation layer, wherein the first conductive layer is located on the first metal passivation layer, and the second metal passivation layer is located on the second conductive layer. This invention forms a stacked structure of a first nitride dielectric layer, a first oxide dielectric layer, and a second nitride dielectric layer, and simultaneously forms a first metal passivation layer and / or a second metal passivation layer, which can better protect the first, second, and third conductive layers, effectively prevent device aging, thereby significantly reducing line losses and extending service life.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a three-dimensional spiral inductor, its fabrication method, and an electronic device thereof. Background Technology

[0002] With the development of semiconductor technology and the increase in chip integration, Moore's Law has encountered a major bottleneck, resulting in technical problems such as increased interconnect delay and power consumption. Three-dimensional integrated circuits provide a good solution to these problems. Among them, the three-dimensional spiral inductor is one of the most widely used passive components in three-dimensional integrated circuits.

[0003] However, the three-dimensional spiral inductors in related technologies mostly use metal materials directly deposited as inductor coils without protective measures, resulting in problems such as high line loss, rapid device aging, and short service life. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, one embodiment of the present invention provides a three-dimensional spiral inductor, comprising:

[0006] Base;

[0007] A first nitride dielectric layer is located on the substrate, and a first conductive layer is formed in the first nitride dielectric layer;

[0008] A first oxide dielectric layer is located on the first nitride dielectric layer, and a second conductive layer is formed in the first oxide dielectric layer that penetrates the first oxide dielectric layer in the thickness direction, and the second conductive layer is electrically connected to the first conductive layer.

[0009] A second nitride dielectric layer is located on the first oxide dielectric layer, and a third conductive layer is formed in the second nitride dielectric layer, wherein the third conductive layer is electrically connected to the second conductive layer;

[0010] It also includes a first metal passivation layer located in the first nitride dielectric layer, and / or a second metal passivation layer located in the second nitride dielectric layer, wherein the first conductor layer is located on the first metal passivation layer and the second metal passivation layer is located on the second conductor layer.

[0011] Exemplarily, it also includes a third nitride dielectric layer covering the second conductive layer.

[0012] For example, the thickness range of the first metal passivation layer and the second metal passivation layer is independently 50nm-100nm.

[0013] For example, the materials of the first metal passivation layer and the second metal passivation layer include at least one of the following:

[0014] MoTi, TiN, and TiW.

[0015] For example, the first nitride dielectric layer includes a first sub-nitride dielectric layer and a second sub-nitride dielectric layer, wherein:

[0016] The first subnitride dielectric layer is located on the substrate;

[0017] The first conductive layer is located on the first sub-nitride dielectric layer;

[0018] The second sub-nitride dielectric layer is located on the first conductor layer and the first sub-nitride dielectric layer, and the second conductor layer penetrates the second sub-nitride dielectric layer located on the first conductor layer and is electrically connected to the first conductor layer.

[0019] For example, the thickness of the first sub-nitride dielectric layer ranges from 10 nm to 100 nm, and the thickness of the second sub-nitride dielectric layer located on the first conductive layer ranges from 1 nm to 5 nm.

[0020] For example, the second nitride dielectric layer includes a third sub-nitride dielectric layer and a fourth sub-nitride dielectric layer, wherein:

[0021] The third sub-nitride dielectric layer is located on the first oxide dielectric layer;

[0022] The third conductor layer is located on the third sub-nitride dielectric layer, and the second conductor layer penetrates the third sub-nitride dielectric layer and is electrically connected to the third conductor layer;

[0023] The fourth sub-nitride dielectric layer is located on the third conductor layer and the third sub-nitride dielectric layer.

[0024] For example, the thickness of the third sub-nitride dielectric layer ranges from 1 nm to 5 nm, and the thickness of the fourth sub-nitride dielectric layer located on the third conductive layer ranges from 1 nm to 5 nm.

[0025] For example, the thickness of the third nitride dielectric layer ranges from 1 nm to 5 nm.

[0026] Exemplarily, it also includes a second oxide dielectric layer, which is located on the second nitride dielectric layer.

[0027] Another aspect of this invention provides a method for preparing a three-dimensional spiral inductor, comprising:

[0028] Provide a base;

[0029] A first nitride dielectric layer is formed on the substrate and a first conductive layer is formed within the first nitride dielectric layer;

[0030] A first oxide dielectric layer is formed on the first nitride dielectric layer;

[0031] The first oxide dielectric layer is etched to form a via;

[0032] A second conductive layer is formed to fill the through-hole, and the second conductive layer is electrically connected to the first conductive layer;

[0033] A second nitride dielectric layer is formed covering the first oxide dielectric layer and a third conductive layer is located in the second nitride dielectric layer, wherein the third conductive layer is electrically connected to the second conductive layer;

[0034] The method further includes:

[0035] A first metal passivation layer is formed in the first nitride dielectric layer, and / or a second metal passivation layer is formed in the second nitride dielectric layer, wherein the first conductor layer is located on the first metal passivation layer and the second metal passivation layer is located on the second conductor layer.

[0036] For example, prior to forming the second conductive layer, the method further includes:

[0037] A third nitride dielectric layer is formed to cover the sidewalls of the through-hole.

[0038] For example, the thickness range of the first metal passivation layer and the second metal passivation layer is independently 50nm-100nm.

[0039] For example, the materials of the first metal passivation layer and the second metal passivation layer include at least one of the following:

[0040] MoTi, TiN, and TiW.

[0041] Exemplarily, the first nitride dielectric layer includes a first sub-nitride dielectric layer and a second sub-nitride dielectric layer, forming a first nitride dielectric layer located on the substrate and a first conductive layer located in the first nitride dielectric layer, including:

[0042] The first subnitride dielectric layer is formed on the substrate;

[0043] The first conductive layer is formed on the first sub-nitride dielectric layer;

[0044] A second sub-nitride dielectric layer is formed on the first conductor layer and the first sub-nitride dielectric layer, and the second conductor layer penetrates the second sub-nitride dielectric layer located on the first conductor layer and is electrically connected to the first conductor layer.

[0045] For example, the thickness of the first sub-nitride dielectric layer ranges from 10 nm to 100 nm, and the thickness of the second sub-nitride dielectric layer located on the first conductive layer ranges from 1 nm to 5 nm.

[0046] Exemplarily, the second nitride dielectric layer includes a third sub-nitride dielectric layer and a fourth sub-nitride dielectric layer, forming a second nitride dielectric layer covering the first oxide dielectric layer and a third conductive layer located in the second nitride dielectric layer, including:

[0047] The third sub-nitride dielectric layer is formed on the first oxide dielectric layer;

[0048] The third conductive layer is formed on the third sub-nitride dielectric layer, and the second conductive layer penetrates the third sub-nitride dielectric layer and is electrically connected to the third conductive layer;

[0049] The fourth sub-nitride dielectric layer is formed on the third conductor layer and the third sub-nitride dielectric layer.

[0050] For example, the thickness of the third sub-nitride dielectric layer ranges from 1 nm to 5 nm, and the thickness of the fourth sub-nitride dielectric layer located on the third conductive layer ranges from 1 nm to 5 nm.

[0051] For example, the thickness of the third nitride dielectric layer ranges from 1 nm to 5 nm.

[0052] Exemplarily, etching the first oxide dielectric layer to form a via includes:

[0053] Etch the first oxide dielectric layer to form the portion of the via located in the first oxide dielectric layer;

[0054] The third nitride dielectric layer is formed on the sidewall of the portion of the through hole located in the first oxide dielectric layer;

[0055] Continue etching the first nitride dielectric layer located on the first conductive layer to form the via.

[0056] Exemplarily, after etching the first nitride dielectric located on the first conductive layer, the method further includes:

[0057] The through-hole was cleaned using argon-containing plasma.

[0058] Exemplarily, before forming the first nitride dielectric layer on the substrate, the method further includes a step of cleaning and drying the substrate, wherein:

[0059] The substrate is cleaned using at least one of the following methods: extreme ultraviolet lithography, chemical cleaning, deionized water cleaning, water-air two-fluid cleaning, and mega-sonic cleaning.

[0060] The temperature range for drying the substrate is 90 degrees Celsius to 120 degrees Celsius.

[0061] Exemplarily, after forming a second nitride dielectric layer covering the first oxide dielectric layer and a third conductive layer located in the second nitride dielectric layer, the method further includes:

[0062] A second oxide dielectric layer is formed on the second nitride dielectric layer.

[0063] In another aspect, the present invention provides an electronic device comprising the three-dimensional spiral inductor described above or a three-dimensional spiral inductor prepared according to the preparation method described above.

[0064] The three-dimensional spiral inductor, its fabrication method, and electronic device of this invention employ a stacked structure of a first nitride dielectric layer, a first oxide dielectric layer, and a second nitride dielectric layer to encapsulate a first conductive layer, a second conductive layer, and a third conductive layer. Simultaneously, a first metal passivation layer is formed beneath the first conductive layer and / or a second metal passivation layer is formed on the third conductive layer to further protect the first, second, and third conductive layers. This effectively prevents aging of the three-dimensional spiral inductor due to high temperature or oxidizing atmosphere during fabrication, as well as corrosion from external water and oxygen. It also effectively prevents device aging caused by external or internal component heating during use, thereby significantly reducing the line loss of the three-dimensional spiral inductor, improving the device's quality factor, and extending its service life. Attached Figure Description

[0065] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0066] In the attached image:

[0067] Figures 1A-1E The diagram shows a cross-sectional view of a three-dimensional spiral inductor obtained by sequentially implementing a method for preparing a three-dimensional spiral inductor according to a specific embodiment of the present invention.

[0068] Figure 2A flowchart illustrating a method for preparing a three-dimensional spiral inductor according to a specific embodiment of the present invention is shown;

[0069] Figure 3 A schematic diagram of the structure of a three-dimensional spiral inductor according to a specific embodiment of the present invention is shown. Detailed Implementation

[0070] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0071] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0072] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0075] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0076] To fully understand this invention, detailed steps and structures will be set forth in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0077] Below, refer to Figure 1E and Figure 3 The three-dimensional spiral inductor of the present invention will be described in detail below, specifically as follows: Figure 1EAs shown, the three-dimensional spiral inductor of this embodiment includes: a substrate 100; a first nitride dielectric layer 101 located on the substrate 100, wherein a first conductive layer 102 is formed in the first nitride dielectric layer 101; a first oxide dielectric layer 104 located on the first nitride dielectric layer 101, wherein a second conductive layer 107 is formed in the first oxide dielectric layer 104, penetrating the first oxide dielectric layer 104 in the thickness direction, and the second conductive layer 107 is electrically connected to the first conductive layer 102; the second nitride dielectric layer 104... The first oxide dielectric layer 108 is located on the first oxide dielectric layer 104. A third conductive layer 109 is formed in the second nitride dielectric layer 108 and is electrically connected to the second conductive layer 107. The second nitride dielectric layer 108 also includes a first metal passivation layer 103 located in the first nitride dielectric layer 101 and / or a second metal passivation layer 110 located in the second nitride dielectric layer 108. The first conductive layer 102 is located on the first metal passivation layer 103 and the second metal passivation layer 110 is located on the third conductive layer 109.

[0078] In one example, such as Figure 1E and Figure 3 As shown, in this embodiment of the invention, the second conductor layer 107 of the three-dimensional spiral inductor is electrically connected to the first conductor layer 102 and the third conductor layer 109. The stacked structure of the first nitride dielectric layer 101, the first oxide dielectric layer 104, and the second nitride dielectric layer 108 together serves to cover the first conductor layer 102, the second conductor layer 107, and the third conductor layer 109. This stacked structure design effectively utilizes the good compactness of the first nitride dielectric layer 101 and the second nitride dielectric layer 108, as well as the easy processing performance and good planarity of the first oxide dielectric layer 104, thereby effectively preventing the three-dimensional spiral inductor from being damaged by external or internal temperature fluctuations during use. This reduces elemental aging caused by high temperature and effectively prevents corrosion from external water and oxygen during the fabrication process. Simultaneously, a first metal passivation layer 103 is formed under the first conductive layer 102, and / or a second metal passivation layer 110 is formed on the third conductive layer 109. The first metal passivation layer 103 and the second metal passivation layer 110 have better oxidation resistance, effectively suppressing the aging of the first conductive layer 102, the second conductive layer 107, and the third conductive layer 109 caused by high temperature or oxidizing atmosphere during the fabrication process. It also further reduces device aging caused by external or internal device heating during use, further mitigating device aging issues.

[0079] Therefore, the three-dimensional spiral inductor of this invention has a stacked structure of a first nitride dielectric layer, a first oxide dielectric layer, and a second nitride dielectric layer to cover the first conductor layer, the second conductor layer, and the third conductor layer. It also has a first metal passivation layer located under the first conductor layer and / or a second metal passivation layer located on the third conductor layer to further protect the first, second, and third conductor layers. This effectively prevents aging caused by high temperature or oxidizing atmosphere during the fabrication process of the three-dimensional spiral inductor, as well as corrosion from external water and oxygen. Furthermore, it effectively prevents device aging caused by external or internal device heating during use, thereby significantly reducing the line loss of the three-dimensional spiral inductor, improving the device's quality factor, and extending its service life.

[0080] In one example, such as Figure 1E As shown, substrate 100 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors; or substrate 100 may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc.; or substrate 100 may be a glass substrate. Although several examples of materials that can form substrate 100 have been described herein, any material that can serve as substrate 100 falls within the spirit and scope of the embodiments of the present invention.

[0081] In one example, such as Figure 1E As shown, the three-dimensional spiral inductor also includes a third nitride dielectric layer 106 covering the second conductive layer 107. The third nitride dielectric layer 106 effectively prevents water and oxygen from corroding the second conductive layer 107. Simultaneously, the third nitride dielectric layer 106, together with the first nitride dielectric layer 101 and the second nitride dielectric layer 108, provides comprehensive coverage for the first conductive layer 102, the second conductive layer 107, and the third conductive layer 109, thereby more effectively preventing water and oxygen corrosion and providing better protection. Exemplarily, the thickness of the third nitride dielectric layer ranges from 1 nm to 5 nm. Exemplarily, the materials of the first nitride dielectric layer 101, the second nitride dielectric layer 108, and the third nitride dielectric layer 106 include silicon nitride.

[0082] In one example, such as Figure 1E As shown, the materials of the first metal passivation layer 103 and the second metal passivation layer 110 include at least one of the following: MoTi, TiN, and TiW. For example, the thicknesses of the first metal passivation layer 103 and the second metal passivation layer 110 are each independently in the range of 50 nm to 100 nm.

[0083] In one example, such as Figure 1E As shown, the materials of the first conductive layer 102 and the third conductive layer 109 include copper, aluminum, molybdenum, titanium, etc., and the materials of the second conductive layer 107 include copper, aluminum, gold, silver, etc. The thickness of the first conductive layer 102, the second conductive layer 107, and the third conductive layer 109 should be selected according to the design requirements of the three-dimensional spiral inductor. Figure 3 As shown, multiple first conductive layers 102 and multiple third conductive layers 109 are respectively disposed on two mutually parallel planes, and the first conductive layers 102 and the third conductive layers 109 are disposed in different directions; the second conductive layer 107 is perpendicular to the first conductive layer 102 and the third conductive layer 109, and its shape includes, but is not limited to, a cylinder. The multiple first conductive layers 102, the multiple second conductive layers 107 and the multiple third conductive layers 109 are connected end to end to form a three-dimensional spiral structure.

[0084] In one example, such as Figure 1E As shown, the three-dimensional spiral inductor of this embodiment of the invention also includes a second oxide dielectric layer 111 located on the second nitride dielectric layer 108. The second oxide dielectric layer 111 has good planar properties, which can help improve the flatness of the device.

[0085] In one example, such as Figure 1E As shown, the first oxide dielectric layer 104 and the second oxide dielectric layer 111 are made of silicon oxide, and the thickness of the first oxide dielectric layer 104 and the second oxide dielectric layer 111 can be a suitable thickness selected according to the design requirements of the actual three-dimensional spiral inductor.

[0086] In one example, such as Figure 1EAs shown, the first nitride dielectric layer 101 includes a first sub-nitride dielectric layer 1011 and a second sub-nitride dielectric layer 1012, wherein: the first nitride dielectric layer 1011 is located on the substrate 100; a first conductive layer 102 is located on the first sub-nitride dielectric layer 1011; the second sub-nitride dielectric layer 1012 is located on the first sub-nitride dielectric layer 1011 and covers the first conductive layer 102, and the second conductive layer 107 penetrates the first conductive layer 102 and is electrically connected to the first conductive layer 102. Exemplarily, when the three-dimensional spiral inductor includes a first metal passivation layer 103, the first metal passivation layer 103 is located on the first sub-nitride dielectric layer 1011, and the first conductive layer 102 is located on the first metal passivation layer 103. For example, the thickness of the first sub-nitride dielectric layer 1011 ranges from 10 nm to 100 nm; the second sub-nitride layer 1012 includes a portion located on the first conductive layer 102 and a portion located on the first sub-nitride layer 1012, wherein the second sub-nitride layer 1012 located on the first conductive layer 102 refers to the portion of the second sub-nitride dielectric layer 1012 covering the surface of the first conductive layer 102, and the thickness of the second sub-nitride dielectric layer 1012 located on the first conductive layer 102 ranges from 1 nm to 5 nm. For example, the first sub-nitride dielectric layer 1011 and the second sub-nitride dielectric layer 1012 covering the first conductive layer 102 can effectively prevent the corrosion of the first conductive layer 102 by subsequent fabrication processes and external water and oxygen, and can effectively reduce the degradation of inductor performance.

[0087] In one example, such as Figure 1E As shown, the second nitride dielectric layer 108 includes a third sub-nitride dielectric layer 1081 and a fourth sub-nitride dielectric layer 1082, wherein: the third sub-nitride dielectric layer 1081 is located on the first oxide dielectric layer 104; the third conductive layer 109 is located on the third sub-nitride dielectric layer 1081, and the second conductive layer 107 penetrates the third sub-nitride dielectric layer 1081 and is electrically connected to the third conductive layer 109; the fourth sub-nitride dielectric layer 1082 is located on the third conductive layer 109 and the third sub-nitride dielectric layer 1081. Exemplarily, when the three-dimensional spiral inductor includes a second metal passivation layer 110, the second metal passivation layer 110 is located on the third conductive layer 109, and the fourth sub-nitride dielectric layer 1082 is located on the second metal passivation layer 110 and the third sub-nitride dielectric layer 1081. For example, the thickness of the third sub-nitride dielectric layer 1081 ranges from 1 nm to 5 nm, and the thickness of the fourth sub-nitride dielectric layer 1082 located on the third conductive layer 109 ranges from 1 nm to 5 nm. For example, the third sub-nitride dielectric layer 1081 and the fourth sub-nitride dielectric layer 1082 covering the third conductive layer 109 can effectively prevent the third conductive layer 109 from being eroded by subsequent fabrication processes and external water and oxygen, and can effectively reduce the degradation of inductor performance.

[0088] In summary, the three-dimensional spiral inductor of this invention employs a stacked structure of a first nitride dielectric layer, a first oxide dielectric layer, and a second nitride dielectric layer to encapsulate the first, second, and third conductive layers. Simultaneously, a first metal passivation layer is formed beneath the first conductive layer and / or a second metal passivation layer is formed on the third conductive layer to further protect the first, second, and third conductive layers. This effectively prevents aging caused by high temperatures or oxidizing atmospheres during the fabrication process of the three-dimensional spiral inductor, as well as corrosion from external water and oxygen. It also effectively prevents device aging caused by external or internal component heating during use, thereby significantly reducing the line loss of the three-dimensional spiral inductor, improving the device's quality factor, and extending its service life. Exemplarily, a third nitride dielectric layer is also formed to encapsulate the second conductive layer, providing better protection. Exemplarily, a second oxide dielectric layer is also formed to improve the flatness of the device.

[0089] Another aspect of this invention provides a method for preparing a three-dimensional spiral inductor, such as... Figure 2 As shown, the fabrication method of this three-dimensional spiral inductor mainly includes the following steps:

[0090] In step S210, a substrate is provided;

[0091] In step S220, a first nitride dielectric layer and a first conductive layer are formed on the substrate;

[0092] In step S230, a first oxide dielectric layer is formed on the first nitride dielectric layer;

[0093] In step S240, the first oxide dielectric layer is etched to form a via;

[0094] In step S250, a second conductive layer is formed to fill the through-hole, and the second conductive layer is electrically connected to the first conductive layer;

[0095] In step S260, a second nitride dielectric layer covering the first oxide dielectric layer and a third conductive layer located in the second nitride dielectric layer are formed, wherein the third conductive layer is electrically connected to the second conductive layer;

[0096] Meanwhile, the method for fabricating a three-dimensional spiral inductor according to the present invention further includes: forming a first metal passivation layer located in the first nitride dielectric layer, and / or a second metal passivation layer located in the second nitride dielectric layer, wherein the first conductor layer is located on the first metal passivation layer, and the second metal passivation layer is located on the second conductor layer.

[0097] The fabrication method of the three-dimensional spiral inductor in this invention involves forming a stacked structure of a first nitride dielectric layer, a first oxide dielectric layer, and a second nitride dielectric layer to cover the first conductor layer, the second conductor layer, and the third conductor layer. Simultaneously, a first metal passivation layer is formed under the first conductor layer and / or a second metal passivation layer is formed on the third conductor layer to further protect the first, second, and third conductor layers. This effectively prevents aging of the three-dimensional spiral inductor due to high temperature or oxidizing atmosphere during fabrication, as well as corrosion from external water and oxygen. It also effectively prevents device aging caused by external or internal component heating during use, thereby significantly reducing the line loss of the three-dimensional spiral inductor, improving the device's quality factor, and extending its service life.

[0098] Below, refer to Figures 1A to 2 The method for preparing the three-dimensional spiral inductor of the present invention is described in detail, wherein, Figures 1A-1E The diagram shows a cross-sectional view of a three-dimensional spiral inductor obtained by sequentially implementing a method for preparing a three-dimensional spiral inductor according to a specific embodiment of the present invention. Figure 2 A flowchart illustrating a method for fabricating a three-dimensional spiral inductor according to a specific embodiment of the present invention is shown. Exemplarily, as... Figure 2 As shown, the method for preparing the three-dimensional spiral inductor of the present invention includes the following steps:

[0099] First, execute step S210, such as Figure 1A As shown, a substrate 100 is provided. Exemplarily, the substrate 100 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors; or the substrate 100 may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc.; or the substrate 100 may also be a glass substrate. Although several examples of materials that can form the substrate 100 have been described herein, any material that can serve as the substrate 100 falls within the spirit and scope of the invention.

[0100] Next, proceed to step S220, as follows: Figure 1A As shown, a first nitride dielectric layer 101 is formed on a substrate 100, and a first conductive layer 102 is formed within the first nitride dielectric layer 101. Exemplarily, various deposition methods commonly used in the art can be employed to form the first nitride dielectric layer 101 and the first conductive layer 102. For example, chemical vapor deposition (CVD) can be used to form the first nitride dielectric layer 101, where the material of the first nitride dielectric layer 101 includes silicon nitride (SiN). xDuring deposition, the reaction gases include silane, ammonia, and hydrogen. It should be noted that at higher reaction temperatures, SiN... x The thin film is formed relatively quickly, and the SiN produced by the reaction... x The short residence time in a hydrogen-rich atmosphere makes it difficult for NH bonds to form, and at higher temperatures, SiN... x Hydrogen in the thin film is prone to volatilization, thus reducing the SiN content. x The hydrogen content in the thin film can therefore be adjusted by temperature in SiN. x The hydrogen content in the thin film; the first conductive layer 102 can be formed using chemical vapor deposition (CVD) or physical vapor deposition (PVD). For example, the first nitride dielectric layer 101 effectively prevents subsequent fabrication processes and external water and oxygen from eroding the first conductive layer 102.

[0101] In one example, the material of the first conductor layer 102 includes copper, aluminum, molybdenum, titanium, etc., and the thickness of the first conductor layer 102 can be a suitable thickness selected according to the design requirements of the three-dimensional spiral inductor.

[0102] In one example, before forming the first nitride dielectric layer 101 on the substrate 100, the method further includes cleaning and drying the substrate 100, wherein: the substrate 100 is cleaned using at least one of the following methods: extreme ultraviolet lithography, chemical cleaning, deionized water cleaning, water-air two-fluid cleaning, and megasonic cleaning; and the temperature range for drying the substrate 100 is 90 degrees Celsius to 120 degrees Celsius. Exemplarily, after cleaning the substrate 100, ideally, the surface of the substrate 100 is free of particles with a diameter greater than 1 micrometer.

[0103] In one example, the method of this embodiment of the invention further includes: forming a first metal passivation layer 103 located in a first nitride dielectric layer 101, and / or a second metal passivation layer 110 located in a second nitride dielectric layer 108 formed in a subsequent process, wherein a first conductive layer 102 is located on the first metal passivation layer 103, and the second metal passivation layer 110 is located on a third conductive layer 109 formed in a subsequent process. Exemplarily, various deposition methods commonly used in the art can be employed to form the first metal passivation layer 103, for example, physical vapor deposition (PVD) or electroplating can be used to form the first metal passivation layer 103. Exemplarily, the material of the first metal passivation layer 103 includes at least one of the following: MoTi, TiN, and TiW. Exemplarily, the thickness of the first metal passivation layer 103 ranges from 50 nm to 100 nm.

[0104] In one example, such as Figure 1AAs shown, the first nitride dielectric layer 101 includes a first sub-nitride dielectric layer 1011 and a second sub-nitride dielectric layer 1012, forming a first nitride dielectric layer 101 located on a substrate 100 and a first conductive layer 102 located in the first nitride dielectric layer 101. The process includes: forming a first sub-nitride dielectric layer 1011 on the substrate 100; forming a first conductive layer 102 on the first sub-nitride dielectric layer 1011; forming a second sub-nitride dielectric layer 1012 on the first conductive layer 102 and the first sub-nitride dielectric layer 1011; and electrically connecting a second conductive layer 107 through the second sub-nitride dielectric layer 1012 located on the first conductive layer 102 to the first conductive layer 102.

[0105] For example, forming a first metal passivation layer 103 in a first nitride dielectric layer 101 includes: forming the first metal passivation layer 103 on the first nitride dielectric layer 1011, and forming a first conductive layer 102 on the first metal passivation layer 103. For example, after forming the first metal passivation layer 103 and the first conductive layer 102, the method further includes a step of patterning the first metal passivation layer 103 and the first conductive layer 102, for example, by photolithography. For example, the thickness of the first sub-nitride dielectric layer 1011 ranges from 10 nm to 100 nm, and the thickness of the second sub-nitride dielectric layer 1012 located on the first conductive layer 102 ranges from 1 nm to 5 nm. For example, the first sub-nitride dielectric layer 1011 and the second sub-nitride dielectric layer 1012 covering the first conductor layer 102 can effectively prevent the corrosion of the first conductor layer 102 by subsequent manufacturing processes and external water and oxygen, and can effectively reduce the degradation of inductor performance.

[0106] Next, proceed to step S230, as follows: Figure 1B As shown, a first oxide dielectric layer 104 is formed on the first nitride dielectric layer 101. Exemplarily, various deposition methods commonly used in the art can be employed to form the first oxide dielectric layer 104. For example, chemical vapor deposition (CVD) can be used to form the first oxide dielectric layer 104. When the material of the first oxide dielectric layer 104 includes silicon oxide, the reactant gases include silane (SiH) and nitrous oxide (N2O). Exemplarily, the first oxide dielectric layer 104 has easy processing properties and good planarity, which can effectively improve the flatness of the device.

[0107] Next, proceed to step S240, as follows: Figure 1CAs shown, the first oxide dielectric layer 104 is etched to form a via 105. Various etching processes commonly used in the art can be employed to etch the first oxide dielectric layer 104 to form the via 105. For example, deep reactive ion etching (DRIE) can be used to etch the first oxide dielectric layer 104 to form the via 105. Exemplarily, the via 105 should expose the surface of the first conductive layer 102.

[0108] In one example, such as Figure 1C As shown, before the subsequent formation of the second conductive layer 107 filling the via 105, a third nitride dielectric layer 106 covering the sidewalls of the via 105 is further included. Exemplarily, various deposition methods commonly used in the art can be employed to form the third nitride dielectric layer 106; for example, chemical vapor deposition (CVD) can be used to form the third nitride dielectric layer 106. Exemplarily, the thickness of the third nitride dielectric layer 106 ranges from 1 nm to 5 nm. Exemplarily, the material of the third nitride dielectric layer 106 includes silicon nitride. The third nitride dielectric layer 106 effectively prevents water and oxygen from eroding the subsequently formed second conductive layer 107.

[0109] In one example, etching the first oxide dielectric layer 104 to form a via 105 includes: etching the first oxide dielectric layer 104 to form a portion of the via 105 located in the first oxide dielectric layer 104; forming a third nitride dielectric layer 106 on the sidewall of the portion of the via 105 located in the first oxide dielectric layer 104; and continuing to etch the first nitride dielectric layer 101 on the first conductive layer 102 to form the via 105. Exemplarily, various etching processes commonly used in the art can be employed to etch the first nitride dielectric layer 101 on the first conductive layer 102. For example, a deep reactive ion etching (DRIE) method can be used to etch the first nitride dielectric layer 101 on the first conductive layer 102. Exemplarily, continuing to etch the first nitride dielectric layer 101 on the first conductive layer 102 includes: continuing to etch a second sub-nitride dielectric layer 1012 on the first conductive layer 102 to form the via 105.

[0110] Next, proceed to step S250, as follows: Figure 1DAs shown, a second conductive layer 107 is formed to fill the via 105, and the second conductive layer 107 is electrically connected to the first conductive layer 102. Exemplarily, various deposition methods commonly used in the art can be employed to form the second conductive layer 107, such as chemical vapor deposition (CVD), electroplating, or evaporation. Exemplarily, the material of the second conductive layer 107 includes copper, aluminum, gold, silver, etc., and the thickness of the second conductive layer 107 can be a suitable thickness selected according to the design requirements of the three-dimensional spiral inductor. Exemplarily, after forming the second conductive layer 107, the process further includes chemical mechanical polishing of the second conductive layer 107 to remove burrs and protrusions near the via 105. Exemplarily, the top surface of the second conductive layer 107 is higher than the via 105 to facilitate electrical connection between the subsequently formed third conductive layer 109 and the second conductive layer 107.

[0111] In one example, after etching the first nitride dielectric layer 101 located on the first conductive layer 102, the process further includes cleaning the via 105 with argon plasma. By cleaning the via 105 with argon plasma, particulate residues in the via 105 can be removed, and the surface of the first conductive layer 102 can be roughened, increasing the surface roughness and thus increasing the surface tension of the first conductive layer 102.

[0112] Next, proceed to step S260, as follows: Figure 1E As shown, a second nitride dielectric layer 108 is formed covering the first oxide dielectric layer 104, and a third conductive layer 109 is located within the second nitride dielectric layer 108. The third conductive layer 109 is electrically connected to the second conductive layer 107. Exemplarily, various deposition methods commonly used in the art can be employed to form the second nitride dielectric layer 108 and the third conductive layer 109. For example, chemical vapor deposition (CVD) can be used to form the second nitride dielectric layer 108, and chemical vapor deposition (CVD) or physical vapor deposition (PVD) can be used to form the third conductive layer 109. The second nitride dielectric layer 108 effectively prevents subsequent fabrication processes and external water and oxygen from eroding the third conductive layer 109.

[0113] In one example, the material of the third conductor layer 109 includes copper, aluminum, molybdenum, titanium, etc., and the thickness of the third conductor layer 109 can be reasonably selected according to the design requirements of the three-dimensional spiral inductor.

[0114] In one example, such as Figure 1EAs shown, after forming the third conductive layer 109, a second metal passivation layer 110 can be formed within the second nitride dielectric layer 108, with the second metal passivation layer 110 located on the third conductive layer 109. Exemplarily, various deposition methods commonly used in the art can be employed to form the second metal passivation layer 110; for example, physical vapor deposition (PVD) can be used to form the second metal passivation layer 110. Exemplarily, the material of the second metal passivation layer 110 includes at least one of the following: MoTi, TiN, and TiW. Exemplarily, the thickness of the second metal passivation layer 110 ranges from 50 nm to 100 nm.

[0115] In one example, such as Figure 1E As shown, the second nitride dielectric layer 108 includes a third sub-nitride dielectric layer 1081 and a fourth sub-nitride dielectric layer 1082, forming a second nitride dielectric layer 108 covering the first oxide dielectric layer 104 and a third conductive layer 109 located in the second nitride dielectric layer 108. The process includes: forming the third sub-nitride dielectric layer 1081 on the first oxide dielectric layer 104; forming the third conductive layer 109 on the third sub-nitride dielectric layer 1081; and electrically connecting the second conductive layer 107 through the third sub-nitride dielectric layer 1081 and the third conductive layer 109; and forming the fourth sub-nitride dielectric layer 1082 on the third conductive layer 109 and the third sub-nitride dielectric layer 1081.

[0116] For example, forming a second metal passivation layer 110 in the second nitride dielectric layer 108 includes: forming the second metal passivation layer 110 on the third conductive layer 109, and forming a fourth sub-nitride dielectric layer 1082 on the second metal passivation layer 110 and the third sub-nitride dielectric layer 1081.

[0117] After forming the third conductive layer 109 and the second metal passivation layer 110, the method further includes a step of patterning the third conductive layer 109 and the second metal passivation layer 110. For example, the third conductive layer 109 and the second metal passivation layer 110 can be patterned by photolithography. Exemplarily, the thickness of the third sub-nitride dielectric layer 1081 ranges from 1 nm to 5 nm; the fourth sub-nitride dielectric layer 1082 includes a portion located on the third conductive layer 109 and a portion located on the third sub-nitride layer 1081, wherein the fourth sub-nitride dielectric layer 1082 located on the third conductive layer 109 refers to the portion of the fourth sub-nitride dielectric layer 1082 covering the surface of the third conductive layer 109, and the thickness of the fourth sub-nitride dielectric layer 1082 located on the third conductive layer 109 ranges from 1 nm to 5 nm. The third sub-nitride dielectric layer 1081 and the fourth sub-nitride dielectric layer 1082 covering the third conductor layer 109 can effectively prevent the third conductor layer 109 from being eroded by subsequent fabrication processes and external water and oxygen, and can effectively reduce the degradation of inductor performance.

[0118] In one example, such as Figure 1E As shown, after forming the second nitride dielectric layer 108, a second oxide dielectric layer 111 is formed on the second nitride dielectric layer 108. The second oxide dielectric layer 111 has good planarity, which helps to improve the flatness of the device. Exemplarily, after forming the second oxide dielectric layer 111, the second oxide dielectric layer 111 can also be planarized.

[0119] In one example, the material of the second oxide dielectric layer 111 includes silicon oxide, and the thickness of the second oxide dielectric layer 111 can be reasonably selected according to the design requirements of the actual three-dimensional spiral inductor.

[0120] This concludes the description of the key steps in the preparation method of the three-dimensional spiral inductor according to the embodiments of the present invention. The preparation of the complete three-dimensional spiral inductor may include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0121] In summary, the fabrication method of the three-dimensional spiral inductor according to the embodiments of the present invention covers the first conductive layer, the second conductive layer, and the third conductive layer by forming a stacked structure of a first nitride dielectric layer, a first oxide dielectric layer, and a second nitride dielectric layer. Simultaneously, a first metal passivation layer is formed under the first conductive layer and / or a second metal passivation layer is formed on the third conductive layer to further protect the first, second, and third conductive layers. This effectively prevents aging of the three-dimensional spiral inductor due to high temperature or oxidizing atmosphere during fabrication, as well as corrosion from external water and oxygen. It also effectively prevents device aging caused by external or internal component heating during use, thereby significantly reducing the line loss of the three-dimensional spiral inductor, improving the device's quality factor, and extending its service life.

[0122] In another aspect, the present invention provides an electronic device comprising the aforementioned three-dimensional spiral inductor or a three-dimensional spiral inductor prepared according to the aforementioned preparation method.

[0123] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including the aforementioned three-dimensional spiral inductor. The electronic device in this embodiment of the invention has better performance due to the use of the aforementioned three-dimensional spiral inductor.

[0124] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A three-dimensional spiral inductor, characterized in that, include: Base; A first nitride dielectric layer is located on the substrate, and a first conductive layer is formed in the first nitride dielectric layer; A first oxide dielectric layer is located on the first nitride dielectric layer, and a second conductive layer is formed in the first oxide dielectric layer that penetrates the first oxide dielectric layer in the thickness direction, and the second conductive layer is electrically connected to the first conductive layer. A second nitride dielectric layer is located on the first oxide dielectric layer, and a third conductive layer is formed in the second nitride dielectric layer, wherein the third conductive layer is electrically connected to the second conductive layer; It also includes a first metal passivation layer located in the first nitride dielectric layer and a second metal passivation layer located in the second nitride dielectric layer, wherein the first conductor layer is located on the first metal passivation layer and the second metal passivation layer is located on the second conductor layer; It also includes a third nitride dielectric layer covering the second conductor layer; It also includes a second oxide dielectric layer, which is located on the second nitride dielectric layer.

2. The three-dimensional spiral inductor according to claim 1, characterized in that, The thickness range of the first metal passivation layer and the second metal passivation layer is independently 50nm-100nm.

3. The three-dimensional spiral inductor according to claim 1, characterized in that, The materials of the first metal passivation layer and the second metal passivation layer include at least one of the following: MoTi, TiN, and TiW.

4. The three-dimensional spiral inductor according to claim 1, characterized in that, The first nitride dielectric layer includes a first sub-nitride dielectric layer and a second sub-nitride dielectric layer, wherein: The first subnitride dielectric layer is located on the substrate; The first conductive layer is located on the first sub-nitride dielectric layer; The second sub-nitride dielectric layer is located on the first conductor layer and the first sub-nitride dielectric layer, and the second conductor layer penetrates the second sub-nitride dielectric layer located on the first conductor layer and is electrically connected to the first conductor layer.

5. The three-dimensional spiral inductor according to claim 4, characterized in that, The thickness of the first sub-nitride dielectric layer ranges from 10 nm to 100 nm, and the thickness of the second sub-nitride dielectric layer located on the first conductive layer ranges from 1 nm to 5 nm.

6. The three-dimensional spiral inductor according to claim 1, characterized in that, The second nitride dielectric layer includes a third sub-nitride dielectric layer and a fourth sub-nitride dielectric layer, wherein: The third sub-nitride dielectric layer is located on the first oxide dielectric layer; The third conductor layer is located on the third sub-nitride dielectric layer, and the second conductor layer penetrates the third sub-nitride dielectric layer and is electrically connected to the third conductor layer; The fourth sub-nitride dielectric layer is located on the third conductor layer and the third sub-nitride dielectric layer.

7. The three-dimensional spiral inductor according to claim 6, characterized in that, The thickness of the third sub-nitride dielectric layer ranges from 1 nm to 5 nm, and the thickness of the fourth sub-nitride dielectric layer located on the third conductive layer ranges from 1 nm to 5 nm.

8. The three-dimensional spiral inductor according to claim 1, characterized in that, The thickness of the third nitride dielectric layer ranges from 1 nm to 5 nm.

9. A method for fabricating a three-dimensional spiral inductor, characterized in that, include: Provide a base; A first nitride dielectric layer is formed on the substrate and a first conductive layer is formed within the first nitride dielectric layer; A first oxide dielectric layer is formed on the first nitride dielectric layer; The first oxide dielectric layer is etched to form a via; A second conductive layer is formed to fill the through-hole, and the second conductive layer is electrically connected to the first conductive layer; A second nitride dielectric layer is formed covering the first oxide dielectric layer and a third conductive layer is located in the second nitride dielectric layer, wherein the third conductive layer is electrically connected to the second conductive layer; The method further includes: A first metal passivation layer is formed in the first nitride dielectric layer, and a second metal passivation layer is formed in the second nitride dielectric layer, wherein the first conductor layer is located on the first metal passivation layer, and the second metal passivation layer is located on the second conductor layer; Before forming the second conductive layer, the process also includes: A third nitride dielectric layer is formed to cover the sidewalls of the through-hole; After forming a second nitride dielectric layer covering the first oxide dielectric layer and a third conductive layer located within the second nitride dielectric layer, the method further includes: A second oxide dielectric layer is formed on the second nitride dielectric layer.

10. The preparation method according to claim 9, characterized in that, The thickness range of the first metal passivation layer and the second metal passivation layer is independently 50nm-100nm.

11. The preparation method according to claim 9, characterized in that, The materials of the first metal passivation layer and the second metal passivation layer include at least one of the following: MoTi, TiN, and TiW.

12. The preparation method according to claim 9, characterized in that, The first nitride dielectric layer includes a first sub-nitride dielectric layer and a second sub-nitride dielectric layer, forming a first nitride dielectric layer located on the substrate and a first conductive layer located in the first nitride dielectric layer, including: The first subnitride dielectric layer is formed on the substrate; The first conductive layer is formed on the first sub-nitride dielectric layer; A second sub-nitride dielectric layer is formed on the first conductor layer and the first sub-nitride dielectric layer, and the second conductor layer penetrates the second sub-nitride dielectric layer located on the first conductor layer and is electrically connected to the first conductor layer.

13. The preparation method according to claim 12, characterized in that, The thickness of the first sub-nitride dielectric layer ranges from 10 nm to 100 nm, and the thickness of the second sub-nitride dielectric layer located on the first conductive layer ranges from 1 nm to 5 nm.

14. The preparation method according to claim 9, characterized in that, The second nitride dielectric layer includes a third sub-nitride dielectric layer and a fourth sub-nitride dielectric layer, forming a second nitride dielectric layer covering the first oxide dielectric layer and a third conductive layer located in the second nitride dielectric layer, comprising: The third sub-nitride dielectric layer is formed on the first oxide dielectric layer; The third conductive layer is formed on the third sub-nitride dielectric layer, and the second conductive layer penetrates the third sub-nitride dielectric layer and is electrically connected to the third conductive layer; The fourth sub-nitride dielectric layer is formed on the third conductor layer and the third sub-nitride dielectric layer.

15. The preparation method according to claim 14, characterized in that, The thickness of the third sub-nitride dielectric layer ranges from 1 nm to 5 nm, and the thickness of the fourth sub-nitride dielectric layer located on the third conductive layer ranges from 1 nm to 5 nm.

16. The preparation method according to claim 9, characterized in that, The thickness of the third nitride dielectric layer ranges from 1 nm to 5 nm.

17. The preparation method according to claim 9, characterized in that, Etching the first oxide dielectric layer to form a via includes: Etch the first oxide dielectric layer to form the portion of the via located in the first oxide dielectric layer; The third nitride dielectric layer is formed on the sidewall of the portion of the through hole located in the first oxide dielectric layer; Continue etching the first nitride dielectric layer located on the first conductive layer to form the via.

18. The preparation method according to claim 17, characterized in that, After etching the first nitride dielectric located on the first conductive layer, the process further includes: The through-hole was cleaned using argon-containing plasma.

19. The preparation method according to claim 9, characterized in that, Before forming the first nitride dielectric layer on the substrate, the method further includes a step of cleaning and drying the substrate, wherein: The substrate is cleaned using at least one of the following methods: extreme ultraviolet lithography, chemical cleaning, deionized water cleaning, water-air two-fluid cleaning, and mega-sonic cleaning. The temperature range for drying the substrate is 90℃-120℃.

20. An electronic device, characterized in that, The electronic device includes the three-dimensional spiral inductor as described in any one of claims 1-8 or the three-dimensional spiral inductor prepared by the preparation method according to any one of claims 9-19.

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