A super storage and computing NoC circuit based on pulse ADC circuit

Abstract

The present invention discloses a super storage and computing integrated NoC circuit based on a pulse ADC circuit, and specifically relates to the field of NoC technology, including a mounted multi-core collaborative super storage and computing NoC circuit; the mounted multi-core collaborative super storage and computing NoC circuit includes: a quantized adaptive pulse ADC circuit; the quantized adaptive pulse ADC circuit includes: a buffer capacitor, a first NMOS transistor, a second NMOS transistor, a third NOMS transistor, a fourth NOMS transistor, a NOR gate, a power consumption reduction circuit and an operational amplifier. The present invention realizes the function of converting the charge quantity to the number of pulses by setting a quantized adaptive pulse ADC circuit, and allows the discharge capacitor to be adjusted according to the number of primary storage and computing integrated cores mounted on itself, thereby adaptively adjusting the quantization accuracy; through the mounted multi-core collaborative super storage and computing NoC circuit, a low-power reconfigurable multi-core collaborative solution is realized, and the decoupling between the primary storage and computing integrated cores is realized by using pulses as a data interaction method between the primary storage and computing core and the super storage and computing NoC.

Description

Technical Field

[0001] The present invention relates to the field of NoC technology, and more specifically, to a super storage and computing integrated NoC circuit based on a pulse ADC circuit. Background Art

[0002] It is known that with the development of artificial neural network technology, commercial neural network acceleration applications have put forward higher requirements on hardware computing power, which requires faster response speed, higher computing energy efficiency and higher autonomous controllability. However, under the classic von Neumann architecture, data processing and storage are separated, and large-scale data processing will lead to frequent data migration, which not only wastes CPU performance and reduces the ability to respond quickly, but also generates additional power consumption. Therefore, the new data-centric computing architecture-storage-computing integrated technology has been further developed. Among them, the storage-computing integrated chip provides a new neural network hardware design idea: by embedding a certain amount of computing power inside the memory, For example, computing units are embedded in the chip periphery or storage array to reduce data migration between memory and processor, thereby improving computing speed, alleviating bandwidth pressure and reducing power consumption. From the computing paradigm, there are two types of storage and computing architectures: digital and analog. Among them, the computing unit of the digital storage and computing solution is implemented by a digital adder or multiplier, while the analog storage and computing solution realizes multiplication and accumulation through current, voltage superposition or charge accumulation. At this stage, since the design of the multiplication and addition circuits in the analog storage and computing solution is simpler and more effective, and the neural network has relatively high requirements for calculation accuracy, the analog storage and computing chip has more advantages in accelerating neural networks.

[0003] Among them, the common core structure of analog storage and computing integration includes three parts: input unit, output unit and storage computing unit, and the peripheral circuit mainly includes memory access interface and control circuit, etc.; among them, the input unit converts the external input digital signal into an analog signal that can be used for the storage and computing integration array; the storage unit calculates the input analog signal and transmits the calculation result to the output unit in the form of analog voltage or current, and the output unit outputs the digital signal after analog-to-digital conversion; at present, there are many storage and computing integration circuit designs based on different storage media, including SRAM, FeFET, MRAM, Nand Flash, Nor Flash, RRAM, PCRAM, etc. Among them, due to the mature technology and the direct use of the most advanced process nodes, the analog storage and computing integration design based on SRAM has shown a greater cost-effectiveness advantage; the existing storage and computing integration technology integrates static memory (SRAM) and logic computing unit in one unit; in many designs, the matrix data required for matrix-vector multiplication operation is stored in SRAM, and the vector information from outside the SRAM is received, and the multiplication and accumulation calculation is performed by the logic computing unit.

[0004] However, in actual use, due to the limitation of signal margin, the parallel computing capability of a single integrated storage and computing core has a certain limit. An excessively large array size will cause the errors introduced by the process and noise to exceed the recognition range of the ADC circuit, reducing the reliability of the calculation results. The multi-core architecture achieves greater computing parallelism through the collaborative work of multiple integrated storage and computing cores, while the signal margin of a single core remains unchanged. This structure brings about a larger inter-core circuit. In order to merge the calculation results of multiple cores, the calculation results of each core will be summarized through the inter-core circuit to generate a total result. Since the input data form and function of the traditional inter-core circuit based on the digital circuit design method are fixed, the reconfiguration cost is very high. In addition, the digital inter-core circuit requires additional circuit overhead to merge the calculation results of the integrated storage and computing cores in the column direction, resulting in unnecessary power consumption and area overhead.

[0005] In view of this, a super storage and computing NoC circuit based on pulse ADC circuit is proposed as a further improvement. Summary of the invention

[0006] In order to overcome the problems that the traditional multi-core solution based on digital circuit design method has a fixed input data form and function, a high reconfiguration cost, and causes unnecessary power consumption and area overhead. The present invention utilizes the characteristics of the charge transfer storage and calculation integrated circuit with a pulse ADC, where the number of output pulses represents the calculation result and there is no interference between two adjacent pulses. By deploying a super storage and calculation integrated NoC circuit with this storage and calculation integrated core as a bit-cell, a multi-core collaborative circuit with low power consumption and reconfigurable characteristics is formed, so that the coordinated work of the storage and calculation integrated cores in the column direction can be easily realized through the NoC, thereby achieving greater computational parallelism.

[0007] The embodiments of the present invention provide a super storage and computing integrated NoC circuit based on a pulse ADC circuit to solve the problems raised in the above background technology.

[0008] To achieve the above object, the present invention provides the following technical solution: a super storage and computing integrated NoC circuit based on a pulse ADC circuit, the super storage and computing integrated NoC circuit comprising: a mounted multi-core collaborative super storage and computing NoC circuit;

[0009] The mounted multi-core collaborative super storage computing NoC circuit includes: a quantized adaptive pulse ADC circuit;

[0010] The quantized adaptive pulse ADC circuit comprises: a buffer capacitor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a NOR gate, a power consumption reduction circuit and an operational amplifier;

[0011] The positive electrode of the buffer capacitor is connected to the input terminal Vref, the input terminal Vcb l and the drain electrode D of the first NMOS transistor respectively;

[0012] The source S of the first NMOS transistor is connected to the drain D of the second NMOS transistor, and the gate G of the first NMOS transistor is connected to the bias voltage Vb;

[0013] The source S of the second NMOS transistor, the drain D of the third NMOS transistor, and the drain D of the fourth NMOS transistor are all connected to the positive electrode of the power consumption reduction circuit, and the gate G of the second NMOS transistor is connected to the output end of the NOR gate;

[0014] The source S of the third NOMS transistor and the source S of the fourth NOMS transistor are both grounded;

[0015] The two input terminals of the operational amplifier are respectively connected to the input terminal Vref and the positive electrode of the power consumption reduction circuit, and the output terminal of the operational amplifier is connected to the gate G of the fourth NOMS transistor through a plurality of inverters in sequence.

[0016] Further, the power consumption reduction circuit is configured as: a plurality of small capacitors of equal capacitance connected in parallel;

[0017] One ends of the plurality of small capacitors are connected to each other and are arranged as the positive electrode of the power consumption reduction circuit, and the other ends of the plurality of small capacitors are grounded.

[0018] Furthermore, the mounted multi-core collaborative super storage computing NoC circuit also includes: a quantized adaptive pulse ADC coupling structure;

[0019] The quantized adaptive pulse ADC coupling structure is as follows: a plurality of quantized adaptive pulse ADC circuits are connected to discharge capacitors via Tgate.

[0020] Furthermore, the conduction of the Tgate is controlled by a discharge capacitor signal. When the discharge capacitor signal is high, the corresponding quantized adaptive pulse ADC circuits are coupled to each other; each Tgate corresponds to a discharge capacitor signal.

[0021] Furthermore, the discharge capacitor signal is derived from a configuration register.

[0022] Further, when the quantized adaptive pulse ADC circuits are coupled to each other to form a quantized adaptive pulse ADC coupling structure, the discharge capacitor size is the sum of all the discharge capacitors.

[0023] Furthermore, the super storage and computing integrated NoC circuit also includes: a charge transfer type primary storage and computing integrated core, and a plurality of the primary storage and computing integrated cores are connected in the mounted multi-core collaborative super storage and computing NoC circuit.

[0024] Furthermore, the mounted multi-core collaborative super storage and computing NoC circuit also includes: a mounted super storage and computing integrated array structure; the mounted super storage and computing integrated array structure is configured as: an array with charge transfer type primary storage and computing integrated cores as bit-cell.

[0025] Furthermore, the output pulse of the primary storage-computing integrated core is a voltage pulse, and the voltage pulse is converted into a current pulse by a pulse current source.

[0026] Technical effects and advantages of the present invention:

[0027] 1. Compared with the existing technology, by setting a quantized adaptive pulse ADC circuit, the function of converting charge quantity to pulse quantity is realized. At the same time, the discharge capacitor capacitance is allowed to be adjusted according to the number of primary storage and computing cores mounted on itself, thereby adaptively adjusting the quantization accuracy.

[0028] 2. Compared with the existing technology, by setting up a mounted multi-core collaborative super-storage and computing NoC circuit, this structure realizes a low-power reconfigurable multi-core collaborative solution, and uses pulses as the data interaction method between the primary storage and computing core and the super-storage and computing NoC to realize the decoupling between the primary storage and computing integrated cores; due to the pulse encoding method and low bandwidth requirements, the circuit area overhead of this solution is very small, and the control can be achieved through configuration registers, and the cost is very low; the use of the pulse ADC circuit coupling structure allows the results of multiple quantized adaptive pulse ADC circuits to be aggregated, thereby achieving higher computing parallelism; this aggregation is performed directly in the analog domain, so the power consumption is extremely low; utilizing the discharge characteristics of the pulse ADC circuit, this structure is directly implemented through parallel capacitors, and the circuit area overhead is extremely low. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the quantized adaptive pulse ADC circuit of the present invention.

[0030] Figure 2 It is a schematic diagram of the quantized adaptive pulse ADC coupling structure of the present invention.

[0031] Figure 3 This is a schematic diagram of the super storage computing NoC structure of the present invention.

[0032] Figure 4 This is a schematic diagram of the structure of the primary storage and computing integrated array.

[0033] Figure 5 It is a structural diagram of the pulse ADC circuit.

[0034] Figure 6 This is a schematic diagram of the primary storage and computing core structure based on the quantized adaptive pulse ADC circuit.

[0035] Figure 7 Schematic diagram of the mounted super storage and computing integrated array structure

[0036] Figure 8 Schematic diagram of the structure of the pulse current source.

[0037] Fig. 9 Schematic diagram showing the weighted behavior of the pulse current source.

[0038] The accompanying drawings are marked as follows:

[0039] 1. Mounted multi-core collaborative super storage computing NoC circuit;

[0040] 11. Quantized adaptive pulse ADC circuit;

[0041] C1, buffer capacitor; N1, first NMOS transistor; N2, second NMOS transistor;

[0042] N3, the third NOMS transistor; N4, the fourth NOMS transistor; NOR, NOR gate; COM, operational amplifier; 12, quantized adaptive pulse ADC coupling structure;

[0043] 13. Mounted super storage and computing integrated array structure;

[0044] 2. Reduce power consumption circuit; C, small capacitor; C2, discharge capacitor;

[0045] 3. Primary storage and computing integrated core;

[0046] 4. Pulse current source. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0048] As attached Figure 1-9 A super storage and computing integrated NoC circuit based on a pulse ADC circuit is shown, and the super storage and computing integrated NoC circuit includes: a mounted multi-core collaborative super storage and computing NoC circuit 1;

[0049] The mounted multi-core collaborative super storage computing NoC circuit 1 includes: a quantized adaptive pulse ADC circuit 11;

[0050] Wherein, the quantized adaptive pulse ADC circuit 11 is abbreviated as QAPADC;

[0051] The quantized adaptive pulse ADC circuit 11 includes: a buffer capacitor C1, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a NOR gate NOR, a power consumption reduction circuit 2 and an operational amplifier COM;

[0052] The positive electrode of the buffer capacitor C1 is connected to the input terminal Vref, the input terminal Vcb l and the drain electrode D of the first NMOS transistor N1 respectively;

[0053] The source S of the first NMOS transistor N1 is connected to the drain D of the second NMOS transistor N2, and the gate G of the first NMOS transistor N1 is connected to the bias voltage Vb;

[0054] The source S of the second NMOS transistor N2, the drain D of the third NMOS transistor N3, and the drain D of the fourth NMOS transistor N4 are all connected to the positive electrode of the power consumption reduction circuit 2, and the gate G of the second NMOS transistor N2 is connected to the output end of the NOR gate NOR;

[0055] The source S of the third NOMS transistor N3 and the source S of the fourth NOMS transistor N4 are both grounded;

[0056] Two input terminals of the operational amplifier COM are respectively connected to the input terminal Vref and the positive electrode of the power consumption reduction circuit 2 , and the output terminal of the operational amplifier COM is sequentially connected to the gate G of the fourth NOMS transistor N4 through a plurality of inverters.

[0057] Among them, the mounted multi-core collaborative super storage and computing NoC circuit 1 realizes the decoupled collaborative work of multiple primary storage and computing integration based on the mounting method, and realizes a low-cost reconfigurable multi-core storage and computing integration solution by mounting different numbers of primary storage and computing integration cores 3;

[0058] Among them, the charge of all pulse current sources on the array structure of the super storage computing NoC will be summarized in the quantized adaptive pulse ADC circuit 11, and its structure is as follows: Figure 1 As shown; the quantized adaptive pulse ADC circuit 11 converts the result into a pulse output sequence, and the final calculation result can be obtained by counting the number of pulses; therefore, the quantized adaptive pulse ADC circuit 11 realizes the conversion of charge quantity into pulse quantity, and adaptively adjusts the quantization accuracy according to the number of mounted primary storage and computing integrated cores 3.

[0059] In a preferred embodiment, as shown in the attached Figure 1-9 As shown, the power consumption reduction circuit 2 is configured as: a plurality of small capacitors C of equal capacitance connected in parallel;

[0060] One ends of the plurality of small capacitors C are connected to each other and are set as the positive electrode of the power consumption reduction circuit 2, and the other ends of the plurality of small capacitors C are grounded.

[0061] Among them, the discharge of the quantized adaptive pulse ADC circuit 11 is consistent with that of a pulse ADC circuit with pulse release behavior. The quantized adaptive feature is reflected in its correspondence with the mounting characteristics of the super-storage and computing integrated array structure. The power consumption reduction circuit 2 of the quantized adaptive pulse ADC circuit 11 is obtained by mounting a number of small capacitors C with equal capacitance, and the small capacitor C participates in the discharge only when the corresponding En signal is valid; and this En signal is consistent with the mounting control signal in the mounted super-storage and computing integrated array structure 13, that is, the relevant configuration register controls the mounting behavior of the primary storage and computing integrated core 3 in the super-storage and computing integrated array, and regulates the capacitance of the small capacitor C of the quantized adaptive pulse ADC circuit 11 to be positively correlated with the number of primary storage and computing integrated cores 3 mounted to the quantized adaptive pulse ADC circuit 11, thereby realizing the quantized adaptation of the quantized adaptive pulse ADC circuit 11.

[0062] In a preferred embodiment, as shown in the attached Figure 1-9 As shown, the mounted multi-core collaborative super storage computing NoC circuit 1 also includes: a quantized adaptive pulse ADC coupling structure 12; the quantized adaptive pulse ADC coupling structure 12 is: a plurality of quantized adaptive pulse ADC circuits 11 are connected to a discharge capacitor C2 through Tgate.

[0063] The conduction of Tgate is controlled by the discharge capacitor C2 signal. When the discharge capacitor C2 signal is high, the corresponding quantized adaptive pulse ADC circuits 11 are coupled to each other; each Tgate corresponds to a discharge capacitor C2 signal.

[0064] When the quantized adaptive pulse ADC circuits 11 are coupled to each other to form a quantized adaptive pulse ADC coupling structure 12, the discharge capacitor size is the sum of all the discharge capacitors C2.

[0065] Among them, the quantized adaptive pulse ADC coupling structure 12 is used to coordinate the calculation results of multiple quantized adaptive pulse ADC circuits 11, and obtain the overall calculation results of all primary storage-computation integrated cores 3 mounted on the NoC by means of charge balancing; and the constructed super storage-computation NoC circuit can be used to coordinate multiple charge transfer paradigm storage-computation integrated cores to achieve greater computing parallelism, and the multi-core storage-computation integrated architecture achieved by it has the characteristics of low power consumption and reconfigurability, and the control cost is extremely low;

[0066] The specific quantized adaptive pulse ADC coupling structure 12 is a coupling structure based on the quantized adaptive pulse ADC circuit 11, which can achieve higher computational parallelism; Figure 2 As shown, the quantized adaptive pulse ADC circuits 11 belonging to different super-computing NoC column structures are allowed to be connected to the discharge capacitor C2 through Tgate; all discharge capacitor C2 signals are derived from the configuration register

[0067] That is, the conduction of Tgate is controlled by the discharge capacitor C2 signal. When the discharge capacitor C2 signal is high, the corresponding quantized adaptive pulse ADC circuits 11 are coupled with each other. Each Tgate corresponds to a discharge capacitor C2 signal. All Cn signals are derived from the configuration register.

[0068] When the quantized adaptive pulse ADC circuits 11 are coupled to each other to form a quantized adaptive pulse ADC coupling structure 12, the discharge capacitor size is the sum of all the discharge capacitors C2.

[0069] In this way, the size of the discharge capacitor after coupling is proportional to the number of primary storage and computing integrated cores 3 in the entire super storage and computing NoC, thereby continuing to retain the quantization adaptive characteristics.

[0070] During calculation, the charge transfer of all primary storage and computing cores 3 is processed by all coupled quantized adaptive pulse ADC circuits 11. The equivalent super storage and computing NoC structure is as follows: Figure 3 At this time, all primary storage-computation integrated cores 3 generate their own calculation results, and the coupled quantization adaptive pulse ADC circuits 11 output an additional set of summary results, and the results output by these quantization adaptive pulse ADC circuits 11 are the same.

[0071] In a preferred embodiment, as shown in the attached Figure 1-9 As shown, the super storage and computing integrated NoC circuit also includes: a charge transfer type primary storage and computing integrated core 3, and a plurality of primary storage and computing integrated cores 3 are connected to the mounted multi-core collaborative super storage and computing NoC circuit 1; the mounted multi-core collaborative super storage and computing NoC circuit 1 also includes: a mounted super storage and computing integrated array structure 13; the mounted super storage and computing integrated array structure 13 is configured as: an array with the charge transfer type primary storage and computing integrated core 3 as bit-cell; the output pulse of the primary storage and computing integrated core 3 is a voltage pulse, and the voltage pulse is converted into a current pulse through a pulse current source 4;

[0072] The above-mentioned primary storage and computing integrated core 3 includes: a primary storage and computing integrated array for realizing MAC calculation and a pulse ADC circuit for converting the charge quantity into the pulse quantity;

[0073] like Figure 4 The primary storage and computing integrated array shown:

[0074] The storage array consists of a bitcell array with i rows and j columns. In the charge transfer paradigm, each bitcell unit generates a small charge transfer amount △Q after receiving input data from outside the array. i，j , this charge transfer is used to represent the mapping of the product of input data and weight, that is, △Q i,j =f(i nput i *Wi,j ), f() is a linear function, which is determined by the circuit structure of the charge transfer storage and calculation integrated array; therefore, the charge transfer type primary storage and calculation integrated array realizes multiplication operation by converting the result of input data and weight data into transfer charge, and then realizes addition operation by accumulating charge according to Kirchhoff's law, thereby realizing the multiplication and accumulation operation completed in the bit-cell array, and the accumulated calculation structure △Q 0-j The final numerical calculation result needs to be obtained through the pulse ADC circuit structure.

[0075] like Figure 5 The pulse ADC circuit shown: The pulse ADC circuit is abbreviated as PADC;

[0076] The pulse ADC circuit uses the charge integrator counter circuit proposed in [] as the functional main body, which is used to convert the charge from the charge transfer type primary storage and calculation integrated array into pulses;

[0077] The specific circuit includes: a buffer capacitor C1, a first NMOS transistor N1, a NOR gate NOR, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a discharge capacitor C2, and inverters IV0, IV1, and IV2.

[0078] The working process of the pulse ADC circuit is as follows Figure 5 As shown by the dotted arrow, first a SET signal is given to charge C1 to Vref and discharge C2 to GND; the circuit is initialized, and then the SET signal is removed;

[0079] After the SET signal is removed, N2 is turned on, and the charge from the Vcb l line is injected into C1, and the charge on C1 is transferred to C2 at the same time; here, the gate bias voltage Vb of N1 is to limit the speed of charging C2 and maintain it at a stable flow rate so that it will not cause unreasonable fluctuations in the charging voltage of C2 due to the sudden accumulation of a large amount of charge on Vcb l;

[0080] When the charge on C2 accumulates to a voltage greater than Vref, through the feedback circuit, N2 is closed and N4 is opened, and C2 begins to be discharged; at this time, the charge input on Vcb l will be temporarily stored in C1; the loop delay composed of the inverter and the comparator ensures that N4 will not be closed immediately after the voltage value of C2 drops below Vref, but will fully discharge C2 during the delay period;

[0081] After the delay, since the voltage of C2 is less than Vref, N4 is closed again and N2 is opened to start the next cycle of charge and discharge. By adopting the above technical solution, the calculation result of the primary storage and computing array will be temporarily accumulated in C1 and gradually released through the C2 capacitor until it is finally discharged completely. The number of discharges is the calculation result of the charge transfer storage and computing array.

[0082] Then the charge transfer type primary storage and computing integrated core 3 based on the pulse ADC circuit is as follows Figure 6 As shown;

[0083] The input of this circuit is a digital signal, the calculated intermediate value is the analog charge, and the calculated result is the number of pulses emitted; finally, a counter structure can be used to count the number of pulses and convert the calculated intermediate value into a digital signal that can be recognized by the computer.

[0084] The mounted multi-core collaborative super storage and computing NoC circuit 1 also includes: a mounted super storage and computing integrated array structure 13; the mounted super storage and computing integrated array structure 13 is configured as: an array with charge transfer type primary storage and computing integrated core 3 as bit-cel.

[0085] The output pulse of the primary storage and computing core 3 is a voltage pulse, which is converted into a current pulse by the pulse current source 4.

[0086] The mounted multi-core collaborative super storage and computing NoC circuit 1 also includes: a mounted super storage and computing integrated array structure 13, such as Figure 7 As shown, the structure uses the charge transfer type primary storage and computing integrated core 3 as the bit-cell to build a storage and computing integrated array, namely the so-called mounted super storage and computing integrated array structure 13; it realizes the aggregation of calculation results of multiple storage and computing integrated single cores based on the current paradigm storage and computing integrated design method.

[0087] The output pulse of the primary storage-computation integrated core 3 is a voltage pulse, which is converted into a current pulse after passing through a pulse current source 4; and the working principle of the pulse current source 4 is as follows: Figure 8 As shown, it consists of an inverter, a NOR gate, and two PMOS tubes; when an external pulse input is received and the En signal is valid, the pulse current source generates a current pulse, and its pulse width is consistent with the pulse width of the pulse input.

[0088] like Fig. 9The weighted behavior of the pulse current source 3 is shown. When the fl ag signal is 0, the external pulse input cannot act on P2. Therefore, at each external pulse input, the amount of charge transferred to the quantized adaptive pulse ADC circuit 11 is i0×Wp, where i0 is the output current of a single PMOS tube current source and Wp is the current pulse width. When the fl ag signal is high, P2 is also turned on. In fact, the amount of charge transferred by each external pulse input is 2i0×Wp. Since the pulses output by the pulse ADC circuit do not interfere with each other, not only will the output pulse of a primary storage-computing integrated core 3 not act on other storage-computing integrated cores, but this output pulse will not affect the work of the primary storage-computing integrated core 3 itself. In this way, the mutual coupling between the primary storage-computing integrated core 3 and the super storage-computing NoC is isolated, and the two only interact in a one-way manner through the output pulse of the primary storage-computing integrated core 3.

[0089] The mounting characteristic is reflected in that: when the En signal corresponding to the primary storage-computing integrated core 3 is invalid, the output pulse of the storage-computing integrated core cannot act on the pulse current source circuit; at this time, the output result of the primary storage-computing integrated core 3 is not 0, and no charge can be transferred to the quantized adaptive pulse ADC circuit 11, that is, it is not mounted in the super storage-computing NoC;

[0090] Only when the corresponding En signal is valid, the output result of the primary storage and computing integrated core 3 can be summarized by the quantized adaptive pulse ADC circuit 11, that is, mounted in the super storage and computing NoC. The specific value of En is determined by the configuration register.

[0091] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0092] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A super storage and computing NoC circuit based on a pulse ADC circuit, characterized in that: The super storage and computing integrated NoC circuit comprises: a mounted multi-core collaborative super storage and computing NoC circuit (1); The mounted multi-core collaborative super storage computing NoC circuit (1) comprises: a quantized adaptive pulse ADC circuit (11); The quantized adaptive pulse ADC circuit (11) comprises: a buffer capacitor (C1), a first NMOS transistor (N1), a second NMOS transistor (N2), a third NMOS transistor (N3), a fourth NMOS transistor (N4), a NOR gate (NOR), a power consumption reduction circuit (2) and an operational amplifier (COM); The positive electrode of the buffer capacitor (C1) is respectively connected to the input terminal Vref, the input terminal Vcbl and the drain electrode D of the first NMOS transistor (N1); The source S of the first NMOS transistor (N1) is connected to the drain D of the second NMOS transistor (N2), and the gate G of the first NMOS transistor (N1) is connected to a bias voltage Vb; The source electrode S of the second NMOS transistor (N2), the drain electrode D of the third NMOS transistor (N3), and the drain electrode D of the fourth NMOS transistor (N4) are all connected to the positive electrode of the power consumption reduction circuit (2), and the gate electrode G of the second NMOS transistor (N2) is connected to the output end of the NOR gate (NOR); The source electrode S of the third NOMS transistor (N3) and the source electrode S of the fourth NOMS transistor (N4) are both grounded; The two input terminals of the operational amplifier (COM) are respectively connected to the input terminal Vref and the positive electrode of the power consumption reduction circuit (2), and the output terminal of the operational amplifier (COM) is sequentially connected to the gate G of the fourth NOMS transistor (N4) through a plurality of inverters; The power consumption reduction circuit (2) is configured as: a plurality of small capacitors (C) of equal capacitance connected in parallel; One ends of the plurality of small capacitors (C) are connected to each other and are arranged as the positive electrode of the power consumption reduction circuit (2), and the other ends of the plurality of small capacitors (C) are grounded; The mounted multi-core collaborative super storage computing NoC circuit (1) further includes: a quantized adaptive pulse ADC coupling structure (12); The quantized adaptive pulse ADC coupling structure (12) comprises: a plurality of quantized adaptive pulse ADC circuits (11) are connected to a discharge capacitor (C2) via Tgate; The conduction of the Tgate is controlled by a discharge capacitor (C2) signal. When the discharge capacitor (C2) signal is high, the corresponding quantized adaptive pulse ADC circuits (11) are coupled to each other. Each Tgate corresponds to a discharge capacitor (C2) signal.

2. The super storage and computing integrated NoC circuit based on the pulse ADC circuit according to claim 1, characterized in that: The discharge capacitor (C2) signal is derived from a configuration register.

3. The super storage and computing integrated NoC circuit based on the pulse ADC circuit according to claim 1, characterized in that: When the quantized adaptive pulse ADC circuits (11) are coupled to each other to form a quantized adaptive pulse ADC coupling structure (12), the discharge capacitance is the sum of all discharge capacitances (C2).

4. The super storage and computing integrated NoC circuit based on the pulse ADC circuit according to claim 1, characterized in that: The super storage and computing integrated NoC circuit also includes: a charge transfer type primary storage and computing integrated core (3), and a plurality of the primary storage and computing integrated cores (3) are connected in the mounted multi-core collaborative super storage and computing NoC circuit (1).

5. The super storage and computing integrated NoC circuit based on the pulse ADC circuit according to claim 4, characterized in that: The mounted multi-core collaborative super storage and computing NoC circuit (1) further comprises: a mounted super storage and computing integrated array structure (13); the mounted super storage and computing integrated array structure (13) is configured as: an array with charge transfer type primary storage and computing integrated cores (3) as bit-cells.

6. The super storage and computing integrated NoC circuit based on the pulse ADC circuit according to claim 5, characterized in that: The output pulse of the primary integrated storage and computing core (3) is a voltage pulse, and the voltage pulse is converted into a current pulse through a pulse current source (4).

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