Display device and electronic equipment

Abstract

The present application discloses a display device and an electronic device. The display device expands an original output channel into multiple output channels that synchronously output multiple data signals by adding a first shift latch circuit and a second shift latch circuit after a first decoding circuit and a second decoding circuit, and correspondingly increases the number of digital-to-analog converters after the first shift latch circuit and the second shift latch circuit. The display device can synchronously charge multiple sub-pixels in a column of sub-pixels. Compared with one digital-to-analog converter driving a column of sub-pixels, the improvement enables multiple digital-to-analog converters to drive a column of sub-pixels. The number of sub-pixels that each digital-to-analog converter can drive is upper bounded. As the number of digital-to-analog converters increases, the number of sub-pixels that can be driven in a column also increases. This improves the load capacity of each output channel of the data driver, thereby facilitating display driving of display devices with larger resolutions or sizes.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and an electronic device. Background Art

[0002] As the resolution or size of a display screen increases, the load capacity of a data driver that provides data signals when driving the display screen must also be increased, otherwise insufficient charging will occur, affecting the display effect. Summary of the Invention

[0003] The present application provides a display device and an electronic device to alleviate the technical problem of low load capacity of a data driver.

[0004] In a first aspect, the present application provides a display device, which includes a data driver, the data driver including a first decoding circuit, a first shift latch circuit, a second decoding circuit, a second shift latch circuit and a digital-to-analog conversion circuit, the first decoding circuit including a first decoder; the first shift latch circuit including a first shift latch sub-circuit, the input end of each first shift latch sub-circuit being connected to the output end of a first decoder; the second decoding circuit including a second decoder; the second shift latch circuit including a second shift latch sub-circuit, the input end of each second shift latch sub-circuit being connected to the output end of a second decoder; the digital-to-analog conversion circuit including a digital-to-analog conversion sub-circuit, each digital-to-analog conversion sub-circuit being respectively connected to the output end of a first shift latch sub-circuit and the output end of a second shift latch sub-circuit, each digital-to-analog conversion sub-circuit including a plurality of digital-to-analog converters, the plurality of digital-to-analog converters in each digital-to-analog conversion sub-circuit synchronously outputting multiple data signals to a column of sub-pixels.

[0005] In some embodiments, the first shift latch sub-circuit includes a first shift register module and a first latch module, the input end of the first shift register module is connected to the output end of a first decoder; the input end of the first latch module is connected to the output end of the first shift register module, and the output end of the first latch module is connected to the first input end of the digital-to-analog conversion sub-circuit.

[0006] In some embodiments, the first shift register module includes multiple cascaded first shift registers, the input end of the first-stage first shift register is connected to the output end of a first decoder, and the output end of each first shift register is connected to the first latch module.

[0007] In some embodiments, the first latch module includes a plurality of first latches, an input end of each first latch is connected to an output end of a first shift register, and an output end of each first latch is connected to a first input end of a digital-to-analog converter.

[0008] In some embodiments, the second shift latch sub-circuit includes a second shift register module and a second latch module, the input end of the second shift register module is connected to the output end of a second decoder; the input end of the second latch module is connected to the output end of the second shift register module, and the output end of the second latch module is connected to the second input end of the digital-to-analog conversion sub-circuit.

[0009] In some embodiments, the second shift register module includes multiple cascaded second shift registers, the input end of the first-stage second shift register is connected to the output end of a second decoder, and the output end of each second shift register is connected to the second latch module.

[0010] In some embodiments, the second latch module includes a plurality of second latches, an input end of each second latch is connected to an output end of a second shift register, and an output end of each second latch is connected to a second input end of a digital-to-analog converter.

[0011] In some embodiments, the display device further includes a display panel, which further includes multiple sub-pixels and multiple data lines, and each digital-to-analog converter in each digital-to-analog conversion sub-circuit is connected to different sub-pixels in a column of sub-pixels through a data line.

[0012] In some embodiments, the display device further includes a plurality of scan lines, each of which is connected to a plurality of adjacent rows of sub-pixels.

[0013] In some embodiments, the display device further includes a clock line and a synchronization trigger line, a clock line connected to each first decoder, each second decoder, the first shift latch circuit, and the second shift latch circuit; a synchronization trigger line connected to the first shift latch circuit and the second shift latch circuit.

[0014] In some embodiments, the display device further includes a glass substrate, and the glass substrate is provided with a data driver.

[0015] In a second aspect, the present application provides an electronic device comprising the above-mentioned display device.

[0016] The display device and electronic device provided by the present application can expand the original output channel into multiple output channels that synchronously output multiple data signals by adding a first shift latch circuit and a second shift latch circuit after the first decoding circuit and the second decoding circuit, and correspondingly increasing the number of digital-to-analog converters after the first shift latch circuit and the second shift latch circuit. This can synchronously charge multiple sub-pixels in a column of sub-pixels. Compared with one digital-to-analog converter driving a column of sub-pixels, the improvement can enable multiple digital-to-analog converters to drive a column of sub-pixels. The number of sub-pixels that each digital-to-analog converter can drive is upper bounded. As the number of digital-to-analog converters increases, the number of sub-pixels that can be driven in a column also increases. This improves the load capacity of each output channel of the data driver, thereby facilitating display driving of display devices with larger resolutions or sizes.

[0017] Furthermore, since the data driver provided in the present application does not use an operational amplifier circuit to improve its load capacity, the glass substrate in the display device can be prevented from reducing the performance of the operational amplifier circuit, thereby avoiding affecting the display effect when a glass substrate is used. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0019] Figure 1 Schematic diagram of the structure of a data driver in related technology.

[0020] Figure 2 A schematic diagram of the structure of a data driver provided in an embodiment of the present application.

[0021] Figure 3 for Figure 2 The timing diagram of the data driver is shown.

[0022] Figure 4 for Figure 2 Schematic diagram of the structure of the shift latch subcircuit.

[0023] Figure 5 for Figure 4 A timing diagram of the shift latch subcircuit shown.

[0024] Figure 6 for Figure 4 Another timing diagram of the shift latch subcircuit shown.

[0025] Figure 7 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0026] Figure 8 for Figure 7A schematic diagram of the driving timing of the display panel. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. The features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0029] Figure 1 This is a schematic diagram of the structure of a data driver in related art. In this data driver, under the control of a clock signal, a shift register processes a serially connected input signal. Then, under the control of a latch control signal, latches 1, 2, ..., and N output their respective latched results to corresponding level conversion modules. Each level conversion module then outputs its respective level conversion results in parallel to corresponding decoders 1, 2, ..., and N. Each decoder inputs its decoding results to the corresponding digital-to-analog converter, which then outputs the corresponding data signal to the sub-pixels in the corresponding column. For example, the horizontally arranged decoder 1 and the vertically arranged decoder N respectively output their decoding results to the digital-to-analog converter 1, and the digital-to-analog converter 1 outputs the data signal Source1 to the first column of sub-pixels; the horizontally arranged decoder 2 and the vertically arranged decoder 2 respectively output their decoding results to the digital-to-analog converter 2, and the digital-to-analog converter 2 outputs the data signal Source2 to the second column of sub-pixels; and so on, the horizontally arranged decoder N and the vertically arranged decoder 1 respectively output their decoding results to the digital-to-analog converter N, and the digital-to-analog converter N outputs the data signal SourceN to the Nth column of sub-pixels.

[0030] The decoders 1, 2, ..., and N arranged horizontally may constitute a first decoding circuit 10 , and the decoders 1, 2, ..., and N arranged vertically may constitute a second decoding circuit 30 .

[0031] from Figure 1As can be seen, one decoder arranged horizontally and one decoder arranged vertically correspond to one DAC, and each outputs a data signal to charge a column of sub-pixels. As the resolution or size of the display device increases, the number of sub-pixels in each column also increases. Consequently, each DAC needs to charge more sub-pixels, which requires increasing the load capacity of each DAC. Otherwise, insufficient charging will occur due to the low load capacity of the DAC.

[0032] In this case, it is necessary to propose a solution that uses a decoder arranged horizontally and a decoder arranged vertically to correspond to multiple digital-to-analog converters, outputting corresponding multiple data signals to simultaneously charge multiple sub-pixels in a column. This can drive display devices with larger resolutions or sizes.

[0033] In view of this, this embodiment provides a display device, see Figures 2 to 8 ,like Figure 2 As shown, the display device includes a data driver, which includes a first decoding circuit 10, a first shift latch circuit 20, a second decoding circuit 30, a second shift latch circuit 40 and a digital-to-analog conversion circuit 50. The first decoding circuit 10 includes a first decoder 11; the first shift latch circuit 20 includes a first shift latch sub-circuit 21, and the input end of each first shift latch sub-circuit 21 is connected to the output end of the first decoder 11; the second decoding circuit 30 includes a second decoder 31; the second shift latch circuit 40 includes The second shift latch sub-circuit 41, the input end of each second shift latch sub-circuit 41 is connected to the output end of a second decoder 31; the digital-to-analog conversion circuit 50 includes a digital-to-analog conversion sub-circuit 51, each digital-to-analog conversion sub-circuit 51 is respectively connected to the output end of a first shift latch sub-circuit 21 and the output end of a second shift latch sub-circuit 41, each digital-to-analog conversion sub-circuit 51 includes multiple digital-to-analog converters 52, and the multiple digital-to-analog converters 52 in each digital-to-analog conversion sub-circuit 51 synchronously output multiple data signals to a column of sub-pixels.

[0034] It is understandable that compared to Figure 1The data driver shown in the display device provided in this embodiment expands the original single output channel into multiple output channels that synchronously output multiple data signals by adding a first shift latch circuit 20 and a second shift latch circuit 40 after the first decoding circuit 10 and the second decoding circuit 30, and correspondingly increasing the number of digital-to-analog converters 52 after the first shift latch circuit 20 and the second shift latch circuit 40. This allows for synchronous charging of multiple sub-pixels in a column of sub-pixels. Compared to driving a column of sub-pixels with one digital-to-analog converter 52, the improvement enables multiple digital-to-analog converters 52 to drive a column of sub-pixels. The number of sub-pixels that each digital-to-analog converter 52 can drive is subject to an upper limit. As the number of digital-to-analog converters 52 increases, the number of sub-pixels that can be driven in a column also increases. This improves the load capacity of each output channel of the data driver, thereby facilitating display driving of display devices with larger resolutions or sizes.

[0035] It needs to be explained that Figure 2 The data driver shown also includes Figure 1 The shift registers, latches 1 to N, and level conversion modules shown in FIG.

[0036] In one embodiment, the display device further includes a clock line and a synchronization trigger line, wherein a clock line is connected to each first decoder 11, each second decoder 31, the first shift latch circuit 20, and the second shift latch circuit 40; and a synchronization trigger line is connected to the first shift latch circuit 20 and the second shift latch circuit 40.

[0037] It should be noted that the clock line is used to transmit a clock signal, and the synchronization trigger line is used to transmit a synchronization trigger signal, which can control each first latch 25 and each second latch 45 to synchronously output their respective latched data.

[0038] In one embodiment, the display device further includes a glass substrate, and the glass substrate is provided with a data driver.

[0039] It is understandable that since the data driver provided in this embodiment does not use an operational amplifier circuit to improve the load capacity, it can prevent the glass substrate in the display device from reducing the performance of the operational amplifier circuit, and can avoid affecting the display effect when using a glass substrate.

[0040] In one embodiment, Figure 2 As shown, the first shift latch sub-circuit 21 includes a first shift register module 22 and a first latch module 24. The input end of the first shift register module 22 is connected to the output end of a first decoder 11; the input end of the first latch module 24 is connected to the output end of the first shift register module 22, and the output end of the first latch module 24 is connected to the first input end of the digital-to-analog conversion sub-circuit 51.

[0041] It should be noted that the first shift register module 22 is used to perform shift processing on the decoding result of the first decoder 11 , so as to output a plurality of shift results corresponding to the decoding result to the first latch module 24 .

[0042] in, Figure 2 The description is made using a 1-bit input signal as an example. If the input signal is 2 bits, the first shift register module 22 includes four cascaded first shift registers 23, and correspondingly, the first latch module 24 includes four first latches 25. The same applies to input signals of other bits.

[0043] In one embodiment, Figure 2 As shown, the first shift register module 22 includes multiple cascaded first shift registers 23 , the input end of the first-stage first shift register 23 is connected to the output end of a first decoder 11 , and the output end of each first shift register 23 is connected to the first latch module 24 .

[0044] It should be noted that, after the plurality of cascaded first shift registers 23 perform shift processing on the decoding results of the first decoder 11 , they will generate corresponding multiple groups of shift results.

[0045] In one embodiment, Figure 2 As shown, the first latch module 24 includes a plurality of first latches 25 , the input end of each first latch 25 is connected to the output end of a first shift register 23 , and the output end of each first latch 25 is connected to the first input end of a digital-to-analog converter 52 .

[0046] It should be noted that each first latch 25 is used to latch a group of shift results generated by the first shift register 23 .

[0047] In one embodiment, Figure 2 As shown, the second shift latch sub-circuit 41 includes a second shift register module 42 and a second latch module 44. The input end of the second shift register module 42 is connected to the output end of a second decoder 31; the input end of the second latch module 44 is connected to the output end of the second shift register module 42, and the output end of the second latch module 44 is connected to the second input end of the digital-to-analog conversion sub-circuit 51.

[0048] It should be noted that the second shift register module 42 is used to perform shift processing on the decoding result of the second decoder 31 to output multiple groups of shift results corresponding to the decoding result to the second latch module 44 .

[0049] in, Figure 2The description is made using a 1-bit input signal as an example. If the input signal is 2 bits, the second shift register module 42 includes four cascaded second shift registers 43, and correspondingly, the second latch module 44 includes four second latches 45. The same applies to input signals of other bits.

[0050] In one embodiment, Figure 2 As shown, the second shift register module 42 includes multiple cascaded second shift registers 43 , the input end of the first-stage second shift register 43 is connected to the output end of a second decoder 31 , and the output end of each second shift register 43 is connected to the second latch module 44 .

[0051] It should be noted that, after the plurality of cascaded second shift registers 43 perform shift processing on the decoding results of the second decoder 31 , they will generate a corresponding plurality of shift results.

[0052] In one embodiment, Figure 2 As shown, the second latch module 44 includes a plurality of second latches 45 , the input end of each second latch 45 is connected to the output end of a second shift register 43 , and the output end of each second latch 45 is connected to the second input end of a digital-to-analog converter 52 .

[0053] It should be noted that each second latch 45 is used to latch a group of shift results generated by the second shift register 43 .

[0054] Figure 3 for Figure 2 The timing diagram of the data driver is shown. Under the control of the clock signal and the synchronous trigger signal, the first decoder 11 and the second decoder 31 output the corresponding first decoding results and second decoding results to the first shift register 23 and the second shift register 43 at time t1 and time t2 respectively for shift processing. The first latch 25 and the second latch 45 then synchronously output the results to the two digital-to-analog converters 52. The two digital-to-analog converters 52 output data signals Source1a and Source1b respectively.

[0055] Figure 4 for Figure 2 Schematic diagram of the shift latch subcircuit. In other words, Figure 4 The shift latch subcircuit shown can be Figure 2 The circuit structure of the first shift latch sub-circuit 21 shown in FIG. 1 includes a first shift register module 22 and a first latch module 24 connected in sequence; it can also be Figure 2 The circuit structure of the second shift latch sub-circuit 41 shown includes a second shift register module 42 and a second latch module 44 connected in sequence.

[0056] Combine Figure 2 、 Figure 4 It can be seen that the first shift register 23 , the second shift register, the first latch 25 and the second latch 45 may all include a plurality of NAND gates connected to each other.

[0057] Figure 5 for Figure 4 A timing diagram of the shift latch subcircuit shown. Figure 6 for Figure 4 Another timing diagram of the shift latch subcircuit shown in FIG. The shift latch subcircuit can shift and latch the input data and then output it as the corresponding output data under the control of the clock signal and the synchronous trigger signal.

[0058] In one embodiment, Figure 7 As shown, the display device also includes a display panel, which includes a plurality of sub-pixels, a plurality of data lines, and a plurality of scan lines. The plurality of sub-pixels are arranged in an array. Each scan line is connected to a plurality of adjacent rows of sub-pixels. Each digital-to-analog converter 52 in each digital-to-analog conversion sub-circuit 51 is connected to a different sub-pixel in a column of sub-pixels via a data line.

[0059] For example, the first scan line is used to transmit the first scan signal Scan1, and the first scan line connects the sub-pixels in the first and second rows; the second scan line is used to transmit the second scan signal Scan2, and the second scan line connects the sub-pixels in the third and fourth rows. The connection relationship of other rows can be deduced in this way.

[0060] Combine Figure 8 As shown, the first scan signal Scan1 synchronously scans the sub-pixels in the first and second rows, data signals Source1a to SourceNa are written into the sub-pixels in the first row, and data signals Source1b to SourceNb are written into the sub-pixels in the second row. The second scan signal Scan2 synchronously scans the sub-pixels in the third and fourth rows, data signals Source1a to SourceNa are written into the sub-pixels in the third row, and data signals Source1b to SourceNb are written into the sub-pixels in the fourth row. That is, by simultaneously scanning the sub-pixels in two adjacent rows, data signals Source1a to SourceNa are written into the sub-pixels in odd-numbered rows, and data signals Source1b to SourceNb are written into the sub-pixels in even-numbered rows. The driving timing for other rows is similar, and ultimately, data signals are written into the sub-pixels in all rows, thereby displaying a frame of image.

[0061] Each column of sub-pixels is of the same color. For example, the first column of sub-pixels from left to right is red sub-pixels, the second column of sub-pixels from left to right is green sub-pixels, the third column of sub-pixels from left to right is blue sub-pixels, and so on.

[0062] In other embodiments, each scan line may be connected to three adjacent rows of sub-pixels. Each DAC 52 in each DAC sub-circuit 51 is connected to three adjacent sub-pixels in a column of sub-pixels via a data line. In this case, the DAC sub-circuit has three DACs to generate data signals Source1a to SourceNa, data signals Source1b to SourceNb, and data signals Source1c to SourceNc, respectively.

[0063] For example, when synchronously scanning the sub-pixels in the first, second, and third rows, data signals Source1a to SourceNa are written to the sub-pixels in the first row, data signals Source1b to SourceNb are written to the sub-pixels in the second row, and data signals Source1c to SourceNc are written to the sub-pixels in the third row. When synchronously scanning the sub-pixels in the fourth, fifth, and sixth rows, data signals Source1a to SourceNa are written to the sub-pixels in the fourth row, data signals Source1b to SourceNb are written to the sub-pixels in the fifth row, and data signals Source1c to SourceNc are written to the sub-pixels in the sixth row. That is, by simultaneously scanning the sub-pixels of three adjacent rows, the data signals Source1a~SourceNa are written to the sub-pixels in the 1st, 4th, 7th... rows, the data signals Source1b~SourceNb are written to the sub-pixels in the 2nd, 5th, 8th... rows, and the data signals Source1c~SourceNc are written to the sub-pixels in the 3rd, 6th, 9th... rows. The driving timing of other rows is similar, and finally the data signals of the sub-pixels in all rows are written, so that one frame of picture can be displayed.

[0064] In summary, the data driver provided by the present application can reduce the total number of rows that each analog-to-digital converter needs to write data signals for while keeping the resolution or size unchanged, that is, the number of loaded rows is reduced, and the charging time that can be performed is more sufficient. Since the charging rate = actual charging potential / target potential, the charging rate is also improved.

[0065] Therefore, if the charging rate remains unchanged, the data driver provided in this application can drive a display screen with a higher resolution, which means that the overall load capacity is improved.

[0066] In one embodiment, this embodiment provides an electronic device, which includes the above-mentioned display device.

[0067] It is understandable that since the electronic device provided in this embodiment includes the above-mentioned display device, it is also possible to expand the original single output channel into multiple output channels that synchronously output multiple data signals by adding the first shift latch circuit 20 and the second shift latch circuit 40 after the first decoding circuit 10 and the second decoding circuit 30, and correspondingly increase the number of digital-to-analog converters 52 after the first shift latch circuit 20 and the second shift latch circuit 40. This allows multiple sub-pixels in a column of sub-pixels to be charged synchronously. Compared to one digital-to-analog converter 52 driving a column of sub-pixels, the improvement enables multiple digital-to-analog converters 52 to drive a column of sub-pixels. The number of sub-pixels that each digital-to-analog converter 52 can drive is limited to an upper limit. As the number of digital-to-analog converters 52 increases, the number of sub-pixels that can be driven in a column also increases. This improves the load capacity of each output channel of the data driver, thereby facilitating display driving of display devices with larger resolutions or sizes.

[0068] Furthermore, since the data driver provided in this embodiment does not use an operational amplifier circuit to improve the load capacity, the glass substrate in the display device can be prevented from reducing the performance of the operational amplifier circuit, thereby avoiding affecting the display effect when a glass substrate is used.

[0069] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0070] The display device and electronic device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized in that: The display device includes a data driver, and the data driver includes: a first decoding circuit, wherein the first decoding circuit includes a first decoder; a first shift latch circuit, the first shift latch circuit comprising first shift latch sub-circuits, an input end of each first shift latch sub-circuit being connected to an output end of the first decoder; a second decoding circuit, wherein the second decoding circuit includes a second decoder; a second shift latch circuit, the second shift latch circuit comprising second shift latch sub-circuits, an input terminal of each second shift latch sub-circuit being connected to an output terminal of the second decoder; A digital-to-analog conversion circuit, comprising digital-to-analog conversion sub-circuits, each of which is connected to an output end of the first shift latch sub-circuit and an output end of the second shift latch sub-circuit, each of which comprises a plurality of digital-to-analog converters, wherein the plurality of digital-to-analog converters in each of the digital-to-analog conversion sub-circuits synchronously output multiple data signals to a column of sub-pixels.

2. The display device according to claim 1, wherein The first shift latch sub-circuit includes: a first shift register module, wherein an input end of the first shift register module is connected to an output end of the first decoder; A first latch module, wherein an input end of the first latch module is connected to an output end of the first shift register module, and an output end of the first latch module is connected to a first input end of the digital-to-analog conversion sub-circuit.

3. The display device according to claim 2, wherein: The first shift register module includes a plurality of cascaded first shift registers, the input end of the first-stage first shift register is connected to the output end of the first decoder, and the output end of each first shift register is connected to the first latch module.

4. The display device according to claim 3, wherein The first latch module includes a plurality of first latches, the input end of each first latch is connected to the output end of the first shift register, and the output end of each first latch is connected to the first input end of the digital-to-analog converter.

5. The display device according to claim 1, wherein The second shift latch sub-circuit includes: a second shift register module, wherein an input end of the second shift register module is connected to an output end of the second decoder; A second latch module, wherein the input end of the second latch module is connected to the output end of the second shift register module, and the output end of the second latch module is connected to the second input end of the digital-to-analog conversion sub-circuit.

6. The display device according to claim 5, wherein: The second shift register module includes a plurality of cascaded second shift registers, the input end of the first-stage second shift register is connected to the output end of a second decoder, and the output end of each second shift register is connected to the second latch module.

7. The display device according to claim 6, wherein: The second latch module includes a plurality of second latches, wherein the input end of each second latch is connected to the output end of the second shift register, and the output end of each second latch is connected to the second input end of the digital-to-analog converter.

8. The display device according to any one of claims 1 to 7, characterized in that: The display device further includes a display panel, and the display panel further includes: multiple sub-pixels; A plurality of data lines, each digital-to-analog converter in each of the digital-to-analog conversion sub-circuits is connected to different sub-pixels in a column of sub-pixels via one of the data lines.

9. The display device according to any one of claims 1 to 7, characterized in that: The display device further includes a plurality of scan lines, each of which is connected to a plurality of adjacent rows of sub-pixels.

10. The display device according to any one of claims 1 to 7, characterized in that: The display device further includes: a clock line connected to each of the first decoders, each of the second decoders, the first shift latch circuit, and the second shift latch circuit; A synchronization trigger line is connected to the first shift latch circuit and the second shift latch circuit.

11. The display device according to any one of claims 1 to 7, characterized in that: The display device further includes a glass substrate provided with the data driver.

12. An electronic device, characterized in that: The electronic device comprises the display device according to any one of claims 1 to 11.

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