Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a pad composite layer on a substrate, the pad composite layer including a first barrier layer and a pad material layer; forming an inorganic anti-reflection layer on the surface of the pad composite layer and a photoresist material layer on the surface of the inorganic anti-reflection layer; patterning the photoresist material layer to form a photoresist layer; using the photoresist layer as a mask, adopting a first dry etching process to etch the inorganic anti-reflection layer and the pad composite layer until the first barrier layer is exposed, forming a groove in the inorganic anti-reflection layer and the pad composite layer, and forming a pad layer with the pad material layer; after the first dry etching process, removing the photoresist layer; after removing the photoresist layer, adopting a second dry etching process to etch the inorganic anti-reflection layer and the first barrier layer at the bottom of the groove, so as to remove the inorganic anti-reflection layer and the first barrier layer at the bottom of the groove, while improving the line accuracy of the formed pad layer and avoiding the problem of increasing the resistance of the pad layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor integrated circuit manufacturing, the requirements for process linewidth dimensions, line edge roughness (abbreviated as LWR), and resistance in the chip manufacturing process are becoming increasingly strict. Reducing resistance and improving linewidth accuracy have become important means to improve the performance of semiconductor devices.

[0003] During the lithography process, when light passes through the photoresist and reaches the high-reflection feature material, light reflection occurs, resulting in the exposure of the photoresist outside the pattern to be exposed. Therefore, the accuracy of the lithography pattern is reduced, and the line edge roughness is very poor.

[0004] Currently, metal aluminum copper (AlCu) is used as the top-layer encapsulation bonding block material to connect and bond with the external circuit, and is widely used in the manufacturing of semiconductor logic products and memory products. The traditional top-layer metal aluminum copper pad process structure includes a titanium nitride / aluminum copper / titanium nitride structure. The bottom-layer titanium nitride (TIN) is used as a metal adhesion barrier layer. During the lithography process, the top-layer titanium nitride has a poor anti-reflection layer effect and is prone to problems of line accuracy deviation.

[0005] Therefore, the existing process for forming the top-layer metal aluminum copper pad needs to be further improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0007] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a pad composite material layer on the substrate, the pad composite material layer including a first barrier layer and a pad material layer located on the surface of the first barrier layer; forming an inorganic anti-reflection layer on the surface of the pad composite material layer and a photoresist material layer located on the surface of the inorganic anti-reflection layer; patterning the photoresist material layer to form a photoresist layer; using the photoresist layer as a mask, adopting a first dry etching process to etch the inorganic anti-reflection layer and the pad composite material layer until the first barrier layer is exposed, forming a groove in the inorganic anti-reflection layer and the pad composite material layer, and forming a pad layer with the pad material layer; after the first dry etching process, removing the photoresist layer; after removing the photoresist layer, adopting a second dry etching process to etch the inorganic anti-reflection layer and the first barrier layer at the bottom of the groove to remove the inorganic anti-reflection layer and the first barrier layer at the bottom of the groove.

[0008] Optionally, the pad composite layer further includes: a second barrier layer located on the surface of the pad material layer; the groove is also located within the second barrier layer; in the second dry etching process, while removing the first barrier layer at the bottom of the groove, the inorganic antireflection layer and the second barrier layer are removed.

[0009] Optionally, the material of the second barrier layer includes titanium nitride.

[0010] Optionally, the thickness of the second barrier layer is less than the thickness of the first barrier layer.

[0011] Optionally, the thickness range of the first barrier layer is from 50 nm to 120 nm; the thickness range of the second barrier layer is from 20 nm to 80 nm.

[0012] Optionally, the thickness range of the inorganic antireflection layer is from 20 nm to 60 nm.

[0013] Optionally, the etching selectivity of the second dry etching process for the inorganic antireflection layer and the first barrier layer ranges from 3:1 to 10:1.

[0014] Optionally, the material of the inorganic antireflection layer includes silicon oxynitride; the material of the first barrier layer includes titanium nitride or tantalum nitride.

[0015] Optionally, the process parameters of the second dry etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power range is from 100 watts to 800 watts, the gas pressure in the etching chamber ranges from 5 mTorr to 8 mTorr, and the etching gas flow rate is from 50 sccm to 100 sccm.

[0016] Optionally, the process parameters of the first dry etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power range is from 300 watts to 800 watts, the gas pressure in the etching chamber ranges from 5 mTorr to 8 mTorr, and the etching gas flow rate is from 100 sccm to 300 sccm.

[0017] Optionally, the refractive index of the inorganic antireflection layer is between that of the substrate and the photoresist material layer.

[0018] Optionally, the formation process of the inorganic antireflection layer includes plasma enhanced chemical vapor deposition.

[0019] Optionally, the material of the pad material layer includes a metal, and the metal includes aluminum copper, silver, or platinum.

[0020] Optionally, the substrate includes a base structure and a dielectric layer located on the base structure; the material of the dielectric layer includes a dielectric material, and the dielectric material includes one or a combination of more than one of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride.

[0021] Optionally, the base structure includes a base, a device layer located on the base, and an interconnect layer located on the device layer, and the interconnect layer is electrically connected to the device layer; the solder pad layer is electrically connected to the interconnect layer.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, an inorganic antireflection layer with a lower cost is used between the solder pad composite layer and the photoresist material layer. During the photolithography process of patterning the photoresist material layer, it is beneficial to reduce the standing wave effect caused by the light reflection problem, improve the pattern transfer accuracy, and further improve the line accuracy of the formed solder pad layer; in addition, the inorganic antireflection layer is removed by the second dry etching process, so that the surface of the solder pad layer is not covered by the inorganic antireflection layer, avoiding the open circuit problem of the inorganic antireflection layer when the solder pad layer is connected to the external circuit; at the same time, during the second dry etching process, by selecting an appropriate etching selectivity for the inorganic antireflection layer and the first barrier layer, the inorganic antireflection layer and the first barrier layer at the bottom of the groove can be removed simultaneously, and the first barrier layer can play a role in protecting the substrate, reducing the etching damage to the substrate, and overall being beneficial to improving the performance of the device.

[0024] Furthermore, the solder pad composite layer further includes: a second barrier layer located on the surface of the solder pad material layer. While playing the role of a metal adhesion barrier layer, the second barrier layer can reduce the light reflection problem during the photolithography process and further improve the line accuracy of the formed solder pad layer.

[0025] Furthermore, in the second dry etching process, while removing the first barrier layer at the bottom of the groove, the inorganic antireflection layer and the second barrier layer are removed. Removing the second barrier layer makes the surface of the solder pad layer not covered by the second barrier layer, avoiding the problem of excessive resistance introduced by the second barrier layer when the solder pad layer is connected to the external circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 3 is a cross-sectional schematic diagram of a process for forming a semiconductor structure;

[0027] Figure 4 is a flowchart of the steps of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0028] Figures 5 to 10 These are schematic structural diagrams of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed implementation manners

[0029] It should be noted that the "surface" and "on" in this specification are used to describe the relative spatial position relationship and do not limit whether there is direct contact.

[0030] As described in the background art, the existing formation process of the top metal aluminum-copper pad needs to be further improved, and the performance of the top metal aluminum-copper pad urgently needs to be enhanced. Now, an analysis will be made in combination with the formation process of a semiconductor structure.

[0031] Figures 1 to 3 This is a cross-sectional schematic diagram of the formation process of a semiconductor structure.

[0032] Please refer to Figure 1 , a substrate is provided, the substrate includes a base 101 and an oxide layer 102 located on the surface of the base 101; a pad composite layer is formed on the surface of the substrate, the pad composite layer includes a first barrier material layer 103, a pad material layer 104 located on the surface of the first barrier material layer 103, and a second barrier material layer 105 located on the surface of the pad material layer 104.

[0033] Please refer to Figure 2 , a photoresist material layer (not shown in the figure) is formed on the surface of the pad composite layer; the photoresist material layer is patterned to form a photoresist layer 106.

[0034] Please refer to Figure 3 , using the photoresist layer 106 as a mask, the pad composite layer is etched to form a pad composite layer, the pad composite layer includes a first barrier layer 107, a pad layer 108, and a second barrier layer 109. The first barrier layer 107 is formed from the first barrier material layer 103, the pad layer 108 is formed from the pad material layer 104, and the second barrier layer 109 is formed from the second barrier material layer 105; after forming the pad composite layer, the photoresist layer 106 is removed.

[0035] The above method is used to form a pad composite layer, which serves as a pad and is used to connect to an external circuit in subsequent packaging processes. Among them, the material of the pad layer 108 is aluminum copper, and the materials of the first barrier layer 107 and the second barrier layer 109 are both titanium nitride, and both play the role of a metal adhesion barrier layer. In the photolithography process of patterning the photoresist material layer, in order to save costs, a bottom anti-reflective coating (abbreviated as BARC) is generally not spin-coated, and the second barrier material layer 105 serves as an anti-reflective layer to reduce light reflection occurring during photolithography.

[0036] However, the insufficient anti-reflection ability of the second barrier material layer 105 results in a standing wave effect ( Figure 2 as shown by the dashed line in Figure 3 ), which in turn leads to a line accuracy deviation problem in the formed pad composite layer (as shown by the dashed line in

[0037] ). In addition, since the second barrier layer 109 is difficult to remove, in subsequent packaging processes, the second barrier layer 109 remaining on the top of the pad layer 108 will introduce a large resistance, thereby affecting the performance of the semiconductor device.

[0038] To solve the above problems, in a method for forming a semiconductor structure provided by the present invention, a low-cost inorganic anti-reflective layer is adopted between the pad composite material layer and the photoresist material layer. During the photolithography process of patterning the photoresist material layer, it is beneficial to reduce the standing wave effect caused by light reflection problems, improve the pattern transfer accuracy, and thus facilitate improving the line accuracy of the formed pad layer; in addition, a second dry etching process is used to remove the inorganic anti-reflective layer, so that the surface of the pad layer is not covered by the inorganic anti-reflective layer, avoiding the problem of open circuit when the inorganic anti-reflective layer is connected to the external circuit; at the same time, during the second dry etching process, an appropriate etching selectivity for the inorganic anti-reflective layer and the first barrier layer is selected, and the inorganic anti-reflective layer and the first barrier layer at the bottom of the groove can be removed simultaneously, and the first barrier layer can play a role in protecting the substrate, reducing the etching damage to the substrate, and overall facilitating improving the performance of the device.

[0039] Figure 4 It is a step flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] In this embodiment, the method for forming the semiconductor structure includes the following steps:

[0041] Step S21, providing a substrate.

[0042] Step S22, form a pad composite layer on the substrate, where the pad composite layer includes a first barrier layer and a pad material layer located on the surface of the first barrier layer;

[0043] Step S23, form an inorganic antireflection layer on the surface of the pad composite layer and a photoresist material layer located on the surface of the inorganic antireflection layer;

[0044] Step S24, pattern the photoresist material layer to form a photoresist layer;

[0045] Step S25, using the photoresist layer as a mask, adopt a first dry etching process to etch the inorganic antireflection layer and the pad composite layer until the first barrier layer is exposed, form a groove in the inorganic antireflection layer and the pad composite layer, and form a pad layer with the pad material layer;

[0046] Step S26, after the first dry etching process, remove the photoresist layer;

[0047] Step S27, after removing the photoresist layer, adopt a second dry etching process to etch the inorganic antireflection layer and the first barrier layer at the bottom of the groove to remove the inorganic antireflection layer and the first barrier layer at the bottom of the groove.

[0048] The following will be described in detail with reference to the accompanying drawings.

[0049] Figures 5 to 10 is a schematic structural diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0050] Please refer to Figure 5 , provide a substrate.

[0051] The substrate includes a substrate structure 201 and a dielectric layer 202 located on the substrate structure 201.

[0052] The material of the dielectric layer 202 includes a dielectric material, and the dielectric material includes one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the dielectric layer 202 is silicon oxide.

[0053] The substrate structure 201 includes a substrate (not shown in the figure), a device layer (not shown in the figure) located on the substrate, and a metal interconnection layer (not shown in the figure) located on the device layer, and the inter-metal connection layer is electrically connected to the device layer. The subsequently formed pad layer is used to electrically connect the metal interconnection layer to an external circuit.

[0054] The device layer includes an isolation structure (not shown in the figure) and a device structure (not shown in the figure) located within the isolation structure. The device structure includes transistors, diodes, triodes, capacitors, inductors, or conductive structures, etc.

[0055] Please refer to Figure 6 , a pad composite layer is formed on the substrate. The pad composite layer includes a first barrier layer 203 and a pad material layer 204 located on the surface of the first barrier layer 203.

[0056] The pad material layer 204 is used to form a pad layer. The first barrier layer 203 helps to improve the adhesion between the pad material layer 204 and the substrate and blocks the diffusion of ions in the pad material layer 204 towards the substrate.

[0057] In this embodiment, the material of the first barrier layer 203 is titanium nitride. In another embodiment, the material of the first barrier layer can also be tantalum nitride or other materials.

[0058] The thickness range of the first barrier layer 203 is from 50 nm to 120 nm.

[0059] The material of the pad material layer 204 includes metals, and the metals include aluminum copper, silver, or platinum. In this embodiment, the material of the pad material layer 204 is aluminum copper. In other embodiments, the material of the pad material layer can also be silver or platinum or other materials.

[0060] In this embodiment, the pad composite layer further includes: a second barrier layer 205 located on the surface of the pad material layer 204. The second barrier layer 205 can further reduce the light reflection problem during the lithography process while acting as a metal adhesion and barrier layer, so as to further improve the line accuracy of the formed pad layer.

[0061] In other embodiments, the second barrier layer 205 may not be formed.

[0062] In this embodiment, the material of the second barrier layer 205 is titanium nitride. In another embodiment, the material of the second barrier layer can also be tantalum nitride or other materials.

[0063] In this embodiment, the material of the second barrier layer 205 is the same as that of the first barrier layer 203.

[0064] In this embodiment, the thickness of the second barrier layer 205 is less than that of the first barrier layer 203. The purpose of making the thickness of the second barrier layer 205 less than that of the first barrier layer 203 is that in the subsequent second dry etching process, by using an appropriate etching selectivity for the inorganic anti-reflection layer and the first barrier layer, the first barrier layer at the bottom of the groove can be removed while removing the inorganic anti-reflection layer and the second barrier layer.

[0065] The thickness range of the second barrier layer 205 is 20 nm to 80 nm.

[0066] Please refer to Figure 7 , an inorganic anti-reflection layer 206 and a photoresist material layer 207 located on the surface of the inorganic anti-reflection layer 206 are formed on the surface of the pad composite material layer.

[0067] In this embodiment, the thickness range of the inorganic anti-reflection layer 206 is 20 nm to 60 nm.

[0068] The refractive index of the inorganic anti-reflection layer 206 is between that of the substrate and the photoresist material layer 207.

[0069] The material of the inorganic anti-reflection layer 206 includes silicon oxynitride. In this embodiment, the material of the inorganic anti-reflection layer 206 is silicon oxynitride. The preparation method of the silicon oxynitride material film is simple, and the cost is lower than that of the organic anti-reflection material, which is conducive to the popularization of the process.

[0070] The formation process of the inorganic anti-reflection layer 206 includes plasma enhanced chemical vapor deposition.

[0071] Please refer to Figure 8 , pattern the photoresist material layer 207 (as Figure 7 shown), to form a photoresist layer 208.

[0072] So far, a low-cost inorganic anti-reflection layer 206 is used between the pad composite material layer and the photoresist material layer 207. During the photolithography process of patterning the photoresist material layer 207, it is beneficial to reduce the standing wave effect caused by the light reflection problem, improve the pattern transfer accuracy, and thus is beneficial to improving the line accuracy of the subsequent formed pad layer.

[0073] Please refer to Figure 9 , using the photoresist layer 208 as a mask, adopt a first dry etching process to etch the inorganic anti-reflection layer 206 and the pad composite material layer until the first barrier layer 203 is exposed, form a groove 209 in the inorganic anti-reflection layer 206 and the pad composite material layer, and form a pad layer 210 with the pad material layer 204; after the first dry etching process, remove the photoresist layer 208.

[0074] In this embodiment, the groove 209 is also located within the second barrier layer 205.

[0075] In this embodiment, the process parameters of the first dry etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power ranges from 300 watts to 800 watts, the gas pressure within the etching chamber ranges from 5 mTorr to 8 mTorr, and the etching gas flow rate ranges from 100 sccm to 300 sccm.

[0076] Please refer to Figure 10 , after removing the photoresist layer 208, a second dry etching process is used to etch the inorganic anti-reflection layer 206 (as Figure 9 shown) and the first barrier layer 203 at the bottom of the groove 209 to remove the inorganic anti-reflection layer 206 and the first barrier layer 203 at the bottom of the groove 211.

[0077] Using the second dry etching process to remove the inorganic anti-reflection layer 206 makes the surface of the solder pad layer free from the coverage of the inorganic anti-reflection layer 206, avoiding the problem of open circuit when the solder pad layer is connected to the external circuit; meanwhile, during the second dry etching process, by selecting an appropriate etching selectivity for the inorganic anti-reflection layer 206 and the first barrier layer 203, the inorganic anti-reflection layer 206 and the first barrier layer 203 at the bottom of the groove 209 can be removed simultaneously, and the first barrier layer 203 can play a role in protecting the substrate, reducing the etching damage to the substrate, which is generally beneficial to improving the performance of the device.

[0078] In this embodiment, in the second dry etching process, while removing the first barrier layer at the bottom of the groove, the inorganic anti-reflection layer and the second barrier layer 205 (as Figure 9 shown) are removed. Removing the second barrier layer makes the surface of the solder pad layer free from the coverage of the second barrier layer, avoiding the problem of excessive resistance introduced by the second barrier layer when the solder pad layer is connected to the external circuit.

[0079] In this embodiment, the etching selectivity of the second dry etching process for the inorganic anti-reflection layer 206 and the first barrier layer 203 ranges from 3:1 to 10:1.

[0080] In this embodiment, the process parameters of the second dry etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power ranges from 100 watts to 800 watts, the gas pressure within the etching chamber ranges from 5 mTorr to 8 mTorr, and the etching gas flow rate ranges from 50 sccm to 100 sccm.

[0081] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Forming a pad composite material layer on the substrate, the pad composite material layer comprising a first barrier layer, a pad material layer located on a surface of the first barrier layer, and a second barrier layer located on a surface of the pad material layer, wherein the thickness of the second barrier layer is less than that of the first barrier layer, and the material of the second barrier layer is the same as that of the first barrier layer; forming an inorganic anti-reflection layer on the surface of the pad composite material layer and a photoresist material layer located on the surface of the inorganic anti-reflection layer; Patterning the photoresist material layer to form a photoresist layer; Using the photoresist layer as a mask, a first dry etching process is used to etch the inorganic anti-reflection layer and the pad composite material layer until the first barrier layer is exposed, a groove is formed in the inorganic anti-reflection layer and the pad composite material layer, and a pad layer is formed with the pad material layer; After the first dry etching process, removing the photoresist layer; After removing the photoresist layer, a second dry etching process is used to etch the inorganic anti-reflection layer, the second barrier layer and the first barrier layer at the bottom of the groove to remove the inorganic anti-reflection layer, the second barrier layer and the first barrier layer at the bottom of the groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second barrier layer includes titanium nitride.

3. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the second barrier layer is smaller than that of the first barrier layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The thickness of the first barrier layer is in a range of 50 nm to 120 nm; the thickness of the second barrier layer is in a range of 20 nm to 80 nm.

5. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the inorganic anti-reflection layer is in the range of 20 nm to 60 nm.

6. The method for forming a semiconductor structure according to claim 1, wherein: The etching selectivity ratio of the second dry etching process to the inorganic anti-reflection layer and the first barrier layer is in a range of 3:1 to 10:

1.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the inorganic anti-reflection layer includes silicon oxynitride; the material of the first barrier layer includes titanium nitride or titanium nitride.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process parameters of the second dry etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power ranges from 100 W to 800 W, the gas pressure in the etching chamber ranges from 5 mTorr to 8 mTorr, and the etching gas flow rate is 50 sccm to 100 sccm.

9. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the first dry etching process include: the etching gas includes one or more of Cl2, CF4, and BCl3, the etching power ranges from 300 W to 800 W, the gas pressure in the etching chamber ranges from 5 mTorr to 8 mTorr, and the etching gas flow rate is 100 sccm to 300 sccm.

10. The method for forming a semiconductor structure according to claim 1, wherein: The refractive index of the inorganic anti-reflection layer is between that of the substrate and the photoresist material layer.

11. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming the inorganic anti-reflection layer includes plasma enhanced chemical vapor deposition.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the pad material layer includes metal, and the metal includes aluminum copper, silver or platinum.

13. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes a base structure and a dielectric layer located on the base structure; the material of the dielectric layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbon nitride.

14. The method for forming a semiconductor structure according to claim 13, wherein: The substrate structure comprises a substrate, a device layer located on the substrate, and an interconnection layer located on the device layer, wherein the interconnection layer is electrically connected to the device layer; and the pad layer is electrically connected to the interconnection layer.

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