Display panel and display module

Abstract

A display panel is provided, which includes a display area and a peripheral area, the peripheral area including a first signal line arrangement area and a second signal line arrangement area; the first signal line arrangement area including a plurality of first signal lines, and the second signal line arrangement area including a plurality of second signal lines. The first signal line arrangement area close to the boundary of the display area includes a plurality of first lead-out positions, a plurality of first lead-out lines are correspondingly led out from the plurality of first lead-out positions and are correspondingly connected with the plurality of first signal lines; the first lead-out line is connected with a data line; one first reference lead-out position is included in the plurality of first lead-out positions, a first reference signal line is led out at the first reference lead-out position and is connected with a first reference data line. The second signal line arrangement area close to the boundary of the display area includes a plurality of second lead-out positions, a plurality of second lead-out lines are correspondingly led out from the plurality of second lead-out positions and are correspondingly electrically connected with the plurality of second signal lines; the second lead-out line is electrically connected with a gate line.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and display module. Background Technology

[0002] The display panel has a display area and a bezel area, where the display area is used to display the image. Existing display panels have relatively wide bezels. Summary of the Invention

[0003] On one hand, a display panel is provided. The display panel includes a display area and a peripheral area. The display area includes a plurality of pixels arranged in an array, the array extending along a first direction and a second direction respectively. Each pixel includes a plurality of sub-pixels arranged along the first direction. The peripheral area includes a first signal line arrangement area and a second signal line arrangement area surrounding the display area. The first signal line arrangement area includes a plurality of first signal lines extending in the same direction, and the second signal line arrangement area includes a plurality of second signal lines extending in the same direction. Both the first signal line arrangement area and the second signal line arrangement area are elongated strips and include boundaries that are close to each other but do not overlap, and the boundaries extend in the same direction. The first signal line arrangement area near the boundary of the display area includes multiple first lead-out positions. Multiple first lead-out lines are led out from each of these positions and electrically connected to the multiple first signal lines. The first lead-out lines are electrically connected to the data lines. One of the multiple first lead-out positions is a first reference lead-out position. A first reference lead-out line is led out from the first reference lead-out position and electrically connected to a first reference data line. The width of the first signal line arrangement area corresponding to the first reference lead-out position is b0. The width b of the first signal line arrangement area corresponding to at least partially continuous first target lead-out positions (excluding the first reference lead-out position) satisfies: b0 - [int(kΔ1 / P1)](W data +S data )≤b≤b0-[int(kΔ1 / P1)-1](W data +S data ); where Δ1 is the distance between the first target extraction position and the first reference extraction position in the first direction, P1 is the arrangement period of the pixels in the first direction, k is the number of sub-pixels in a pixel, and W data S is the width of the first signal line. dataThe spacing of the first signal lines is defined as follows. The second signal line arrangement area near the boundary of the display area includes a plurality of second lead-out positions, from which a plurality of second lead-out lines are led out one-to-one and electrically connected to a plurality of second signal lines in a corresponding manner; the second lead-out lines are electrically connected to the gate lines; at least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction.

[0004] In some embodiments, the first direction and the second direction are perpendicular. The extension directions of at least a portion of the first signal line arrangement area and at least a portion of the second signal line arrangement area are different from both the first direction and the second direction.

[0005] In some embodiments, for the at least partially continuously distributed first target lead-out positions, the width b1 of the first signal line arrangement area corresponding to the first target lead-out position of the sub-pixel with the same color as the sub-pixel electrically connected to the first reference data line satisfies: b1=b0-[int(kΔ1 / P1)](W data +S data ).

[0006] In some embodiments, the at least partially continuous distribution of the first target lead-out positions includes three continuously distributed first target lead-out positions, each of which is electrically connected to one of the three sub-pixels of a pixel, and the total width of the three first lead-out lines corresponding to the three continuously distributed first target lead-out positions is less than or equal to the arrangement period of a sub-pixel in the first direction.

[0007] In another aspect, a display panel is provided. The display panel includes a display area and a peripheral area. The display area includes a plurality of pixels arranged in an array, the array extending along a first direction and a second direction respectively. Each pixel includes a plurality of sub-pixels arranged along the first direction. The peripheral area includes a first signal line arrangement area and a second signal line arrangement area surrounding the display area. The first signal line arrangement area includes a plurality of first signal lines extending in the same direction, and the second signal line arrangement area includes a plurality of second signal lines extending in the same direction. Both the first and second signal line arrangement areas are elongated strips and include boundaries that are close to each other but do not overlap, the boundaries extending in the same direction. The first signal line arrangement area near the boundary of the display area includes a plurality of first lead-out positions, and the plurality of first lead-out lines are led out from the plurality of first lead-out positions one-to-one and electrically connected to the plurality of first signal lines one-to-one; the first lead-out lines are electrically connected to data lines. The second signal line arrangement area near the boundary of the display area includes multiple second lead-out positions. Multiple second lead-out lines are led out from these positions one-to-one and electrically connected to multiple second signal lines. The second lead-out lines are electrically connected to the gate lines. At least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction. One of the multiple second lead-out positions includes a second reference lead-out position. A second reference lead-out line is led out from the second reference lead-out position and electrically connected to a second reference gate line. The width of the second signal line arrangement area corresponding to the second reference lead-out position is c0. Among the at least partially continuous second target lead-out positions other than the second reference lead-out position, the width c of the second signal line arrangement area corresponding to each second target lead-out position satisfies: c0 - [int(kΔ2 / P1) + 1](W gate +S gate )≤c≤c0-[int(kΔ2 / P1)-1](W gate +S gate ), where Δ2 is the distance between the second target lead-out position and the second reference lead-out position in the first direction, W gate S is the width of the second signal line. gate The spacing of the second signal line.

[0008] In some embodiments, the distance between the first reference lead-out position and the second reference lead-out position in the first direction is less than one arrangement period of the pixel in the first direction X; the at least partially continuous second target lead-out positions and the at least partially continuous first target lead-out positions are alternately distributed in the first direction.

[0009] In some embodiments, among the at least partially continuous first target lead-out positions, m second target lead-out positions are respectively set on both sides of every three first target lead-out positions, where m is one of the three values ​​of 4, 5, and 6.

[0010] In some embodiments, the three first target lead-out positions are arranged at equal intervals, and m second target lead-out positions are arranged at equal intervals, wherein the distance between the three first target lead-out positions is greater than the distance between the m second target lead-out positions.

[0011] In some embodiments, the three first target lead-out positions are arranged at equal intervals, and the m second target lead-out positions are arranged at equal intervals. The width occupied by the three first target lead-out positions in the first direction is smaller than the width occupied by the m second target lead-out positions in the first direction.

[0012] In some embodiments, the angle between the first lead and the first signal line electrically connected thereto is greater than or equal to 90 degrees; the angle between the second lead and the second signal line electrically connected thereto is greater than or equal to 90 degrees.

[0013] In another aspect, a display panel is provided. The display panel includes a display area and a peripheral area. The display area includes a plurality of pixels arranged in an array, the array extending along a first direction and a second direction respectively. Each pixel includes a plurality of sub-pixels arranged along the first direction. The peripheral area includes a first signal line arrangement area and a second signal line arrangement area surrounding the display area. The first signal line arrangement area includes a plurality of first signal lines extending in the same direction, and the second signal line arrangement area includes a plurality of second signal lines extending in the same direction. Both the first and second signal line arrangement areas are elongated strips and include boundaries that are close to each other but do not overlap, the boundaries extending in the same direction. The first signal line arrangement area near the boundary of the display area includes a plurality of first lead-out positions, and the plurality of first lead-out lines are led out from the plurality of first lead-out positions one-to-one and electrically connected to the plurality of first signal lines one-to-one; the first lead-out lines are electrically connected to data lines. The second signal line arrangement area near the boundary of the display area includes multiple second lead-out positions. Multiple second lead-out lines are led out from these positions one-to-one and electrically connected to multiple second signal lines. The second lead-out lines are electrically connected to the gate lines. At least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction. One of the multiple second lead-out positions includes a second reference lead-out position. A second reference signal line is led out from the second reference lead-out position and electrically connected to the second reference gate line. The width of the second signal line arrangement area corresponding to the second reference lead-out position is c0. Among the at least partially continuous second target lead-out positions other than the second reference lead-out position, the width c of the second signal line arrangement area corresponding to each second target lead-out position satisfies: c0 - [int(Δ3 / P] sub2 )+1](W gate +S gate )≤c≤c0-[int(Δ3 / P sub2 )-1](W gate +S gate ), where Δ3 is the distance between the second target lead-out position and the second reference lead-out position in the second direction, P sub2 W represents the arrangement period of sub-pixel S0 in the second direction. gate S is the width of the second signal line. gate The spacing of the second signal line.

[0014] In some embodiments, for the at least partially continuously distributed second target lead-out positions, the width c1 of the second signal line arrangement area corresponding to a second lead-out position electrically connected to a target gate line spaced an odd number of gate lines apart from the second reference gate line satisfies: c1=c0-[int(Δ3 / P sub2 )](Wgate +S gate ).

[0015] In some embodiments, the width c satisfies: c = c0 - [int(Δ3 / P)] sub2 )](W gate +S gate ).

[0016] In some embodiments, the width b satisfies: b = b0 - [int(kΔ1 / P1)](W gate +S gate ), where P1 is the arrangement period of the pixels in the first direction.

[0017] In some embodiments, the first signal line arrangement area is closer to the display area than the second signal line arrangement area; or, the second signal line arrangement area is closer to the display area than the first signal line arrangement area.

[0018] In another aspect, a display panel is provided. The display panel includes a display area and a peripheral area. The display area includes a plurality of pixels arranged in an array, the array extending along a first direction and a second direction respectively. Each pixel includes a plurality of sub-pixels arranged along the first direction. The peripheral area includes a first signal line arrangement area and a second signal line arrangement area surrounding the display area. The first signal line arrangement area includes a plurality of first signal lines extending in the same direction, and the second signal line arrangement area includes a plurality of second signal lines extending in the same direction. Both the first and second signal line arrangement areas are elongated strips and include boundaries that are close to each other but do not overlap, the boundaries extending in the same direction. The first signal line arrangement area near the boundary of the display area includes a plurality of first lead-out positions, and the plurality of first lead-out lines are led out from the plurality of first lead-out positions one-to-one and electrically connected to the plurality of first signal lines one-to-one; the first lead-out lines are electrically connected to data lines. The second signal line arrangement area near the boundary of the display area includes multiple second lead-out positions. Multiple second lead-out lines are led out from these positions one-to-one and electrically connected to multiple second signal lines. The second lead-out lines are electrically connected to the gate lines. At least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction. When the second signal line arrangement area is closer to the display area than the first signal line arrangement area, and the first lead-out lines are led out along the second direction, the included angle θ1 between the first signal line arrangement area adjacent to the second signal line arrangement area and the second signal line arrangement area adjacent to the first signal line arrangement area satisfies: sinθ1=[I1(W data +S data)cosα1] / P1, where α1 is the angle between the second signal line in the second signal line arrangement area adjacent to the first signal line arrangement area and the first direction; I1 is the number of first target lead-out positions corresponding to the arrangement period range of a pixel in the first direction, and P1 is the arrangement period of the pixel in the first direction.

[0019] In another aspect, a display panel is provided. The display panel includes a display area and a peripheral area. The display area includes a plurality of pixels arranged in an array, the array extending along a first direction and a second direction respectively. Each pixel includes a plurality of sub-pixels arranged along the first direction. The peripheral area includes a first signal line arrangement area and a second signal line arrangement area surrounding the display area. The first signal line arrangement area includes a plurality of first signal lines extending in the same direction, and the second signal line arrangement area includes a plurality of second signal lines extending in the same direction. Both the first and second signal line arrangement areas are elongated strips and include boundaries that are close to each other but do not overlap, the boundaries extending in the same direction. The first signal line arrangement area near the boundary of the display area includes a plurality of first lead-out positions, and the plurality of first lead-out lines are led out from the plurality of first lead-out positions one-to-one and electrically connected to the plurality of first signal lines one-to-one; the first lead-out lines are electrically connected to data lines. The second signal line arrangement area near the boundary of the display area includes multiple second lead-out positions. Multiple second lead-out lines are led out from these positions one-to-one and electrically connected to multiple second signal lines. The second lead-out lines are electrically connected to the gate lines. At least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction. When the first signal line arrangement area is closer to the display area than the second signal line arrangement area, and the second lead-out lines are led out along the second direction, the included angle θ2 between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the second signal line in the second signal line arrangement area adjacent to the first signal line arrangement area satisfies: sinθ2=[I2(W gate +S gate )coxα2] / P1, where α2 is the angle between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the first direction; I2 is the number of second target lead-out positions corresponding to the arrangement period range of a pixel in the first direction, and P1 is the arrangement period of the pixel in the first direction.

[0020] In another aspect, a display panel is provided. The display panel includes a display area and a peripheral area. The display area includes a plurality of pixels arranged in an array, the array extending along a first direction and a second direction respectively. Each pixel includes a plurality of sub-pixels arranged along the first direction. The peripheral area includes a first signal line arrangement area and a second signal line arrangement area surrounding the display area. The first signal line arrangement area includes a plurality of first signal lines extending in the same direction, and the second signal line arrangement area includes a plurality of second signal lines extending in the same direction. Both the first and second signal line arrangement areas are elongated strips and include boundaries that are close to each other but do not overlap, the boundaries extending in the same direction. The first signal line arrangement area near the boundary of the display area includes a plurality of first lead-out positions, and the plurality of first lead-out lines are led out from the plurality of first lead-out positions one-to-one and electrically connected to the plurality of first signal lines one-to-one; the first lead-out lines are electrically connected to data lines. The second signal line arrangement area near the boundary of the display area includes multiple second lead-out positions. Multiple second lead-out lines are led out from these positions one-to-one and electrically connected to multiple second signal lines. The second lead-out lines are electrically connected to the gate lines. At least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction. When the first signal line arrangement area is closer to the display area than the second signal line arrangement area, and the second lead-out lines are led out along the first direction, the included angle θ3 between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the second signal line in the second signal line arrangement area adjacent to the first signal line arrangement area satisfies: sinθ3=[I3(W gate +S gate )sinα3] / P2, where α3 is the angle between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the first direction; I3 is the number of second target lead-out positions corresponding to the arrangement period range of a pixel in the second direction, where P2 is the arrangement period of a pixel in the second direction.

[0021] In some embodiments, the angle θ between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the second signal line in the second signal line arrangement area adjacent to the first signal line arrangement area ranges from 1° to 5°.

[0022] In some embodiments, the width of the first lead is greater than the width of the first signal line connected thereto; and / or, the width of the second lead is greater than the width of the second signal line connected thereto.

[0023] In another aspect, a display panel is provided. The display panel includes a display area and a peripheral area. The display area includes a plurality of pixels arranged in an array, the array extending along a first direction and a second direction respectively. Each pixel includes a plurality of sub-pixels arranged along the first direction. The peripheral area includes a first signal line arrangement area and a second signal line arrangement area surrounding the display area. The first signal line arrangement area includes a plurality of first signal lines extending in the same direction, and the second signal line arrangement area includes a plurality of second signal lines extending in the same direction. Both the first and second signal line arrangement areas are elongated strips and include boundaries that are close to each other but do not overlap, the boundaries extending in the same direction. The first signal line arrangement area near the boundary of the display area includes a plurality of first lead-out positions, and the plurality of first lead-out lines are led out from the plurality of first lead-out positions one-to-one and electrically connected to the plurality of first signal lines one-to-one; the first lead-out lines are electrically connected to data lines. The second signal line arrangement area near the boundary of the display area includes multiple second lead-out positions. Multiple second lead-out lines are led out from these positions one-to-one and electrically connected to multiple second signal lines. The second lead-out lines are electrically connected to the gate lines. At least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction. The display panel includes a gate driving circuit located in the non-display area. The gate driving circuit has multiple shift register units, at least a portion of which are electrically connected to the gate lines for sending gate driving signals to the gate lines. The overall span of the multiple shift register units in the second direction is smaller than the overall span of the pixels in the display area in the second direction.

[0024] In some embodiments, the display area includes a column of pixel units with the longest span. In the plane where the display panel is located, the first orthographic projection of the plurality of shift register units on the straight line where the column of pixels with the longest span is located is within the range of the second orthographic projection of the column of pixels with the longest span on the straight line where it is located.

[0025] In some embodiments, the distribution period of the shift register units distributed on at least one side of the display area is less than the distribution period of the sub-pixels in the second direction.

[0026] In some embodiments, the distribution contour of the shift register units on at least one side of the display area is the same as the outer contour of the display area on the corresponding side.

[0027] In some embodiments, the ratio between the first orthographic projection and the second orthographic projection is in the range of [0.1, 0.9].

[0028] In some embodiments, the plurality of shift register units are located on both sides of the display area.

[0029] In some embodiments, a common electrode lead is further included between the boundary of the display area and the nearest signal line arrangement area, wherein the signal line arrangement area closest to the boundary of the display area is either the first signal line arrangement area or the second signal line arrangement area. In this embodiment, the outline of the common electrode lead at least partially matches the outer outline of the corresponding display area; alternatively, virtual sub-pixels are included around the periphery of the display area, and the common electrode lead at least partially extends along the overall outer outline formed by the sub-pixels and the virtual sub-pixels in the display area.

[0030] In some embodiments, the minimum distance 'a' between the outer contour of the display area and the area closest to the signal line arrangement is greater than or equal to 1. The signal line arrangement area closest to the boundary of the display surface area is either the first signal line arrangement area or the second signal line arrangement area.

[0031] In some embodiments, the arrangement period P1 of the pixels in the first direction is in the range of [60μm, 900μm]; the arrangement period P2 of the pixels in the second direction is in the range of [60μm, 900μm]. The width P of the sub-pixel in the first direction... sub1 Within the range of [20μm, 900μm]; the width P of the sub-pixel in the second direction sub2 Within the range of [20μm, 900μm].

[0032] In some embodiments, the width W of the first signal line data Within the range of [1μm, 20μm]; the spacing S of the first signal line data Within the range of [1μm, 20μm]. The width W of the second signal line is... gate Within the range of [1μm, 20μm]; the spacing S of the second signal line gate Within the range of [1μm, 20μm].

[0033] In some embodiments, the first reference lead-out position is the first lead-out position closest to the maximum width of the first signal line arrangement area.

[0034] In some embodiments, the second reference lead-out position is the second lead-out position closest to the maximum width of the second signal line arrangement area.

[0035] In some embodiments, the display panel includes a data line bonding area, which includes a plurality of data line bonding pins, and the first signal line is electrically connected to each of the data line bonding pins in a one-to-one correspondence. The first signal line arrangement area is located in the peripheral area between the gate driving circuit and the display area (non-display area) and between the data line bonding area and the display area (non-display area). The second signal line arrangement area is located in the peripheral area between the gate driving circuit and the display area (non-display area) and between the data line bonding area and the display area (non-display area).

[0036] In some embodiments, the display panel includes a data line bonding area, which includes a plurality of data line bonding pins, and the first signal line is electrically connected to each of the data line bonding pins in a one-to-one correspondence. The display panel also includes a gate line bonding area, which includes a plurality of gate line bonding pins, and the second signal line is electrically connected to each of the gate line bonding pins in a one-to-one correspondence. The first signal line arrangement area is located in the non-display area between the gate line bonding area and the display area, and in the non-display area between the data line bonding area and the display area within the peripheral area. The second signal line arrangement area is located in the non-display area between the gate line bonding area and the display area, and in the non-display area between the data line bonding area and the display area within the peripheral area.

[0037] On the other hand, a display module is provided. The display module includes a display panel as described in any of the above embodiments. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0039] Figure 1 This is a structural diagram of a display panel according to some embodiments;

[0040] Figure 2A This is a structural diagram of a display panel according to some embodiments;

[0041] Figure 2B This is a structural diagram of a display panel according to some embodiments;

[0042] Figure 3 This is a structural diagram of a display panel according to some embodiments;

[0043] Figure 4 for Figure 3 A magnified view of a section at point B in the middle;

[0044] Figure 5A for Figure 4 A magnified view of a section at point C;

[0045] Figure 5B for Figure 5A A magnified view of a section at point H in the middle;

[0046] Figure 5C This is a structural diagram of a display panel according to some embodiments;

[0047] Figure 6 for Figure 5A A magnified view of a section at point D;

[0048] Figure 7 for Figure 5A Another magnified view of a section at point D;

[0049] Figure 8 for Figure 4 A magnified view of a section at point E in the middle;

[0050] Figure 9A This is a structural diagram of a display panel according to some embodiments;

[0051] Figure 9B This is a structural diagram of a display panel according to some embodiments;

[0052] Figure 10 This is a structural diagram of a display panel according to some embodiments;

[0053] Figure 11 for Figure 5A Another enlarged view of a section at point D;

[0054] Figure 12A This is a structural diagram of a display panel according to some embodiments;

[0055] Figure 12B This is a structural diagram of a display panel according to some embodiments;

[0056] Figure 12C This is a structural diagram of a display panel according to some embodiments;

[0057] Figure 12D This is a structural diagram of a display panel according to some embodiments;

[0058] Figure 12E This is a structural diagram of a display panel according to some embodiments;

[0059] Figure 12FThis is a structural diagram of a display panel according to some embodiments;

[0060] Figure 13 This is a structural diagram of a display panel according to some embodiments;

[0061] Figure 14A This is a structural diagram of a display panel according to some embodiments;

[0062] Figure 14B This is a structural diagram of a display panel according to some embodiments;

[0063] Figure 15 This is a structural diagram of a display panel according to some embodiments;

[0064] Figure 16 This is a structural diagram of a display panel according to some embodiments;

[0065] Figure 17 This is a structural diagram of a display panel according to some embodiments;

[0066] Figure 18 This is a structural diagram of a display panel according to some embodiments;

[0067] Figure 19 This is a structural diagram of a display panel according to some embodiments;

[0068] Figure 20 This is a structural diagram of a display module according to some embodiments. Detailed Implementation

[0069] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0070] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "some embodiments," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0071] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0072] In describing some embodiments, the term "connection" and its derived expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0073] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0074] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0075] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0076] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0077] Figure 1 This is a structural diagram of a display panel 100 according to some embodiments.

[0078] Please see Figure 1 Some embodiments of this disclosure provide a display panel 100. This display panel 100 can be a liquid crystal display panel. An exemplary structure of the liquid crystal display panel is described below.

[0079] Please see Figure 1 In some examples, the display panel 100 described above includes an array substrate 110, a cell substrate 120, and a liquid crystal layer 130 disposed between the array substrate 110 and the cell substrate 120.

[0080] The array substrate 110 includes a first substrate 111 and a gate metal layer 112, a gate insulating layer GI, an active layer 113, a source / drain metal layer 114, and a planarization layer PVX sequentially disposed on the first substrate 111. The source / drain metal layer 114 overlaps with the active layer 113.

[0081] In addition, the array substrate 110 also includes a pixel electrode 115 and a common electrode 116, with the pixel electrode 115 connected to the source / drain metal layer 114 via vias.

[0082] Please see Figure 1 In some examples, pixel electrode 115 and common electrode 116 can be disposed on the same layer. In this case, pixel electrode 115 and common electrode 116 are both comb structures including multiple strip sub-electrodes.

[0083] In other examples, the pixel electrode 115 and the common electrode 116 may also be disposed on different layers. In this case, an insulating layer is disposed between the pixel electrode 115 and the common electrode 116. At this time, the common electrode 116 may be disposed on the first substrate 111, while the pixel electrode 115 may be disposed on the gate insulating layer GI.

[0084] In addition, in some other examples, the array substrate 110 may include only the pixel electrode 115 and not the common electrode 116, in which case the common electrode 116 may be located in the cell substrate 120.

[0085] Please see Figure 1 The array substrate 110 also includes a planarization layer 117, wherein the gate metal layer 112, the gate insulating layer GI, the active layer 113, the source drain metal layer 114, the planarization layer PVX, and the pixel electrode 115 are all located between the first substrate 111 and the planarization layer 117.

[0086] Please see Figure 1 The cell substrate 120 includes a second substrate 121 and a color filter layer 122, a black matrix pattern 123, and a protective layer 124 disposed on the second substrate 121. The color filter layer 122 and the black matrix pattern 123 are located between the second substrate 121 and the protective layer 124. In this case, the cell substrate 120 can also be referred to as a color filter (CF) substrate.

[0087] The color filter layer 122 includes at least red photoresist units, green photoresist units, and blue photoresist units, each of which is directly opposite a subpixel on the array substrate 110. The black matrix pattern 123 is used to separate the red, green, and blue photoresist units.

[0088] In some embodiments, the display panel 100 is a monochrome display panel, and the substrate 120 may not include the color filter layer 122; in some embodiments, the color filter layer 122 may also be replaced by a colorless light-transmitting material, such as transparent resin.

[0089] Please see Figure 1 The display panel 100 also includes an upper polarizer 140 disposed on the side of the cell substrate 120 away from the liquid crystal layer 130 and a lower polarizer 150 disposed on the side of the array substrate 110 away from the liquid crystal layer 130.

[0090] The above describes the multiple film layers in the display panel 100. Next, the planar structure of the display panel 100 will be described.

[0091] Figure 2A This is a structural diagram of a display panel 100 according to some embodiments. Figure 2B This is a structural diagram of a display panel 100 according to some other embodiments.

[0092] Please see Figure 2A and Figure 2B The display panel 100 includes a display area AA and a peripheral area BB, wherein the peripheral area BB is located on at least one side of the display area AA. In some examples, the peripheral area BB is arranged around the display area AA.

[0093] Please see Figure 2A and Figure 2B The display area AA includes multiple pixels S arranged in an array, with the array extending along a first direction X and a second direction Y, respectively. Each pixel S includes multiple sub-pixels S0 arranged along the first direction X. See also... Figure 2A The direction pointed to by arrow X is the first direction, while the direction pointed to by arrow Y is the second direction.

[0094] Please see Figure 2A The display panel 100 also includes multiple gate lines GT extending along a first direction X and multiple data lines DT extending along a second direction Y. The multiple gate lines GT and multiple data lines DT can define multiple sub-pixel regions. A sub-pixel S0 is located within one sub-pixel region. The multiple gate lines GT are located in the gate metal layer 112 (e.g., ...). Figure 1 As shown in the figure. Multiple data lines DT are located in the source / drain metal layer 114 (as shown in the figure). Figure 1 As shown in the figure.

[0095] Sub-pixel S0 includes a thin-film transistor (TFT), a pixel electrode 115, and a common electrode 116. Sub-pixel S0 may also include a storage capacitor C (e.g., ...). Figure 1 (As shown).

[0096] The thin-film transistor T includes a gate, a source, a drain, and a channel. The gate of the thin-film transistor T is electrically connected to a gate line GT. In some examples, a portion of the gate line GT is multiplexed as the gate of the thin-film transistor T. The source and drain are located in the source-drain metal layer 114 (e.g., ...). Figure 1 As shown), the channel is located in the active layer 113 (as shown). Figure 1 As shown in the figure.

[0097] Please see Figure 2A A gate line GT is electrically connected to the gate of the thin-film transistor T of a row of sub-pixels S0, a data line DT is electrically connected to the source of the thin-film transistor T of a row of sub-pixels S0, and the drain of the thin-film transistor T is electrically connected to the pixel electrode 115.

[0098] Common electrode 116 (e.g.) Figure 1 (As shown) is electrically connected to the common voltage line to receive the common voltage from the common voltage line.

[0099] When the thin-film transistor T is turned on under the control of the gate drive signal on the gate line GT connected to its gate, the data voltage from the data line DT is transmitted to the pixel electrode 115 through the thin-film transistor T. An electric field can be formed between the pixel electrode 115 and the common electrode 116. When the data voltage transmitted to the pixel electrode 115 is different, the electric field formed between the pixel electrode 115 and the common electrode 116 is different. Due to the dielectric anisotropy of liquid crystal, the liquid crystal molecules in the sub-pixel region rotate (i.e., the alignment direction of the liquid crystal molecules changes), causing the refractive index or transmittance of the liquid crystal to change accordingly, thereby controlling the amount of light emitted from the sub-pixel region, and thus controlling the brightness of the sub-pixel S0.

[0100] In some embodiments, the outer contour of the display area AA includes an arc shape. For example, the display area AA is a rounded rectangle; a rounded rectangle can be understood as a rectangle with at least one rounded corner. See some examples. Figure 2B The display area AA can be circular. In some examples, the display area AA can be elliptical.

[0101] The above describes some of the structures in the display area AA of the display panel 100. The following describes some of the structures in the peripheral area BB.

[0102] Figure 3 This is a structural diagram of a display panel 100 according to some embodiments. Figure 4 for Figure 3 A magnified view of a section at point B in the middle.

[0103] See Figure 3 and Figure 4 The surrounding area BB includes a first signal line arrangement area B10 and a second signal line arrangement area B20 arranged around the display area AA. Both the first signal line arrangement area B10 and the second signal line arrangement area B20 are elongated strips and include adjacent but non-overlapping boundaries that extend in the same direction. It should be noted that the fact that the boundaries of the first signal line arrangement area B10 and the second signal line arrangement area B20 extend in the same direction means that the boundaries of the first signal line arrangement area B10 and the second signal line arrangement area B20 are conformal on their adjacent sides.

[0104] In one specific embodiment, in the first signal line arrangement area B10 and the second signal line arrangement area B20, the boundary of one of them near the display area AA is conformal to the outer contour of the display area AA, and the mutually close boundaries of the first signal line arrangement area B10 and the second signal line arrangement area B20 are conformal to each other.

[0105] In some examples, a portion of the first signal line arrangement area B10 is located on the side of the second signal line arrangement area B20 that is away from the display area AA.

[0106] In other examples, a portion of the second signal line arrangement area B20 is located on the side of the first signal line arrangement area B10 that is away from the display area AA.

[0107] The first signal line arrangement area B10 and the second signal line arrangement area B20 are both elongated strips and include boundaries that are close to each other but do not overlap (see...). Figure 7 Boundary 2 and boundary 3 in the text can be understood as: part of the boundary of the first signal line arrangement area B10 and part of the boundary of the second signal line arrangement area B20 are close to each other but do not overlap.

[0108] Figure 5A for Figure 4 A magnified view of a section at point C.

[0109] Please see Figure 5A The first signal line arrangement area B10 includes multiple first signal lines 161 extending in the same direction. The boundary of the first signal line arrangement area B10 near the display area AA includes multiple first lead-out positions B11. Multiple first lead-out lines 162 are led out from the multiple first lead-out positions B11 one-to-one and are electrically connected to the multiple first signal lines 161 one-to-one. The first lead-out lines 162 are electrically connected to the data line DT. Among the multiple first lead-out positions B11, there is a first reference lead-out position B111. The first reference lead-out line 162m is led out from the first reference lead-out position B111 and is electrically connected to the first reference data line DTm. Wherein, in Figure 5A In the diagram, for ease of illustration, only a portion of the first signal line 161 is shown, while the remaining portion is omitted. The "..." indicates the omitted first signal line 161. The extension direction, arrangement, and lead-out position of the first signal line 161 indicated by "..." are consistent with the characteristics of the first signal line 161 shown in the diagram.

[0110] The fact that multiple first signal lines 161 extend in the same direction can be understood as multiple first signal lines 161 extending conformally to each other. Preferably, the width of the first signal lines 161 is the same, and the spacing between any two first signal lines 161 is the same.

[0111] In addition, the peripheral area BB can also be provided with a third signal line arrangement area B30 and a data line binding area B40. The third signal line arrangement area B30 is located on the side of the first signal line arrangement area B10 away from the display area AA, while the data line binding area B40 is located on the side of the third signal line arrangement area B30 away from the display area AA. The third signal line arrangement area B30 is provided with multiple first lead-in lines 163, while the data line binding area B40 is provided with multiple data line binding pins 164. The multiple first lead-in lines 163 can be configured to correspond one-to-one with and be electrically connected to multiple first signal lines 161, and the multiple first lead-in lines 163 can be configured to correspond one-to-one with and be connected to multiple data line binding pins 164.

[0112] In some embodiments, at the connection point between the first lead-in line 163 and the first signal line 161, the extension directions of the first lead-in line 163 and the first signal line 161 are different; at the connection point between the first signal line 161 and the first lead-out line 162, the extension directions of the first signal line 161 and the first lead-out line 162 are different. That is, there may be a clear boundary (e.g., a bend) between the first lead-in line 163 and the first signal line 161, and there may be a clear boundary (e.g., a bend) between the first signal line 161 and the first lead-out line 162. It is understood that the clear boundary is only a clear geometric boundary and does not necessarily represent that different conductor segments are manufactured by different processes. That is, at least two of the first lead-in line 163, the first signal line 161, and the first lead-out line 162 can be manufactured by a single process. In some examples, the first lead-in line 163 may also include one or more trace segments. For example, the first lead-in line 163 includes two trace segments.

[0113] It can be understood that the first reference signal line 161m is led out at the first reference lead-out position B111, which can be understood as the first reference signal line 161m being led out at the first reference lead-out position B111 through a first reference lead-out line 162m.

[0114] In one specific embodiment, a first signal line 161 is electrically connected to a data line DT via a first lead-out line 162, and the other end of the first signal line 161 is connected to a first lead-in line 163. The end of the first lead-in line 163 away from the first signal line 161 is electrically connected to a data line bonding pin 164. The data line bonding pin 164 is electrically connected to a source driver chip, allowing the source driver chip to transmit data signals to the data line DT sequentially via the first lead-in line 163, the first signal line 161, and the first lead-out line 162.

[0115] In some examples, multiple data line bonding pins 164 can be divided into multiple groups, and one group of data line bonding pins 164 can be electrically connected to a source driver chip.

[0116] For example, the first lead-in line 163, the first signal line 161, and the first lead-out line 162 are disposed on the gate metal layer 112 (e.g., Figure 1 As shown in the figure, the first lead-in line 163, the first signal line 161 and the first lead-out line 162 are arranged on the same layer as the gate line GT.

[0117] The width of the first signal line arrangement area B10 corresponding to the first reference lead-out position B111 is b0; among the first target lead-out positions B112 that are at least partially and continuously distributed other than the first reference lead-out position B111, the width b of the first signal line arrangement area B10 corresponding to each first target lead-out position B112 satisfies:

[0118] b0-[int(kΔ1 / P1)](W data +S data )≤b≤b0-[int(kΔ1 / P1)-1](W data +S data ).

[0119] It should be noted that, in addition to the first target lead-out position B112, the width of the first signal line arrangement area B10 corresponding to the area between the first target lead-out position B112 and the first reference lead-out position B111 can also be designed to satisfy this formula.

[0120] Where Δ1 is the distance between the first target extraction position B112 and the first reference extraction position B111 in the first direction X, P1 is the arrangement period of pixel S in the first direction X, k is the number of sub-pixels S0 in a pixel S, and W data S is the width of the first signal line 161. data The spacing of the first signal lines 161. Specifically, in the first signal line arrangement area B10 corresponding to the first target lead-out position B112, which is at least partially continuously distributed excluding the first reference lead-out position B111, the width of the first signal lines 161 is the same; the spacing of the first signal lines 161 is the same.

[0121] Here, int is the floor function.

[0122] It should be noted that the first reference lead-out position B111 is one of a plurality of first lead-out positions B11, and its position may not be specifically defined; in some embodiments, the first reference lead-out position B111 may be set to the first lead-out position B11 closest to the maximum width of the first signal line arrangement area B10.

[0123] The width b0 of the first signal line arrangement area B10 corresponding to the first reference lead-out position B111 can be defined as: the dimension of the first signal line arrangement area B10 at the first reference lead-out position B111, along the direction perpendicular to the extension direction of the first reference signal line 161m. Specifically, at the first reference lead-out position B111, the width b0 of the first signal line arrangement area B10 includes the width of the first reference signal line 161m.

[0124] In the at least partially continuous distribution of first target lead-out positions B112 other than the first reference lead-out position B111, the width b of the first signal line arrangement area B10 corresponding to each first target lead-out position B112 can be defined as: the dimension of the first signal line arrangement area B10 along the direction perpendicular to the extension direction of the first signal line 161 closest to the display area AA at that position. Specifically, at each first target lead-out position B112, the width b of the first signal line arrangement area B10 may include the width of the first signal line 161 led out from that first target lead-out position B112.

[0125] The following is an exemplary description of the width b0 of the first signal line arrangement area B10 at the first reference lead-out position B111 and the width b of the first signal line arrangement area B10 at the first target lead-out position B112.

[0126] Figure 5B for Figure 5A A magnified view of a portion at point H in the image. Specifically, in... Figure 5B In the diagram, for ease of illustration, only a portion of the first signal line 161 is shown, while the remaining portion is omitted. The "..." indicates the omitted first signal line 161. The extension direction, arrangement, and lead-out position of the first signal line 161 indicated by "..." are consistent with the characteristics of the first signal line 161 shown in the diagram.

[0127] Please see Figure 5B A first reference line segment XA is drawn perpendicular to the first reference signal line 161m, passing through the first reference lead-out position B111. One endpoint of the first reference line segment XA intersects the first reference lead-out position B111, and the other endpoint intersects the boundary of the first signal line arrangement area B10 away from the display area AA. The length of the first reference line segment XA is the width b0 of the first signal line arrangement area B10 at the first reference lead-out position B111.

[0128] Please see Figure 5BAt the first target exit position B112n, the first signal line 161 closest to the display area AA is marked as 161n. A reference line segment XD perpendicular to the first signal line 161n is drawn through the first target exit position B112n. One endpoint of this reference line segment XD intersects the first target exit position B112n, and the other endpoint intersects the boundary of the first signal line arrangement area B10 away from the display area AA. The length of the reference line segment XD is the width b of the first signal line arrangement area B10 corresponding to the first target exit position B112n. It should be noted that the width of the first signal line arrangement area B10 corresponding to the first target exit position B112n includes the width of the first signal line 161n closest to the display area AA at the first target exit position B112n.

[0129] Since multiple first signal lines are arranged side-by-side and extend in the same direction in the first signal line arrangement area B10, the width of the first signal line arrangement area B10 corresponding to each first lead-out position B11 is related to the number and arrangement period of the multiple first signal lines traversed by the reference line segment XD corresponding to that first lead-out position B11. The arrangement period of the first signal lines 161 is equal to the sum of the width of the first signal line 161 and the gap width between two adjacent first signal lines 161. Therefore, the widest point of the first signal line arrangement area B10 is the position where the corresponding reference line segment traverses the largest number of first signal lines. The width at other positions of the first signal line arrangement area B10 is related to the number of first signal lines traversed by the reference line segment XD corresponding to that position.

[0130] In one specific embodiment, the first reference lead-out position B111 is set as the first lead-out position B11 closest to the maximum width of the first signal line arrangement area B10, and the width of the first signal line arrangement area B10 gradually decreases on both sides of the maximum width of the first signal line arrangement area B10.

[0131] Figure 5C This is a structural diagram of a display panel according to some embodiments.

[0132] Please see Figure 5C The arrangement period P1 of pixels S in the first direction X can be understood as the distance between the same positions of two adjacent pixels S in the first direction X. The same position of two adjacent pixels S can be understood as the same position that each of the two pixels S has, for example, it can be the center of pixel S, or the center of the left sub-pixel S0 in pixel S, or the lower left corner of the left sub-pixel S0 in pixel S, or the lower left corner of the pixel electrode of the left sub-pixel S0 in pixel S.

[0133] For a liquid crystal display panel, the width D of a sub-pixel S0 in the first direction X is... sub1It refers to the width of the pixel electrode corresponding to a sub-pixel S0 in the first direction X.

[0134] For display panels that use electroluminescence as their display principle (such as OLED, QLED, or QD-OLED), the width D of a sub-pixel S0 in the first direction X is... sub1 It can refer to the width of the electroluminescent material corresponding to a sub-pixel S0 in the first direction X.

[0135] The following example uses a liquid crystal display panel to illustrate the width of a pixel S in the first direction X.

[0136] Please see Figure 5C A sub-pixel S0 includes a pixel electrode 115 and a common electrode 116. The pixel electrode 115 can be comb-shaped, and the common electrode 116 can be continuously disposed across the entire layer or correspond one-to-one with the pixel electrode 115. The common electrode 116 can be located on the same substrate as the pixel electrode 115, or the pixel electrodes 115 can be located on different substrates separated by the liquid crystal layers. A pixel S includes three sub-pixels S0, therefore, a pixel S includes three pixel electrodes 115. Figure 5C As shown, the arrangement period P1 of a pixel S in the first direction X is defined using the lower left corner of the pixel electrode 115 of the sub-pixel S0 closest to the left in pixel S. The width D of a sub-pixel S0 in the first direction X is... sub1 The maximum width of the pixel electrode 115 of sub-pixel S0 in the first direction X is defined. Specifically, as... Figure 5C As shown, a pixel S can include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B; it should be noted that the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B can have different values ​​of D. sub1 .

[0137] Figure 6 for Figure 5A A magnified view of a portion at point D. Among them, in... Figure 6 , Figure 7 , Figure 9A , Figure 9B , Figure 10 and Figure 11In the diagram, for ease of illustration, only a portion of the first signal line 161 is shown; the remaining portion is omitted. The “…” in the first signal line arrangement area B10 indicates the omitted first signal line 161. The extension direction, arrangement, and lead-out position of the first signal line 161 indicated by “…” are consistent with the characteristics of the first signal line 161 shown in the diagram. Similarly, for ease of illustration, only a portion of the second signal line 171 is shown; the remaining portion is omitted. The “…” in the second signal line arrangement area B20 indicates the omitted second signal line 171. The extension direction, arrangement, and lead-out position of the second signal line 171 indicated by “…” are consistent with the characteristics of the second signal line 171 shown in the diagram. Please refer to… Figure 6 The at least partially continuous distribution of first target lead-out positions B112 (e.g., N first target lead-out positions B112) can be divided into one or more groups of first target lead-out positions BX112. Each group of first target lead-out positions BX112 may include one or more first target lead-out positions B112, and correspondingly, one or more first signal lines 161 may be led out from one group of first target lead-out positions BX112. The one or more first lead-out lines 162 led out from one group of first target lead-out positions BX112 are defined as: a group of first lead-out lines X162.

[0138] In one specific embodiment, a group of first target extraction positions BX112 includes one first target extraction position B112, that is, each first target extraction position B112 constitutes a separate group. At this time, the distance between the first target extraction positions B112 can be equal, or the distance between the first target extraction positions B112 does not have a periodic distribution difference.

[0139] In one specific embodiment, a group of first target extraction positions BX112 includes multiple first target extraction positions B112. The distance between adjacent first target extraction positions B112 in a group of first target extraction positions BX112 is significantly smaller than the distance between a first target extraction position B112 within the group and a first target extraction position B112 outside the group. Alternatively, the distance between the first target extraction positions B112 in each group of first target extraction positions BX112 is a first distance, and the closest distance between a first target extraction position B112 within the group and a first target extraction position B112 outside the group is a second distance. The first distance is smaller than the second distance.

[0140] When a set of first target extraction positions BX112 includes multiple first target extraction positions B112, the number of first target extraction positions B112 in a set of first target extraction positions BX112 can be two, three, four or more, which will not be listed here.

[0141] Figure 7 for Figure 5A Another enlarged view of a section at point D.

[0142] like Figure 7 As shown, in the case where each group of first target lead-out positions B112 includes only one first target lead-out position B112, the at least partially continuously distributed first target lead-out positions B112 are arranged at equal intervals, each first lead-out line 162 is led out from one first lead-out position B11, and multiple first lead-out lines 162 are arranged at equal intervals. Figure 6 As shown, in each group of first target lead-out positions BX112, there are three first target lead-out positions B112. These three first target lead-out positions B112 are close to each other, and the three first lead-out lines 162 corresponding to the three first target lead-out positions B112 are close to each other. Please refer to... Figure 6 In this case, the first signal line arrangement area B10 includes multiple first signal lines 161 that are equally spaced and extend in the same direction, while the at least partially continuous first target lead-out positions B112 are not equally spaced.

[0143] Please see Figure 6 In some examples, a set of first target lead-out positions BX112 includes multiple first target lead-out positions B112. In this case, the distance between the closest first target lead-out positions B112 in two adjacent sets of first target lead-out positions BX112 is greater than the distance between two adjacent first target lead-out positions B112 within a set of first target lead-out positions BX112. For example, multiple first lead-out lines 162 led out from a set of first target lead-out positions BX112 can be connected to multiple data lines DT electrically connected to multiple sub-pixels S0 in a pixel S. For example, a pixel S includes three sub-pixels, and correspondingly, a set of first target lead-out positions BX112 includes three first target lead-out positions B112. One data line DT is electrically connected to a column of sub-pixels S0.

[0144] In one specific embodiment, k first target lead-out positions B112 are provided in the area covered by the orthographic projection of the width interval of a pixel S in the second direction Y. Specifically, in the first direction X, k first target lead-out positions B112 are provided in the first signal line arrangement area B10 for each width interval of a pixel S. These k first target lead-out positions B112 can be set to belong to the same group of first target lead-out positions BX112. The width interval of a pixel S refers to the interval spanned by one arrangement period P1 of pixel S in the first direction X. Specifically, k can be the number of sub-pixels S0 in a pixel S. It should be noted that the term "through" is used repeatedly in this disclosure. In this disclosure, "through" refers to the overlap of the orthographic projections of two structures in a specified direction, or the orthographic projection of a structure in a specified direction being located within a specified length interval. For example, if the first signal line arrangement area B10 passes through the width interval of a pixel S in the first direction X, it means that the projection of the width interval of a pixel S in the second direction Y covers the first signal line arrangement area B10. For example, if the first signal line arrangement area B10 passes through a column of pixels S in the first direction X, it means that the orthogonal projection of the column of pixels S in the second direction Y covers the first signal line arrangement area B10.

[0145] For example, one pixel contains three sub-pixels, and k is 3. (e.g.) Figure 6 As shown, a set of first target lead-out positions B112 includes three first target lead-out positions B112. That is, in at least partially continuous distribution of first target lead-out positions B112 (e.g., N first target lead-out positions B112), every three first target lead-out positions B112 form a group, and a group of first target lead-out positions BX112 are close to each other. The three first target lead-out positions B112 are almost at the same location. In other words, when the three first signal lines 161 are led out at almost the same location, every time they pass through a width interval of one pixel S, a group of first signal lines X161 is led out from the first signal line arrangement area B10. That is, three first signal lines 161 are led out from the first signal line arrangement area B10 through the first lead-out line 162, thus reducing the number of first signal lines 161 in the first signal line arrangement area B10 by three. Among them, on one side of the first reference lead-out position B111, for every first signal line 161 reduced, the width of the first signal line arrangement area B10 will decrease by W. data +S data .

[0146] For example, after each column of pixels S, a set of first signal lines X161 is drawn out from the first signal line arrangement area B10, and the number of first signal lines X161 in each set of first signal lines X161 is 3.

[0147] Wherein, Δ1 / P1 represents the number of columns of pixels S that the first signal line arrangement area B10, located between the first target lead-out position B112 and the first reference lead-out position B111, passes through in the first direction X.

[0148] Among them, a column of pixels S includes k columns of sub-pixels S0. Each column of sub-pixels S0 is electrically connected to a data line DT, and the data line DT corresponds one-to-one with the first signal line 161. Therefore, in the area between the first target lead-out position B112 and the first reference lead-out position B111, there are k·Δ1 / P1 first signal lines 161 led out from the first signal line arrangement area B10 through the first lead-out line 162. That is, k·Δ1 / P1 first lead-out positions B11 are set in this area.

[0149] In some examples, where a set of first target lead-out positions B112 includes multiple first target lead-out positions B112, portions of the multiple first lead-out lines 162 corresponding to the multiple first target lead-out positions B112 may extend along the second direction Y; and the first lead-out lines 162 and their electrically connected data lines DT may not be on the same straight line. For example, as... Figure 6 As shown by the dotted circle, at the point where the first lead 162 and the data line DT meet, the first lead 162 can be bent to achieve the connection. It can be understood that at this time, the first target lead position B112 corresponding to the first lead 162 is not on the same straight line as the data line DT connected to the first lead 162.

[0150] Specifically, for each first signal line 161 led out, the width of the first signal line arrangement area B10 will decrease (W). data +S data Therefore, after drawing out k·Δ1 / P1 first signal lines 161, the width of the first signal line arrangement area B10 will be reduced by (kΔ1 / P1)(W). data +S data ).

[0151] By setting both the first signal line arrangement area B10 and the second signal line arrangement area B20 to be elongated strips, including mutually close but non-overlapping boundaries with the same extension direction, and by ensuring that among the at least partially continuously distributed first target lead-out positions B112 other than the first reference lead-out position B111, the width b of the first signal line arrangement area B10 corresponding to each first target lead-out position B112 satisfies b0-[int(kΔ1 / P1)](W data +S data )≤b≤b0-[int(kΔ1 / P1)-1](W data +S dataWhen implementing this design, the orderly lead-out of the first signal line 161 can be achieved while ensuring a narrow bezel on the display panel. This avoids unnecessary bridging of the first signal line 161 with other signal lines, thereby reducing signal line overlap capacitance and improving the display effect of the display panel. Optionally, the width of the first signal line arrangement area B10 corresponding to the area between the first target lead-out position B112 and the first reference lead-out position B111 is also designed to satisfy this formula. This can further standardize the shape of the first signal line arrangement area B10 between the first lead-out positions B11, ensuring the orderly extension of the first signal line arrangement area B10 and improving the reliability of the display panel.

[0152] In one specific embodiment, the first target lead-out position B112 may be located in a group of first target lead-out positions BX112. The number of first target lead-out positions B112 in a group of first target lead-out positions BX112 may be three. The first lead-out lines 162 corresponding to the three first target lead-out positions B112 are electrically connected to three data lines DT respectively. The three data lines DT are electrically connected to three sub-pixels S0 respectively. The three sub-pixels are located in the same pixel S.

[0153] In one specific embodiment, the extension directions of at least a portion of the first signal line arrangement area B10 and at least a portion of the second signal line arrangement area B20 are different from both the first direction X and the second direction Y. For example, the first direction X and the second direction Y are perpendicular. That is, the extension directions of at least a portion of the first signal line arrangement area B10 and at least a portion of the second signal line arrangement area B20 are different from the row extension direction of the sub-pixel S0; the extension directions of at least a portion of the first signal line arrangement area B10 and at least a portion of the second signal line arrangement area B20 are different from the column extension direction of the sub-pixel S0. This embodiment ensures that a narrower border can still be achieved when the outer contour of the display area AA is not rectangular. Specifically, the outer contour of the display area AA can be a non-rectangular quadrilateral, pentagon, hexagon, octagon, ellipse, circle, etc., or it can be an irregular shape. For example, when the outer contour of the display area AA is an octagon, the octagon can be a rectangle with its four corners cut off. That is, four sides of the octagon are parallel to the row extension direction or column extension direction of the sub-pixel S0, and the extension directions of at least a portion of the first signal line arrangement area B10 and at least a portion of the second signal line arrangement area B20 are parallel to the extension direction of at least one of the other four sides of the octagon. For example, when the outer contour of the display area AA is elliptical, at least a portion of the first signal line arrangement area B10 or at least a portion of the second signal line arrangement area B20 extends conformally to the outer contour of the display area AA. In a specific embodiment, refer to... Figure 3 and Figure 4The outer contour of the display area AA includes an arc shape, and at least a portion of the first signal line arrangement area B10 and at least a portion of the second signal line arrangement area B20 can be distributed on the side of the arc-shaped display area AA away from the center of the display area AA.

[0154] Please see Figure 7 In other examples, among the at least partially continuous first target lead-out positions B112, a group of first target lead-out positions BX112 may include only one first target lead-out position B112, in which case it can also be considered that the first target lead-out positions B112 are not grouped. In this case, for each column of pixels S passed in the first direction X, k first target lead-out positions B112 are provided in the first signal line arrangement area B10. In the above embodiment, for each column of sub-pixels S0 passed, one first target lead-out position B112 is provided in the first signal line arrangement area B10.

[0155] For example, in the at least partially continuous distribution of the first target lead-out positions B112, any two adjacent first target lead-out positions B112 are equidistant in the first direction X.

[0156] For example, in the at least partially continuous first target extraction positions B112, the distance between two adjacent first target extraction positions B112 in the first direction X is equal to the arrangement period of sub-pixels S0 in the first direction X. It should be noted that the arrangement period of sub-pixels S0 in the first direction X can be greater than the width Dsub1 of one sub-pixel S0 in the first direction X (e.g., ...). Figure 5C As shown in the diagram, necessary gaps are left between sub-pixels S0 so that signal lines (e.g., data lines DL) can pass through. For example, the sub-pixels S0 have equal arrangement periods in the first direction X.

[0157] In some examples, when a first target lead-out position B112 is included in a set of first target lead-out positions BX112, the first lead-out line 162 may extend along the second direction Y and be on the same straight line as the data line DT connected to the first lead-out line 162; for example, the first target lead-out position B112 corresponding to the first lead-out line 162 is also located on the straight line of the data line DT connected to the first lead-out line 162.

[0158] The wiring in the first signal line layout area B10 has been described above. Next, the wiring in the second signal line layout area B20 will be described.

[0159] Please see Figure 7The second signal line arrangement area B20 includes multiple second signal lines 171 extending in the same direction. The boundary of the second signal line arrangement area B20 near the display area AA includes multiple second lead-out positions B22. Multiple second lead-out lines 172 are led out from the multiple second lead-out positions B22 one by one and are electrically connected to the multiple second signal lines 171 one by one. The second lead-out lines 172 are electrically connected to the gate line GT.

[0160] The multiple second signal lines 171 extend in the same direction, which can be understood as the multiple second signal lines 171 extending parallel to each other in a conformal manner. Preferably, the second signal lines 171 have the same width, and the spacing between any two second signal lines 171 is the same.

[0161] Among them, a second signal line 171 is connected to a gate line GT (e.g., a second lead 172) via a second lead 172. Figure 2A (As shown) Electrical connection.

[0162] Figure 8 for Figure 4 A magnified view of a section at point E in the middle.

[0163] Please see Figure 8 In the surrounding area BB, there are also multiple second lead-in lines 173. The multiple second lead-in lines 173 are located on the side of the second signal line arrangement area B20 away from the display area AA. The multiple second lead-in lines 173 correspond one-to-one with the multiple second signal lines 171 and are electrically connected.

[0164] In some embodiments, at the connection point between the second lead-in line 173 and the second signal line 171, the extension directions of the second lead-in line 173 and the second signal line 171 are different; at the connection point between the second signal line 171 and the second lead-out line 172, the extension directions of the second signal line 171 and the second lead-out line 172 are different. That is, there may be a clear boundary (e.g., a bend) between the second lead-in line 173 and the second signal line 171, and there may be a clear boundary (e.g., a bend) between the second signal line 171 and the second lead-out line 172. It is understood that the clear boundary is only a clear geometric division and does not necessarily represent that different conductor segments are manufactured by different processes. That is, at least two of the second lead-in line 173, the second signal line 171, and the second lead-out line 172 can be manufactured by a single process. In some examples, the second lead-in line 173 may also include one or more trace segments. For example, the second lead-in line 173 includes two trace segments. In some examples, the second lead-in line 173 may also include one or more traces; for example, the second lead-in line 173 includes two traces.

[0165] In one specific embodiment, a second signal line 171 is electrically connected to a gate line GT via a second lead-out line 172, and the other end of the second signal line 171 is connected to a second lead-in line 173.

[0166] In some examples, the end of the second lead-in line 173 away from the second signal line 171 can be electrically connected to the shift register unit, so that the shift register unit can output a gate drive signal to the second lead-in line 173, and the gate drive signal is transmitted to the gate line GT in sequence through the second lead-in line 173 and the second lead-out line 172.

[0167] In other examples, the peripheral region BB may be provided with multiple gate line bonding pins, which are located on the side away from the second signal line arrangement region B20 where the multiple second lead-in lines 173 are located. These gate line bonding pins are used for electrical connection with the gate driver chip, which outputs a gate drive signal. The gate drive signal is transmitted to the gate line GT sequentially through the gate line bonding pins, the second lead-in lines 173, the second signal lines 171, and the second lead-out lines 172. For example, the second lead-in lines 173, the second signal lines 171, and the second lead-out lines 172 are disposed on the source / drain metal layer 114 (e.g., ...). Figure 1 As shown in the figure, the second lead-in line 173, the second signal line 171 and the second lead-out line 172 are set on the same layer as the data line DT.

[0168] Please refer to Figure 7 At least one first lead-out position B11 and at least one second lead-out position B22 are arranged alternately in the first direction X. It should be noted that the alternating arrangement of m first lead-out positions B11 and n second lead-out positions B22 in the first direction X can be understood as first arranging m first lead-out positions B11, then arranging n second lead-out positions B22, then arranging m more first lead-out positions B11, then arranging n more second lead-out positions, and so on. For example, Figure 7 The diagram shows three first lead-out positions B11 and one second lead-out position B22 arranged alternately in the first direction X.

[0169] In some examples, a first lead-out position B11 and multiple second lead-out positions B22 can be arranged alternately in the first direction X. In this case, multiple second lead-out positions B22 are provided between two adjacent first lead-out positions B11.

[0170] In other examples, multiple first lead-out positions B11 and one second lead-out position B22 can be arranged alternately in the first direction X. In this case, multiple first lead-out positions B11 are provided between two adjacent second lead-out positions B22.

[0171] In other examples, multiple first lead-out positions B11 and multiple second lead-out positions B22 can be arranged alternately in the first direction X.

[0172] The first signal line 161 is located in the first signal line arrangement area B10, while the second signal line 171 is located in the second signal line arrangement area B20. Therefore, the first signal line 161 and the second signal line 171 do not overlap. If the two signal lines overlap, a capacitance will be generated between them, thus forming a load. Since the first signal line 161 and the second signal line 171 do not overlap, the load on the first signal line 161 and the second signal line 171 can be kept relatively small.

[0173] Furthermore, in some examples, the film layer containing the second signal line 171 is located on the side of the film layer containing the first signal line 161 that is away from the first substrate 111. If the first signal line 161 and the second signal line 171 overlap, the second signal line 171 will experience a step-up phenomenon when passing the first signal line 161. In this case, the second signal line 171 may break due to the step difference. In addition, an insulating layer is provided between the first signal line 161 and the second signal line 171. Therefore, the insulating layer will experience a step-up phenomenon, which may cause a partial area of ​​the first signal line 161 to be exposed. When the second signal line 171 is provided, it will cause the second signal line 171 to be short-circuited with the first signal line 161, thereby causing a short circuit between the second signal line 171 and the first signal line 161. Therefore, in some embodiments of this disclosure, since there is no overlap between the first signal line 161 and the second signal line 171, the phenomenon of signal line breakage and short circuit between the first signal line 161 and the second signal line 171 can be avoided.

[0174] In some embodiments, the first direction X and the second direction Y are perpendicular, which facilitates the arrangement of sub-pixels S0.

[0175] In some embodiments, for the at least partially continuously distributed first target lead-out positions B112, the width b1 of the first signal line arrangement area B10 corresponding to the first target lead-out position B112, which has the same color as the sub-pixel S0 electrically connected to the first reference data line DTm, satisfies: b1=b0-[int(kΔ1 / P1)](W data +S data ).

[0176] Specifically, multiple sub-pixels S0 in a column of sub-pixels S0 have the same color. In this case, k-1 sub-pixels S0 are spaced apart between two adjacent sub-pixels S0 with the same color in the first direction X.

[0177] Specifically, the first signal line arrangement area B10 at the first target lead-out position B112 has 161 fewer first signal lines (int(k·Δ1 / P1)) than at the first reference lead-out position B111. Therefore, the width of the first signal line arrangement area B10 at the first target lead-out position B112 is reduced by [int(kΔ1 / P1)](W) compared to the width of the first signal line arrangement area B10 at the first reference lead-out position B111. data +S data Therefore, the width b1 of the first signal line arrangement area B10 corresponding to the first target lead-out position B112 satisfies: b1=b0-[int(kΔ1 / P1)](W data +S data This is to further ensure the orderly lead-out of the first lead-out line 162 and reduce the signal line overlap capacitance.

[0178] In some examples, the above formula: b0-[int(kΔ1 / P1)](W data +S data )≤b≤b0-[int(kΔ1 / P1)-1](W data +S data This applies to the portion of the first signal line arrangement area B10 that is far from the display area AA and does not have a third signal line arrangement area B30.

[0179] In some examples, the above formula b1=b0-[int(kΔ1 / P1)](W data +S data This applies to the portion of the first signal line arrangement area B10 that is far from the display area AA and does not have a third signal line arrangement area B30.

[0180] Please refer to it again. Figure 6 In some embodiments, the at least partially continuously distributed first target lead-out positions B112 include three continuously distributed first target lead-out positions B112. Each of the three continuously distributed first target lead-out positions B112 is electrically connected to one of the three sub-pixels S0 of a pixel S. The total width of the three first lead-out lines 162 corresponding to the three continuously distributed first target lead-out positions B112 is less than or equal to the arrangement period P of the sub-pixel S0 in the first direction X. sub1 .

[0181] It should be noted that the overall width of the multiple first leads 162 can be understood as the sum of the widths of the multiple first leads 162 and the sum of the widths of the gaps between all adjacent first leads 162. For example, the overall width of the three first leads 162 can be understood as follows: the three first leads 162, taken perpendicular to the direction in which they extend, result in three segments arranged in sequence, namely two segments located on both sides and one segment located in the middle of the two segments; the two segments located on both sides each have an endpoint relative to the entire three segments, and the distance between the two endpoints is the overall width of the three first leads 162.

[0182] It should be noted that the arrangement period P of sub-pixel S0 in the first direction X sub1 This can be understood as the distance between two adjacent sub-pixels S0 at the same position within a pixel S along the first direction X. The same position between two adjacent pixels S0 can be understood as the common location shared by the two sub-pixels S0, such as the center of sub-pixels S0, or the lower right corner of sub-pixels S0 (e.g.,...). Figure 5C (As shown).

[0183] Among them, the total width of the three first lead-out lines 162 corresponding to the three consecutively distributed first target lead-out positions B112 is less than or equal to the arrangement period P of a sub-pixel S0 in the first direction X. sub1 At this time, the three consecutively distributed first target lead-out positions B112 can be a set of first target lead-out positions B112. Furthermore, the total width of the three first lead-out lines 162 corresponding to the three consecutively distributed first target lead-out positions B112 is less than or equal to the arrangement period P of a sub-pixel S0 in the first direction X. sub1 Thus, when etching the lead-out lines, the arrangement density of the three first lead-out lines 162 can be as close as possible to the arrangement density of the first signal line 161 to ensure that the first lead-out lines 162 have sufficient linewidth.

[0184] The following describes the width of the second signal line arrangement area B20.

[0185] Figure 9A This is a structural diagram of a display panel according to some embodiments.

[0186] Please see Figure 9A In some embodiments, the plurality of second lead-out positions B22 includes a second reference lead-out position B221, the second reference lead-out line 172m is led out from the second reference lead-out position B221 and electrically connected to the second reference gate line; the width of the second signal line arrangement area B20 corresponding to the second reference lead-out position B221 is c0 (e.g., Figure 8(As shown); among the second target lead-out positions B222 that are at least partially and continuously distributed except for the second reference lead-out position B221, the width c of the second signal line arrangement area B20 corresponding to each second target lead-out position B222 satisfies: c0-[int(kΔ2 / P1)+1](W gate +S gate )≤c≤c0-[int(kΔ2 / P1)-1](W gate +S gate ).

[0187] Where Δ2 is the distance between the second target launch position and the second reference launch position B221 in the first direction X, W gate S is the width of the second signal line 171. gate The spacing of the second signal lines 171. Specifically, in the second signal line arrangement area B20 corresponding to the second target lead-out positions B222 that are at least partially continuously distributed from the second reference lead-out position B221 to the second signal line arrangement area B20, the width of the second signal lines 171 is the same; the spacing of the second signal lines 171 is the same.

[0188] Among the at least partially continuous second target lead-out positions B222 other than the second reference lead-out position B221, the width c of the second signal line arrangement area B20 corresponding to each second target lead-out position B222 can be defined as: the dimension of the second signal line arrangement area B20 along the direction perpendicular to the extension direction of the second signal line 171 closest to the display area AA at that position. It should be noted that at each second target lead-out position B222, the width c of the second signal line arrangement area B20 includes the width of the second signal line 171 extending from that second target lead-out position B222.

[0189] It should be noted that the second reference lead-out position B221 is one of the second lead-out positions B22, and its position may not be specifically defined; in some embodiments, the second reference lead-out position B221 is the second lead-out position B22 closest to the widest point of the second signal line arrangement area B20; the width of the second signal line arrangement area B20 gradually decreases on both sides of the widest point of the second signal line arrangement area B20.

[0190] Since multiple second signal lines 171 are arranged side-by-side and extend in the same direction within the second signal line arrangement area B20, the width of the second signal line arrangement area B20 corresponding to each second lead-out position B22 is related to the number and arrangement period of the second signal lines 171 included at that second lead-out position B22. Specifically, the arrangement period of the second signal lines 171 is equal to the sum of the width of each second signal line 171 and the spacing between two adjacent second signal lines 171. Therefore, the widest point of the second signal line arrangement area B20 is the point containing the largest number of second signal lines 171.

[0191] It should be noted that the at least partially continuously distributed second target lead-out positions B222 may include one or more sets of second target lead-out positions BX222. Each set of second target lead-out positions BX222 may include one or more second target lead-out positions B222. Correspondingly, one or more second signal lines 171 may each be led out from a set of second target lead-out positions BX222 via second lead-out lines 172. One or more second lead-out lines 172 led out from a set of second target lead-out positions BX222 are defined as: a set of second lead-out lines X172.

[0192] It should be noted that the interpretation of "group" in "one or more groups of second target extraction positions BX222" is the same as the interpretation of "group" in "one or more groups of first target extraction positions BX112" mentioned above, and will not be repeated here.

[0193] When a set of second target retrieval positions BX222 includes multiple second target retrieval positions B222, the number of second target retrieval positions B222 in a set of second target retrieval positions BX222 can be two, three, four or more, which will not be listed here.

[0194] Figure 9B This is a structural diagram of a display panel according to some embodiments.

[0195] In some examples, such as Figure 9B As shown, when each group of second target lead-out positions BX222 includes only one second target lead-out position B222, each second target lead-out position BX222 can be considered as forming a separate group. In this case, the at least partially continuously distributed second target lead-out positions B222 can be arranged at equal intervals, that is, the distance between the second target lead-out positions B222 can be equal. This allows each second lead-out line 172 to lead out from one second lead-out position B22, and multiple second lead-out lines 172 to be arranged at equal intervals. In other examples, such as... Figure 9AAs shown, when each group of second target lead-out positions BX222 includes multiple second target lead-out positions B222, these multiple second target lead-out positions B222 are close to each other, and the multiple second lead-out lines 172 corresponding to the multiple second target lead-out positions B222 are close to each other. Please refer to Figure 9A In this case, the second signal line arrangement area B20 includes multiple second signal lines 171 that are equally spaced and extend in the same direction, while the at least partially continuous second target lead-out positions B222 are not equally spaced.

[0196] Please see Figure 9A In some examples, a set of second target lead-out positions BX222 includes multiple second target lead-out positions B222. In this case, the distance between the closest second target lead-out positions B222 in two adjacent sets of second target lead-out positions BX222 is greater than the distance between two adjacent second target lead-out positions B222 in a set of second target lead-out positions BX222. For example, multiple second lead-out lines 172 led out from a set of second target lead-out positions BX222 are respectively connected to multiple gate lines GT, and one gate line GT is electrically connected to a row of sub-pixels S0.

[0197] In some embodiments, the direction in which the second lead 172 is drawn from the second lead position B22 is the same as or approximately the same as the direction in which the first lead 162 is drawn from the first lead position B11. When the deviation in direction is within 5°, it can be understood that the directions are approximately the same. Having the second lead 172 drawn from the second lead position B22 in the same or approximately the same direction as the first lead 162 drawn from the first lead position B11 can minimize the overlap between the first lead 162 and the second lead 172, thereby reducing the overlap capacitance.

[0198] In some embodiments, the direction in which the second lead 172 is drawn from the second target lead position B222 is perpendicular or substantially perpendicular to the extension direction of the gate line. When the angle between the direction of the second lead 172 drawn from the second target lead position B222 and the gate line GT is within 85°-95°, it can be understood that the direction is substantially perpendicular.

[0199] In some embodiments, the second lead 172 can be directly connected to the gate line GT, or it can be indirectly connected via other signal leads.

[0200] For example, the second lead 172 can be led out from the second target lead-out position B222 and electrically connected to the gate line GT by bending and / or overlapping. Alternatively, the second lead 172 can be led out from the second target lead-out position B222 and extend in a straight line until it reaches one side of the corresponding gate line GT, and then electrically connected to the gate line GT by bending and / or overlapping. Or, the second lead 172 can be connected to the gate line GT via a via.

[0201] For example, an auxiliary lead is also included between the second lead-out line 172 and the gate line GT. One end of the auxiliary lead is electrically connected to the second lead-out line 172, and the other end is electrically connected to the gate line GT. The auxiliary lead and the gate line GT are connected via a via. Specifically, the auxiliary lead can be configured to extend between two adjacent columns of sub-pixels S0. Specifically, one auxiliary lead can be configured to bridge one or more gate lines GT and be electrically connected to one gate line GT. The auxiliary lead bridging the gate line GT is insulated from the gate line GT. Specifically, the electrical connection between the auxiliary lead and the bridging gate line GT can be achieved through a via passing through the insulating layer. The auxiliary lead is electrically connected to the second lead 172, which can be achieved through a via passing through the insulating layer or through a direct electrical connection. A direct electrical connection between the auxiliary lead and the second lead 172 can be understood as the auxiliary lead and the second lead 172 extending continuously and dividing the area on the array substrate. For example, the second lead 172 located between two adjacent columns of pixels S (or two adjacent columns of sub-pixels S0) is defined as an auxiliary lead. Specifically, the auxiliary lead can be a continuously extending lead or can include multiple lead segments, with the first and last segments electrically connected. Specifically, the auxiliary lead can be configured to extend between two adjacent columns of pixels S. In one specific embodiment, multiple auxiliary leads are connected one-to-one with multiple second lead 172s, and the multiple auxiliary leads are collectively arranged extending between two adjacent columns of sub-pixels S0. In another specific embodiment, multiple auxiliary leads are connected one-to-one with multiple second lead 172s, and the multiple auxiliary leads are collectively arranged extending between two adjacent columns of pixels S. In one specific embodiment, multiple auxiliary leads are jointly arranged between two adjacent columns of pixels S (or two adjacent columns of sub-pixels S0), and multiple second leads 172 electrically connected to each of the multiple auxiliary leads form a set of second leads X172. When multiple auxiliary leads connected to each of the set of second leads X172 are jointly arranged between two adjacent columns of pixels S, the set of second leads X172 can be aligned with the two adjacent columns of pixels S. For example, the straight line of the center extension of the set of second leads X172 passes between the two adjacent columns of pixels S. The second target lead-out position B222 in the set of second target lead-out positions BX222 is electrically connected to the second leads 172 in the set of second leads X172. The straight line of the center extension of the set of second leads X172 passes through the center of the set of second target lead-out positions BX222 corresponding to the set of second leads X172. This design avoids signal line redundancy and unnecessary overlap.

[0202] For example, in at least a portion of the second signal line arrangement area B20, m second lead-out positions B22 are provided in the area covered by the orthographic projection of the width interval of a pixel S in the second direction Y. Specifically, in the first direction X, m second target lead-out positions B222 are provided in the second signal line arrangement area B20 for each width interval of a pixel S, and the above m second target lead-out positions B222 belong to the same group of second target lead-out positions BX222. Here, the width interval of pixel S refers to the interval spanned by one arrangement period P1 of pixel S in the first direction X. It should be noted that the term "through" is used multiple times in this disclosure. In this disclosure, "through" means that the orthographic projections of two structures overlap in a specified direction, or that the orthographic projection of a structure in a specified direction is located within a specified length interval. For example, if the second signal line arrangement area B20 passes through the width interval of a pixel S, it means that the width interval of a pixel S covers the projection of the second signal line arrangement area B20 in the second direction Y. For example, if the second signal line arrangement area B20 passes through a column of pixels S in the first direction X, it means that the orthographic projection of the column of pixels S in the second direction Y covers the second signal line arrangement area B20. Here, m can be a positive integer.

[0203] like Figure 9A As shown, for the continuously distributed second target exit positions B222, every three second target exit positions B222 form a group, and every time the width of a pixel S is crossed, a group of second signal lines X171 is led out from the second signal line arrangement area B20 through a group of second exit lines X172. Specifically, for each reduction of one second signal line 171, the width of the second signal line arrangement area B20 decreases by W. gate +S gate .

[0204] Wherein, Δ2 / P1 represents the number of width intervals of pixels S that the second signal line arrangement area B20, located between the second target lead-out position B222 and the second reference lead-out position B221, passes through in the first direction X.

[0205] In some examples, where a set of second target lead-out positions BX222 includes multiple second target lead-out positions B222, portions of the multiple second lead-out lines 172 corresponding to the multiple second target lead-out positions B222 can extend along the second direction Y. Since each gate line GT connects to a row of sub-pixels S0, and the gate line GT extends along the first direction X, the second lead-out line 172 and the gate line GT are not on the same straight line. For example, as shown... Figure 9A As shown, the second lead 172 needs to be bent at certain locations to connect with the gate line GT.

[0206] Specifically, for each second signal line 171 that is led out, the width of the second signal line arrangement area B20 will decrease by W. gate +S gate Therefore, after drawing out k·Δ2 / P1 second signal lines 171, the width of the second signal line arrangement area B20 will decrease by k(Δ2 / P1)(W). gate +S gate ).

[0207] By setting both the first signal line arrangement area B10 and the second signal line arrangement area B20 to be elongated strips, including mutually close but non-overlapping boundaries with the same extension direction, and by ensuring that in the at least partially continuous distribution of the second target lead-out positions B222 (excluding the second reference lead-out position B221), the width b of the first signal line arrangement area B10 corresponding to each first target lead-out position B112 satisfies c0-[int(kΔ2 / P1)+1](W gate +S gate )≤c≤c0-[int(kΔ2 / P1)-1](W gate +S gate When implementing this design, the orderly routing of the second signal line 171 can be achieved while ensuring a narrow bezel on the display panel. This avoids unnecessary bridging between the second signal line 171 and other signal lines, thereby reducing signal line overlap capacitance and improving the display effect of the display panel. Optionally, the width of the first signal line arrangement area B10 corresponding to the area between the first target routing position B112 and the first reference routing position B111 is also designed to satisfy this formula. This can further standardize the shape of the second signal line arrangement area B20 between the second routing positions B22, ensuring the orderly extension of the second signal line arrangement area B20 and improving the reliability of the display panel.

[0208] Please see Figure 9B In other examples, within the at least partially continuous distribution of the second target lead-out positions B222, a group of second target lead-out positions BX222 may include only one second target lead-out position B222, meaning the second target lead-out positions B222 can be considered ungrouped; specifically, the second target lead-out positions B222 can be evenly distributed. In this case, for every pixel S width interval, k second target lead-out positions B222 are set in the second signal line arrangement area B20.

[0209] For example, in the at least partially continuous distribution of the second target lead-out positions B222, any two adjacent second target lead-out positions B222 are equidistant in the first direction X.

[0210] For example, in the at least partially continuous distribution of the second target extraction positions B222, the distance between two adjacent second target extraction positions B222 in the first direction X is equal to the arrangement period P of the sub-pixel S0 in the first direction X. sub1 .

[0211] Figure 10 This is a structural diagram of a display panel according to some embodiments.

[0212] In some embodiments, such as Figure 10 As shown, the distance D1 between the first reference lead-out position B111 and the second reference lead-out position B221 in the first direction X is less than the arrangement period P1 of one pixel S in the first direction X. In some embodiments, the distance D1 between the first reference lead-out position B111 and the second reference lead-out position B221 in the first direction X is less than the width D of one sub-pixel S0 in the first direction X. sub1 Wherein, the arrangement period P1 of a pixel S in the first direction X and the width D of a sub-pixel S0 in the first direction X are defined. sub1 like Figure 5C As shown.

[0213] The distance between the first reference lead-out position B111 and the second reference lead-out position B221 in the first direction X is less than the arrangement period P1 of one pixel S in the first direction X. This allows the lead-out patterns of the first target lead-out position B112 and the second target lead-out position B222 to be implemented in the same peripheral area, improving the compactness of the peripheral area design and the integration of the display panel design. For example, the first target lead-out position B112 and the second target lead-out position B222 can be alternately distributed in the first direction X. For example, the first target lead-out position group BX112 and the second target lead-out position group BX222 can be alternately distributed in the first direction X. By setting the above-mentioned alternate distribution of target lead-out positions, the overall width of the first signal line arrangement area B10 and the second signal line arrangement area B20 can be further reduced, which is beneficial for the display panel to achieve a narrower bezel. It is understood that the orthographic projections of the first signal line arrangement area B10 and the second signal line arrangement area B20 in the first direction X overlap.

[0214] In some embodiments, in at least partially continuous first target lead-out positions B112, m second target lead-out positions B222 are respectively arranged on both sides of every three first target lead-out positions B112, where m is one of the three values ​​of 4, 5, and 6; for example, the m second target lead-out positions BX222 are composed of a set of second target lead-out positions BX222. At the position where the first target lead-out positions B112 are led out, the second target lead-out positions B222 also have a high density, which can make the total width of the first signal line arrangement area B10 and the second signal line arrangement area B20 smaller or rapidly smaller, which is beneficial to improving the display appearance.

[0215] In some embodiments, please refer to Figure 6 A set of first target lead-out positions BX112 may include three first target lead-out positions B112. A set of first lead-out lines X162 are led out from a set of first target lead-out positions BX112. Therefore, a set of first lead-out lines X162 includes three first lead-out lines 162.

[0216] In some embodiments, m is an integer greater than or equal to 3, for example, m is one of 3, 4, 5, and 6; in at least partially continuous first target exit positions B112, m second target exit positions B222 are respectively arranged on both sides of every three first target exit positions B112; the three first target exit positions B112 are arranged at equal intervals, and the m second target exit positions B222 are arranged at equal intervals. This arrangement results in neat wiring and facilitates cabling. For example, as... Figure 9AAs shown, the m second target lead-out positions B222 can belong to a group of second target lead-out positions BX222; and the three first target lead-out positions B112 can belong to a group of second target lead-out positions BX112. For example, the three first lead-out lines 162 corresponding to the three first target lead-out positions are arranged at equal intervals, and the m second lead-out lines 172 corresponding to the m second target lead-out positions B222 are arranged at equal intervals. This arrangement facilitates the electrical connection of the first lead-out lines 162 with the corresponding data lines DT, and facilitates the electrical connection of the second lead-out lines 172 with the corresponding gate lines GT. For example, the spacing between the three first target lead-out positions B112 is greater than the spacing between the m second target lead-out positions B222. Specifically, the spacing between the three first target lead-out positions B112 can be the distance between two adjacent first target lead-out positions B112 in a set of first target lead-out positions BX112; and the spacing between the m second target lead-out positions B222 can be the distance between two adjacent second target lead-out positions B222 in a set of second target lead-out positions BX222. In this way, the second lead-out positions B222 in a set of second target lead-out positions BX222 are more concentratedly distributed, which is beneficial to have a larger gap between the first lead-out line 162 and the second lead-out line 172, and reduce the interference of signal transmission on the display effect. Preferably, among the three first target lead-out positions B112, the distance between one of the two outer first target lead-out positions B112 and its nearest second target lead-out position B222 is equal to the distance between the other B112 and its nearest second target lead-out position B222. This helps to make the gap between the first lead-out line 162 and the second lead-out line 172 as large as possible, reducing the interference of signal transmission on the display effect.

[0217] In some embodiments, m is an integer greater than or equal to 3, for example, m is one of 3, 4, 5, or 6; in the at least partially continuous distribution of the first target lead-out positions B112, m second target lead-out positions B222 are respectively arranged on both sides of every three first target lead-out positions B112; three first lead-out lines 162 are respectively led out from the three first target lead-out positions B112, and m second lead-out lines 172 are respectively led out from the m second target lead-out positions B222. The three first lead-out lines 162 are arranged at equal intervals, and the m second lead-out lines 172 are arranged at equal intervals, so that the wiring is neat. For example, the m second lead-out lines 172 can belong to a group of second lead-out lines X172; and the three first lead-out lines 162 can belong to a group of first lead-out lines X162. For example, the three first leads 162 are arranged at equal intervals, and the m second leads 172 are arranged at equal intervals. This arrangement facilitates, for example, the electrical connection between the first leads 162 and the corresponding data line DT, and the electrical connection between the second leads 172 and the corresponding gate line GT. For example, the spacing between the three first leads 162 is greater than the spacing between the m second leads 172. Specifically, the spacing between the three first leads 162 can be the distance between two adjacent first leads 162 in a group of first leads X162; while the spacing between the m second leads 172 can be the distance between two adjacent second leads 172 in a group of second leads X172. Thus, the second leads in a group of second leads X172 are more concentrated, which helps to create a larger gap between the first leads 162 and the second leads 172, reducing interference from signal transmission to the display effect. Furthermore, for example, among the three first leads 162, the distance between one first lead 162 and its nearest second lead 172 is equal to the distance between the other first lead 162 and its nearest second lead 172. This arrangement is beneficial for the uniform arrangement of signal lines and improves the manufacturing yield of the display panel.

[0218] In some embodiments, m is an integer greater than or equal to 3, for example, m is one of 3, 4, 5, and 6; in the at least partially continuous distribution of the first target lead-out positions B112, m second target lead-out positions B222 are respectively arranged on both sides of every three first target lead-out positions B112; three first lead-out lines 162 are respectively led out from the three first target lead-out positions B112, and m second lead-out lines 172 are respectively led out from the m second target lead-out positions B222; the three first target lead-out positions B112 are arranged at equal intervals, the m second target lead-out positions B222 are arranged at equal intervals, and the overall width occupied by the three first target lead-out positions B112 in the first direction X is less than the overall width occupied by the m second target lead-out positions B222 in the first direction X; for example, the overall width occupied by a group of first target lead-out positions B112 in the first direction X is less than the overall width occupied by a group of second target lead-out positions BX222 in the first direction X. This configuration avoids the distance between two adjacent second target lead-out positions B222 being too small, thus ensuring that the uniformity of the distribution of the first lead-out line 162 and the second lead-out line 172 is controlled within an ideal range.

[0219] In some of the embodiments described above, the setting of the second lead-out position B22 is related to the arrangement period of the pixel S in the first direction X, while in other embodiments, the setting of the second lead-out position B22 may also be related to the arrangement period of the pixel S in the second direction Y.

[0220] In some embodiments, reference Figure 8 Among the multiple second lead-out positions B22, there is a second reference lead-out position B221. The second reference signal line 171m is led out from the second reference lead-out position B221 and electrically connected to the second reference gate line. The width of the second signal line arrangement area B20 corresponding to the second reference lead-out position B221 is c0. Among the at least partially continuous second target lead-out positions B222 other than the second reference lead-out position B221, the width c of the second signal line arrangement area B20 corresponding to each first target lead-out position B112 satisfies: c0-[int(Δ3 / P sub2 )+1](W gate +S gate )≤c≤c0-[int(Δ3 / P sub2 )-1](W gate +S gate ), where Δ3 is the distance between the second target lead-out position B222 and the second reference lead-out position B221 in the second direction Y, P sub2 W represents the arrangement period of sub-pixel S0 in the second direction. gate S is the width of the second signal line 171. gateThe spacing of the second signal lines 171 is defined by this design. This design allows for the orderly routing of the second signal lines 171 while maintaining a narrow bezel on the display panel, thus avoiding unnecessary bridging between the second signal lines 171 and other signal lines, reducing signal line overlap capacitance, and improving the display effect. Optionally, the width of the second signal line arrangement area B20 corresponding to the region between the second target routing position B222 and the second reference routing position B221 is also designed to satisfy this formula. This design further standardizes the shape of the second signal line arrangement area B20 between the second routing positions B22, ensuring the orderly extension of the second signal line arrangement area B20 and improving the reliability of the display panel.

[0221] In some examples, the range of c above applies to the portion of the second signal line arrangement area B20 where the second lead-in line 173 is not provided on the side away from the display area AA.

[0222] In one specific embodiment, the second direction is a direction perpendicular to the first direction; for example, such as Figure 8 As shown, when the first direction is the X direction, the second direction is the Y direction, and the X direction is perpendicular to the Y direction.

[0223] In some of the embodiments above, the second reference lead-out position B221, the second target lead-out position B222, etc. have been described, and will not be repeated here.

[0224] The arrangement period P2 of pixels S in the second direction Y can be understood as the distance between the same positions of two adjacent pixels S in the second direction Y. The same positions of two adjacent pixels S can be understood as the same positions that the two pixels S have respectively, such as the center of pixel S, or the center of the leftmost sub-pixel S0 in pixel S, or the lower left corner of the leftmost sub-pixel S0 in pixel S, or the lower left corner of the pixel electrode of the leftmost sub-pixel S0 in pixel S (e.g.,...). Figure 5C (As shown). It can be understood that when multiple sub-pixels S0 of pixel S are arranged only along the X direction, the arrangement period P of sub-pixels S0 in the second direction Y is... sub2 The arrangement period P2 of pixel S in the second direction Y is equal to that of pixel S.

[0225] In one specific embodiment, P sub2 >P sub1 In a pixel S, the sub-pixels S0 are arranged only along the first direction.

[0226] Please see Figure 7In some examples, a group of second target lead-out positions BX222 includes only one second target lead-out position B222; this can also be understood as the second target lead-out positions B222 not being grouped. In this case, each second lead-out line 172 is led out from one second lead-out position B22, and multiple second lead-out lines 172 are arranged at equal intervals. Since each gate line GT is connected to a row of sub-pixels S0, multiple gate lines GT are arranged at equal intervals. Therefore, the spacing between two adjacent second lead-out lines 172 can be set to be equal to the distance between two adjacent gate lines GT. Specifically, the second lead-out line 172 can be configured to lie on the same straight line as the gate line GT it is connected to and the corresponding second lead-out position B22. Where Δ3 / P sub2 This indicates the number of rows of sub-pixels S0 traversed by the second signal line arrangement area B20, located between the second target lead-out position B222 and the second reference lead-out position B221, in the second direction Y. For each row of sub-pixels S0 traversed, a second signal line 171 is led out from the second signal line arrangement area B20; therefore, the width of the second signal line arrangement area B20 decreases by W. gate +S gate .

[0227] In some embodiments, the orthographic projection of the second signal line arrangement area B20 in the second direction Y overlaps with the orthographic projection of a portion of the sub-pixel S0 in the second direction Y.

[0228] In some embodiments, after the second lead-out line 172 is led out from the second signal line arrangement area B20, the second lead-out line 172 extends directly toward the target gate line GT or the sub-pixel S0 controlled by the target gate line GT until it approaches the target gate line GT or the sub-pixel S0 controlled by the target gate line GT. Here, "directly" can be understood as the extension direction not changing.

[0229] In some embodiments, the second target reference position B222 and the gate line GT electrically connected to the second lead 172 from which it is drawn are located at the same position in the first direction X.

[0230] In some embodiments, the sub-pixel S0 controlled by the gate line GT electrically connected to the second target reference position B222 and the second lead-out line 172 extending from it is located at the same position in the first direction X. For example, refer to Figure 7 In the figure, the sub-pixel S0 controlled by the gate line GT electrically connected to the second target reference position B222 and the second lead line 172 extending from it is located on the same horizontal plane.

[0231] Figure 11 for Figure 5A Another enlarged view of a section at point D.

[0232] Please see Figure 11In other examples, among the at least partially continuous distribution of second target leads B222 other than the second reference lead-out position B221, a group of second target leads BX222 includes multiple second target leads B222. In this case, the distance between two adjacent groups of second target leads BX222 is greater than the distance between two adjacent second target leads B222 within a group of second target leads BX222. For example, multiple second leads 172 derived from a group of second target leads BX222 are electrically connected to multiple gate lines GT, one-to-one, and one gate line GT controls the TFT switching of at least some sub-pixels in a row of sub-pixels S0.

[0233] For example, a set of second target lead-out positions BX222 leads out n second lead-out lines 172. Specifically, n second lead-out lines 172 are led out every n rows of sub-pixels S0. These n second lead-out lines 172 form a set of second lead-out lines X172. Specifically, n is a positive integer; for example, n is one of 1, 2, 3, 4, 5, or 6.

[0234] In some examples, where a set of second target lead-out positions BX222 includes multiple second target lead-out positions B222, portions of the multiple second lead-out lines 172 corresponding to the multiple second target lead-out positions B222 can extend along the first direction X; each gate line GT is connected to a row of sub-pixels S0, and the multiple gate lines GT are arranged at equal intervals, with the spacing between adjacent gate lines GT being unequal to the spacing between adjacent second lead-out lines 172 within the set of second lead-out lines X172. Specifically, the spacing between adjacent second lead-out lines 172 within the set of second lead-out lines X172 can be smaller than the spacing between adjacent gate lines GT; for example, near the position where the second lead-out line 172 connects to the gate line GT, the second lead-out line 172 is bent to achieve electrical connection.

[0235] Please see Figure 11 In some embodiments, the included angle L1 between the first lead 162 and the first signal line 161 electrically connected thereto is greater than or equal to 90°.

[0236] In some embodiments, the angle L2 between the second lead 172 and the second signal line 171 electrically connected thereto is greater than or equal to 90°. An angle greater than or equal to 90° between the lead and the signal line can avoid excessive bending angles in the wiring and reduce the risk of defects.

[0237] In some embodiments, for at least partially continuously distributed second target lead-out positions B222, the width c1 of the corresponding second signal line arrangement area B20 of a second lead-out position B22 electrically connected to a target gate line with an odd number of gate lines GT spaced apart from the second reference gate line satisfies: c1=c0-[int(Δ3 / Psub2 )](W gate +S gate ).

[0238] Specifically, every two adjacent second target lead-out positions B222 constitute a set of second target lead-out positions BX222. Two second signal lines 171 leading out from a set of second target lead-out positions BX222 are electrically connected to two gate lines GT via two second lead-out lines 172, respectively. In some embodiments, the pixels S corresponding to the outer contour of at least a portion of the display area AA of the display panel are arranged in a sawtooth pattern, such as... Figure 11 As shown, the pixels S corresponding to the outer contour of the display area AA extend downwards and recede to the right. For every two Y-axis arrangement cycles of downward extension of two pixels S, the pixels S recede to the right by two X-axis arrangement cycles. When the outer contour of the display area AA of the display panel is circular, the pixels S corresponding to at least part of the outer contour of the display area AA are arranged in this way, which makes the outer contour of the display area AA of the display panel look smoother and conforms to the contour characteristics of the circular AA area. At this time, for the second target lead-out positions B222 that are at least partially continuously distributed, the width c1 of the second signal line arrangement area B20 corresponding to a second lead-out position B22 that is electrically connected to a target gate line with an odd number of gate lines GT spaced apart from the second reference gate line satisfies: c1=c0-[int(Δ3 / P sub2 )](W gate +S gate This allows the second lead-out line 172, which originates from the second target position B222, to be distributed more evenly, avoiding redundant routing.

[0239] In some examples, the above formula c1=c0-[int(Δ3 / P) sub2 )](W gate +S gate This applies to the portion of the second signal line arrangement area B20 that is far from the display area AA and does not have a second lead-in line 173.

[0240] In some embodiments, the width c satisfies: c = c0 - [int(Δ3 / P)] sub2 )](W gate +S gate For example, after each row of sub-pixels S0, a second signal line 171 is drawn out from the second signal line arrangement area B20. Therefore, a second lead-out position B22 corresponds to a row of sub-pixels S0, which can make the second lead-out lines 172 drawn out from the second target lead-out position B222 more evenly distributed and avoid wiring redundancy.

[0241] In some examples, the above formula c = c0 - [int(Δ3 / P)] sub2 )](W gate +S gateThis applies to the portion of the second signal line arrangement area B20 where the second lead-in line 173 is not provided on the side furthest from the display area AA.

[0242] Furthermore, in some embodiments, the width b satisfies: b = b0 - [int(kΔ1 / P1)](W gate +S gate In this design, the second lead-out line 172 led out from the second target lead-out position B222 and the first lead-out line 162 led out from the first target lead-out position B112 are both set to be distributed relatively evenly to avoid redundant routing.

[0243] In some embodiments, multiple gate lines GT are alternately driven by second leads 172 located in the peripheral areas on opposite sides of the display area AA. For example, the peripheral areas on opposite sides of the display area AA each include at least one second signal line arrangement area. For example, the second leads 172 providing gate drive signals to a row of sub-pixels S0 from one side of the display area AA are connected to the gate lines GT at intervals; the second leads 172 providing gate drive signals to a row of sub-pixels S0 from the other side of the display area AA are also connected to the gate lines GT at intervals; in one specific embodiment, the second leads 172 located on one side of the display area AA drive the odd-numbered rows of sub-pixels S0, and the second leads 172 located on the other side of the display area AA drive the even-numbered rows of sub-pixels S0. In this way, the width of each second signal line arrangement area can be smaller, enabling a narrower bezel for the display panel.

[0244] In one example, a second reference lead-out position B22 is included among multiple second lead-out positions B22. The second reference signal line 171m is led out from the second reference lead-out position B221 and electrically connected to the second reference gate line. The width of the second signal line arrangement area B20 corresponding to the second reference lead-out position B221 is c0. Among the at least partially continuous second target lead-out positions B22 other than the second reference lead-out position B221, the width c of the second signal line arrangement area B20 corresponding to each second target lead-out position B222 satisfies: c0-[int(Δ3 / (2P sub2 )+1)](W gate +S gate )≤c≤c0-[int(Δ3 / 2P sub2 -1)](W gate +S gate ), where Δ3 is the distance between the second target lead-out position B222 and the second reference lead-out position B221 in the second direction Y, P sub2 Let W be the arrangement period of sub-pixel S0 in the second direction Y. gate S is the width of the second signal line 171. gateThe spacing of the second signal line 171. Optionally, the width of the second signal line arrangement area B20 corresponding to the region between the second target lead-out position B222 and the second reference lead-out position B221 is also designed to satisfy this formula. In some examples, the range of c above applies to the portion of the second signal line arrangement area B20 where the second lead-in line 173 is not provided on the side away from the display area AA.

[0245] In one example, the width c satisfies: c = c0 - [int(Δ3 / (2P)] sub2 )](W gate +S gate ).

[0246] In some embodiments, the first signal line arrangement area B10 is closer to the display area AA than the second signal line arrangement area B20. In this case, at least a portion of the second lead 172 will extend across the first signal line arrangement area B10 to be electrically connected to the gate line GT.

[0247] In some embodiments, the second signal line arrangement area B20 is closer to the display area AA than the first signal line arrangement area B10. In this case, a portion of the first lead 162 extends across the second signal line arrangement B20 to be electrically connected to the data line DT.

[0248] In some examples, a portion of the second lead 172 near the second signal line 171 extends in a straight line. Exemplarily, this portion of the trace extends along a first direction X; exemplarily, the portion of the trace may extend along a second direction Y.

[0249] In some examples, a portion of the first lead-out line 162 near the first signal line 161 extends in a straight line. For example, this portion of the trace extends along a second direction Y. For example, this portion of the trace extending along the second direction Y crosses the second signal line arrangement area B20.

[0250] Figure 12A This is a structural diagram of a display panel 100 according to some embodiments.

[0251] Please see Figure 12A In some embodiments, when the second signal line arrangement area B20 is closer to the display area AA than the first signal line arrangement area B10, and when the first lead 162 is led out along the second direction Y, in the first signal line arrangement area B10 (e.g., Figure 6 At least a portion of the area shown, the first signal line arrangement area B10 is adjacent to the second signal line arrangement area B20 (as shown). Figure 6 The angle θ1 between the first signal line 161 (as shown) and the second signal line 171 (adjacent to the first signal line arrangement area B10 in the second signal line arrangement area B20) satisfies: sinθ1=[I1(W data +Sdata [cosα1] / P1. Where α1 is the angle between the second signal line 171 of the second signal line arrangement area B20, which is adjacent to the first signal line arrangement area B10, and the first direction X; I1 is the number of first target lead-out positions B112 corresponding to the arrangement period range of a pixel in the first direction X. P1 is the arrangement period of the pixel in the first direction X.

[0252] In the case where the first signal line 161 is led out along the second direction Y, a group of first leads X162 may include multiple first leads 162. Of course, in some other examples, a group of first leads X162 may include only one first lead 162, that is, the first leads 162 are not grouped.

[0253] exist Figure 12A In the given example, a set of first leads X162 includes a first lead 162.

[0254] The following is based on Figure 12A For example, the above embodiments of the application will be described by way of example.

[0255] For example, the first signal line 161 of the first signal line arrangement area B10 adjacent to the second signal line arrangement area B20 is called the first signal line 161R, and the second signal line 171 of the second signal line arrangement area B20 adjacent to the first signal line arrangement area B10 is called the second signal line 171R.

[0256] The first signal line arrangement area B10 also includes a first signal line 161S, wherein the first signal line 161R is electrically connected to one end of the first lead 162 and the first signal line 161S is electrically connected to one end of the first lead 162, and the distance traveled in the first direction X is P1.

[0257] The third auxiliary line M3 is electrically connected to the endpoint of the first lead-out line 162 via the first signal line 161R and is parallel to the second signal line 171R.

[0258] Figure 12B This is a structural diagram of a display panel 100 according to some embodiments.

[0259] Please see Figure 12B Draw a straight line X1, where the straight line X1 is parallel to the first direction X, and the straight line X1 is electrically connected to one end of the first lead-out line 162 through the first signal line 161S.

[0260] A second auxiliary line M2 is drawn perpendicular to the straight line X1 through one end of the first signal line 161R electrically connected to the first lead 162. The second auxiliary line M2 can be on the same straight line as the first lead 162 electrically connected to the first signal line 161R.

[0261] The third auxiliary line M3, the line X1, and the second auxiliary line M2 can form a first right triangle. One acute angle of this first right triangle is the angle between the third auxiliary line M3 and the line X1. Since the third auxiliary line M3 is parallel to the second signal line 171R, and the angle between the second signal line 171R and the line X1 is α1, the angle between the third auxiliary line M3 and the line X1 is also α1. In this case, a portion of the third auxiliary line M3 serves as the hypotenuse of the third right triangle.

[0262] The length of the right-angled side adjacent to acute angle α1 in the first right triangle is: the distance between the first signal line 161R, which is electrically connected to one end of the first lead-out line 162, and the first signal line 161S, which is electrically connected to one end of the first lead-out line 162, is P1.

[0263] Therefore, the length of the hypotenuse of the first right triangle is P1 / cosα1.

[0264] A fourth auxiliary line M4 is drawn perpendicular to the first signal line 161R, passing through one end of the first signal line 161S electrically connected to the first lead-out line 162 (i.e., the intersection of the first signal line 161S and the straight line X1). At the same time, the fourth auxiliary line M4 is perpendicular to the first signal line 161S and passes through the intersection of the first signal line 161S and the third auxiliary line M3.

[0265] At this point, the first signal line 161R, the third auxiliary line M3, and the fourth auxiliary line M4 can form a second right triangle. One acute angle of this second right triangle is the angle between the third auxiliary line M3 and the first signal line 161R. Since the third auxiliary line M3 is parallel to the second signal line 161R, the angle between the third auxiliary line M3 and the first signal line 161R is θ1. Therefore, one acute angle of the second right triangle is θ1. The portion of the fourth auxiliary line M4 is the side opposite to the acute angle θ1. The length of the side opposite to the acute angle θ1 is the distance between the first signal line 161S and the first signal line 161R. The distance between the first signal line 161S and the first signal line 161R is I1(W). data +S data Therefore, in the second right triangle, the length of the side opposite acute angle θ1 is I1(W). data +S data ).

[0266] Furthermore, the hypotenuse of the second right triangle is shared with the hypotenuse of the first right triangle; therefore, the length of the hypotenuse of the second right triangle is P1 / cosα1. Thus, sinθ1=[I1(W data +S data )] / (P1 / cosα1)=[I1(W data +Sdata )cosα1] / P1.

[0267] Where the included angle θ1 satisfies sinθ1=[I1(W data +S data The formula )cosα1] / P1 can make the shape between the adjacent first signal line 161 and second signal line 171 fit better, thereby reducing the overall width of the first signal line arrangement area B10 and the second signal line arrangement area B20 at the corresponding positions, which is beneficial to the realization of a narrower bezel of the display panel.

[0268] Figure 12C This is a structural diagram of a display panel 100 according to some embodiments.

[0269] Please see Figure 12C In some embodiments, when the first signal line arrangement area B10 is closer to the display area AA than the second signal line arrangement area B20, and the second lead 172 is led out along the second direction Y, at least a portion of the first signal line arrangement area B10 (e.g., Figure 6 As shown), the first signal line arrangement area B10 is adjacent to the first signal line 161 of the second signal line arrangement area B20, and the second signal line arrangement area B20 (as shown) Figure 6 As shown, the included angle θ2 between the second signal line 171, which is adjacent to the first signal line arrangement area B10, satisfies: sinθ2=[I2(W gate +S gate [cosα2] / P1. Where α2 is the angle between the first signal line 161, which is adjacent to the second signal line arrangement area B20 in the first signal line arrangement area B10, and the first direction X; I2 is the number of second target lead-out positions B222 corresponding to the arrangement period range of a pixel in the first direction X. P1 is the arrangement period of the pixel in the first direction X.

[0270] In the case where the second signal line 171 is led out along the second direction Y, a group of second target lead-out positions BX222 can include multiple second target lead-out positions B222, in which case multiple second lead-out lines 172 are led out in a group. Alternatively, a group of second target lead-out positions BX222 can include only one second target lead-out position B222. Figure 12C The above embodiments are illustrated by way of example using a set of second target lead-out positions BX222, including a second target lead-out position B222.

[0271] like Figure 12C The arrangement period range of one pixel in the first direction X corresponds to three second target lead-out positions B222, i.e., I2 = 3.

[0272] Among them, the first signal line 161 in the first signal line arrangement area B10, which is adjacent to the second signal line arrangement area B20, is the first signal line 161T. Therefore, the angle between the first signal line 161T and the first direction X is α2.

[0273] The second signal line arrangement area B20 is adjacent to the first signal line arrangement area B10, and the second signal line 171 is designated as the second signal line 171T. Therefore, the angle between the second signal line 171 and the first signal line 161T is θ2. The second signal line arrangement area B20 also includes a second signal line 171U, wherein the second signal line 171T is electrically connected to one end of the second lead 172, and the second signal line 171U is electrically connected to the second lead 172, with a distance P1 traversed in the first direction X.

[0274] Draw a fifth auxiliary line M5, which is parallel to the first signal line 161T and passes through the second signal line 171T, connecting to the endpoint of the second signal line 171T. Since the angle between the second signal line 171T and the first signal line 161T is θ2, the angle between the fifth auxiliary line M5 and the second signal line 171T is also θ2.

[0275] Figure 12D This is a structural diagram of a display panel 100 according to some embodiments.

[0276] Please see Figure 12D A straight line X2 parallel to the first direction X is drawn from one end of the second signal line 171T, which is electrically connected to the second lead 172. The straight line X2 also passes through the intersection of the fifth auxiliary line M5 and the second signal line 171T.

[0277] Draw a seventh auxiliary line M7 perpendicular to the straight line X2, which is electrically connected to one end of the second lead 172 via the second signal line 171U.

[0278] At this point, the seventh auxiliary line M7, the fifth auxiliary line M5, and the line X2 can form a fifth right triangle. One acute angle of the fifth right triangle is the angle between the fifth auxiliary line M5 and the line X2, which is α2. The length of the leg adjacent to the acute angle α2 is P1. Therefore, the length of the hypotenuse of the fifth right triangle is P1 / cosα2.

[0279] A sixth auxiliary line M6 is made perpendicular to the second signal line 171T, connected to one end of the second lead 172 via the second signal line 171U. Simultaneously, the sixth auxiliary line M6 can be perpendicular to the second signal line 171U and passes through the intersection of the second signal line 171U and the fifth auxiliary line M5.

[0280] The second signal line 171T, the fifth auxiliary line M5, and the sixth auxiliary line M6 can form a sixth right triangle. One acute angle of this sixth right triangle is the angle between the fifth auxiliary line M5 and the second signal line 171T, which is θ2. The length of the leg opposite to the acute angle θ2 is the distance between the second signal lines 171T and 171U, while the distance between the second signal lines 171T and 171U is I2(W). data +S data Meanwhile, the sixth right triangle shares its hypotenuse with the fifth right triangle, therefore the length of the hypotenuse of the sixth right triangle is P1 / cosα2. Therefore, sinθ2=[I2(W data +S data )](P1 / cosα2)=[I2(W gate +S gate )cosα2] / P1.

[0281] The included angle θ2 satisfies sinθ2=[I2(W gate +S gate The formula )cosα2] / P1 can make the shape between the adjacent first signal line 161 and second signal line 171 fit better, thereby reducing the overall width of the first signal line arrangement area B10 and the second signal line arrangement area B20 at the corresponding positions, which is beneficial to the realization of a narrower bezel of the display panel.

[0282] Figure 12E This is a structural diagram of a display panel 100 according to some embodiments. Figure 12F This is a structural diagram of a display panel 100 according to some embodiments.

[0283] Please see Figure 12E and Figure 12F In some embodiments, when the first signal line arrangement area B10 is closer to the display area AA than the second signal line arrangement area B20, and the second lead 172 is led out along the first direction X, at least a portion of the first signal line arrangement area B10 (e.g., Figure 6 As shown), the first signal line arrangement area B10 is adjacent to the first signal line 161 of the second signal line arrangement area B20, and the second signal line arrangement area B20 (as shown) Figure 6 As shown, the included angle θ3 between the second signal line 171, which is adjacent to the first signal line arrangement area B10, satisfies:

[0284] sinθ3=[I3(W gate +S gate )sinα3] / P2.

[0285] Wherein, α3 is the angle between the first signal line 161 of the first signal line arrangement area B10, which is adjacent to the second signal line arrangement area B20, and the first direction X; I3 is the number of second target lead-out positions B222 corresponding to the arrangement period range of a pixel in the second direction Y; P2 is the arrangement period of a pixel in the second direction Y.

[0286] In the case where the second lead-out line 172 is led out along the first direction X, a group of second target lead-out positions BX222 can include one second target lead-out position B222, that is, the second target lead-out positions B222 are not grouped. Alternatively, a group of second target lead-out positions BX222 can include multiple second target lead-out positions B222.

[0287] In some examples, I3 can take the value 1.

[0288] Specifically, the first signal line 161 adjacent to the second signal line arrangement area B20 in the first signal line arrangement area B10 is designated as the first signal line 161V, and the second signal line 171 adjacent to the first signal line arrangement area B10 in the second signal line arrangement area B20 is designated as the second signal line 171W. The second signal line arrangement area B20 also includes the second signal line 171V, wherein the second signal line 171W is electrically connected to the endpoint of the second lead 172, and the distance traversed by the second signal line 171V in the second direction Y is P2.

[0289] Draw an eighth auxiliary line M8, which is parallel to the first signal line 161V and electrically connected to the endpoint of the second lead 172 via the second signal line 171W. Therefore, the angle between the eighth auxiliary line M8 and the second signal line 171W is θ3.

[0290] Draw a straight line X3 parallel to the first direction X from the end where the second signal line 171W is electrically connected to the second lead-out line 172.

[0291] A ninth auxiliary line M9, perpendicular to the straight line X3, is made by connecting one end of the second signal line 171V to one end of the second lead-out line 172.

[0292] At this point, the ninth auxiliary line M9, the eighth auxiliary line M8, and the straight line X3 can form a seventh right triangle. One acute angle of this seventh right triangle is the angle between the eighth auxiliary line M8 and the straight line X3. Since the eighth auxiliary line M8 is parallel to the first signal line 161V, the angle between the eighth auxiliary line M8 and the straight line X3 is α3.

[0293] The length of the right-angled side opposite to acute angle α3 is the distance between the end of the second signal line 171V electrically connected to the second lead 172 and the end of the second signal line 171W electrically connected to the second lead 172 in the second direction Y, i.e., P2. The portion of the eighth auxiliary line M8 can be considered as the hypotenuse of the seventh right-angled triangle, and the length of the hypotenuse of the seventh right-angled triangle is P2 / sinα3.

[0294] Draw a tenth auxiliary line M10 perpendicular to the second signal line 171V through the intersection of the second signal line 171V and the eighth auxiliary line M8. The tenth auxiliary line M10 is also perpendicular to the second signal line 171V, and passes through the intersection of the second signal line 171V and the eighth auxiliary line M8 and is electrically connected to one end of the second lead 172.

[0295] The tenth auxiliary line M10, the eighth auxiliary line M8, and the second signal line 171W can form an eighth right triangle, and the eighth right triangle shares the hypotenuse with the seventh right triangle. Therefore, the length of the hypotenuse of the eighth right triangle is P2 / sinα3.

[0296] Furthermore, one acute angle of the eighth right triangle is the angle between the eighth auxiliary line M8 and the second signal line 171W. Since the eighth auxiliary line M8 is parallel to the first signal line 161V, the angle between the eighth auxiliary line M8 and the second signal line 171W is θ3.

[0297] The length of the right-angled side opposite to the acute angle θ3 is the distance between the second signal line 171W and the second signal line 171V, i.e., I3(W gate +S gate Therefore, sinθ3=[I3(W gate +S gate )](P2 / sinα3)=[I3(W gate +S gate )sinα3] / P2.

[0298] Where the included angle θ3 satisfies sinθ3=[I3(W gate +S gate The )sinα3] / P2 can make the shape between the adjacent first signal line 161 and second signal line 171 fit better, thereby reducing the overall width of the first signal line arrangement area B10 and the second signal line arrangement area B20 at the corresponding positions, which is beneficial to the realization of a narrower bezel of the display panel.

[0299] In some specific embodiments, the second signal line arrangement area B20 is closer to the display area AA than the first signal line arrangement area B10. The first signal line arrangement area B10 is adjacent to the first signal line 161 of the second signal line arrangement area B20. The included angle θ between the second signal line arrangement area B20 and the second signal line 171 of the second signal line arrangement area B10 is adjacent to the first signal line arrangement area B10 is in the range of 1° to 5°, that is, 1°≤θ≤5°. Setting the included angle θ in this range is beneficial to the close proximity arrangement of the first signal line arrangement area B10 and the second signal line arrangement area B20.

[0300] In some embodiments, the included angle θ ranges from 3° to 5°.

[0301] In some embodiments, the width of the first lead 162 is greater than the width of the first signal line 161 connected thereto.

[0302] In one specific embodiment, the first lead 162 and the first signal line 161 are fabricated using the same process. Specifically, in fabricating the first lead 162 and the first signal line 161, firstly, a conductive layer is deposited, and then a photoresist layer is formed on the conductive layer. Subsequently, the photoresist layer is exposed and developed to remove the exposed portions, thereby forming a photolithographic pattern. The portion of the photolithographic pattern corresponds to the first signal line 161. Next, the conductive layer is etched using an etchant. During this process, the portions hidden by the photolithographic pattern are retained, while the portions not hidden by the photolithographic pattern are removed, thus forming the first signal line 161 and the first lead 162. Finally, the photolithographic pattern covering the first signal line 161 and the first lead 162 is removed. In one implementation, the designed width of the first lead 162 is equal to the designed width of the first signal line 161 connected to it, and the arrangement density of the first signal line 161 is relatively high, while the arrangement density of the first lead 162 is relatively low. However, during the etching process of the conductive layer, the amount of etching solution in the area where the first lead 162 is located is greater than that in the area where multiple first signal lines 161 are located. Therefore, the etching rate of the first lead 162 is greater than that of the first signal lines 161. Consequently, the first lead 162 is prone to over-etching, resulting in the actual width of the first lead 162 being smaller than its designed width, leading to excessively high resistance. In some embodiments of this disclosure, by making the width of the first lead 162 greater than the width of the first signal line 161 connected to it, the problem of the actual width of the first lead 162 after etching being too small and the resistance being too high can be avoided.

[0303] In one specific embodiment, the metal layer containing the first lead 162 is located on the side of the metal layer containing the second signal line 171 away from the first substrate 111; for example, when the first lead 162 extends across the second signal line 171 (e.g. Figure 7 As shown, the width of the first lead 162 is greater than the width of the first signal line 161 connected to it, that is, the first lead 162 is widened to prevent the first lead 162 from having a short line when passing the second signal line 171.

[0304] In one specific embodiment, the second signal line 171 and the second lead-out line 172 are fabricated using the same process.

[0305] In one specific embodiment, the difference between the width of the first lead-out line 162 and the width of the first signal line 161 is in the range of 0 to 2 μm.

[0306] In addition, in some other embodiments, at least one first sacrificial wire is provided on each side of the first lead 162. By providing the first sacrificial wire, the arrangement density of the first lead 162 can be increased, thereby reducing the etching rate of the first lead 162 and thus avoiding the actual width of the first lead 162 being too small and the resistance being too large.

[0307] In some other embodiments, at least one first sacrificial conductor may be provided on each side of a set of first leads X162.

[0308] Figure 13 This is a structural diagram of a display panel 100 according to some embodiments.

[0309] Please see Figure 13 In one implementation, the width of the second lead 172 is equal to the width of the second signal line 171 connected to it, and the arrangement density of the second signal line 171 is greater than the arrangement density of the second lead 172.

[0310] During the etching process of the conductive layer, the etching solution in the area where the second lead 172 is located is more than that in the area where the multiple second signal lines 171 are located. Therefore, the etching rate of the second lead 172 is greater than that of the second signal lines 171. This can easily cause the second lead 172 to be over-etched, resulting in the actual width of the second lead 172 being smaller than its designed width, and thus causing the resistance of the second lead 172 to be too high.

[0311] Figure 14A This is a structural diagram of a display panel 100 according to some embodiments. Please refer to... Figure 14AIn some embodiments of this disclosure, the width of the second lead 172 is greater than the width of the second signal line 171 connected to it, which can avoid the actual width of the second lead 172 being too small and the resistance being too large.

[0312] Figure 14B This is a structural diagram of a display panel 100 according to some embodiments.

[0313] Please see Figure 14B In some other embodiments, at least one sacrificial wire is provided on each side of the second lead 172. By providing the second sacrificial wire 174, the arrangement density of the second lead 172 can be increased, thereby reducing the etching rate of the second lead 172 and thus avoiding the second lead 172 from having too small an actual width and too large a resistance.

[0314] Specifically, the distance between the closest second sacrificial wire 174 and the closest second lead 172 can be equal to the distance between the second signal lines 171, so that the etching environment of the second lead 172 is close to that of the second signal line 171.

[0315] In some other embodiments, at least one second sacrificial conductor 174 may be provided on each side of a set of second leads X172.

[0316] In some embodiments, the width relationship between the second signal line 171 and the second lead-out line 172 can be analogous to the above-described arrangement of the first signal line 161 and the first lead-out line 162, that is, the second signal line 171 corresponds to the first signal line 161, and the second lead-out line 172 corresponds to the first lead-out line 162. This application will not elaborate further.

[0317] In addition, please refer to [the relevant documents] again. Figure 13 In some embodiments of this disclosure, a signal line sacrificial conductor 171' may also be provided on at least one side of the plurality of second signal lines 171 as a whole.

[0318] In one specific embodiment, a signal line sacrificial conductor 171' is included between two adjacent second lead-in lines 173; preferably, the extension direction of the sacrificial conductor 171' is the same as the extension direction of the second signal lines 171 at their distribution locations; in another specific embodiment, multiple signal line sacrificial conductors 171' are included between two adjacent second lead-in lines 173; preferably, the extension direction of the sacrificial conductors 171' is the same as the extension direction of the second signal lines 171 at their distribution locations; thus, the etching uniformity of multiple second signal lines 171 close to the second lead-in line 173 is ensured.

[0319] In one specific embodiment, a signal line sacrificial conductor 171' is included between two adjacent second leads 172; preferably, the extension direction of the sacrificial conductor 171' is the same as the extension direction of the second signal lines 171 that are adjacent to it; in another specific embodiment, multiple signal line sacrificial conductors 171' are included between two adjacent second leads 172; preferably, the extension direction of the sacrificial conductors 171' is the same as the extension direction of the second signal lines 171 that are adjacent to it; thus, the etching uniformity of the multiple second signal lines 171 near the second leads 172 is ensured.

[0320] Figure 15 This is a structural diagram of a display panel 100 according to some embodiments.

[0321] Please see Figure 15 In some embodiments, the display panel 100 includes a gate drive circuit 180 located in the non-display area BB. The gate drive circuit 180 has a plurality of shift register units GOA, at least a portion of which are electrically connected to a gate line GT for sending a gate drive signal to the gate line GT. The plurality of shift register units GOA may be located on one or both sides of the display area AA.

[0322] For example, when multiple shift register units GOA are located on one side of the display area AA, the number of shift register units GOA is equal to the number of gate lines GT. The shift register units GOA are connected one-to-one with the gate lines GT. At this time, one shift register unit GOA sends a gate drive signal to one gate line GT.

[0323] For example, multiple shift register units GOA are located on both sides of the display area AA; it is possible to configure two shift register units GOA located on both sides of the display area AA to be electrically connected to a gate line, that is, both can send gate drive signals to a gate line GT, thereby increasing the driving capability of the gate drive circuit 180. For example, multiple shift register units GOA can be located on both sides of the display area AA distributed along the X direction.

[0324] In some embodiments, the overall span H1 of the shift register unit GOA of the gate drive circuit 180 in the second direction Y is smaller than the overall span H2 of the pixel S in the display area AA in the second direction Y; Reference Figure 15 The overall span H1 of shift register unit GOA in the second direction Y can be understood as the maximum size occupied by all shift register units GOA in the second direction Y; the overall span H2 of pixel S in the second direction Y can be understood as the maximum size occupied by pixel S with the longest span in the second direction Y.

[0325] By making the overall span H1 of the multiple shift register units GOA in the second direction Y smaller than the overall span H2 of the pixel S in the display area AA in the second direction Y, the space occupied by the multiple shift register units GOA in the second direction Y can be reduced, thus avoiding interference with the arrangement of other signal lines.

[0326] Figure 16 This is a structural diagram of a display panel 100 according to some embodiments. Figure 17 This is a structural diagram of a display panel 100 according to some embodiments.

[0327] Please see Figure 15 , Figure 16 and Figure 17 In some embodiments, the display area AA includes a column of pixels S with the longest span, wherein "a column of pixels S with the longest span" means that among the multiple columns of pixels S in the display panel 100, the column of pixels S has the largest span in the second direction Y, that is, the largest size.

[0328] In the plane of the display panel 100, the first orthographic projection of the plurality of shift register units GOA on the straight line of a column of pixels S with the longest span is located within the second orthographic projection range of the column of pixels S with the longest span on its straight line. Therefore, the shift register units GOA of the gate drive circuit 180 are located only on one or both sides of the column of pixels S with the longest span in the first direction X, and not on one or both sides of the column of pixels S with the longest span in the second direction Y. This arrangement reduces the space occupied by the shift register units GOA in the second direction Y, avoiding interference with the arrangement of other signal lines. For example, the third signal line arrangement area B30 occupies at least one side of the display area AA. The reduced space occupied by the plurality of shift register units GOA in the second direction Y prevents the arrangement of the GOA units from interfering with the arrangement of the third signal line arrangement area B30. Specifically, refer to Figure 15 The third signal line arrangement area B30 overlaps with the second orthographic projection on the straight line containing the longest span pixel S in the column of multiple shift register units GOA. For example, the third signal line arrangement area B30 is respectively set on both sides of the longest span pixel S in the column, which can make the third signal line arrangement area B30 distributed on the display panel, which is beneficial to achieving a narrower bezel on the display panel.

[0329] In some embodiments, the distribution period of the register unit GOA distributed on at least one side of the display area AA is less than the arrangement period Psub2 of the sub-pixel S0 in the second direction Y; this is beneficial for the compact design of the register unit GOA, so as to save its space occupation.

[0330] Please see Figure 16 and Figure 17 In some embodiments, the distribution outline of the shift register unit GOA on at least one side of the display area AA is the same as the outer outline of the corresponding side of the display area AA. This arrangement helps to reduce the distance between the distribution outline of the shift register unit GOA and the outer outline of the display area AA, thereby reducing the size of the peripheral area BB of the display panel 100 and thus narrowing the bezel of the display panel 100.

[0331] In some examples, the shift register cells GOA distributed on at least one side of the display area AA are conformally distributed with the outer contour of the display area AA. For example, if the outer contour of the display area AA is circular, the corresponding distribution contour of the shift register cells GOA distributed on at least one side is arc-shaped.

[0332] In some examples, the shift register units (GOAs) can be arranged extending along the X direction, that is, multiple shift register units (GOAs) are arranged in parallel. In one specific embodiment, see [reference needed]. Figure 16 The multiple shift register units (GOAs) include a reference shift register unit (GOAm). The distance between the reference shift register unit (GOAm) and the pixel S with the longest span in the column is greater than the distance between other shift register units (GOAs) and the pixel S with the longest span in the column. The multiple shift register units (GOAs) extend along a first direction X. This configuration ensures that the arrangement of TFTs in the shift register units (GOAs) remains consistent, which is beneficial for maintaining a uniform TFT fabrication environment during the etching process.

[0333] In some other examples, shift register units (GOAs) are not all arranged to extend along the X-direction. In one specific embodiment, the angle between the extension direction of a shift register unit (GOA) and the X-direction is positively correlated with the distance between the shift register unit (GOA) and the pixel S with the longest span in a row. In another specific embodiment, the angle between the extension direction of a shift register unit (GOA) and the X-direction is positively correlated with the distance between the shift register unit (GOA) and a straight line extending along the X-direction through the center of the display area AA. In yet another specific embodiment, the angle between the extension direction of a shift register unit (GOA) and the X-direction is positively correlated with the distance to the center of the entire group of shift register units (GOAs) on the side where the shift register unit (GOA) is located. In one specific embodiment, a reference shift register unit (GOAm) extends along the X-direction, and the angle between the extension direction of one of the shift register units (GOA) and the X-direction is positively correlated with the distance between the shift register unit (GOA) and the reference shift register unit (GOAm). This arrangement allows each shift register unit (GOA) to maintain an equal or approximately equal distance from the outer contour of the display area AA, achieving a narrower bezel on the display panel.

[0334] In some embodiments, the ratio between the first orthographic projection and the second orthographic projection is in the range of [0.1, 0.9], that is, the size of the gate driving circuit 180 in the second direction Y is 0.1 to 0.9 times the size of a column of pixels S with the longest span in the second direction Y.

[0335] The ratio between the first orthographic projection and the second orthographic projection is greater than or equal to 0.1. This can prevent the gate drive circuit 180 from being too small in the second direction Y, which would result in the arrangement period of the shift register unit GOA being too small, thus causing the distance between multiple transistors in the shift register unit GOA to be too small, which could easily lead to malfunctions.

[0336] The ratio between the first orthographic projection and the second orthographic projection is less than or equal to 0.9, which can prevent the gate drive circuit 180 from being too large in the second direction Y, causing the size occupied by the gate drive circuit 180 in the peripheral area BB to be too large and thus interfering with the setting of the third signal line arrangement area B30.

[0337] In some of the embodiments described above, the gate drive signal is provided by the shift register unit GOA, while in other embodiments, the gate drive signal may also be provided by the gate drive chip.

[0338] Figure 18 This is a structural diagram of a display panel 100 according to some embodiments.

[0339] Please see Figure 18 The peripheral area BB is also provided with multiple grid line bonding pins 190, which are located on one or both sides of the display area AA. These multiple grid line bonding pins 190 are located within the grid line bonding area 191.

[0340] Please see Figure 17 In some examples, the overall span of the plurality of gate bonding pins 190 in the second direction Y is smaller than the overall span of the pixel S in the display area AA in the second direction Y.

[0341] In some examples, within the plane of the display panel 100, the third orthographic projection of the plurality of gate line bonding pins 190 onto the straight line containing a column of pixels S with the longest span is within the range of the second orthographic projection of the column of pixels S with the longest span onto the straight line containing it.

[0342] In some examples, the distribution period of the gate bonding pins 190 in the second direction Y on at least one side of the display area AA is less than the arrangement period of the sub-pixels S0 in the second direction Y.

[0343] In some examples, at least some of the gate line bonded pins 190 are arranged along a straight line.

[0344] In some embodiments, a common electrode lead COM is further included between the boundary of the display area AA and the signal line arrangement area closest to it. The signal line arrangement area closest to the boundary of the display area AA is either the first signal line arrangement area B10 or the second signal line arrangement area B20. In this case, the outline of the common electrode lead COM at least partially overlaps with the outer outline of its corresponding display area AA. Alternatively, a virtual sub-pixel S1 (e.g., ...) is included around the periphery of the display area AA. Figure 11 As shown), at least some of the common electrode leads COM are attached to the overall outer contour extension formed by the sub-pixel S0 and the virtual sub-pixel S1 in the display area AA.

[0345] Among them, such as Figure 11 As shown, when the display area AA includes virtual sub-pixels S1, there are multiple virtual sub-pixels S1, and multiple virtual sub-pixels S1 are arranged around the perimeter of the display area AA. At this time, each row of sub-pixels S0 has at least one virtual sub-pixel S1 at each end, and of course, each column of sub-pixels S0 also has at least one virtual sub-pixel S1 at each end.

[0346] In some examples, the pixel arrangement area includes the entirety of pixel S0 and all virtual sub-pixels S1. In other examples, the pixel arrangement area includes only pixel S0.

[0347] The outline of the common electrode lead COM at least partially is the same as the outer outline of its corresponding display area AA. This can be understood as the outline of the common electrode lead COM at least partially close to its corresponding display area AA being conformal to the outline of its corresponding display area AA.

[0348] The common electrode lead (COM) at least partially extends along the outer contour of the pixel arrangement area, which is beneficial for the compact setting of the display panel and reduces the display panel bezel.

[0349] In some embodiments, such as Figure 7 As shown, the minimum distance 'a' between the outer contour of display area AA and its closest signal line arrangement area is greater than or equal to 1. Specifically, necessary space is left between the display area AA and the signal line arrangement area closest to it to allow for the arrangement of virtual sub-pixels, common electrode traces, and signal line markers. The signal line arrangement area closest to the boundary of the display area AA is either the first signal line arrangement area B10 or the second signal line arrangement area B20.

[0350] Specifically, the substrate 120 includes a black matrix pattern 123, which includes a light-transmitting area. For example, the minimum distance 'a' between the outer contour of the display area AA and its closest signal line arrangement area can be understood as: the distance between the boundary of the signal line arrangement area closest to the center of the display panel on the side closest to the display area and the light-transmitting position of the light-transmitting area closest to the signal line arrangement area.

[0351] Figure 19 This is a structural diagram of a display panel 100 according to some embodiments.

[0352] Please see Figure 19 In some embodiments, the arrangement period P1 of pixels S in the first direction X is in the range of [60μm, 900μm], and the arrangement period P2 of pixels S in the second direction Y is in the range of [60μm, 900μm]. When the arrangement period P1 of pixels S in the first direction X approaches 60μm and the arrangement period P2 in the second direction Y approaches 60μm, the area of ​​pixels S can be made smaller, thereby resulting in a higher PPI (Pixels Per Inch) of the display panel 100.

[0353] When the arrangement period P1 of the pixel S in the first direction X approaches 900μm and the arrangement period P2 in the second direction Y approaches 900μm, the area of ​​the pixel S can be made larger and the manufacturing process of the display panel 100 can be made simpler.

[0354] The width P of sub-pixel S0 in the first direction X sub1 Within the range of [20μm, 900μm]. The width P of subpixel S0 in the second direction Y. sub2 Within the range of [20μm, 900μm].

[0355] Wherein, when the arrangement period P of sub-pixel S0 in the first direction X sub1 Approaching 20 μm, the arrangement period P in the second direction Y sub2 When the pixel size approaches 20μm, the area of ​​the sub-pixel S0 can be made smaller, thereby making the PPI of the display panel 100 higher.

[0356] When the arrangement period P of sub-pixel S0 in the first direction X sub1 Approaching 900 μm, the arrangement period P in the second direction Y sub2 The size is close to 900μm, which allows for a larger area of ​​sub-pixels S0 and simplifies the manufacturing process of the display panel 100. Specifically, a pixel S can include only one sub-pixel S0.

[0357] In some examples, P sub2 =3P sub1P sub2 =P2.

[0358] In some embodiments, the width W of the first signal line 161 data Within the range of [1μm, 20μm], this setting can avoid the width W of the first signal line 161. data If the width is too small (e.g., less than 1 μm), the manufacturing difficulty of the first signal line 161 increases. This, in turn, can reduce the likelihood of open circuits in the first signal line 161. Furthermore, it can avoid the width W of the first signal line 161 being too small. data If the width is too large (e.g., greater than 20μm), the width occupied by multiple first signal lines 161 will be too large, which in turn will result in the width of the first signal line arrangement area B10 being too large, and the width of the peripheral area BB of the display panel 100 being too large, which is not conducive to achieving a narrow bezel.

[0359] The spacing S of the first signal line 161 data Within the range of [1μm, 20μm], this setting can avoid the spacing S of the first signal line 161. data If the spacing is too small (e.g., less than 1 μm), the manufacturing process of the first signal line 161 becomes more difficult, potentially leading to short circuits between adjacent first signal lines 161. Furthermore, it can also prevent the spacing S of the first signal lines 161 from being too small. data If the width is too large (e.g., greater than 20μm), the width occupied by multiple first signal lines 161 will be too large, which in turn will result in the width of the second signal line arrangement area B20 being too large, and the width of the peripheral area BB of the display panel 100 being too large, which is not conducive to achieving a narrow bezel.

[0360] The width W of the second signal line 171 gate Within the range of [1μm, 20μm], this setting can avoid the width W of the second signal line 171. gate If the width is too small (e.g., less than 1 μm), the manufacturing difficulty of the second signal line 171 increases, which in turn reduces the likelihood of open circuits in the first signal line 161. Furthermore, it also avoids the width W of the second signal line 171 being too small. gate If the width is too large (e.g., greater than 20μm), the width occupied by multiple second signal lines 171 will be too large, which in turn will result in the width of the first signal line arrangement area B10 being too large, and the width of the peripheral area BB of the display panel 100 being too large, which is not conducive to achieving a narrow bezel.

[0361] The spacing S of the second signal line 171 gate Within the range of [1μm, 20μm]. This setting avoids the spacing S of the second signal line 171. gate If the spacing is too small (e.g., less than 1 μm), the manufacturing process of the second signal line 171 becomes more difficult, potentially leading to short circuits between adjacent second signal lines 171. Furthermore, it can also prevent the spacing S of the second signal lines 171 from being too small.gate If the width is too large (e.g., greater than 20μm), the width occupied by multiple second signal lines 171 will be too large, which in turn will result in the width of the second signal line arrangement area B20 being too large, and the width of the peripheral area BB of the display panel 100 being too large, which is not conducive to achieving a narrow bezel.

[0362] Please refer to it again. Figure 5A In some embodiments, the display panel 100 includes a data line binding area B40, which includes a plurality of data line binding pins 164; a first signal line 161 can be electrically connected to the corresponding data line binding pin 164. For example, the first signal line 161 is electrically connected to the data line binding pin 164 in a one-to-one correspondence.

[0363] In some examples, multiple data line bonding pins 164 in a data line bonding area B40 are electrically connected to a driver chip.

[0364] In some examples, there can be multiple data cable binding areas B40; in this case, multiple driver chips are also provided in the display panel 100. For example, there can be four data cable binding areas B40.

[0365] When the outer contour of the pixel arrangement area is circular, multiple data line binding areas B40 are symmetrically set with the straight line containing the pixel S with the longest span as the axis of symmetry.

[0366] For example, two data line binding areas B40 are provided on each side of the straight line containing the pixel S with the longest span.

[0367] Please see Figure 15 In some examples, the first signal line arrangement area B10 is located in the area CC1 between the non-display area between the gate drive circuit 180 and the display area AA in the peripheral area BB, and between the non-display area between the data line binding area B40 and the display area AA.

[0368] like Figure 15 As shown, in some examples, the second signal line arrangement area B20 is located in the area CC1 between the non-display area between the gate drive circuit 180 and the display area AA in the peripheral area BB, and between the non-display area between the data line binding area B40 and the display area AA.

[0369] Figure 15 The diagram illustrates at least part of the specific locations of the first signal line arrangement area B10 and the second signal line arrangement area B20 in the entire display panel. The first signal line arrangement area B10 and the second signal line arrangement area B20 are located within the area CC1 circled by the dashed ellipse. The first signal line arrangement area B10 and the second signal line arrangement area B20 in this area satisfy the wiring rules mentioned above.

[0370] Please refer to it again. Figure 18 The display panel 100 includes a data line binding area B40, which includes multiple data line binding pins 164; the first signal line 161 can be electrically connected to the corresponding data line binding pins 164.

[0371] The display panel 100 includes a wire bonding area 191, which includes a plurality of wire bonding pins 190. The second signal line 171 is electrically connected to the wire bonding pins 190 in a one-to-one correspondence.

[0372] The first signal line arrangement area B10 is located in the area CC2 between the non-display area between the gate wire binding area 191 and the display area AA in the peripheral area BB, and between the non-display area between the data line binding area B40 and the display area AA; the second signal line arrangement area B20 is located in the area CC2 between the non-display area between the gate wire binding area 191 and the display area AA in the peripheral area BB, and between the non-display area between the data line binding area B40 and the display area AA.

[0373] Figure 18 The diagram illustrates at least part of the specific locations of the first signal line arrangement area B10 and the second signal line arrangement area B20 in the entire display panel. The first signal line arrangement area B10 and the second signal line arrangement area B20 are located within the area CC2 circled by the dashed ellipse. The first signal line arrangement area B10 and the second signal line arrangement area B20 in this area satisfy the wiring rules mentioned above.

[0374] Figure 20 This is a structural diagram of a display module 1000 according to some embodiments.

[0375] refer to Figure 20 Some embodiments of this disclosure also provide a display module 1000, which includes the display panel 100 provided in the above embodiments. Therefore, the display module 1000 provided in some embodiments of this disclosure has all the beneficial effects of the display panel 100 provided in the above embodiments, which will not be elaborated here.

[0376] The display module 1000 also includes a first flexible circuit board 200, a driver chip 300, and a motherboard 400. One end of the first flexible circuit board 200 is bound to multiple data line binding pins 164 in the display panel 100, while the other end is bound to the motherboard 400. Furthermore, the flexible circuit board 200 may also include the driver chip 300, which can transmit data signals through the first flexible circuit board 200 to the first input line 163, the first signal line 161, the first output line 162, and the data line DT connected to the data line binding pins 164. Specifically, the motherboard 400 provides the necessary input signals to the driver chip 300, and the driver chip 300 generates the data signals required by the display panel 100 based on the signals provided by the motherboard 400 and sends them into the display panel 100.

[0377] In the case where the display panel 100 also includes gate line bonding pins 190, the display module 1000 also includes a second flexible circuit board. One end of the second flexible circuit board is bonded to multiple gate line bonding pins 190 in the display panel 100, and the other end is bonded to the motherboard 400. In addition, the second flexible circuit board is also provided with a gate driver chip. The gate driver chip can transmit gate drive signals through the second flexible circuit board to the second lead-in line 173, the second signal line 171, the second lead-out line 172, and the gate line GT connected to the gate line bonding pins 190. The motherboard 400 provides the necessary input signals to the gate driver chip. The gate driver chip generates the timing signals required by the display panel 100 according to the signals provided by the motherboard 400 and sends them into the display panel 100.

[0378] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

[0379] Without altering the inventive intent of this application, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples in the description of this specification. Furthermore, without altering the inventive intent of this application, the various examples and embodiments may be freely combined.

Claims

1. A display panel, comprising: A display area and a surrounding area, wherein the display area includes a plurality of pixels arranged in an array, the array extending along a first direction and a second direction respectively, and each pixel includes a plurality of sub-pixels arranged along the first direction, characterized in that... The surrounding area includes a first signal line arrangement area and a second signal line arrangement area arranged around the display area; the first signal line arrangement area includes multiple first signal lines extending in the same direction, and the second signal line arrangement area includes multiple second signal lines extending in the same direction; both the first signal line arrangement area and the second signal line arrangement area are elongated strips and include boundaries that are close to each other but do not overlap, and the boundaries extend in the same direction; The first signal line arrangement area near the boundary of the display area includes multiple first lead-out positions. Multiple first lead-out lines are led out from each of these positions and electrically connected to the multiple first signal lines. The first lead-out lines are electrically connected to data lines. One of the multiple first lead-out positions is a first reference lead-out position. A first reference lead-out line is led out from the first reference lead-out position and electrically connected to a first reference data line. The width of the first signal line arrangement area corresponding to the first reference lead-out position is b0. The width b of the first signal line arrangement area corresponding to at least partially and continuously distributed first target lead-out positions (excluding the first reference lead-out position) satisfies the following: b0-[int(kΔ1 / P1)](W data +S data )≤b≤b0-[int(kΔ1 / P1)-1](W data +S data ); in, P1 is the distance between the first target extraction position and the first reference extraction position in the first direction, P1 is the arrangement period of the pixels in the first direction, k is the number of sub-pixels in a pixel, and W is the distance between the first target extraction position and the first reference extraction position in the first direction. data S is the width of the first signal line. data The spacing between the first signal lines; The second signal line arrangement area near the boundary of the display area includes a plurality of second lead-out positions, and a plurality of second lead-out lines are led out from the plurality of second lead-out positions one by one and electrically connected to a plurality of second signal lines one by one; the second lead-out lines are electrically connected to the gate lines; at least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction.

2. The display panel according to claim 1, characterized in that, The first direction and the second direction are perpendicular; The extension directions of at least a portion of the first signal line arrangement area and at least a portion of the second signal line arrangement area are different from the first direction and the second direction.

3. The display panel according to claim 1, characterized in that, For the at least partially continuously distributed first target lead-out positions, the width b1 of the first signal line arrangement area corresponding to the first target lead-out position of the sub-pixel with the same color as the sub-pixel electrically connected to the first reference data line satisfies: b1=b0-[int(kΔ1 / P1)](W data +S data )。 4. The display panel according to claim 1, characterized in that, The at least partially continuous distribution of the first target lead-out positions includes three continuously distributed first target lead-out positions, each of which is electrically connected to one of the three sub-pixels of a pixel. The total width of the three first lead-out lines corresponding to the three continuously distributed first target lead-out positions is less than or equal to the arrangement period of a sub-pixel in the first direction.

5. The display panel according to claim 1, characterized in that, The plurality of second lead-out positions includes a second reference lead-out position, where a second reference lead-out line is led out and electrically connected to a second reference gate line; the width of the second signal line arrangement area corresponding to the second reference lead-out position is c0; among the at least partially continuous second target lead-out positions other than the second reference lead-out position, the width c of the second signal line arrangement area corresponding to each second target lead-out position satisfies: c0-[int(kΔ2 / P1)+1](W gate +S gate )≤c≤c0-[int(kΔ2 / P1)-1](W gate +S gate ), in, W is the distance between the second target lead-out position and the second reference lead-out position in the first direction. gate S is the width of the second signal line. gate The spacing of the second signal line.

6. The display panel according to claim 5, characterized in that, The distance between the first reference lead-out position and the second reference lead-out position in the first direction is less than one arrangement period of the pixel in the first direction X; The at least partially continuous second target lead-out positions and the at least partially continuous first target lead-out positions are alternately distributed in the first direction.

7. The display panel according to claim 6, characterized in that, In the at least partially continuous distribution of the first target lead-out positions, m second target lead-out positions are respectively set on both sides of every three first target lead-out positions, where m is one of the three values ​​of 4, 5, and 6.

8. The display panel according to claim 7, characterized in that, The three first target lead-out positions are arranged at equal intervals, and the m second target lead-out positions are arranged at equal intervals. The distance between the three first target lead-out positions is greater than the distance between the m second target lead-out positions.

9. The display panel according to claim 7, characterized in that, The three first target lead-out positions are arranged at equal intervals, and the m second target lead-out positions are arranged at equal intervals. The width occupied by the three first target lead-out positions in the first direction is less than the width occupied by the m second target lead-out positions in the first direction.

10. The display panel according to claim 1, characterized in that, The angle between the first lead and the first signal line electrically connected thereto is greater than or equal to 90 degrees; the angle between the second lead and the second signal line electrically connected thereto is greater than or equal to 90 degrees.

11. The display panel according to claim 1, characterized in that, The plurality of second lead-out positions includes a second reference lead-out position, where a second reference signal line is led out and electrically connected to a second reference gate line; the width of the second signal line arrangement area corresponding to the second reference lead-out position is c0; among the at least partially continuous second target lead-out positions other than the second reference lead-out position, the width c of the second signal line arrangement area corresponding to each second target lead-out position satisfies: c0-[int(Δ3 / P sub2 )+1](W gate +S gate )≤c≤c0-[int(Δ3 / P sub2 )-1](W gate +S gate ), in, P is the distance between the second target lead-out position and the second reference lead-out position in the second direction. sub2 W represents the arrangement period of sub-pixel S0 in the second direction. gate S is the width of the second signal line. gate The spacing of the second signal line.

12. The display panel according to claim 11, characterized in that, For the at least partially continuously distributed second target lead-out positions, the width c1 of the corresponding second signal line arrangement area of ​​a second lead-out position electrically connected to a target gate line spaced an odd number of gate lines apart from the second reference gate line satisfies: c1=c0-[int(Δ3 / P sub2 )](W gate +S gate )。 13. The display panel according to claim 11, characterized in that, The width c satisfies: c=c0-[int(Δ3 / P sub2 )](W gate +S gate )。 14. The display panel according to claim 11, characterized in that, The width b satisfies: b=b0-[int(kΔ1 / P1)](W gate +S gate ), Wherein, P1 is the arrangement period of the pixels in the first direction.

15. The display panel according to any one of claims 1-14, characterized in that, The first signal line arrangement area is closer to the display area than the second signal line arrangement area; or, the second signal line arrangement area is closer to the display area than the first signal line arrangement area.

16. The display panel according to claim 15, characterized in that, When the second signal line arrangement area is closer to the display area than the first signal line arrangement area, and the first lead-out line is led out along the second direction, the included angle θ1 between the first signal line arrangement area adjacent to the second signal line arrangement area and the second signal line arrangement area adjacent to the first signal line arrangement area satisfies: sinθ1=[I1(W data +S data )cosα1] / P1, Wherein, α1 is the angle between the second signal line in the second signal line arrangement area adjacent to the first signal line arrangement area and the first direction; I1 is the number of first target lead-out positions corresponding to the arrangement period range of a pixel in the first direction; and P1 is the arrangement period of the pixel in the first direction.

17. The display panel according to any one of claims 5-9 and 11-14, characterized in that, The first signal line arrangement area is closer to the display area than the second signal line arrangement area, and the second lead-out line extends along the second direction; the included angle θ2 between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the second signal line in the second signal line arrangement area adjacent to the first signal line arrangement area satisfies: sinθ2=[I2(W gate +S gate )coxα2] / P1, Wherein, α2 is the angle between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the first direction; I2 is the number of second target lead-out positions corresponding to the arrangement period range of a pixel in the first direction; and P1 is the arrangement period of the pixel in the first direction.

18. The display panel according to any one of claims 5-9 and 11-14, characterized in that, The first signal line arrangement area is closer to the display area than the second signal line arrangement area, and the second lead-out line extends along the first direction; the angle θ3 between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the second signal line in the second signal line arrangement area adjacent to the first signal line arrangement area satisfies: sinθ3=[I3(W gate +S gate )sinα3] / P2, Wherein, α3 is the angle between the first signal line in the first signal line arrangement area adjacent to the second signal line arrangement area and the first direction; I3 is the number of second target lead-out positions corresponding to the arrangement period range of a pixel in the second direction, and P2 is the arrangement period of a pixel in the second direction.

19. The display panel according to claim 15, characterized in that, The second signal line arrangement area is closer to the display area than the first signal line arrangement area. The angle θ between the first signal line arrangement area adjacent to the second signal line arrangement area and the second signal line arrangement area adjacent to the first signal line arrangement area has a range of 1° to 5°.

20. The display panel according to any one of claims 1 to 14, 16, and 19, characterized in that, The width of the first lead is greater than the width of the first signal line connected to it; and / or, the width of the second lead is greater than the width of the second signal line connected to it.

21. The display panel according to any one of claims 1 to 14, 16, and 19, characterized in that, The display panel includes a gate driving circuit located in the non-display area. The gate driving circuit has a plurality of shift register units, at least a portion of which are electrically connected to a gate line for sending a gate driving signal to the gate line. The overall span of the plurality of shift register units in the second direction is smaller than the overall span of the pixels in the display area in the second direction.

22. The display panel according to claim 21, characterized in that, The display area includes a column of pixel units with the longest span. In the plane where the display panel is located, the first orthographic projection of the plurality of shift register units on the straight line where the column of pixels with the longest span is located is within the range of the second orthographic projection of the column of pixels with the longest span on the straight line where it is located.

23. The display panel according to claim 21, characterized in that, The distribution period of the shift register units distributed on at least one side of the display area is less than the distribution period of the sub-pixels in the second direction.

24. The display panel according to claim 21, characterized in that, The distribution contour of the shift register units on at least one side of the display area is the same as the outer contour of the display area on the corresponding side.

25. The display panel according to claim 22, characterized in that, The ratio between the first orthographic projection and the second orthographic projection is in the range of [0.1, 0.9].

26. The display panel according to claim 22, characterized in that, The plurality of shift register units are located on both sides of the display area.

27. The display panel according to any one of claims 1 to 14, 16, characterized in that, A common electrode lead is also included between the boundary of the display area and the signal line arrangement area closest to it. The signal line arrangement area closest to the boundary of the display area is either the first signal line arrangement area or the second signal line arrangement area. The outline of the common electrode lead at at least partially locations is the same as the outer outline of the corresponding display area, or... The periphery of the display area includes virtual sub-pixels, and at least some of the common electrode leads are attached to the overall outer contour formed by the sub-pixels in the display area and the virtual sub-pixels.

28. The display panel according to any one of claims 1 to 14, 16, characterized in that, The minimum distance 'a' between the outer contour of the display area and the nearest signal line arrangement area is greater than or equal to 1. The signal line arrangement area closest to the outer contour of the display area is either the first signal line arrangement area or the second signal line arrangement area, and P2 is the arrangement period of one pixel in the second direction.

29. The display panel according to any one of claims 1 to 14, 16, characterized in that, The arrangement period P1 of the pixels in the first direction is in the range of [60μm, 900μm]; the arrangement period P2 of the pixels in the second direction is in the range of [60μm, 900μm]. Width P of subpixel in the first direction sub1 Within the range of [20μm, 900μm]; the width P of the sub-pixel in the second direction sub2 Within the range of [20μm, 900μm].

30. The display panel according to any one of claims 1 to 14, 16, characterized in that, The width W of the first signal line data Within the range of [1μm, 20μm]; the spacing S of the first signal line data Within the range of [1μm, 20μm]; The width W of the second signal line gate Within the range of [1μm, 20μm]; the spacing S of the second signal line gate Within the range of [1μm, 20μm].

31. The display panel according to any one of claims 1 to 14, 16, characterized in that, The first reference lead-out position is the first lead-out position closest to the widest point of the first signal line arrangement area.

32. The display panel according to any one of claims 5-9 and 11-14, characterized in that, The second reference lead-out position is the second lead-out position closest to the widest point of the second signal line arrangement area.

33. The display panel according to claim 21, characterized in that, The display panel includes a data line binding area, which includes multiple data line binding pins. The first signal line is electrically connected to each of the data line binding pins. The first signal line arrangement area is located in the non-display area between the gate driving circuit and the display area in the peripheral area, and in the non-display area between the data line binding area and the display area; The second signal line arrangement area is located in the area between the non-display area between the gate driving circuit and the display area in the peripheral area, and between the non-display area between the data line binding area and the display area.

34. The display panel according to claim 1, characterized in that, The display panel includes a data line binding area, which includes multiple data line binding pins. The first signal line is electrically connected to each of the data line binding pins. The display panel includes a grid line bonding area, which includes a plurality of grid line bonding pins, and the second signal line is electrically connected to the grid line bonding pins one by one; The first signal line arrangement area is located in the non-display area between the gate line binding area and the display area in the peripheral area, and in the non-display area between the data line binding area and the display area; The second signal line arrangement area is located in the non-display area between the gate wire binding area and the display area in the peripheral area, and in the non-display area between the data line binding area and the display area.

35. A display module, characterized in that, include: The display panel according to any one of claims 1-34.

Images