Three-dimensional high-integration MOS transistor and its manufacturing method

Abstract

The present invention provides a three-dimensional highly integrated MOS transistor and a preparation method thereof, wherein the MOS transistor comprises: a three-dimensional substrate, a plurality of devices spaced apart on the outer surface of the three-dimensional substrate, and an interconnection dielectric layer covering the device surface and the three-dimensional substrate surface; the device is a PMOS tube or an NMOS tube; the interconnection dielectric layer has at least a plurality of interconnection metals fixed inside, and the drains of the devices, the sources of the devices, and the gates of the devices are connected correspondingly through the interconnection metals. The MOS transistor in the present invention effectively solves the heat dissipation problem of the MOS transistor by improving the structure of the substrate, increases the integration of the MOS transistor, and fully improves the power density and current density of the MOS transistor, so that high-power MOS transistors can be applied to a wider range of scenarios.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a three-dimensional highly integrated MOS transistor and a preparation method thereof. Background Art

[0002] The third generation of semiconductors, gallium nitride and silicon carbide, are important semiconductor materials for preparing power device substrates. They have a larger bandgap and a higher breakdown electric field, and can produce devices with high withstand voltage, high current and high stability. In recent years, due to the high voltage and high current handling capabilities of power devices using third generation semiconductor substrates, newer MOS transistors have shown great potential in high-efficiency power switching applications.

[0003] Although MOS transistors have made significant progress, the problem of poor heat dissipation performance has not yet been solved. The lattice mismatch and thermal mismatch between different materials of MOS transistors are high, and the device integration is limited, making it difficult to achieve high power density and current density, and the performance is difficult to meet expectations. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a three-dimensional highly integrated MOS transistor and a preparation method thereof, aiming to solve the problems of poor heat dissipation performance and low integration of the MOS transistor.

[0005] To solve the above technical problems, the present invention is implemented as follows: a three-dimensional high-integration MOS transistor comprises: a three-dimensional substrate, a plurality of devices arranged at intervals on the outer surface of the three-dimensional substrate, and an interconnection dielectric layer covering the surface of the device and the surface of the three-dimensional substrate;

[0006] The device is a PMOS tube or an NMOS tube; the interconnection dielectric layer has at least a plurality of interconnection metals fixed inside, and the drains of the devices, the sources of the devices and the gates of the devices are connected correspondingly through the interconnection metals.

[0007] Further, the device is a PMOS tube, which includes a first dielectric layer arranged on the surface of the three-dimensional substrate, a GaN buffer layer arranged on the side of the first dielectric layer away from the three-dimensional substrate, a GaN channel layer arranged on the side of the GaN buffer layer away from the first dielectric layer, two p-GaN layers arranged at intervals on the side of the GaN channel layer away from the GaN buffer layer, a source arranged on the surface of one of the p-GaN layers, a drain arranged on the surface of the other p-GaN layer, a gate arranged on the side of the GaN channel layer away from the GaN buffer layer, and an insulating dielectric layer that at least isolates the GaN channel layer and the gate.

[0008] Furthermore, the three-dimensional substrate is in the shape of a sphere, a polyhedron or a cylinder.

[0009] Furthermore, the three-dimensional substrate is a diamond or boron nitride substrate.

[0010] Furthermore, the three-dimensional substrate is in the shape of a sphere, and the diameter of the sphere is 50-60 μm;

[0011] Or, the three-dimensional substrate is in the shape of a polyhedron, and the diameter of the circumscribed sphere corresponding to the polyhedron is 50-60 μm;

[0012] Alternatively, the three-dimensional substrate is in the shape of a cylinder, the diameter of the cylinder is 50-60 μm, and the height is 50-60 μm.

[0013] Furthermore, the material of the first dielectric layer is AlN, SiO 2 or Si 3 N 4 In any one of the embodiments, the thickness of the first dielectric layer is 20-50 nm.

[0014] Furthermore, the dopant of the GaN buffer layer is C, and the doping concentration is 2×10 18 cm -3 , the thickness of the GaN buffer layer is 10-40 μm;

[0015] The dopant of the GaN channel layer is Si, and the doping concentration is 2×10 16 cm -3 ~5×10 16 cm -3 , the thickness of the GaN channel layer is 5-20 μm;

[0016] The dopant of each p-GaN layer is Mg, and the doping concentration is 1.2×10 19 cm -3 ~5×10 19 cm -3 .

[0017] Furthermore, the interconnect dielectric layer has at least multiple layers;

[0018] The gates of the devices are interconnected through the interconnection metal on the outermost layer of the interconnection dielectric layer;

[0019] The sources and drains of the devices are interconnected through the interconnection metals on different layers except the outermost layer on the interconnection dielectric layer.

[0020] Furthermore, the material of the interconnect dielectric layer is AlN, SiO 2 or Si 3 N 4In any one of the embodiments, the thickness of each layer of the interconnect dielectric layer is 1-5 μm.

[0021] A second aspect of the present invention provides a method for preparing a three-dimensional highly integrated MOS transistor, comprising the steps of:

[0022] Prepare a three-dimensional substrate, grow a first dielectric layer on the outer surface of the three-dimensional substrate, grow a GaN buffer layer on the surface of the first dielectric layer, grow a GaN channel layer on the surface of the GaN buffer layer away from the first dielectric layer, and arrange a plurality of device areas at intervals on the outer surface of the three-dimensional substrate;

[0023] Etching the first dielectric layer, the GaN buffer layer, and the GaN channel layer in a non-device area on the three-dimensional substrate to expose the non-device area of ​​the three-dimensional substrate;

[0024] Implanting ions into the GaN channel layer on each device region on a side away from the GaN buffer layer to form two p-GaN layers spaced apart from each other;

[0025] On each of the device regions, a drain electrode is grown on the surface of one of the p-GaN layers, and a source electrode is grown on the surface of another of the p-GaN layers;

[0026] An insulating dielectric layer is grown on the side of the GaN channel layer on each device region away from the GaN buffer layer, the insulating dielectric layer at least covers a portion of the GaN channel layer, and a gate is grown on the side of the insulating dielectric layer away from the GaN channel layer, so that a plurality of devices are correspondingly formed on the plurality of device regions of the three-dimensional substrate;

[0027] An interconnect dielectric layer is grown on each of the devices and on the exposed non-device areas of the three-dimensional substrate; holes are etched on the interconnect dielectric layer at positions corresponding to the source, the drain and the gate, and interconnect metal is grown on the interconnect dielectric layer and at the holes to enable corresponding connections between the sources, the drains and the gates of the devices.

[0028] Compared with the prior art, the three-dimensional highly integrated MOS transistor and the preparation method thereof in the present invention have the following beneficial effects:

[0029] (1) The three-dimensional substrate provides a better heat dissipation effect for the MOS transistor, which can effectively solve the heat dissipation problem of the MOS transistor; (2) On the basis of the better heat dissipation effect provided by the three-dimensional substrate, a number of devices can be integrated on the MOS transistor, and the source, drain, and gate of each device are connected correspondingly through interconnect metal, which fully improves the power density and current density of the MOS transistor and effectively improves the performance of the MOS transistor; (3) The interconnect metal is fixed to at least the inside of the interconnect dielectric layer, and the interconnect dielectric layer covers the outermost layer of the MOS transistor. The interconnect metal can be led out through the metal wire by etching the interconnect dielectric layer, so that the MOS transistor that can output large current can be further integrated into various application scenarios, greatly expanding the application scope of the MOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic partial cross-sectional diagram after each process in step S100 in embodiment 2 of the present invention is completed;

[0031] Figure 2 is a schematic partial cross-sectional diagram after each process in step S200, step S300 and step S400 in embodiment 2 of the present invention is completed;

[0032] Figure 3 is a schematic partial cross-sectional diagram after each process in step S500 in embodiment 2 of the present invention is completed;

[0033] Figure 4 It is a partial cross-sectional schematic diagram of the PMOS tube in Example 1 of the present invention and a schematic partial cross-sectional schematic diagram after each process in Example 2 is completed.

[0034] Figure 5 It is a schematic cross-sectional view of a three-dimensional local structure of a PMOS tube in Embodiment 1 of the present invention.

[0035] In the accompanying drawings, each figure mark represents: 1. three-dimensional substrate; 2. first dielectric layer; 3. GaN buffer layer; 4. GaN channel layer; 5. p-GaN layer; 6. source; 7. drain; 8. gate; 9. interconnection metal; 10. insulating dielectric layer; 11. interconnection dielectric layer. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0037] Example 1

[0038] See also Figures 4 and 5, a three-dimensional high-integration MOS transistor, comprising: a three-dimensional substrate 1, a plurality of devices spaced apart on the outer surface of the three-dimensional substrate 1, and an interconnect dielectric layer 11 covering the surface of the device and the surface of the three-dimensional substrate 1;

[0039] The device is a PMOS tube or an NMOS tube; the interconnection dielectric layer 11 has at least a plurality of interconnection metals 9 fixed therein, and the drains 7 of the devices, the sources 6 of the devices, and the gates 8 of the devices are connected one by one through the interconnection metals 9 .

[0040] It should be known that the three-dimensional substrate 1 has a certain thickness in three-dimensional directions, preferably the thickness in each direction is equal, and a plurality of devices are preferably integrated on the surface of the three-dimensional substrate 1 at uniform intervals.

[0041] Among the devices on the surface of the three-dimensional substrate 1, the gates 8, the sources 6, and the drains 7 of at least two devices are connected by interconnecting metal 9 to form a group of integrated NMOS or PMOS. Different groups of integrated NMOS or PMOS can be integrated into other identical or different circuits. In this embodiment, Figure 4 The partial cross-sectional view of the MOS transistor shown only provides an example of integrating two devices on the three-dimensional substrate 1. In other embodiments, the MOS transistor may also integrate multiple groups of devices.

[0042] The interconnection metal 9 is used to provide electrical connection conditions between the source electrodes 6 , the drain electrodes 7 , and the gate electrodes 8 of each device, and the interconnection dielectric layer 11 can provide a platform for the interconnection metal 9 to adhere.

[0043] The interconnection dielectric layer 11 can be a single layer or multiple layers. The devices can be interconnected by setting interconnection metals 9 on the surface of the interconnection dielectric layer 11 at different levels, or they can be interconnected by only one layer of the interconnection dielectric layer 11. However, the basic condition is that the interconnection metals 9 used for interconnecting the source electrodes 6, the interconnection metals 9 used for interconnecting the drain electrodes 7, and the interconnection metals 9 used for interconnecting the gate electrodes 8 cannot cross or contact each other. In the case of a large number of integrated devices, it is difficult to avoid the crossing and contact of the three when the interconnection dielectric layer 11 has only one layer. Therefore, it is preferred that the interconnection dielectric layer 11 has multiple layers.

[0044] In this embodiment, the three-dimensional highly integrated MOS transistor has the following advantages: (1) the three-dimensional structure of the substrate is used to provide a better heat dissipation effect for the MOS transistor, which can effectively solve the heat dissipation problem of the MOS transistor; (2) on the basis of the better heat dissipation effect provided by the three-dimensional substrate 1, a plurality of devices can be integrated on the MOS transistor, and the source 6, the drain 7, and the gate 8 of each device are correspondingly connected through the interconnection metal 9, which fully improves the power density and current density of the MOS transistor and effectively improves the performance of the MOS transistor; (3) the interconnection metal 9 is fixed to at least the inside of the interconnection dielectric layer 11, and the interconnection dielectric layer 11 covers the outermost layer of the MOS transistor. The interconnection metal 9 can be led out through the metal wire by etching the interconnection dielectric layer 11, so that the MOS transistor capable of outputting a large current can be further integrated into various application scenarios, greatly expanding the application scope of the MOS transistor.

[0045] Furthermore, the device is a PMOS tube, and the device includes a first dielectric layer 2 arranged on the surface of a three-dimensional substrate 1, a GaN buffer layer 3 arranged on the side of the first dielectric layer 2 away from the three-dimensional substrate 1, a GaN channel layer 4 arranged on the side of the GaN buffer layer 3 away from the first dielectric layer 2, two p-GaN layers 5 arranged at intervals on the side of the GaN channel layer 4 away from the GaN buffer layer 3, a source 6 arranged on the surface of one p-GaN layer 5, a drain 7 arranged on the surface of the other p-GaN layer 5, a gate 8 arranged on the side of the GaN channel layer 4 away from the GaN buffer layer 3, and an insulating dielectric layer 10 that at least isolates the GaN channel layer 4 and the gate 8.

[0046] It should be known that MOS tubes include NMOS tubes and PMOS tubes. NMOS tubes refer to MOS tubes with p-type substrates and n-channels, which carry current by the flow of holes. PMOS tubes refer to MOS tubes with n-type substrates and p-channels, which carry current by the flow of holes.

[0047] In this embodiment, when the MOS tube is a PMOS tube, a gallium nitride substrate is used, and the first dielectric layer 2 forms a buffer layer between the three-dimensional substrate 1 and the GaN buffer layer 3, which can reduce the stress caused by the lattice mismatch between the three-dimensional substrate 1 and the GaN buffer layer 3 and the different thermal expansion coefficients, thereby improving the quality and integrity of the GaN buffer layer 3.

[0048] The insulating dielectric layer 10 is a gate oxide that separates the gate 8 from the source 6 and drain 7 near the gate 8, and also separates the gate 8 from the conductive path connecting the source 6 and drain 7 on the GaN channel layer 4 when the PMOS is turned on. In this embodiment, the insulating dielectric layer 10 is a layer of Al2O3 with a thickness of 50-80 nm. 2 O 3 .

[0049] The substrate is a three-dimensional substrate 1, which makes the heat dissipation effect of the PMOS tube better, effectively solves the defect that the gallium nitride-based PMOS tube cannot be highly integrated due to thermal limitations, makes the integration of the PMOS tube reach a new height, and greatly improves the performance of the MOS transistor.

[0050] In other embodiments, when the MOS device is an NMOS tube, the gallium nitride substrate in the PMOS can be replaced with a p-type silicon substrate, such as a SiC substrate, and a high-doping concentration n region can be formed on the silicon substrate. The insulating dielectric layer 10 on the surface of the NMOS tube can be SiO 2 .

[0051] Furthermore, the three-dimensional substrate 1 is in the shape of a sphere, a polyhedron or a cylinder. Figure 5 The figure shows an example in which the three-dimensional substrate 1 is a sphere in this embodiment.

[0052] Furthermore, the three-dimensional substrate 1 is spherical, and the diameter of the sphere is 50-60 μm;

[0053] Or, the three-dimensional substrate 1 is in the shape of a polyhedron, and the diameter of the circumscribed sphere corresponding to the polyhedron is 50-60 μm;

[0054] Alternatively, the three-dimensional substrate 1 is in a cylindrical shape, with a diameter of 50-60 μm and a height of 50-60 μm.

[0055] It should be understood that those skilled in the art can prepare the three-dimensional substrate 1 by microwave plasma chemical deposition and other methods. The particle size of the three-dimensional substrate 1 is at the micron level, which greatly reduces the device size and is conducive to the miniaturization of PMOS. A spherical three-dimensional substrate 1 is preferably used for preparation and surface treatment.

[0056] Furthermore, the three-dimensional substrate 1 is a diamond or boron nitride substrate.

[0057] The thermal conductivity of the substrate materials commonly used in power devices (sapphire, silicon, silicon carbide) is low, which greatly limits the demand for device heat dissipation and high-power performance. Diamond and boron nitride are both heat dissipation materials with high thermal conductivity and low thermal expansion coefficient. The use of high thermal conductivity diamond or boron nitride heat dissipation substrates can meet the heat dissipation requirements of PMOS under high power and realize the application of high-power PMOS.

[0058] Furthermore, the material of the first dielectric layer is AlN, SiO 2 or Si 3 N 4 In any one of the above embodiments, the thickness of the first dielectric layer is 20-50 nm.

[0059] Specifically, the first dielectric layer 2 is used as a buffer layer between the three-dimensional substrate 1 and the GaN buffer layer 3, and AlN, SiO 2 or Si3 N 4 Any of the materials can alleviate the stress caused by the lattice mismatch and different thermal expansion coefficients between the three-dimensional substrate 1 and the GaN buffer layer 3. At the same time, these materials have excellent thermal conductivity and strong thermal stability, which greatly improves the heat dissipation capacity of the MOS transistor.

[0060] Furthermore, the dopant of the GaN buffer layer 3 is C, and the doping concentration is 2×10 18 cm -3 , the thickness of the GaN buffer layer 3 is 10~40μm;

[0061] The dopant of the GaN channel layer 4 is Si, and the doping concentration is 2×10 16 cm -3 ~5×10 16 cm -3 , the thickness of the GaN channel layer 4 is 5 to 20 μm;

[0062] The dopant of each p-GaN layer 5 is Mg, and the doping concentration is 1.2×10 19 cm -3 ~5×10 19 cm -3 .

[0063] Further, the interconnect dielectric layer 11 has at least multiple layers;

[0064] The gates 8 of the devices are interconnected through the interconnection metal 9 on the outermost layer of the interconnection dielectric layer 11;

[0065] The source electrodes 6 and the drain electrodes 7 of each device are interconnected through interconnection metals 9 on different layers of the interconnection dielectric layer 11 except the outermost layer.

[0066] The main purpose of setting up multiple interconnection dielectric layers 11 is to ensure that the interconnection metals 9 of the source 6, the drain 7 and the gate 8 will not cross each other on the surface of the same interconnection dielectric layer 11. When multiple devices are integrated on the three-dimensional substrate 1, only setting up one interconnection dielectric layer 11 cannot completely ensure that the interconnection metals 9 connecting the source 6, the drain 7, and the gate 8 will not cross each other.

[0067] Furthermore, the material of the interconnect dielectric layer 11 is AlN, SiO 2 or Si 3 N 4 In any one of the above, the thickness of each layer of the interconnect dielectric layer 11 is 1-5 μm.

[0068] The interconnect dielectric layer 11 is on the outermost side of the MOS transistor, and AlN, SiO 2 or Si 3 N 4The interconnect dielectric layer 11 made of the materials plays the role of isolating various devices, supporting the interconnect metal 9 and dissipating heat. These materials have excellent thermal conductivity and strong thermal stability, which is beneficial to the heat dissipation of PMOS.

[0069] Here, an embodiment is provided, as shown in Figures 4 and 5, a three-dimensional substrate made of spherical diamond material with a diameter of 50 μm and an outer surface roughness of less than 0.3 nm is selected, and a plurality of PMOS tubes are arranged at intervals on the outer surface of the three-dimensional substrate.

[0070] The PMOS tube includes:

[0071] The first dielectric layer AlN layer disposed on the surface of the three-dimensional substrate 1 has a thickness of 30 nm; the GaN buffer layer 3 disposed on the side of the first dielectric layer 2 away from the three-dimensional substrate 1 has a thickness of 20 μm, and C is used as a dopant with a doping concentration of 2×10 18 cm -3 The GaN channel layer 4 is disposed on the side of the GaN buffer layer 3 away from the first dielectric layer 2, and Si is used as a dopant with a doping concentration of 2×10 16 cm -3 ~5×10 16 cm -3 ; Two p-GaN layers 5 are arranged at intervals on the side of the GaN channel layer 4 away from the GaN buffer layer 3, and Mg is used as a dopant with a doping concentration of 1.2×10 19 cm -3 ~2×10 19 cm -3 ; a source electrode 6 disposed on the surface of a p-GaN layer 5, the source electrode 6 is a stacked metal Ti (25 nm) / Au (75 nm) or Ti (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm); a drain electrode 7 disposed on the surface of another p-GaN layer 5, the drain electrode 7 is a stacked metal Ti (25 nm) / Au (75 nm) or Ti (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm); a gate electrode 8 disposed on the GaN channel layer 4 away from the GaN buffer layer 3, the gate electrode 8 is a stacked metal (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm); at least the insulating dielectric layer 10 isolating the GaN channel layer 4 and the gate electrode 8 is Al 2 O 3 layer with a thickness of 50~80nm.

[0072] The interconnect dielectric layer 11 has three layers, and an AlN layer is selected. The interconnect metal 9 between the source electrodes 6 of each device is fixed to the innermost layer of the interconnect dielectric layer 11, the interconnect metal 9 between the drain electrodes 7 of each device is fixed to the middle layer of the interconnect dielectric layer 11, and the interconnect metal 9 between the gate electrodes 8 of each device is fixed to the outermost layer of the interconnect dielectric layer 11. The thickness of each layer is 2 μm. The interconnect metal 9 is made of Au material.

[0073] The typical feature of this PMOS transistor is that it uses a spherical diamond substrate to epitaxially grow a gallium nitride base, and ions are implanted into the GaN channel layer 4 to form multiple p-GaN layers 5. It has obvious advantages. It utilizes the extremely high thermal conductivity of the spherical diamond three-dimensional substrate 1 to effectively solve the problem of device heat dissipation. The source electrodes 6, drain electrodes 7, and gate electrodes 8 of several devices on each spherical diamond three-dimensional substrate 1 are electrically connected to each other, which fully improves the power density and current density. The electrodes are connected by an interconnecting metal 9 to facilitate the lead-out of gold wires. The transistor can be integrated into other circuits to output large currents, and has a variety of application scenarios.

[0074] Example 2

[0075] like Figures 1 to 4 As shown, the method for preparing a three-dimensional highly integrated MOS transistor comprises the steps of:

[0076] S100: preparing a three-dimensional substrate 1, growing a first dielectric layer 2 on the outer surface of the three-dimensional substrate 1, growing a GaN buffer layer 3 on the surface of the first dielectric layer 2, growing a GaN channel layer 4 on the surface of the GaN buffer layer 3 away from the first dielectric layer 2, and the outer surface of the three-dimensional substrate 1 is provided with a plurality of device regions at intervals;

[0077] S200: etching the first dielectric layer 2, the GaN buffer layer 3 and the GaN channel layer 4 in the non-device region on the three-dimensional substrate 1 to expose the non-device region of the three-dimensional substrate 1;

[0078] S300: ion implantation is performed on the side of the GaN channel layer 4 on each device region away from the GaN buffer layer 3 to form two p-GaN layers 5 spaced apart from each other;

[0079] S400: On each device region, a drain electrode 7 is grown on the surface of a p-GaN layer 5, and a source electrode 6 is grown on the surface of another p-GaN layer 5; an insulating dielectric layer 10 is grown on the side of the GaN channel layer 4 on each device region away from the GaN buffer layer 3, the insulating dielectric layer 10 at least covers a portion of the GaN channel layer 4, and a gate electrode 8 is grown on the side of the insulating dielectric layer 10 away from the GaN channel layer 4, so that a plurality of devices are correspondingly formed on a plurality of device regions of the three-dimensional substrate 1;

[0080] S500: growing an interconnect dielectric layer 11 on each device and the exposed non-device area on the three-dimensional substrate 1; etching openings on the interconnect dielectric layer 11 at positions corresponding to the source 6, the drain 7 and the gate 8, and growing interconnect metal 9 on the interconnect dielectric layer 11 and at the openings to connect the source 6, the drain 7 and the gate 8 of the device accordingly.

[0081] Specifically, Figure 1 As shown, step S100 includes:

[0082] S110: preparing spherical diamonds with a diameter of 50 to 60 μm by microwave plasma chemical vapor deposition, performing three-dimensional dynamic friction polishing on the spherical diamonds to make the surface roughness of the spherical diamonds less than 0.3 nm, and performing ultrasonic cleaning on the spherical diamonds to remove surface impurities to obtain a three-dimensional substrate 1, wherein a plurality of device regions are arranged at intervals on the outer surface of the three-dimensional substrate 1;

[0083] S120: growing a first dielectric layer 2 of 20-50 nm on the outer surface of the spherical diamond by vacuum interconnected magnetron sputtering or atomic layer deposition, wherein the thickness of the first dielectric layer 2 is preferably 30 nm;

[0084] S130: growing a GaN buffer layer 3 with a thickness of 10 to 40 μm on the surface of the first dielectric layer 2 by hydride vapor phase epitaxy, molecular beam epitaxy or metal organic chemical vapor deposition, wherein the thickness of the GaN buffer layer 3 is preferably 20 μm;

[0085] like Figure 2 As shown, step 200 includes:

[0086] The first dielectric layer 2 , the GaN buffer layer 3 and the GaN channel layer 4 in the non-device region on the three-dimensional substrate 1 are removed by dry etching and wet etching to expose the non-device region of the three-dimensional substrate 1 .

[0087] like Figure 2 As shown, step S300 includes:

[0088] In each device region, ion implantation is performed on the GaN channel layer 4 by photolithography and ion implantation to form two p-GaN layers 5 spaced apart from each other.

[0089] like Figure 2 As shown, step S400 includes:

[0090] S410: In each device region, Al is grown on the side of the GaN channel layer 4 away from the GaN buffer layer 3 by plasma enhanced chemical vapor deposition or atomic layer deposition. 2 O 3 , forming an insulating dielectric layer 10, using photolithography and ICP (SF 6) etching process to partially open holes in the two p-GaN layers 5;

[0091] S420: Layered metal Ti (25 nm) / Au (75 nm) or Ti (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm) is deposited at the openings of the two p-GaN layers 5 by thermal evaporation, magnetron sputtering or electron beam evaporation to form a drain 7 and a source 6 on the two p-GaN layers 5, respectively. 2 Annealing in an environment to form a better ohmic contact;

[0092] S430: On the side of the insulating dielectric layer 10 away from the GaN channel layer 4, a stacked metal gate Ti (25 nm) / Al (75 nm) / Ni (25 nm) / Au (75 nm) is evaporated by photolithography and evaporation process, and the gate is formed after gold is removed. 2 Annealing is performed in an environment to form a better ohmic contact, and a plurality of devices are correspondingly formed on a plurality of device regions of the three-dimensional substrate 1 .

[0093] like Figure 3~4 As shown, step S500 includes:

[0094] S510: growing 1-5 μm AlN on each device and filling the exposed non-device area on the three-dimensional substrate 1, flattening the spherical surface to form a flat interconnect dielectric layer 11;

[0095] Through photolithography and ICP dry etching (SF 6 ) Opening holes in the interconnect dielectric layer 11 on the source 6 of each device to expose the source metal; covering by photolithography, and evaporating metal Au on the spherical surface by evaporation or magnetron sputtering to form interconnect metal 9, and after degumming, the source electrodes 6 of the devices are connected correspondingly through the interconnect metal 9;

[0096] S520: Continue to grow 1-5 μm AlN on the spherical surface of the device by magnetron sputtering or pulsed laser deposition to form a second interconnect dielectric layer 11;

[0097] Through photolithography and ICP dry etching (SF 6 ) Opening a hole in the interconnect dielectric layer 11 on the drain 7 of each device to expose the drain 7 metal; covering by photolithography, and evaporating metal Au on the spherical surface by evaporation or magnetron sputtering to form interconnect metal 9, and after degumming, the drains 7 of the devices are connected correspondingly through the interconnect metal 9;

[0098] S530: Continue to grow 1-5 μm AlN on the spherical surface of the device by magnetron sputtering or pulsed laser deposition to form a third interconnect dielectric layer 11;

[0099] Through photolithography and ICP dry etching (SF 6 ) A hole is opened on the interconnect dielectric layer 11 on the gate 8 of each device to expose the gate 8 metal; it is covered by a photolithography process, and metal Au is evaporated on the spherical surface by evaporation or magnetron sputtering to form an interconnect metal 9. After degumming, the gates 8 of the devices are connected correspondingly through the interconnect metal 9.

[0100] It should be understood that, firstly, those skilled in the art can select appropriate chemical vapor deposition methods to grow each layer, and select appropriate etching methods to expose the surface or openings of certain layers, including but not limited to the deposition methods of the device and the interconnect dielectric layer 11 in the above embodiment; the shape of the PMOS, the material of the device, and the material of the interconnect dielectric layer 11 can also be replaced, and a detailed description is provided in the first part of the embodiment; the source 6, the drain 7, and the gate 8 of the device can select appropriate metal electrodes as long as they can form a good ohmic contact;

[0101] Secondly, the steps in the above embodiments are not limited in order, and some processes can be exchanged in order. In addition, the description of each aspect of the above embodiments has its own emphasis, and for the part not described in detail in a certain part, reference can be made to the relevant description of other embodiments.

[0102] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-dimensional highly integrated MOS transistor, characterized in that: include: A three-dimensional substrate, a plurality of devices spaced apart on the outer surface of the three-dimensional substrate, and an interconnect dielectric layer covering the surfaces of the devices and the three-dimensional substrate; The device is a PMOS tube or an NMOS tube; The interconnect dielectric layer has at least a plurality of interconnect metals fixed therein, and the drains of the devices, the sources of the devices, and the gates of the devices are connected one by one through the interconnect metals; Wherein, the interconnection dielectric layer is multi-layered, and the interconnection metals between the drains of the devices, the interconnection metals between the sources of the devices, and the interconnection metals between the gates of the devices do not contact or cross each other; The three-dimensional substrate is in the shape of a sphere, and the diameter of the sphere is 50-60 μm; or, the three-dimensional substrate is in the shape of a polyhedron, and the diameter of the circumscribed sphere corresponding to the polyhedron is 50-60 μm; or, the three-dimensional substrate is in the shape of a cylinder, and the diameter of the cylinder is 50-60 μm and the height is 50-60 μm.

2. The transistor according to claim 1, characterized in that The device is a PMOS tube, and the device includes a first dielectric layer arranged on the surface of the three-dimensional substrate, a GaN buffer layer arranged on the side of the first dielectric layer away from the three-dimensional substrate, a GaN channel layer arranged on the side of the GaN buffer layer away from the first dielectric layer, two p-GaN layers arranged at intervals on the side of the GaN channel layer away from the GaN buffer layer, a source electrode arranged on the surface of one of the p-GaN layers, a drain electrode arranged on the surface of the other p-GaN layer, a gate electrode arranged on the side of the GaN channel layer away from the GaN buffer layer, and an insulating dielectric layer at least isolating the GaN channel layer and the gate electrode.

3. The transistor according to claim 2, characterized in that The three-dimensional substrate is a diamond or boron nitride substrate.

4. The transistor according to claim 2, characterized in that The material of the first dielectric layer is any one of AlN, SiO2 or Si3N4, and the thickness of the first dielectric layer is 20-50 nm.

5. The transistor according to claim 2, characterized in that The dopant of the GaN buffer layer is C, and the doping concentration is 2×10 18 cm -3 , the thickness of the GaN buffer layer is 10-40 μm; The dopant of the GaN channel layer is Si, and the doping concentration is 2×10 16 cm -3 ~5×10 16 cm -3 , the thickness of the GaN channel layer is 5-20 μm; The dopant of each p-GaN layer is Mg, and the doping concentration is 1.2×10 19 cm -3 ~5×10 19 cm -3 .

6. The transistor according to any one of claims 1 to 5, characterized in that The interconnect dielectric layer has at least multiple layers; The gates of the devices are interconnected through the interconnection metal on the outermost layer of the interconnection dielectric layer; The sources and drains of the devices are interconnected through the interconnection metals on different layers except the outermost layer on the interconnection dielectric layer.

7. The transistor according to claim 6, characterized in that The material of the interconnect dielectric layer is any one of AlN, SiO2 or Si3N4, and the thickness of each layer of the interconnect dielectric layer is 1-5 μm.

8. The method for preparing a three-dimensional highly integrated MOS transistor according to any one of claims 1 to 7, characterized in that: Includes steps: Prepare a three-dimensional substrate, grow a first dielectric layer on the outer surface of the three-dimensional substrate, grow a GaN buffer layer on the surface of the first dielectric layer, grow a GaN channel layer on the surface of the GaN buffer layer away from the first dielectric layer, and arrange a plurality of device areas at intervals on the outer surface of the three-dimensional substrate; Etching the first dielectric layer, the GaN buffer layer, and the GaN channel layer in a non-device area on the three-dimensional substrate to expose the non-device area of ​​the three-dimensional substrate; Implanting ions into the side of the GaN channel layer on each device region away from the GaN buffer layer to form two p-GaN layers spaced apart; On each of the device regions, a drain electrode is grown on the surface of one of the p-GaN layers, and a source electrode is grown on the surface of another of the p-GaN layers; An insulating dielectric layer is grown on the side of the GaN channel layer on each device region away from the GaN buffer layer, the insulating dielectric layer at least covers a portion of the GaN channel layer, and a gate is grown on the side of the insulating dielectric layer away from the GaN channel layer, so that a plurality of devices are correspondingly formed on the plurality of device regions of the three-dimensional substrate; Growing an interconnect dielectric layer on each of the devices and the exposed non-device region on the three-dimensional substrate; Openings are etched on the interconnect dielectric layer at positions corresponding to the source, the drain and the gate, and interconnect metal is grown on the interconnect dielectric layer and at the openings to connect the sources, the drains and the gates of the device accordingly.

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