A multi-stage trench power device and a method for manufacturing the same

Abstract

The application discloses a multistage trench type power device and a preparation method thereof. The preparation method comprises the following steps: providing an epitaxial wafer, the epitaxial wafer comprising a silicon carbide epitaxial layer, a first surface of the silicon carbide epitaxial layer comprising a gate region and source regions located on both sides of the gate region; based on a preset width condition of a gate trench and a source trench, forming the gate trench in the gate region and the source trench comprising at least two stages of trenches in the source regions by one-time photolithography; forming a first voltage-withstanding mask structure at the bottom of the gate trench and a second voltage-withstanding mask structure at the bottom and both sides of the source trench; wherein the second voltage-withstanding mask structure is a multistage step structure comprising at least three stages of steps; forming a gate structure in the gate trench; and forming a source electrode at the top of the source trench. The technical scheme provided by the application improves the problem that the gate oxide layer in the trench type power device is easily broken down, and simplifies the preparation process of the power device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor devices, and particularly relate to a multi-level trench power device and a preparation method thereof. BACKGROUND

[0002] As a representative of the third generation semiconductor material, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon material, SiC material has a large band gap, high breakdown field, high thermal conductivity, high electron saturation velocity, strong radiation resistance and other advantages, so the multi-level trench power device prepared by using SiC material not only can operate stably at a higher temperature, but also is suitable for high-voltage and high-frequency scenarios.

[0003] At present, in the multi-level trench power device prepared by using SiC material, the trench SiC power device has the advantages of large current density and small cell size; however, in the trench SiC power device, the high electric field at the bottom of the trench and the slot angle can increase the electric field on the gate oxide layer, and thus the gate oxide layer is prone to breakdown. In the related technology, a source trench with a multi-level trench is formed in the source region and a gate trench with a multi-level trench is formed in the gate region by multiple etching, and then ion implantation is performed based on the source trench and the gate trench to form an electric field shielding structure at the bottom and the sidewall of the source trench and the gate trench. However, the multiple etching method can increase the difficulty of preparing the trench SiC power. Therefore, how to improve the problem of breakdown of the gate oxide layer in the trench SiC power device while simplifying the preparation process of the trench SiC power is a technical problem to be solved by those skilled in the art. SUMMARY

[0004] Embodiments of the present application provide a multi-level trench power device and a preparation method thereof to improve the problem of breakdown of the gate oxide layer in the trench power device while simplifying the preparation process of the power device.

[0005] According to an aspect of the present application, a preparation method of a multi-level trench power device is provided, comprising:

[0006] An epitaxial wafer is provided, the epitaxial wafer comprising a silicon carbide epitaxial layer, the silicon carbide epitaxial layer having opposite first and second surfaces, the first surface comprising a gate region and source regions located on both sides of the gate region;

[0007] Based on a preset width condition of the gate trench and the source trench, a gate trench is formed in the gate region and a source trench is formed in the source region by one-time photolithography process; wherein the source trench is a multi-level trench.

[0008] forming a first voltage-withstanding mask structure at the bottom of the gate trench, and forming a second voltage-withstanding mask structure at the bottom and two sides of the source trench; wherein the second voltage-withstanding mask structure is a multi-stage stepped structure;

[0009] forming a gate structure in the gate trench;

[0010] forming a source at the top of the source trench.

[0011] Optionally, the forming of the gate trench in the gate region and the forming of the source trench in the source region through one photoetching process comprises:

[0012] forming a mask layer on the first surface of the silicon carbide epitaxial layer, and patterning the mask layer based on a photoetching process;

[0013] etching the silicon carbide epitaxial layer based on the patterned mask layer to form a first stage trench of the gate trench in the gate region and a first stage trench of the source trench in the source region; wherein the width of the first stage trench of the source trench is greater than the width of the gate trench;

[0014] forming a sacrificial layer, and based on the width of the first stage trench of the source trench being greater than the width of the gate trench, forming the sacrificial layer on the sidewall of the first stage trench of the source trench and filling the sacrificial layer in the gate trench;

[0015] etching the sacrificial layer at the bottom of the first stage trench to form an opening in the sacrificial layer at the bottom of the first stage trench;

[0016] etching the silicon carbide epitaxial layer exposed by the opening to form a second stage trench of the source trench at the bottom of the first stage trench; the source trench is a two-stage trench comprising the first stage trench and the second stage trench.

[0017] Optionally, before the forming of the gate trench in the gate region and the forming of the source trench in the source region through one photoetching process, the method further comprises:

[0018] performing ion implantation on the silicon carbide epitaxial layer to form a first conductive type lightly doped region, a second conductive type doped region and a first conductive type heavily doped region arranged in sequence and away from the second surface in the silicon carbide epitaxial layer, and a second conductive type heavily doped region in the source region; wherein the second conductive type heavily doped region extends vertically from the first surface into the first conductive type lightly doped region;

[0019] etching the silicon carbide epitaxial layer based on the patterned mask layer to form a first stage trench of the gate trench in the gate region and a first stage trench of the source trench in the source region, comprises:

[0020] In the same etching process, the silicon carbide epitaxial layer in the gate region and the silicon carbide epitaxial layer in the source region are etched until a preset cutoff position is reached to form a gate trench in the gate region and a first-stage trench of a source trench in the source region; wherein, the preset cutoff position is located between the interface of the first conductivity type lightly doped region away from the second surface and the interface of the second conductivity type heavily doped region near the second surface; the width of the second conductivity type heavily doped region is greater than the width of the first-stage trench of the source trench;

[0021] Etching the silicon carbide epitaxial layer exposed by the opening, and forming a second-level trench of the source trench at the bottom of the first-level trench, including:

[0022] The silicon carbide epitaxial layer exposed by the opening is etched to form a second-level trench at the bottom of the first-level trench, penetrating at least a portion of the heavily doped region of the second conductivity type.

[0023] Optionally, a first breakdown voltage masking structure is formed at the bottom of the gate trench, and a second breakdown voltage masking structure is formed at the bottom and both sides of the source trench, including:

[0024] After removing the sacrificial layer, the silicon carbide epitaxial layer is implanted with doped ions of the second conductivity type based on the mask layer to form the first breakdown voltage masking structure at the bottom of the gate trench, and to form the second-level step and the third-level step of the second breakdown voltage masking structure at the bottom of the source trench; wherein, the heavily doped region of the second conductivity type located on the sidewall of the source trench is used as the first-level step of the second breakdown voltage masking structure.

[0025] Optionally, the first lightly doped region and the first heavily doped region of the first conductivity type are doped with N-type dopant ions; the second doped region of the second conductivity type and the second heavily doped region of the second conductivity type are doped with P-type dopant ions.

[0026] Alternatively, the first lightly doped region and the first heavily doped region of the first conductivity type are doped with P-type dopant ions; the second doped region of the second conductivity type and the second heavily doped region of the second conductivity type are doped with N-type dopant ions.

[0027] Optionally, a gate structure is formed in the gate trench, including:

[0028] A first oxide layer is formed on the surface of the gate trench and the surface of the source trench;

[0029] filling a polysilicon material in the source trench of the gate trench; wherein the first oxide layer and the polysilicon in the gate trench are used to form the gate structure;

[0030] forming a source on the top of the source trench, comprising:

[0031] forming a second oxide layer on the upper surface of the gate structure;

[0032] forming the source on the side of the second oxide layer away from the gate structure and the surface not covered by the second oxide layer.

[0033] Optionally, after forming the source on the side of the second oxide layer away from the gate structure and the surface not covered by the second oxide layer, further comprising:

[0034] forming a passivation layer on the side of the source away from the silicon carbide epitaxial layer and opening a source hole in the passivation layer;

[0035] performing a thinning process on the back surface of the epitaxial wafer;

[0036] forming a substrate on the second surface of the silicon carbide epitaxial layer;

[0037] forming a drain on the side of the substrate away from the silicon carbide epitaxial layer.

[0038] According to another aspect of the present application, a multi-stage trench type power device is provided, which is formed by the method for manufacturing the multi-stage trench type power device according to any one of the embodiments of the present application; the multi-stage trench type power device comprises:

[0039] a silicon carbide epitaxial layer having opposite first and second surfaces, the first surface comprising a gate region and source regions on both sides of the gate region;

[0040] a gate trench formed in the gate region and a source trench formed in the source region; wherein the source trench is a multi-stage trench;

[0041] a first voltage-withstanding masking structure at the bottom of the gate trench;

[0042] a second voltage-withstanding masking structure at the bottom and both sides of the source trench; wherein the second voltage-withstanding masking structure is a multi-stage stepped structure;

[0043] a gate structure in the gate trench;

[0044] a source on the top of the source trench.

[0045] Optionally, the silicon carbide epitaxial layer comprises a first-conductivity-type lightly-doped region, a second-conductivity-type doped region and a first-conductivity-type heavily-doped region arranged in sequence away from the second surface; and a second-conductivity-type heavily-doped region located at the source region; wherein the second-conductivity-type heavily-doped region extends vertically from the first surface into the first-conductivity-type lightly-doped region;

[0046] The source trench comprises a first-stage trench and a second-stage trench; the first-stage trench of the source trench is etched in the same etching process as the gate trench, and a preset etching stop position is located between an interface of the first-conductivity-type lightly-doped region away from the second surface and an interface of the second-conductivity-type heavily-doped region close to the second surface.

[0047] The width of the first-stage trench of the source trench is greater than the width of the gate trench; the width of the second-conductivity-type heavily-doped region is greater than the width of the first-stage trench of the source trench; and the second-stage trench of the source trench penetrates at least part of the second-conductivity-type heavily-doped region.

[0048] Optionally, the first voltage-withstanding mask structure is a second-conductivity-type heavily-doped region formed at the bottom of the gate trench.

[0049] The second voltage-withstanding mask structure is a second-conductivity-type heavily-doped region formed at the bottom and two sides of the source trench.

[0050] The embodiment of the present application provides a multi-stage trench type power device and a preparation method thereof, based on that a first voltage-withstanding mask structure is formed at the bottom of a gate trench in a silicon carbide epitaxial layer, a source trench with multi-stage trenches is formed at two sides of the gate trench, and a second voltage-withstanding mask structure is formed at the bottom and two sides of the source trench, the voltage-withstanding performance of the corner region at the bottom of the gate trench is improved, and the problem of easy breakdown in the electric field concentration region is solved. In addition, in the technical solution provided by the present application, based on the width relationship between the source trench and the gate trench, the gate trench can be formed in the gate region and the source trench with multi-stage trenches can be formed in the source region through one-time photolithography process, and the preparation process of the trench type SiC power is simplified.

[0051] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings described below only show some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings.

[0053] Figure 1 is a flow chart of a preparation method of a multi-stage trench power device provided by an embodiment of the present application;

[0054] Figure 2 is a flow chart of another preparation method of a multi-stage trench power device provided by an embodiment of the present application;

[0055] Figure 3 is a cross-sectional structure diagram of step S210 in the preparation method of a multi-stage trench power device provided by an embodiment of the present application;

[0056] Figure 4 is a cross-sectional structure diagram of step S220 in the preparation method of a multi-stage trench power device provided by an embodiment of the present application;

[0057] Figures 5 to 9 is a cross-sectional structure diagram of step S230 in the preparation method of a multi-stage trench power device provided by an embodiment of the present application;

[0058] Figure 10 is a cross-sectional structure diagram of step S240 in the preparation method of a multi-stage trench power device provided by an embodiment of the present application;

[0059] Figure 11 is a cross-sectional structure diagram of step S250 in the preparation method of a multi-stage trench power device provided by an embodiment of the present application;

[0060] Figure 12 is a cross-sectional structure diagram of step S260 in the preparation method of a multi-stage trench power device provided by an embodiment of the present application;

[0061] Figure 13 is a cross-sectional structure diagram of a multi-stage trench power device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0062] In order to make the technical personnel in the art better understand the present application, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.

[0063] It should be noted that the terms "first", "second" and the like in the description and in the claims of the present application and in the above-described drawings mean for distinguishing like objects and do not necessarily indicate a specific order or sequence. It is to be understood that the data used herein can be interchanged, where appropriate, so that embodiments of the present application described herein can be carried out in other than the order shown or described herein. Furthermore, the terms "comprise", "comprising", "has", "having", "includes", "including", and the like are intended to cover non-exclusive inclusions, such that processes, methods, systems, products, or devices that comprise, have, include or the like a series of steps or units are not limited to those expressly listed, but can include other steps or units not expressly listed or inherent to such processes, methods, products, or devices.

[0064] The embodiment of the present application provides a preparation method of a multi-stage trench type power device, Figure 1 is a flow chart of the preparation method of the multi-stage trench type power device provided by the embodiment of the present application, referring to Figure 1 , comprising:

[0065] S110, providing an epitaxial wafer, the epitaxial wafer comprising a silicon carbide epitaxial layer, the silicon carbide epitaxial layer having opposite first and second surfaces, the first surface comprising a gate region and source regions located on both sides of the gate region.

[0066] S120, based on a preset width condition of the gate trench and the source trench, forming the gate trench in the gate region and the source trench in the source region through one-time photolithography process; wherein the source trench is a multi-stage trench.

[0067] Specifically, the photolithography process is an important step in the semiconductor device manufacturing process, which uses exposure and development to draw geometric pattern structures on the photoresist layer, and then transfers the pattern on the photo mask to the mask layer through etching process to realize the patterning of the mask layer; and then the silicon carbide epitaxial layer exposed by the mask layer is etched through the etching process, so as to obtain a trench with a preset shape. The source trench is a multi-stage trench comprising at least two stages of trenches, and the multi-stage trench can be understood as comprising at least two through trenches with different widths in the extension direction of the trench. Since the source trench comprises at least two trenches with different widths, in the related art, at least two photolithography processes are usually required to form. In the embodiment of the present application, based on the preset width condition of the gate trench and the source trench, only one-time mask layer patterning process (photolithography process) is required on the first surface of the silicon carbide epitaxial layer, and then the first surface is etched based on the patterned mask layer, so as to form the gate trench and the source trench comprising at least two stages of trenches.

[0068] The first level trench of the source trench and the gate trench are etched simultaneously, and the preset width conditions of the source trench and the gate trench include that the width of the gate trench is smaller than the first level trench of the source trench, so that when the sacrificial layer material is deposited, only a layer of the sacrificial layer is covered on the groove wall in the first level trench of the source trench, and the sacrificial layer is filled in the gate trench, so that the gate trench can be protected by the sacrificial layer when the bottom of the first level trench is etched. Therefore, it is not necessary to prepare a mask layer on the first surface again and to pattern the mask layer by a photolithography process. By analogy, when the next level trench (for example, the third level trench) of the source trench is etched, the deposited sacrificial layer material needs to be covered on the groove wall of the etched trench (for example, the first level trench and the second level trench) of the source trench, and the top sacrificial layer of the next level trench (the third level trench) is exposed.

[0069] In S130, a first voltage-withstanding mask structure is formed at the bottom of the gate trench, and a second voltage-withstanding mask structure is formed at the bottom and two sides of the source trench. The second voltage-withstanding mask structure is a multi-level step structure.

[0070] Specifically, the first voltage-withstanding mask structure at the bottom of the gate trench and the second voltage-withstanding mask structure at the bottom and two sides of the source trench can be formed by ion implantation. The voltage-withstanding performance of the corner region at the bottom of the gate trench is improved, the problem of breakdown in the electric field concentration region is solved, the static electricity bearing capacity of the device to a harsh environment and the tolerance of the device to a high-voltage peak in a circuit are improved. Moreover, after the gate trench is formed, the first voltage-withstanding mask structure at the bottom of the gate trench is formed, so that the ion implantation depth during formation of the first voltage-withstanding mask structure is increased. After the source trench is formed, the second voltage-withstanding mask structure at the bottom of the source trench is formed, so that the ion implantation depth during formation of the second voltage-withstanding mask structure is increased. The second voltage-withstanding mask structure is a multi-level step structure including at least three levels. Further, an insulating medium layer with a large thickness can be formed at the bottom of the trench, so that the problem that a conventional high-temperature furnace tube oxidation process cannot form a silicon dioxide layer with a large thickness in the trench is solved, and the voltage-withstanding performance of the bottom of the trench and the reliability of the device are further improved.

[0071] In S140, a gate structure is formed in the gate trench.

[0072] In S150, a source electrode is formed at the top of the source trench.

[0073] The embodiment of the present application provides a preparation method of a multi-stage trench type power device, based on the fact that a first voltage-withstanding mask structure is formed at the bottom of a gate trench in a silicon carbide epitaxial layer, a source trench with multi-stage trenches is formed at both sides of the gate trench, and a second voltage-withstanding mask structure is formed at the bottom and both sides of the source trench, so that the voltage-withstanding performance of the corner region at the bottom of the gate trench is improved, and the problem of easy breakdown in the electric field concentration region is solved. In addition, based on the width relationship between the source trench and the gate trench, the gate trench can be formed in the gate region and the source trench with multi-stage trenches can be formed in the source region through one-time photolithography process, so that the preparation process of the trench type SiC power is simplified.

[0074] The above is the core inventive concept of the present application, and the preparation method of the multi-stage trench type power device with the gate trench being a single-stage trench and the source trench being a two-stage trench will be specifically described below with reference to the drawings.

[0075] Figure 2 is a flow chart of another preparation method of a multi-stage trench type power device provided by the embodiment of the present application, Figures 3 to 12 is a cross-sectional structure schematic diagram of steps S210-S260 in the preparation method of the multi-stage trench type power device; refer to Figures 2 to 12 The preparation method of the multi-stage trench type power device comprises the following steps.

[0076] S210, providing an epitaxial wafer, the epitaxial wafer comprising a silicon carbide epitaxial layer, the silicon carbide epitaxial layer having opposite first and second surfaces, the first surface comprising a gate region and source regions located on both sides of the gate region.

[0077] Specifically, referring to Figure 3 The material of the epitaxial wafer comprises silicon carbide (SiC), and the silicon carbide epitaxial layer 20 can be understood as a film layer structure with a partial thickness of the epitaxial wafer. An N+ silicon carbide semiconductor substrate with an N-silicon carbide epitaxial layer 20 can be used to prepare the multi-stage trench type power device. The second surface of the silicon carbide epitaxial layer 20 faces the semiconductor substrate, and the first surface of the silicon carbide epitaxial layer 20 is the front surface of the epitaxial wafer. When performing a front surface process on the epitaxial wafer, etching is performed to form a trench in the first surface comprising the gate region Q1 and the source regions Q2 located on both sides of the gate region Q1. The silicon carbide semiconductor substrate can be directly used as the substrate 10 of the device, or the semiconductor substrate can be thinned and then used as the substrate 10 of the device.

[0078] S220, ion implantation is performed on the silicon carbide epitaxial layer to form, in the silicon carbide epitaxial layer, a first-conductivity-type lightly-doped region, a second-conductivity-type doped region and a first-conductivity-type heavily-doped region which are arranged in sequence and away from the second surface, and a second-conductivity-type heavily-doped region in the source region; wherein the second-conductivity-type heavily-doped region extends perpendicularly from the first surface into the first-conductivity-type lightly-doped region.

[0079] Specifically, referring to Figure 4 , the first-conductivity-type lightly-doped region 21, the second-conductivity-type doped region 22 and the first-conductivity-type heavily-doped region 23 are formed in the silicon carbide epitaxial layer 20 by ion implantation from the first surface, and a second-conductivity-type heavily-doped region 24 is formed in the source region Q2. The first-conductivity-type lightly-doped region 21 is used to form a drift region of the multi-stage trench SiC power device; the second-conductivity-type doped region 22 is used to form a well region of the multi-stage trench SiC power device; the first-conductivity-type heavily-doped region 23 is used to form a contact source region of the multi-stage trench SiC power device. The second-conductivity-type heavily-doped region 24 is used to prepare a second voltage-withstanding masking structure on both sides of the gate trench. For silicon carbide material, ion implantation is generally performed at 500-600℃ by a high-temperature ion implantation device to reduce damage to the silicon carbide material lattice.

[0080] wherein, referring to Figure 4 , the ions implanted in the first-conductivity-type lightly-doped region 21 and the first-conductivity-type heavily-doped region 23 are N-type doping ions; the ions implanted in the second-conductivity-type doped region 22 and the second-conductivity-type heavily-doped region 24 are P-type doping ions. It is understood that Figure 4 P+ and N+ in the drawings represent a high ion doping concentration in the region, and P- and N- represent a low ion doping concentration in the region. In other embodiments of the present application, the ions implanted in the first-conductivity-type lightly-doped region 21 and the first-conductivity-type heavily-doped region 23 are P-type doping ions; the ions implanted in the second-conductivity-type doped region 22 and the second-conductivity-type heavily-doped region 24 are N-type doping ions. Optionally, the N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions.

[0081] S230, based on a preset width condition of the gate trench and the source trench, a gate trench is formed in the gate region and a source trench is formed in the source region by one-time photolithography; wherein the source trench is a two-stage trench including a first-stage trench and a second-stage trench.

[0082] wherein the step of forming the gate trench in the gate region and the source trench in the source region by one-time photolithography specifically includes:

[0083] S2301. Form a mask layer on the first surface of the silicon carbide epitaxial layer, and pattern the mask layer based on a photolithography process.

[0084] Specifically, referring to FIG. 2A, SiO2 is deposited on the first surface of the silicon carbide epitaxial layer 20 as the mask layer 30 by a deposition process such as CVD. Photoresist PR is spin-coated on the surface of the mask layer 30. The photoresist PR is exposed and developed to form a desired pattern. Then, the mask layer 30 is etched based on the patterned photoresist PR, and the mask layer 30 is patterned. The patterned mask layer 30 exposes the preset positions of the gate trench and the preset positions of the source trench. Figure 5

[0085] S2302. Etch the silicon carbide epitaxial layer based on the patterned mask layer to form a gate trench in the gate region and a first-stage trench of a source trench in the source region; wherein the width of the first-stage trench of the source trench is greater than the width of the gate trench.

[0086] Specifically, referring to FIG. 2B, in the same etching process, the silicon carbide epitaxial layer 20 in the gate region Q1 and the silicon carbide epitaxial layer 20 in the source region Q2 are etched to a preset stop position to form the gate trench 50 in the gate region Q1 and the first-stage trench 401 of the source trench 40 in the source region Q2; wherein the preset stop position is between the interface of the first-conductivity-type lightly doped region 21 away from the second surface and the interface of the second-conductivity-type heavily doped region 24 close to the second surface; and the width of the second-conductivity-type heavily doped region 24 is greater than the width of the first-stage trench 401 of the source trench 40. The etching process can be a plasma dry etching process such as RIE or ICP etching process. Figure 6

[0087] S2303. Form a sacrificial layer based on the width of the first-stage trench of the source trench being greater than the width of the gate trench to form the sacrificial layer on the sidewall of the first-stage trench of the source trench and fill the gate trench with the sacrificial layer.

[0088] Specifically, referring to FIG. 2C, the ALD (Atomic Layer Deposition) process is used to deposit a sacrificial layer 60 material different from the mask layer 30 material, such as silicon nitride (SiN). Based on the width of the first-stage trench 401 of the source trench 40 being greater than the width of the gate trench 50, the sacrificial layer 60 material is deposited on the sidewall and bottom of the first-stage trench 401 to form the sacrificial layer 60 on the sidewall of the first-stage trench 401 of the source trench 40; and is deposited in the gate trench 50 to fill the gate trench 50 with the sacrificial layer 60. In addition, the sacrificial layer 60 is also formed on the surface of the mask layer 30. Figure 7

[0089] ​​​Optionally, the width of the first-stage trench 401 of the source trench 40 is 2 times or more than 2 times of the width of the gate trench 50, so as to ensure that the material of the sacrificial layer 60 is deposited on the sidewall of the first-stage trench 401 of the source trench 40 and the sacrificial layer 60 is filled in the gate trench 50.

[0090] S2304, etching the sacrificial layer at the bottom of the first-stage trench to form an opening in the sacrificial layer at the bottom of the first-stage trench.

[0091] Specifically, since the mask layer 30 can also block the implantation of the doping ions to the contact source region, the well region and the drift region in the subsequent process of forming the first voltage-withstanding mask structure 80 and the second voltage-withstanding mask structure 70, the material of the sacrificial layer 60 is different from that of the mask layer 30, so as to reduce the etching loss of the mask layer 30 when etching the sacrificial layer 60 at the bottom of the first-stage trench 401. In addition, the sacrificial layer 60 on the surface of the mask layer 30 can also protect the mask layer 30.

[0092] S2305, etching the exposed silicon carbide epitaxial layer to form a second-stage trench of the source trench at the bottom of the first-stage trench and remove the sacrificial layer.

[0093] Specifically, referring to Figure 8 , etching the exposed silicon carbide epitaxial layer 20 to form a second-stage trench 402 of the source trench 40 at the bottom of the first-stage trench 401, including: etching the exposed silicon carbide epitaxial layer 20 to form a second-stage trench 402 at the bottom of the first-stage trench 401, which penetrates at least part of the second-conductivity-type heavily doped region 24. Figure 8 An example is shown in which the second-stage trench 402 penetrates the second-conductivity-type heavily doped region 24 at the bottom of the first-stage trench 401. Referring to Figure 9 , removing the sacrificial layer 60.

[0094] S240, implanting the second-conductivity-type doping ions into the silicon carbide epitaxial layer based on the mask layer, to form a first voltage-withstanding mask structure at the bottom of the gate trench and a second-stage step and a third-stage step of the second voltage-withstanding mask structure at the bottom of the source trench. The second-conductivity-type heavily doped region on the sidewall of the source trench is used as the first-stage step of the second voltage-withstanding mask structure.

[0095] Specifically, referring to Figure 10, based on the mask layer 30, the silicon carbide epitaxial layer 20 is implanted with ions of the second conductivity type for doping to form a first voltage withstand mask structure 80 at the bottom of the gate trench 50 and a second voltage withstand mask structure 70 with a second level step 702 and a third level step 703 at the bottom of the source trench 40. The second conductivity type heavily doped region 24 on the sidewall of the source trench 40 is used as the first level step 701 of the second voltage withstand mask structure. The width of the second level step 702 is equal to or approximately equal to the width of the first level trench 401. The width of the third level step 703 is equal to or approximately equal to the width of the second level trench 402. The first voltage withstand mask structure 80 and the second voltage withstand mask structure 70 are both second conductivity type heavily doped regions 24 formed in the silicon carbide epitaxial layer 20.

[0096] Based on the gate trench 50 and the source trench 40, the first voltage withstand mask structure 80 and the second voltage withstand mask structure 70 with the second level step 702 and the third level step 703 are formed in the silicon carbide epitaxial layer 20 by ion implantation, which solves the problem of difficulty in forming a deep P+ mask layer and damage caused by high-dose and high-energy P+ ion implantation in the silicon carbide material, improves the reliability of the device, and better shields and protects the gate trench 50.

[0097] S250, forming a gate structure in the gate trench.

[0098] Specifically, referring to Figure 11 , a first oxide layer is formed on the surface of the gate trench 50 and the surface of the source trench 40; a polysilicon material is filled in the source trench 40 of the gate trench 50; and the first oxide layer 91 and the polysilicon gate 92 located in the gate trench 50 are used to constitute a gate structure 90. The first oxide layer 91 is used as a gate insulating layer. The polysilicon filled in the source trench 40 is used to form a filling structure Dummy.

[0099] S260, forming a source on the top of the source trench.

[0100] Specifically, referring to Figure 12 , a second oxide layer is formed on the upper surface of the gate structure; a source S is formed on the side of the second oxide layer away from the gate structure and the surface not covered by the second oxide layer. The second oxide layer is used as an interlayer insulating layer ILD to isolate the source S from the gate structure 90.

[0101] The embodiment of the present application provides a preparation method of a multi-level trench type power device. The source trench 40 is a two-level step trench structure, the P+ region is implanted deeper, and the P+ region is a three-level step structure. The width of the source trench 40 is twice the width of the gate trench 50. One photolithography process can form the structures of the gate trench 50, the two-level source trench, and the P+ three-level step, thereby greatly simplifying the process.

[0102] On the basis of any of the above embodiments, after forming the source electrode on the side of the second oxide layer away from the gate structure and the surface covered by the second oxide layer, the method further comprises:

[0103] forming a passivation layer 101 on the side of the source electrode away from the silicon carbide epitaxial layer 20 and opening a source hole in the passivation layer 101; thinning the back surface of the epitaxial wafer; forming a substrate 10 on the second surface of the silicon carbide epitaxial layer 20; forming a drain electrode D on the side of the substrate away from the silicon carbide epitaxial layer 20, forming a multi-stage trench type power device as shown in Figure 13 .

[0104] The materials of the source electrode 70 and the drain electrode 60 include metal. When a positive bias voltage is applied to the gate structure, an N-channel is formed between the N-type drift region and the N-type source contact region, electrons flow from the N-type source contact region, pass through the N-type drift region through the N-channel, and the source electrode and the drain electrode are turned on. The trench type SiC power device further comprises a passivation layer 101 on the source electrode 70 and a protective layer 102. The material of the passivation layer 101 can include silicon nitride (SiN), and the material of the protective layer 102 can include polyimide (PI)

[0105] The embodiment of the present application also provides a multi-stage trench type power device formed by the preparation method of the multi-stage trench type power device described in any of the above embodiments; referring to Figure 13 , the multi-stage trench type power device comprises:

[0106] a silicon carbide epitaxial layer 20, the silicon carbide epitaxial layer 20 has opposite first and second surfaces, and the first surface includes a gate region and source regions on both sides of the gate region;

[0107] a gate trench is formed in the gate region, and a source trench is formed in the source region; wherein the source trench is a multi-stage trench including at least two stages of trenches;

[0108] a first voltage withstand masking structure 80 located at the bottom of the gate trench;

[0109] a second voltage withstand masking structure 70 located at the bottom and both sides of the source trench; wherein the second voltage withstand masking structure 70 is a multi-stage step structure including at least three stages of steps;

[0110] a gate structure 90 located in the gate trench;

[0111] a source electrode S located at the top of the source trench.

[0112] The embodiment of the present application provides a multi-stage trench type power device, based on the first voltage-withstanding mask structure 80 formed at the bottom of the gate trench in the silicon carbide epitaxial layer 20, the source trench with the multi-stage trench is formed at the two sides of the gate trench, and the second voltage-withstanding mask structure 70 is formed at the bottom and the two sides of the source trench, so that the voltage-withstanding performance of the corner area at the bottom of the gate trench is improved, and the breakdown problem easily occurring in the electric field concentration area is improved. In addition, in the technical scheme provided by the present application, based on the width relationship between the source trench and the gate trench, the gate trench can be formed in the gate region and the source trench with the multi-stage trench can be formed in the source region through one-time photolithography process, so that the preparation process of the trench type SiC power is simplified.

[0113] Optionally, the silicon carbide epitaxial layer 20 comprises a first-conductivity-type lightly doped region 21, a second-conductivity-type doped region 22 and a first-conductivity-type heavily doped region 23 which are sequentially and laminatedly arranged away from the second surface; and a second-conductivity-type heavily doped region 24 located in the source region; wherein the second-conductivity-type heavily doped region 24 extends vertically into the first-conductivity-type lightly doped region 21 from the first surface.

[0114] The source trench is a multi-stage trench comprising a first-stage trench and a second-stage trench; the first-stage trench of the source trench is etched in the same etching process as the gate trench, and the preset stop position of etching is located between the interface of the first-conductivity-type lightly doped region 21 away from the second surface and the interface of the second-conductivity-type heavily doped region 24 close to the second surface. The width of the first-stage trench of the source trench is greater than the width of the gate trench; and the width of the second-conductivity-type heavily doped region 24 is greater than the width of the first-stage trench of the source trench. The first-conductivity-type lightly doped region 21 is used for forming a drift region of the multi-stage trench type power device; the first-conductivity-type doped region is used for forming a well region of the multi-stage trench type power device; and the first-conductivity-type heavily doped region 23 is used for forming a contact source region of the multi-stage trench type power device.

[0115] Optionally, the width of the first-stage trench of the source trench is 2 times or more than 2 times the width of the gate trench.

[0116] Optionally, the first voltage-withstanding mask structure 80 is the second-conductivity-type heavily doped region 24 formed at the bottom of the gate trench; and the second voltage-withstanding mask structure 70 is the second-conductivity-type heavily doped region 24 formed at the bottom and the two sides of the source trench.

[0117] Specifically, the first voltage-withstanding mask structure 80 can be formed at the bottom of the gate trench by ion implantation, and the second voltage-withstanding mask structure 70 can be formed at the bottom and two sides of the source trench. The voltage-withstanding performance of the corner area at the bottom of the gate trench is improved, the breakdown problem in the electric field concentration area is solved, the static electricity bearing capacity of the device to the harsh environment and the tolerance to the high voltage peak in the circuit are improved. Moreover, after the gate trench is formed, the first voltage-withstanding mask structure 80 is formed at the bottom of the gate trench, which can increase the ion implantation depth when the first voltage-withstanding mask structure 80 is formed. After the source trench is formed, the second voltage-withstanding mask structure 70 is formed at the bottom of the source trench, which can increase the ion implantation depth when the second voltage-withstanding mask structure 70 is formed. Further, an insulating medium layer with a larger thickness can be formed at the bottom of the trench, which solves the problem that the conventional high-temperature furnace tube oxidation process cannot form a silicon dioxide layer with a larger thickness in the trench, and further improves the voltage-withstanding capacity of the bottom of the trench and the reliability of the device.

[0118] It should be noted that the above only describes the preferred embodiments of the present application and the principles of the applied technology. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A method of manufacturing a multi-stage trench power device, characterized by, The application relates to a method for manufacturing a silicon carbide (SiC) power device, and belongs to the technical field of semiconductor device manufacturing. The method comprises the following steps: providing an epitaxial wafer, wherein the epitaxial wafer comprises a silicon carbide epitaxial layer, the silicon carbide epitaxial layer has opposite first and second surfaces, the first surface comprises a gate region and source regions located on both sides of the gate region; based on a preset width condition of the gate trench and the source trench, a gate trench is formed in the gate region and a source trench is formed in the source region through one-time photolithography; wherein the source trench is a multistage trench; the source trench comprises a first-stage trench, and the preset width condition of the gate trench and the source trench comprises that the width of the gate trench is smaller than the width of the first-stage trench of the source trench; a first voltage-resistant mask structure is formed at the bottom of the gate trench, and a second voltage-resistant mask structure is formed at the bottom and both sides of the source trench; wherein the second voltage-resistant mask structure is a multistage stepped structure; a gate structure is formed in the gate trench; a source electrode is formed at the top of the source trench; and the method comprises the following steps: forming a mask layer on the first surface of the silicon carbide epitaxial layer, and patterning the mask layer based on photolithography; etching the silicon carbide epitaxial layer based on the patterned mask layer to form a gate trench in the gate region and a first-stage trench of a source trench in the source region; wherein the preset width condition is that the width of the first-stage trench of the source trench is greater than the width of the gate trench; forming a sacrifice layer, and based on the width of the first-stage trench of the source trench being greater than the width of the gate trench, the sacrifice layer is formed on the sidewall of the first-stage trench of the source trench and the sacrifice layer is filled in the gate trench; after the sacrifice layer is formed, the first-stage trench of the source trench has a hollow region; etching the sacrifice layer at the bottom of the first-stage trench to form an opening in the sacrifice layer at the bottom of the first-stage trench; etching the silicon carbide epitaxial layer exposed by the opening to form a second-stage trench of the source trench at the bottom of the first-stage trench; and the source trench is a two-stage trench comprising the first-stage trench and the second-stage trench. Before the gate trench is formed in the gate region and the source trench is formed in the source region through one-time photolithography, the method further comprises the following steps: ion implantation is performed on the silicon carbide epitaxial layer to form a first conductive type lightly doped region, a second conductive type doped region and a first conductive type heavily doped region which are sequentially and vertically away from the second surface and are arranged in layers in the silicon carbide epitaxial layer, and a second conductive type heavily doped region is formed in the source region; wherein the second conductive type heavily doped region vertically extends into the first conductive type lightly doped region from the first surface; and etching the silicon carbide epitaxial layer based on the patterned mask layer to form a gate trench in the gate region and a first-stage trench of a source trench in the source region, comprises the following steps: ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The method of claim 1, wherein the trench power device is a multi-level trench power device. ​ ​ ​ In the same etching process, the silicon carbide epitaxial layer in the gate region and the silicon carbide epitaxial layer in the source region are etched to a preset stop position to form a gate trench in the gate region and a first-stage trench of a source trench in the source region; the preset stop position is between the interface of the first-conductivity-type lightly-doped region away from the second surface and the interface of the second-conductivity-type heavily-doped region close to the second surface; the width of the second-conductivity-type heavily-doped region is greater than the width of the first-stage trench of the source trench; The silicon carbide epitaxial layer exposed by the opening is etched to form a second-stage trench of the source trench at the bottom of the first-stage trench, comprising: The silicon carbide epitaxial layer exposed by the opening is etched to form a second-stage trench penetrating at least part of the second-conductivity-type heavily-doped region at the bottom of the first-stage trench.

3. The method of claim 1, wherein the trench power device is a multi-level trench power device. A first voltage-withstanding mask structure is formed at the bottom of the gate trench, and a second voltage-withstanding mask structure is formed at the bottom and both sides of the source trench, comprising: After the sacrificial layer is removed, the silicon carbide epitaxial layer is implanted with second-conductivity-type doping ions based on the mask layer to form the first voltage-withstanding mask structure at the bottom of the gate trench and the second-stage and third-stage steps of the second voltage-withstanding mask structure at the bottom of the source trench; the second-conductivity-type heavily-doped region on the sidewall of the source trench serves as the first-stage step of the second voltage-withstanding mask structure.

4. The preparation method of the multi-stage trench power device according to claim 2, characterized in that: The first-conductivity-type lightly-doped region and the first-conductivity-type heavily-doped region are doped with N-type doping ions; the second-conductivity-type doped region and the second-conductivity-type heavily-doped region are doped with P-type doping ions; Or, the first-conductivity-type lightly-doped region and the first-conductivity-type heavily-doped region are doped with P-type doping ions; The second-conductivity-type doped region and the second-conductivity-type heavily-doped region are doped with N-type doping ions.

5. The method of claim 1, wherein the trench power device is a multi-level trench power device. A gate structure is formed in the gate trench, comprising: A first oxide layer is formed on the surface of the gate trench and the surface of the source trench; A polysilicon material is filled in the gate trench and the source trench; the first oxide layer and the polysilicon in the gate trench are used to constitute the gate structure; A source electrode is formed on the top of the source trench, comprising: A second oxide layer is formed on the upper surface of the gate structure; The source electrode is formed on the side of the second oxide layer away from the gate structure and the surface not covered by the second oxide layer.

6. The fabrication method of a multi-stage trench power device according to claim 5, wherein After the source electrode is formed on the side of the second oxide layer away from the gate structure and the surface not covered by the second oxide layer, further comprising: A passivation layer is formed on the side of the source electrode away from the silicon carbide epitaxial layer, and a source hole is formed in the passivation layer; The back surface of the epitaxial wafer is thinned; A substrate is formed on the second surface of the silicon carbide epitaxial layer; A drain electrode is formed on the side of the substrate away from the silicon carbide epitaxial layer.

7. A multi-stage trench power device, characterized by, The multi-stage trench power device is formed by the method of any one of claims 1-6, and comprises: a silicon carbide epitaxial layer having opposite first and second surfaces, the first surface comprising gate regions and source regions on both sides of the gate regions; gate trenches are formed in the gate regions, and source trenches are formed in the source regions; wherein the source trenches are multi-stage trenches, and the gate trenches are single-stage trenches; a first voltage-withstanding masking structure is located at the bottom of the gate trenches; a second voltage-withstanding masking structure is located at the bottom and both sides of the source trenches; wherein the second voltage-withstanding masking structure is a multi-stage stepped structure; a gate structure is located in the gate trenches; a source is located at the top of the source trenches.

8. The multi-stage trench power device of claim 7, wherein: the silicon carbide epitaxial layer comprises a first-conductivity-type lightly-doped region, a second-conductivity-type doped region, and a first-conductivity-type heavily-doped region arranged in sequence away from the second surface, and a second-conductivity-type heavily-doped region located in the source regions; wherein the second-conductivity-type heavily-doped region extends vertically from the first surface into the first-conductivity-type lightly-doped region; the source trenches are two-stage trenches comprising first-stage trenches and second-stage trenches; the first-stage trenches of the source trenches are formed in the same etching process as the gate trenches, and the preset etching stop position is located between the interface between the first-conductivity-type lightly-doped region away from the second surface and the interface between the second-conductivity-type heavily-doped region close to the second surface; wherein the width of the first-stage trenches of the source trenches is greater than the width of the gate trenches; the width of the second-conductivity-type heavily-doped region is greater than the width of the first-stage trenches of the source trenches; and the second-stage trenches of the source trenches penetrate at least part of the second-conductivity-type heavily-doped region.

9. The multi-stage trench power device of claim 8, wherein: the first voltage-withstanding masking structure is a second-conductivity-type heavily-doped region formed at the bottom of the gate trenches; the second voltage-withstanding masking structure is a second-conductivity-type heavily-doped region formed at the bottom and both sides of the source trenches.

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