A GaAs ultra-wideband double-pole double-throw switch

Abstract

The present invention relates to a gallium arsenide ultra-wideband double-pole double-throw switch, which has an operating range of 1 GHz to 17 GHz, and includes a receiving end RX, a transmitting end TX, an antenna end ANT1, an antenna end ANT2, an input inductor, an output inductor, four branches and a microstrip line connecting each device; the components and structures of the four branches are the same, and each branch includes: a first gallium arsenide pHEMT and a second gallium arsenide pHEMT connected in series, a third gallium arsenide pHEMT connected in parallel with the first gallium arsenide pHEMT, a grounded DC blocking capacitor C0 connected in series with the third gallium arsenide pHEMT, and two control voltage signal terminals. The double-pole double-throw switch of the present invention has an insertion loss of less than 2.15 dB; in an isolated state, the isolation is greater than 22.08 dB; and has the characteristics of small insertion loss and wide operating frequency band in a conducting state. In addition, the double-pole double-throw switch of the present invention can be monolithically integrated with modules such as low-noise amplifiers, power amplifiers, antennas, etc. in WiFi‑FEM or radar systems, which can further reduce the volume and power consumption of the entire system and improve the reliability of the system.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a gallium arsenide ultra-wideband double-pole double-throw switch. Background Art

[0002] With the development of communication technology, the RF front end is constantly developing towards wider frequency band, smaller size, lighter weight, higher power and lower cost, and its system has been greatly improved in process materials and design architecture. In the WiFi-FEM system, the dual-band working requirements require the transceiver components to be able to convert in two frequency bands at the same time. In the RF component system of the multi-function radar, in order to obtain the polarization matrix of the measured ground object pixel to fully describe the electromagnetic scattering characteristics of the radar target, it is also necessary to use a double-pole double-throw switch to connect the transceiver port to the two antenna ports, where the antenna end includes a horizontally polarized antenna and a vertically polarized antenna.

[0003] Microwave monolithic integrated circuit (MMIC) is widely used in the frequency range of 1GHz~100GHz due to its advantages of small size, light weight, good stability and low power consumption. GaAs has a two-dimensional electron gas structure that can reduce the electron scattering of power impurities, thereby greatly improving the carrier concentration and electron mobility. GaAs process MMIC has advantages such as high speed, low dielectric loss and high reliability. As the process continues to mature, the preparation cost is also continuously reduced, which further expands its application range.

[0004] In the related art, the typical circuit structure of the switch circuit is a series-parallel-series mechanism. Figure 1 As shown, the gate resistance is not represented in the overall circuit in the process flow. In practice, the addition of gate resistance can avoid the interference of DC bias on RF signals and reduce the loss of pHEMT on signal paths. Figure 1In the switch branch shown, taking the TX end to ANT1 branch as an example, the Q1, Q2 transistors and the Q3 transistor are in opposite bias states. When Vg1 is high and Vg2 is low, that is, Q1 and Q2 are turned on and Q3 is turned off, the branch switch is in the transmitting state, and the RF signal is output from the TX end to the ANT1 end through the inductors L1, Q1, Q2, and L2. Only a very small amount of signal will pass through Q3 to the DC blocking capacitor C0 and then to the ground for loss. When Vg1 is low and Vg2 is high, that is, Q1 and Q2 are turned off and Q3 is turned on, the branch switch is in the off state, and only a very small part of the RF signal will pass through the cut-off Q1, and then the turned-on Q3 is shorted to the ground through the DC blocking capacitor C0. The cut-off Q2 again ensures that the RF signal is almost impossible to reach the ANT1 end. Of course, at this time, it is possible that the RF signal is transmitted from the TX end to the ANT2 port, or it is possible that any ANT end receives the signal and enters the RX end. The specific situation should be determined according to the conditions of each bias.

[0005] Although the above-mentioned switching circuit can reduce the insertion loss to a certain extent, since the signal passes through the transistor directly, it will inevitably cause additional insertion loss and reduce the linearity of the circuit. Summary of the invention

[0006] In view of the problems existing in the above-mentioned prior art, the present invention provides a gallium arsenide ultra-wideband double-pole double-throw switch. The operating range of the double-pole double-throw switch of the present invention is 1GHz~17GHz, and the insertion loss is less than 2.15dB; in the isolated state, the isolation is greater than 22.08dB; it has the characteristics of small insertion loss in the on state and wide operating frequency band. In addition, the double-pole double-throw switch of the present invention can be monolithically integrated with low-noise amplifiers, power amplifiers, antennas and other modules in WiFi-FEM or radar systems, which can further reduce the volume and power consumption of the entire system and improve the reliability of the system.

[0007] A gallium arsenide ultra-wideband double-pole double-throw switch of the present invention has an operating range of 1 GHz to 17 GHz, and is specifically composed of a receiving end RX, a transmitting end TX, an antenna end ANT1, an antenna end ANT2, an input inductor, an output inductor, four branches, and a microstrip line connecting various devices;

[0008] The components and structures of the four branches are the same, and each branch includes: a first gallium arsenide pHEMT and a second gallium arsenide pHEMT connected in series, a third gallium arsenide pHEMT connected in parallel with the first gallium arsenide pHEMT, a grounded DC blocking capacitor C0 connected in series with the third gallium arsenide pHEMT, and two control voltage signal terminals; the first gallium arsenide pHEMT and the second gallium arsenide pHEMT share a control voltage signal terminal, and the third gallium arsenide pHEMT branch uses a control voltage signal terminal alone;

[0009] The first gallium arsenide pHEMT or the second gallium arsenide pHEMT of each branch is connected to the first gallium arsenide pHEMT or the second gallium arsenide pHEMT of the other two adjacent branches to form four nodes, and the four nodes are respectively connected to the receiving end RX, the transmitting end TX, the antenna end ANT1 and the antenna end ANT2 via at least one input inductor or at least one output inductor;

[0010] Generally, the receiving end RX is an inward receiving port, and the receiving end RX is connected to the input end of a low-noise chip; the transmitting end TX is an outward output port, and the transmitting end TX is connected to the output end of a power amplifier.

[0011] Further, in the gallium arsenide ultra-wideband double-pole double-throw switch of the present invention, the four branches are branch I, branch II, branch III and branch IV, the transmitting end TX leads to the antenna end ANT1 via branch I, the transmitting end TX leads to the antenna end ANT2 via branch IV, the antenna end ANT1 leads to the receiving end RX via branch II, and the antenna end ANT2 leads to the receiving end RX via branch III;

[0012] The node where the transmitting terminal TX connects the two branches of the antenna terminal ANT1 and the antenna terminal ANT2 via an input inductor is the first node among the four nodes, and the first node is adjacent to the input inductor; the second node among the four nodes is the node connecting the branch I, the branch II and the node leading to the antenna terminal ANT1 via an output inductor; the third node among the four nodes is the node connecting the branch II, the branch III and the node leading to the receiving terminal RX via an input inductor; the fourth node among the four nodes is the node connecting the branch III, the branch IV and the node leading to the antenna terminal ANT2 via an inductor;

[0013] In the branch I, the first node is connected in series to the drain of the first gallium arsenide pHEMT, the source of the first gallium arsenide pHEMT is connected to the drain of the third gallium arsenide pHEMT to form an N1 node, the N1 node is connected in series to the drain of the second gallium arsenide pHEMT, and the source of the second gallium arsenide pHEMT is connected to the second node.

[0014] The four branches of the present invention are connected end to end to form a square network, and the four corners of the square network are four nodes.

[0015] Furthermore, in the GaAs ultra-wideband double-pole double-throw switch of the present invention, the gate widths of the first GaAs pHEMT and the first GaAs pHEMT are both 50 um, the gate indexes are both 6, the isolations are both from -27 dB to -4 dB when the series connections are turned off, and the insertion losses are both from -0.42 dB to -0.48 dB when the series connections are turned on; the gate width of the third GaAs pHEMT is 50 um, the gate index is 2, the insertion loss is from -0.007 dB to -0.086 dB when the parallel connections are turned off, and the isolation is from -10.3 dB to -8.3 dB when the parallel connections are turned on.

[0016] Furthermore, in the GaAs ultra-wideband double-pole double-throw switch of the present invention, the first GaAs pHEMT, the first GaAs pHEMT and the third GaAs pHEMT are all switch pHEMTs, and a kilo-ohm resistor is connected in series at the gate of the switch pHEMT.

[0017] Furthermore, in the GaAs ultra-wideband double-pole double-throw switch of the present invention, the control voltage signal terminal is in a high level state or a low level state, and the high level and low level states of the control voltage signal terminal signal in each branch do not affect each other.

[0018] Furthermore, in the GaAs ultra-wideband double-pole double-throw switch of the present invention, the input inductor and the output inductor are both inductors prepared by bending a high-impedance microstrip line.

[0019] Furthermore, in the GaAs ultra-wideband double-pole double-throw switch of the present invention, the material structure of the microstrip line includes: a first metal layer, a second metal layer, and a semiconductor material located between the first metal layer and the second metal layer.

[0020] Furthermore, in the GaAs ultra-wideband double-pole double-throw switch of the present invention, the DC blocking capacitors are all capacitors with a material structure of metal-insulating layer-metal MIM.

[0021] Furthermore, in the GaAs ultra-wideband double-pole double-throw switch of the present invention, the input inductor, the output inductor, the microstrip line, the DC blocking capacitor and the GaAs pHEMT use the same substrate.

[0022] Furthermore, in the gallium arsenide ultra-wideband double-pole double-throw switch of the present invention, the material of the substrate is silicon nitride, gallium arsenide or silicon.

[0023] Compared with the prior art, the present invention has the following beneficial technical effects:

[0024] The GaAs ultra-wideband double-pole double-throw switch of the present invention has an operating range of 1 GHz to 17 GHz, an insertion loss of less than 2.15 dB, and an isolation degree of greater than 22.08 dB in an isolated state. It has the characteristics of low insertion loss and wide operating frequency band in a conducting state. In addition, the double-pole double-throw switch of the present invention can be integrated with low-noise amplifiers, power amplifiers, antennas and other modules in WiFi-FEM or radar systems, which can further reduce the volume and power consumption of the entire system and improve the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of two circuits of a transmitting branch switch in the background technology;

[0026] Figure 2 is a schematic structural diagram of a gallium arsenide ultra-wideband double-pole double-throw switch according to embodiment 1 of the present invention;

[0027] Figure 3 1 is an equivalent schematic diagram of an isolation branch of a gallium arsenide ultra-wideband double-pole double-throw switch according to Embodiment 1 of the present invention;

[0028] Figure 4 1 is an equivalent schematic diagram of a conducting branch of a gallium arsenide ultra-wideband double-pole double-throw switch according to embodiment 1 of the present invention;

[0029] Figure 5 It is a schematic diagram of the test results of the S parameters of the GaAs ultra-wideband double-pole double-throw switch provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0030] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation methods of the present invention are now described in detail with reference to the accompanying drawings. The described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. If the specific conditions are not specified in the specific implementation methods, they shall be carried out according to the conventional conditions or the conditions recommended by the manufacturer.

[0031] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described exemplarily below do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims. The terms used in the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0032] A gallium arsenide ultra-wideband double-pole double-throw switch of the present invention, the operating range of the double-pole double-throw switch is 1GHz~17GHz, and is specifically composed of a receiving end RX, a transmitting end TX, an antenna end ANT1, an antenna end ANT2, an input inductor, an output inductor, four branches and a microstrip line connecting various devices;

[0033] The components and structures of the above four branches are the same, and each of the above branches includes: a first gallium arsenide pHEMT and a second gallium arsenide pHEMT connected in series, a third gallium arsenide pHEMT connected in parallel with the first gallium arsenide pHEMT, a grounded DC blocking capacitor C0 connected in series with the third gallium arsenide pHEMT, and two control voltage signal terminals; the first gallium arsenide pHEMT and the second gallium arsenide pHEMT share one control voltage signal terminal, and the third gallium arsenide pHEMT branch uses one control voltage signal terminal alone;

[0034] The first gallium arsenide pHEMT or the second gallium arsenide pHEMT of each branch is connected to the first gallium arsenide pHEMT or the second gallium arsenide pHEMT of the other two adjacent branches to form four nodes, and the four nodes are respectively connected to the receiving end RX, the transmitting end TX, the antenna end ANT1 and the antenna end ANT2 via at least one input inductor or at least one output inductor;

[0035] Generally, the receiving end RX is an inward receiving port, and the receiving end RX is connected to the input end of a low-noise chip; the transmitting end TX is an outward output port, and the transmitting end TX is connected to the output end of a power amplifier.

[0036] In some implementations, the four branches are branch I, branch II, branch III and branch IV, the transmitting end TX leads to the antenna end ANT1 via branch I, the transmitting end TX leads to the antenna end ANT2 via branch IV, the antenna end ANT1 leads to the receiving end RX via branch II, and the antenna end ANT2 leads to the receiving end RX via branch III;

[0037] The node where the transmitting terminal TX connects the two branches of the antenna terminal ANT1 and the antenna terminal ANT2 via an input inductor is the first node among the four nodes, and the first node is adjacent to the input inductor; the second node among the four nodes is the node connecting the branch I, the branch II and the node leading to the antenna terminal ANT1 via an output inductor;

[0038] In the branch I, the first node is connected in series to the drain of the first gallium arsenide pHEMT, the source of the first gallium arsenide pHEMT is connected to the drain of the third gallium arsenide pHEMT to form an N1 node, the N1 node is connected in series to the drain of the second gallium arsenide pHEMT, and the source of the second gallium arsenide pHEMT is connected to the second node.

[0039] In some embodiments, the gate width of the first gallium arsenide pHEMT and the first gallium arsenide pHEMT are both 50um, the gate index is 6, the isolation is from -27dB to -4dB when the series is turned off, and the insertion loss is from -0.42dB to -0.48dB when the series is turned on; the gate width of the third gallium arsenide pHEMT is 50um, the gate index is 2, the insertion loss is from -0.007dB to -0.086dB when the parallel is turned off, and the isolation is from -10.3dB to -8.3dB when the parallel is turned on.

[0040] In some embodiments, the first gallium arsenide pHEMT, the first gallium arsenide pHEMT, and the third gallium arsenide pHEMT are all switch pHEMTs, and a kilo-ohm resistor is serially connected at the gate of the switch pHEMT.

[0041] In some implementations, the control voltage signal terminal is in a high level state or a low level state, and the high level and low level states of the control voltage signal terminal signal in each of the branches do not affect each other.

[0042] In some implementations, the input inductor and the output inductor are both inductors prepared by bending a high-impedance microstrip line.

[0043] In some embodiments, the material structure of the microstrip line includes: a first metal layer, a second metal layer, and a semiconductor material located between the first metal layer and the second metal layer.

[0044] In some embodiments, the DC blocking capacitors are all capacitors with a material structure of metal-insulating layer-metal MIM.

[0045] In some embodiments, the input inductor, the output inductor, the microstrip line, the DC blocking capacitor and the GaAs pHEMT use the same substrate.

[0046] In some embodiments, the substrate is made of silicon nitride, gallium arsenide or silicon.

[0047] The present invention is further described in detail below in conjunction with specific embodiments. Example 1

[0048] like Figure 2As shown, a gallium arsenide ultra-wideband double-pole double-throw switch of the present invention includes a transmitting end TX, a receiving end RX, an antenna end ANT1, an antenna end ANT2, an input inductor, an output inductor, four branches and a microstrip line connecting each device. The four branches are branch I, branch II, branch III and branch IV.

[0049] Branch I, branch II, branch III and branch IV all include: a first gallium arsenide pHEMT Q1, a second gallium arsenide pHEMT Q2, a third gallium arsenide pHEMT Q3, a DC blocking capacitor, an N1 node and two control voltage signal terminals, and the two control voltage signal terminals are respectively a control voltage signal terminal Vg1 and a control voltage signal terminal Vg2.

[0050] The transmitting end TX leads to the antenna end ANT1 via branch I, the transmitting end TX leads to the antenna end ANT2 via branch IV, the antenna end ANT1 leads to the receiving end RX via branch II, and the antenna end ANT2 leads to the receiving end RX via branch III.

[0051] The node where the transmitter TX connects the two branches of the antenna terminal ANT1 and the antenna terminal ANT2 through an input inductor L1 is the first node among the four nodes, and the first node is adjacent to the input inductor L1; the second node among the four nodes is the node connecting branch I, branch II and the node leading to the antenna terminal ANT1 through an output inductor L2.

[0052] In this embodiment 1, the structure of the branch is described by taking branch I as an example, which is as follows:

[0053] The first node is connected in series to the drain D1 of the first gallium arsenide pHEMT Q1, the source S1 of the first gallium arsenide pHEMT Q1 is connected to the drain D3 of the third gallium arsenide pHEMT Q3 to form the N1 node, the N1 node is connected in series to the drain D2 of the second gallium arsenide pHEMT Q2; the source of the third gallium arsenide pHEMT Q3 is connected in series to the DC blocking capacitor C0 to be grounded;

[0054] The source S2 of the second GaAs pHEMT Q2 is connected to the second node and output to the antenna terminal ANT1 after passing through the output inductor L2.

[0055] The gate G1 of the first gallium arsenide pHEMT Q1 and the gate G2 of the second gallium arsenide pHEMT Q2 are both connected to the control voltage signal terminal Vg1 via a kilo-ohm-level isolation resistor R, and are simultaneously controlled by the control voltage signal terminal Vg1. Since the gate has its own resistance in the process flow, it is not shown in the schematic diagram. The gate G3 of the third gallium arsenide pHEMT Q3 is connected to the control voltage Vg2 via an isolation resistor R.

[0056] The output inductor L1 and the output inductor L2 have different performances under different signal transmission conditions and need to be determined according to the direction of signal flow, but their function is to act as a matching circuit to offset the capacitive nature of the system under high frequency conditions.

[0057] Exemplarily, the gate width of the first gallium arsenide pHEMT Q1 and the second gallium arsenide pHEMT Q2 is 50 um, and the gate index is 6; the gate width of the third gallium arsenide pHEMT Q3 is 50 um, and the gate index is 2.

[0058] Optionally, the operating range of the above-mentioned GaAs ultra-wideband double-pole double-throw switch includes 1 GHz to 17 GHz.

[0059] Optionally, in the GaAs ultra-wideband double-pole double-throw switch, the input inductor L1, the output inductor L2, the microstrip line, the first GaAs pHEMT Q1, the second GaAs pHEMT Q2 and the third GaAs pHEMT use the same substrate. Exemplarily, the substrate is made of silicon nitride, GaAs or silicon.

[0060] In this embodiment 1, the input inductor L1 and the output inductor L2 are both made by bending a high impedance microstrip line. Specifically, the performance parameters of the input inductor L1 and the output inductor L2 are: L=0.437nH, w=8um, s=4um, n=1.5, term_w=8um, dx=35um, dy=60um.

[0061] In this embodiment 1, the DC blocking capacitors C0 are all metal-insulator-metal MIM capacitors. The performance parameters of the DC blocking capacitors C0 are: C=0.156pF, W=20um, L=20um, airW=12um, airL=10um. Example 2

[0062] like Figure 3 As shown, this embodiment 2 is an equivalent circuit diagram of the isolation branch of the GaAs ultra-wideband double-pole double-throw switch of the above-mentioned embodiment 1.

[0063] When the control voltage signal terminal Vg1 turns off the first gallium arsenide pHEMT Q1 and the second gallium arsenide pHEMT Q2, the first gallium arsenide pHEMT Q1 and the second gallium arsenide pHEMT Q2 may be equivalent to an off capacitor Coff.

[0064] When the control voltage signal terminal Vg2 turns on the third GaAs pHEMT Q3 , the third GaAs pHEMT Q3 can be regarded as a very small on-resistance Ron.

[0065] At this time, only a small amount of signal passes through the turn-off capacitor Coff1, and then reaches the ground through the grounding resistor, and it is almost impossible to pass through the turn-off capacitor Coff2; looking from the input terminal Pin to the output terminal Pout is equivalent to an open circuit. Example 3

[0066] like Figure 4 As shown, this embodiment 3 is an equivalent circuit diagram of the conduction branch of the GaAs ultra-wideband double-pole double-throw switch of the above-mentioned embodiment 1.

[0067] When the control voltage signal terminal Vg1 turns on the first gallium arsenide pHEMT Q1 and the second gallium arsenide pHEMT Q2 , the first gallium arsenide pHEMT Q1 and the second gallium arsenide pHEMT Q2 may be equivalent to an on-resistance Ron.

[0068] When the third GaAs pHEMT Q3 is turned off by the control voltage signal terminal Vg2, the third GaAs pHEMT Q3 can be regarded as a very small off capacitor Coff.

[0069] At this time, only a very small signal is lost during the transmission process, and the view from the input terminal Pin to the output terminal Pout is equivalent to a path. Example 4

[0070] like Figure 5 As shown, in the present embodiment 4, the ultra-wideband double-pole double-throw switch of the above embodiment 1 is tested in the range of 1 GHz to 17 GHz and in the on state. Figure 5 3 is a schematic diagram of the test results of the S parameters of the GaAs ultra-wideband double-pole double-throw switch of the above-mentioned embodiment 1. It can be seen that the insertion loss of the double-pole double-throw switch is less than 2.15dB, and the isolation degree is greater than 22.08dB in the isolated state.

[0071] The present invention is described by the above-mentioned specific implementation methods and embodiments, and it should be understood by those skilled in the art that various changes and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. The parts not described in detail in the present specification are known to those skilled in the art. In addition, various modifications may be made to the present invention for specific situations or specific circumstances without departing from the scope of the present invention. Therefore, the present invention is not limited to the disclosed specific embodiments, but should include all implementation methods falling within the scope of the claims of the present invention.

Claims

1. A gallium arsenide ultra-wideband double-pole double-throw switch, characterized in that: The double-pole double-throw switch has an operating range of 1 GHz to 17 GHz, and specifically includes a receiving end RX, a transmitting end TX, an antenna end ANT1, an antenna end ANT2, an input inductor, an output inductor, four branches, and a microstrip line connecting various devices; The components and structures of the four branches are the same, and each branch includes: a first gallium arsenide pHEMT and a second gallium arsenide pHEMT connected in series, a third gallium arsenide pHEMT connected in parallel with the first gallium arsenide pHEMT, a grounded DC blocking capacitor C0 connected in series with the third gallium arsenide pHEMT, and two control voltage signal terminals; the first gallium arsenide pHEMT and the second gallium arsenide pHEMT share a control voltage signal terminal, and the third gallium arsenide pHEMT branch uses a control voltage signal terminal alone; The first gallium arsenide pHEMT or the second gallium arsenide pHEMT of each branch is connected to the first gallium arsenide pHEMT or the second gallium arsenide pHEMT of the other two adjacent branches to form four nodes, and the four nodes are respectively connected to the receiving end RX, the transmitting end TX, the antenna end ANT1 and the antenna end ANT2 via at least one input inductor or at least one output inductor; The four branches are branch I, branch II, branch III and branch IV, the transmitting end TX leads to the antenna end ANT1 via branch I, the transmitting end TX leads to the antenna end ANT2 via branch IV, the antenna end ANT1 leads to the receiving end RX via branch II, and the antenna end ANT2 leads to the receiving end RX via branch III; The node where the transmitting terminal TX connects the two branches of the antenna terminal ANT1 and the antenna terminal ANT2 via an input inductor is the first node among the four nodes, and the first node is adjacent to the input inductor; the second node among the four nodes is the node connecting the branch I, the branch II and the node leading to the antenna terminal ANT1 via an output inductor; the third node among the four nodes is the node connecting the branch II, the branch III and the node leading to the receiving terminal RX via an input inductor; the fourth node among the four nodes is the node connecting the branch III, the branch IV and the node leading to the antenna terminal ANT2 via an inductor; In the branch I, the first node is connected in series to the drain of the first gallium arsenide pHEMT, the source of the first gallium arsenide pHEMT is connected to the drain of the third gallium arsenide pHEMT to form an N1 node, the N1 node is connected in series to the drain of the second gallium arsenide pHEMT, and the source of the second gallium arsenide pHEMT is connected to the second node.

2. The gallium arsenide ultra-wideband double-pole double-throw switch according to claim 1, characterized in that: The gate width of the first gallium arsenide pHEMT and the second gallium arsenide pHEMT are both 50um, the gate index is both 6, the isolation is -27dB~-4dB when the series is turned off, and the insertion loss is -0.42dB~-0.48dB when the series is turned on; the gate width of the third gallium arsenide pHEMT is 50um, the gate index is 2, the insertion loss is -0.007dB~-0.086dB when the parallel is turned off, and the isolation is -10.3dB~-8.3dB when the parallel is turned on.

3. The gallium arsenide ultra-wideband double-pole double-throw switch according to claim 1 or 2, characterized in that: The first gallium arsenide pHEMT, the second gallium arsenide pHEMT and the third gallium arsenide pHEMT are all switch pHEMTs, and a kilo-ohm resistor is connected in series at the gate of the switch pHEMT.

4. The gallium arsenide ultra-wideband double-pole double-throw switch according to claim 3, characterized in that: The control voltage signal terminal is in a high level state or a low level state, and the high level and low level states of the control voltage signal terminal in each branch do not affect each other.

5. The gallium arsenide ultra-wideband double-pole double-throw switch according to claim 4, characterized in that: The input inductor and the output inductor are both inductors prepared by bending a high-impedance microstrip line.

6. The gallium arsenide ultra-wideband double-pole double-throw switch according to claim 5, characterized in that: The material structure of the microstrip line includes: a first metal layer, a second metal layer, and a semiconductor material located between the first metal layer and the second metal layer.

7. The GaAs ultra-wideband double-pole double-throw switch according to claim 6, characterized in that: The DC blocking capacitors are all capacitors whose material structure is metal-insulating layer-metal MIM.

8. The gallium arsenide ultra-wideband double-pole double-throw switch according to claim 7, characterized in that: The input inductor, the output inductor, the microstrip line, the DC blocking capacitor and the gallium arsenide pHEMT use the same substrate.

9. The gallium arsenide ultra-wideband double-pole double-throw switch according to claim 8, characterized in that: The substrate is made of silicon nitride, gallium arsenide or silicon.

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