Semiconductor manufacturing methods and semiconductor structures

Abstract

This invention relates to a semiconductor manufacturing method and a semiconductor structure. The semiconductor manufacturing method includes at least the following steps: providing a wafer, forming trenches on the front side of the wafer; depositing dielectric layers on the front and back sides of the wafer; depositing polysilicon on the dielectric layers on the front and back sides of the wafer to form a first polysilicon layer on the front side of the wafer and a second polysilicon layer on the back side of the wafer, the first polysilicon layer filling the trenches and covering the openings of the trenches; performing ion implantation on the back side of the wafer to partially or completely transform the second polysilicon layer into an amorphous silicon layer; simultaneously etching the first polysilicon layer on the front side of the wafer and the amorphous silicon layer on the back side of the wafer, wherein during the etching process, the etching rate of the amorphous silicon layer is greater than the etching rate of the first polysilicon layer. This semiconductor manufacturing method can adjust the stress on both sides of the wafer, effectively solving the problem of wafer warpage.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and particularly relates to a semiconductor manufacturing method and semiconductor structure. Background Technology

[0002] Since the introduction of Moore's Law, the density of microelectronic devices has almost followed its predictions. For semiconductor technology, continuously shrinking the structural size of semiconductor devices, improving speed, enhancing performance, increasing density, and reducing the cost per unit of integrated circuit are all important development goals. As the size of semiconductor devices shrinks, the electronic characteristics of the devices must also be maintained or even improved to meet the requirements of the market for applied electronic products.

[0003] Generally, reducing the structural size of semiconductor devices increases the aspect ratio of pattern gaps (or trenches). For example, in the current manufacturing process of memory / logic / power chips, more stringent deep trench capacitors are required, but increasingly deeper and narrower trenches have a serious impact on wafer warpage.

[0004] Currently, such as Figure 1 As shown, deep trench capacitors are typically constructed by first creating trenches 101' on the surface of wafer 100', then depositing doped polysilicon 2' on both sides, and finally etching away any excess polysilicon 2'. However, polysilicon generates compressive stress, causing the wafer substrate to bulge. Furthermore, the larger the trench aspect ratio, the more pronounced the wafer substrate warpage becomes, affecting the electrical performance of the semiconductor device. Summary of the Invention

[0005] In view of the shortcomings of related technologies, the present invention provides a semiconductor manufacturing method and semiconductor structure that can adjust the stress on both sides of the wafer and effectively solve the problem of wafer warping.

[0006] The first aspect of this application provides a semiconductor manufacturing method, comprising at least the following steps:

[0007] A wafer is provided, on which trenches are formed;

[0008] Dielectric layers are deposited on the front and back sides of the wafer;

[0009] Polysilicon is deposited on the dielectric layers on the front and back sides of the wafer to form a first polysilicon layer on the front side of the wafer and a second polysilicon layer on the back side of the wafer. The first polysilicon layer fills the trench and covers the opening of the trench.

[0010] Ion implantation is performed on the back side of the wafer to partially or completely transform the second polycrystalline silicon layer into an amorphous silicon layer;

[0011] The first polysilicon layer on the front side and the amorphous silicon layer on the back side of the wafer are etched simultaneously. During the etching process, the etching rate of the amorphous silicon layer is greater than that of the first polysilicon layer.

[0012] When the first polysilicon layer on the front side is etched to the required thickness and etching stops, the thickness of the amorphous silicon layer remaining on the back side of the wafer after etching, or the sum of the thicknesses of the second polysilicon layer and the amorphous silicon layer, is less than the thickness of the first polysilicon layer remaining on the front side of the wafer.

[0013] In some embodiments of the first aspect, during the etching process, the wafer is placed in an etchant, and wet etching is used to simultaneously etch the first polycrystalline silicon layer and the amorphous silicon layer.

[0014] In some embodiments of the first aspect, the selected etchant has an etching rate ratio of polycrystalline silicon to amorphous silicon of 5:6 to 11:14.

[0015] In some embodiments of the first aspect, the dielectric layer is silicon oxide, and the selected etching solution has an etching rate selection ratio of silicon oxide:polycrystalline silicon:amorphous silicon = 1:100:120 to 1:110:140.

[0016] In some embodiments of the first aspect, the etching rate of the first polysilicon layer is The etching rate of the amorphous silicon layer is The etching rate of silicon oxide is

[0017] In some embodiments of the first aspect, after etching, the thickness of the first polysilicon layer retained on the front side of the wafer is [missing information]. The thickness of the amorphous silicon layer retained on the back side of the wafer is...

[0018]

[0019] In some embodiments of the first aspect, during the deposition of the polysilicon layer, a polysilicon layer is simultaneously deposited on the dielectric layers on the front and back sides of the wafer using a chemical vapor deposition process.

[0020] In some embodiments of the first aspect, the ion implantation energy is 100–150 keV, and the ion implantation dose is 1 × e 14 ~1×e 15 cm -2 .

[0021] In some embodiments of the first aspect, the aspect ratio of the trench is 4 to 8.

[0022] A second aspect of this application provides a semiconductor structure manufactured according to any one of the semiconductor manufacturing methods described in the first aspect above, comprising:

[0023] A wafer, with trenches formed on its front side;

[0024] A dielectric layer, which is formed on the front and back sides of the wafer;

[0025] A first polysilicon layer is formed on the dielectric layer on the front side of the wafer, and the first polysilicon layer fills the trench and covers the opening of the trench.

[0026] An amorphous silicon layer is formed on the dielectric layer on the back side of the wafer, and the thickness of the amorphous silicon layer is less than the thickness of the first polycrystalline silicon layer.

[0027] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0028] (1) The semiconductor manufacturing method provided in at least one embodiment of this application cleverly utilizes the polycrystalline silicon layer deposited on both sides during the semiconductor gate manufacturing process to transform part or all of the polycrystalline silicon layer on the back side into an amorphous state. By utilizing the different etching rates of amorphous silicon and polycrystalline silicon, the stress on both sides is adjusted, effectively controlling the warpage problem of the wafer substrate and improving the flatness of the semiconductor device. No additional complex processes are required, and the whole process has a high degree of compatibility with the original process and is easy to implement.

[0029] (2) In the semiconductor structure provided in at least one embodiment of this application, during the formation process, the polycrystalline silicon layer on the back side is partially or completely transformed into an amorphous state, and the stress on both sides is controlled by etching, so that the stress difference on both sides of the semiconductor structure is small and has good flatness. Attached Figure Description

[0030] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0031] Figure 1 This is a schematic diagram of wafer warpage caused by the deep trench capacitor manufacturing method in the prior art;

[0032] Figure 2 A flowchart illustrating a semiconductor manufacturing method provided in an embodiment of this application;

[0033] Figure 3 This is a cross-sectional view of the semiconductor structure after performing step S3 in the semiconductor manufacturing method provided according to the embodiments of this application;

[0034] Figure 4 This is a cross-sectional view of the semiconductor structure after performing step S4 in the semiconductor manufacturing method provided according to the embodiments of this application;

[0035] Figure 5This is a cross-sectional view of the semiconductor structure after performing step S6 in the semiconductor manufacturing method provided according to the embodiments of this application.

[0036] In the picture:

[0037] Existing technologies: 100', wafer; 101', trench; 2', polysilicon;

[0038] Embodiments of this application: 100, wafer; 101, trench; 103, dielectric layer; 2, polysilicon layer; 201, first polysilicon layer; 202, second polysilicon layer; 3, amorphous silicon layer. Detailed Implementation

[0039] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0040] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0041] The terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0042] The term "aspect ratio" is used to describe the ratio of the height to the width of any opening formed in wafer 100. Elements not specifically shown or described in this application may take on a variety of forms known to those skilled in the art. Furthermore, when a layer is referred to as being "on top of" another layer or "on top of" a substrate, it may be directly on top of another layer or on top of the substrate, or an intermediate layer may also be present.

[0043] The following detailed reference is made to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to denote the same or similar parts. In the drawings, the shape and thickness of one embodiment may be enlarged for clarity and convenience.

[0044] In a first aspect of this application, a semiconductor manufacturing method is provided. This method, by filling and processing the formed deep trenches, can avoid warpage defects and effectively improve the flatness of the wafer. For example... Figure 2 As shown, the semiconductor manufacturing method includes at least the following steps:

[0045] S1. A wafer is provided, and a trench is formed on the front side of the wafer;

[0046] S2. Deposit dielectric layers on the front and back sides of the wafer;

[0047] S3. Polysilicon is deposited on the dielectric layers on the front and back sides of the wafer to form a first polysilicon layer on the front side of the wafer and a second polysilicon layer on the back side of the wafer. The first polysilicon layer fills the trench and covers the opening of the trench.

[0048] S4. Perform ion implantation on the back side of the wafer to partially or completely transform the second polycrystalline silicon layer into an amorphous silicon layer.

[0049] S5. The first polysilicon layer on the front side and the amorphous silicon layer on the back side of the wafer are etched simultaneously. During the etching process, the etching rate of the amorphous silicon layer is greater than that of the first polysilicon layer.

[0050] S6. When the first polysilicon layer on the front side is etched to the required thickness and etching is stopped, the thickness of the amorphous silicon layer retained on the back side of the wafer after etching, or the sum of the thicknesses of the second polysilicon layer and the amorphous silicon layer, is less than the thickness of the first polysilicon layer retained on the front side of the wafer.

[0051] The semiconductor manufacturing method provided in this application cleverly utilizes the polycrystalline silicon layers formed on both the front and back sides after double-sided deposition during semiconductor gate manufacturing to adjust the stress on both sides of the wafer substrate, thereby controlling the flatness of the wafer. This eliminates the need for additional complex processes, and the entire process is highly compatible with existing technologies and easy to implement. Specifically, the polycrystalline silicon layer on the back side is partially or completely transformed into an amorphous state. By utilizing the different etching rates of amorphous silicon and polycrystalline silicon, different film thicknesses are generated after simultaneous etching on both sides. This reduces excess compressive stress on the back side of the wafer, effectively controlling wafer substrate warpage and improving the flatness of the semiconductor device.

[0052] Furthermore, it is understood that only the steps related to the improvements of this application are shown in the above methods, not all of them. Therefore, the steps are not seamlessly connected, and other necessary or unnecessary steps may be interspersed between the two steps as needed.

[0053] The following will describe in detail each step of the semiconductor manufacturing method provided in the embodiments of this application, with reference to cross-sectional views of the semiconductor structure during the semiconductor manufacturing process.

[0054] In step S1, a wafer 100 is provided. The wafer 100 can be made of bulk silicon, a doped or undoped semiconductor substrate, or silicon-on-insulator (SOI), or any other semiconductor material suitable for fabricating a chip substrate. The wafer 100 includes a front side and a back side; typically, the front side of the wafer 100 is used to form functional areas such as circuits or transistors, and the side opposite to the front side is the back side of the wafer 100. In this embodiment, the specifications and thickness of the wafer 100 are not limited and can be selected by the designer as needed.

[0055] A trench 101 is formed on the front side of wafer 100. The trench 101 is used to subsequently fill and form a dummy gate or a gate. The trench 101 can be formed by photolithography and etching on the front side of wafer 100. The location of the trench 101 on the front side of wafer 100 is defined by photolithography, and then the trench 101 is formed by etching on the front side of wafer 100 with the aid of a patterned hard mask layer. The etching process can be wet etching or dry etching, plasma etching, laser drilling, etc. In some embodiments, in order to achieve the requirements of deep trench capacitors, the depth and width of the formed trench 101 are 4 to 8.

[0056] In step S2, a dielectric layer 103 is deposited on both the front and back sides of wafer 100. The dielectric layer 103 may comprise any suitable dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The dielectric layer 103 can be formed by any suitable method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), high-density plasma (HDP) processes, atomic layer deposition (ALD), etc. Figure 3 As shown, a medium layer 103 is deposited at the bottom and sidewalls of the trench 101.

[0057] In step S3, polysilicon is deposited on the dielectric layers 103 on both the front and back sides of wafer 100. In some embodiments, polysilicon is deposited simultaneously on both the front and back sides of wafer 100 using a chemical vapor deposition process. Specifically, during the deposition process, wafer 100 is placed in a boat within a polysilicon tube, and gas is introduced to generate a chemical reaction on the surface of wafer 100, depositing polysilicon. Polysilicon layers 2 are deposited simultaneously on both the front and back sides. The polysilicon layer 2 on the front side of wafer 100 is a first polysilicon layer 201, and the polysilicon layer 2 on the back side of wafer 100 is a second polysilicon layer 202. The first polysilicon layer 201 on the front side of wafer 100 fills the trench 101 and covers the opening of the trench 101. Figure 3 As shown.

[0058] The presence of the trench 101 on the front side of the wafer 100 causes stress inconsistency on both sides of the wafer 100 during the deposition of polysilicon, which in turn causes the wafer 100 to warp and bend. In particular, the greater the aspect ratio of the trench 101, the more prominent the stress inconsistency becomes, and the more severe the warping problem becomes.

[0059] To adjust the stress on both sides of wafer 100 and thus improve the warpage problem of wafer 100, such as... Figure 4 As shown, in step S4, ion implantation is performed on the back side of wafer 100 to partially or completely transform the second polycrystalline silicon layer 202 into an amorphous silicon layer 3. Ion implantation can disrupt the surface lattice of the polycrystalline silicon layer 2, transforming the crystalline polycrystalline silicon into an amorphous state. A high-energy ion implanter can be used during the ion implantation process; optionally, the ion implantation energy is 100–150 keV, and the ion implantation dose is 1 × e-1. 14 ~1×e 15 cm -2 After ion implantation using ions with the above-mentioned energy and dosage range, the second polycrystalline silicon layer 202 within the required thickness range can be transformed into amorphous silicon, and the amorphous state can be controlled to further control the difference in etching rate between polycrystalline silicon and amorphous silicon during the etching process.

[0060] After converting at least a portion of the polycrystalline silicon on the back side of wafer 100 into amorphous silicon in step S4, during the etching process in step S5, since the etching rate of amorphous silicon is greater than that of polycrystalline silicon, the etching speed of the amorphous silicon layer 3 on the back side of wafer 100 is faster, while the etching speed of the first polycrystalline silicon layer 201 on the front side of wafer 100 is slower. In the same amount of time, more of the amorphous silicon layer 3 on the back side is etched away, which reduces the degree of stress inconsistency between the front and back sides, improves the warping problem, and can even obtain a completely flat wafer 100.

[0061] In the manufacturing process, the surface of the trench 101 on the front side of wafer 100 needs to be etched to remove excess polysilicon. In step S5, a wet etching process can be used to etch both sides of wafer 100 simultaneously. Wafer 100 is placed in an etchant, and the first polysilicon layer 201 on the front side and the amorphous silicon layer 3 on the back side of wafer 100 are etched simultaneously through a chemical reaction. In the wet etching process, because the etchant has different selectivity ratios for polysilicon and amorphous silicon, the etching rates on the two sides of wafer 100 are different, which can reduce or offset the inconsistency of stress on the two sides to a certain extent, thereby controlling the flatness of wafer 100.

[0062] Because different etchants have different selectivity ratios, the etching rate on both sides of wafer 100 can be controlled by selecting different etchants, thereby controlling the film thickness on both sides and ultimately controlling the flatness of wafer 100. In some embodiments, the selectivity ratio of the etchant selected during wet etching is: polysilicon: amorphous silicon = 5:6 to 11:14. Etching solutions with selectivity ratios within this range can control the etching of the polysilicon layer 2 and the amorphous silicon layer 3 on both sides of wafer 100 to a degree that reduces or cancels out the stress difference, resulting in better control over the flatness of wafer 100 after etching.

[0063] In some embodiments, the dielectric layer 103 is silicon oxide, and the etching rate selectivity ratio of the etchant chosen during wet etching is: silicon oxide:polycrystalline silicon:amorphous silicon = 1:100:120 to 1:110:140. Optionally, in one embodiment, the selectivity ratio is 1:107:139. Etching at this selectivity ratio allows the etching rates for the front and back sides of the wafer 100 to be optimally adjusted, so that the stress of the remaining film thickness on both sides after etching can be basically offset, avoiding warping and achieving good wafer flatness.

[0064] In some embodiments, the etchant is Spin D, Spin E, or KOH, etc. These etchants can achieve the selectivity within the above-mentioned range and have good etching uniformity, which can reduce the warpage of the wafer. Among them, Spin D and Spin E are mixed acids, namely sulfuric acid, nitric acid, HF acid and phosphoric acid, mixed in different proportions to obtain a mixture, which is collectively referred to as Spin D or Spin E in the art.

[0065] In some embodiments, the etching rate of the first polysilicon layer 201 is The etching rate of amorphous silicon layer 3 is The etching rate of silicon oxide is This allows the thickness of the polycrystalline silicon layer 2 on the front side and the amorphous silicon layer 3 on the back side of wafer 100 to reach a level of stress balance, achieving good flatness.

[0066] After etching the first polysilicon layer 201 on the front side to the required thickness, the etching process is complete. Figure 5 As shown, the thickness of the amorphous silicon layer 3 retained on the back side of the wafer 100 after etching (when the second polysilicon layer 202 is completely transformed into the amorphous silicon layer 3) or the sum of the thicknesses of the second polysilicon layer and the amorphous silicon layer (when the second polysilicon layer 202 is partially transformed into the amorphous silicon layer 3) is less than the thickness of the first polysilicon layer 201 retained on the front side of the wafer 100. In some embodiments, after etching, the thickness of the first polysilicon layer 201 retained on the front side of the wafer 100 is... (Trench depth not included), the thickness of the amorphous silicon layer 3 retained on the back side of wafer 100 is... This thickness range corresponds to the etching rate of polycrystalline silicon and amorphous silicon during the etching process. The etching rate of amorphous silicon is less than that of polycrystalline silicon. Therefore, after the etching process, the thickness of the first polycrystalline silicon layer retained on the front side of the wafer is greater than the thickness of the amorphous silicon layer retained on the back side of the wafer or the thickness of the second polycrystalline silicon layer and amorphous silicon layer.

[0067] A second aspect of this application provides a semiconductor structure manufactured according to the semiconductor manufacturing method of the first aspect described above. This semiconductor structure exhibits a small stress difference across its two sides and good flatness.

[0068] The semiconductor structure includes a wafer 100 with a trench 101 formed on the front side, dielectric layers 103 formed on the front and back sides of the wafer 100, a first polysilicon layer 201 formed on the dielectric layer 103 on the front side of the wafer 100, the first polysilicon layer 201 filling the trench 101 and covering the opening of the trench 101, and an amorphous silicon layer 3 formed on the dielectric layer 103 on the back side of the wafer 100, the thickness of the amorphous silicon layer 3 being less than the thickness of the first polysilicon layer 201, thereby reducing or unifying the stress difference between the front and back sides of the wafer 100, reducing the warpage process, and improving the flatness of the wafer 100.

[0069] In some embodiments, during the execution of step S4 by the semiconductor manufacturing method provided in the first aspect of this application, when part but not all of the second polysilicon layer 202 is transformed into an amorphous silicon layer 3, it can be understood that in the obtained semiconductor structure, there may still be a second polysilicon layer 202 between the dielectric layer 103 on the back side of the wafer 100 and the amorphous silicon layer 3 (this case is not shown in the figure).

[0070] Finally, it should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0071] The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A semiconductor manufacturing method, characterized in that, At least the following steps are included: A wafer is provided, and trenches are formed on the front side of the wafer; Dielectric layers are deposited on the front and back sides of the wafer; Polysilicon is deposited on the dielectric layers on the front and back sides of the wafer to form a first polysilicon layer on the front side of the wafer and a second polysilicon layer on the back side of the wafer, wherein the first polysilicon layer fills the trench and covers the opening of the trench. Ion implantation is performed on the back side of the wafer to partially or completely transform the second polycrystalline silicon layer into an amorphous silicon layer; The first polycrystalline silicon layer on the front side and the amorphous silicon layer on the back side of the wafer are etched simultaneously. During the etching process, the etching rate of the amorphous silicon layer is greater than that of the first polycrystalline silicon layer. When the first polysilicon layer on the front side is etched to the required thickness and etching stops, the thickness of the amorphous silicon layer remaining on the back side of the wafer after etching, or the sum of the thicknesses of the second polysilicon layer and the amorphous silicon layer, is less than the thickness of the first polysilicon layer remaining on the front side of the wafer.

2. The semiconductor manufacturing method according to claim 1, characterized in that, During the etching process, the wafer is placed in the etching solution, and wet etching is used to simultaneously etch the first polycrystalline silicon layer and the amorphous silicon layer.

3. The semiconductor manufacturing method according to claim 2, characterized in that, The selected etching solution has the following etching rate ratio: polycrystalline silicon: amorphous silicon = 5:6 to 11:

14.

4. The semiconductor manufacturing method according to claim 3, characterized in that, The dielectric layer is silicon oxide, and the selected etching solution has the following etching rate ratio: silicon oxide: polycrystalline silicon: amorphous silicon = 1:100:120 to 1:110:

140.

5. The semiconductor manufacturing method according to claim 4, characterized in that, The etching rate of the first polysilicon layer is The etching rate of the amorphous silicon layer is The etching rate of the silicon oxide is 6. The semiconductor manufacturing method according to claim 3, characterized in that, After etching, the thickness of the first polysilicon layer remaining on the front side of the wafer is [missing information]. The thickness of the amorphous silicon layer retained on the back side of the wafer is 7. The semiconductor manufacturing method according to claim 1, characterized in that, During the deposition of the polycrystalline silicon layer, the polycrystalline silicon layer is simultaneously deposited on the dielectric layers on the front and back sides of the wafer using a chemical vapor deposition process.

8. The semiconductor manufacturing method according to claim 1, characterized in that, The ion implantation energy is 100–150 keV, and the ion implantation dose is 1 × e-1. 14 ~1×e 15 cm -2 .

9. The semiconductor manufacturing method according to claim 1, characterized in that, The depth-to-width ratio of the trench is 4 to 8.

10. A semiconductor structure manufactured by the semiconductor manufacturing method according to claim 1, characterized in that, include: A wafer, on the front side of which trenches are formed; A dielectric layer is formed on the front and back sides of the wafer; A first polysilicon layer is formed on the dielectric layer on the front side of the wafer, the first polysilicon layer filling the trench and covering the opening of the trench; An amorphous silicon layer is formed on the dielectric layer on the back side of the wafer, and the thickness of the amorphous silicon layer is less than the thickness of the first polycrystalline silicon layer.

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